[llvm] [RISCV] Use `experimental-p` extension for zero-extended narrow unsigned types (PR #213260)

[Rajveer Singh Bharadwaj via llvm-commits]

https://github.com/Rajveer100 created https://github.com/llvm/llvm-project/pull/213260

Resolves #211361

The bits `31:8` remain zero after packed addition due to `padd.b` carry-out as per ABI, hence we can generate more optimised code instead of `zext.b` + `add`.

>From 094966c1e0582fb84ab75990213fc8e885bea8d4 Mon Sep 17 00:00:00 2001
From: Rajveer <rajveer.developer at icloud.com>
Date: Fri, 31 Jul 2026 17:41:45 +0530
Subject: [PATCH] [RISCV] Use `experimental-p` extension for zero-extended
 narrow unsigned types

Resolves #211361

The bits `31:8` remain zero after packed addition due to `padd.b`
carry-out as per ABI, hence we can generate more optimised code instead
of `zext.b` + `add`.
---
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp      | 14 ++++++++++++++
 ...tal-p-extension-narrow-unsigned-arithmetic.ll | 16 ++++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/experimental-p-extension-narrow-unsigned-arithmetic.ll

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 611306b6ab7b3..3a7c5277e0011 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1816,6 +1816,20 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     if (tryShrinkShlLogicImm(Node))
       return;
 
+    if (N0->getOpcode() == ISD::ADD && N1C->getZExtValue() == 255) {
+      SDValue AddN0 = N0->getOperand(0);
+      SDValue AddN1 = N0.getOperand(1);
+
+      EVT ValTyN0 = AddN0.getValueType(), ValTyN1 = AddN1.getValueType();
+      if (AddN0.getOpcode() == ISD::AssertZext &&
+          AddN1.getOpcode() == ISD::AssertZext && ValTyN0 == ValTyN1) {
+        SDNode *PADDB =
+            CurDAG->getMachineNode(RISCV::PADD_B, DL, ValTyN0, AddN0, AddN1);
+        ReplaceNode(Node, PADDB);
+        return;
+      }
+    }
+
     break;
   }
   case ISD::MUL: {
diff --git a/llvm/test/CodeGen/RISCV/experimental-p-extension-narrow-unsigned-arithmetic.ll b/llvm/test/CodeGen/RISCV/experimental-p-extension-narrow-unsigned-arithmetic.ll
new file mode 100644
index 0000000000000..85434a8397505
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/experimental-p-extension-narrow-unsigned-arithmetic.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p \
+; RUN:   -verify-machineinstrs < %s | \
+; RUN:   FileCheck --check-prefixes=CHECK,RV32 %s
+
+define zeroext i8 @f(i8 zeroext %x, i8 zeroext %y) {
+; CHECK-LABEL: f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    padd.b a0, a1, a0
+; CHECK-NEXT:    ret
+entry:
+  %add = add i8 %y, %x
+  ret i8 %add
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}