[llvm] [VPlan] Remove redundant x && (y && x) -> x && y combine (PR #213219)

[Ramkumar Ramachandra via llvm-commits]

================
@@ -1188,16 +1192,9 @@ static bool simplifyLogicalRecipe(VPSingleDefRecipe *Def, VPBuilder &Builder,
   }
 
   // x && (x && y) -> x && y
-  if (match(Def, m_LogicalAnd(m_VPValue(X),
-                              m_LogicalAnd(m_Deferred(X), m_VPValue())))) {
-    Def->replaceAllUsesWith(Def->getOperand(1));
-    return true;
-  }
-
-  // x && (y && x) -> x && y
-  if (match(Def, m_LogicalAnd(m_VPValue(X),
-                              m_LogicalAnd(m_VPValue(Y), m_Deferred(X))))) {
-    Def->replaceAllUsesWith(Builder.createLogicalAnd(X, Y));
+  if (match(Def, m_c_LogicalAnd(m_VPValue(X),
+                                m_c_LogicalAnd(m_Deferred(X), m_VPValue())))) {
+    Def->replaceAllUsesWith(Def->getOperand(Def->getOperand(1) == X ? 0 : 1));
----------------
artagnon wrote:

Maybe just change this instance as well:

```cpp
        cast<VPRecipeWithIRFlags>(Def)->hasNoSignedWrap() &&
            cast<VPRecipeWithIRFlags>(Def->getOperand(Def->getOperand(0) == X))
                ->hasNoSignedWrap()};
```

and go ahead and land this?

https://github.com/llvm/llvm-project/pull/213219