[llvm] [LV] Vectorize bounded (i % 2^N) loads in read only loops w/o RT checks. (PR #207279)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 31 01:17:06 PDT 2026
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/207279
>From 46b0439a97669c210f976511244ce618ea88cda3 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Sat, 23 May 2026 14:01:58 +0100
Subject: [PATCH 1/3] [LV] Vectorize bounded (i % 2^N) loads in read only loops
w/o RT checks.
Add dedicated handling for loops accessing pointers based on bounded IVs
(like A[i % 2^N]). Currently we already vectorize such loops, but with a
wrap predicate that ensures that i % 2^N does not wrap.
This limits the VF to < 2 ^ N, and in many cases results in dead vector
loops, unless the trip counts are very small.
This patch adds dedicated detection for such loads and a new widening
kind (CM_Widen_Bounded). Loops with such loads can be vectorized without
runtime checks, if the VF >= Bound and Bound % VF == 0. This ensures
that the addresses for a single vector access never wrap.
Note that we need to currently handle this both in legacy widening
decision code and new VPlan-based widening. Without the code in the
legacy decision logic, we would create and add the no-wrap predicate and
with that there's no benefit.
The initial version is limited to read-only loops, which means we do not
need to worry about dependencies yet. I will share follow-ups soon to
support writes as well. To avoid churn, the helper is added to
LoopAccessAnalysis.
---
.../llvm/Analysis/LoopAccessAnalysis.h | 8 +
.../Vectorize/LoopVectorizationLegality.h | 4 +
llvm/lib/Analysis/LoopAccessAnalysis.cpp | 32 ++
.../Vectorize/LoopVectorizationLegality.cpp | 17 +-
.../Transforms/Vectorize/LoopVectorize.cpp | 46 ++-
.../Transforms/Vectorize/VPlanTransforms.cpp | 41 +++
.../LoopVectorize/AArch64/bounded-load.ll | 281 +++++++--------
.../LoopVectorize/bounded-load-predicated.ll | 72 ++--
.../LoopVectorize/bounded-load-user-ic.ll | 45 ++-
.../LoopVectorize/bounded-load-vf-ranges.ll | 338 +++++++++++-------
.../Transforms/LoopVectorize/bounded-load.ll | 84 +++--
.../runtime-check-small-bounded-ranges.ll | 10 +-
12 files changed, 579 insertions(+), 399 deletions(-)
diff --git a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
index 392321448c895..05a9d606e96a2 100644
--- a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
+++ b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
@@ -919,6 +919,14 @@ getPtrStride(PredicatedScalarEvolution &PSE, Type *AccessTy, Value *Ptr,
const DenseMap<Value *, const SCEV *> &StridesMap, bool Assume,
bool ShouldCheckWrap = true);
+/// If \p PtrSCEV is a bounded access of the form `Base + ElemSize * (i % 2^N)`
+/// where Base is loop invariant in \p L and ElemSize equals the allocation size
+/// of \p AccessTy, returns the bound 2^N.
+LLVM_ABI std::optional<uint64_t> getBoundedAccessBound(const SCEV *PtrSCEV,
+ Type *AccessTy,
+ const Loop *L,
+ ScalarEvolution &SE);
+
/// Returns the distance between the pointers \p PtrA and \p PtrB iff they are
/// compatible and it is possible to calculate the distance between them. This
/// is a simple API that does not depend on the analysis pass.
diff --git a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
index 3e8db73fd79d2..4ea0c037e4489 100644
--- a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+++ b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
@@ -389,6 +389,10 @@ class LoopVectorizationLegality {
/// loop. Do not use after invoking 'createVectorizedLoopSkeleton' (PR34965).
LLVM_ABI int isConsecutivePtr(Type *AccessTy, Value *Ptr) const;
+ /// If \p I is a bounded (i % 2^N) load in a read-only loop, returns its
+ /// bound (2^N).
+ LLVM_ABI std::optional<uint64_t> getBoundedLoadBound(Instruction *I) const;
+
/// Returns true if \p V is invariant across all loop iterations according to
/// SCEV.
LLVM_ABI bool isInvariant(Value *V) const;
diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
index 1f13106214ea9..1674610925784 100644
--- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
+++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
@@ -1708,6 +1708,38 @@ llvm::getPtrStride(PredicatedScalarEvolution &PSE, Type *AccessTy, Value *Ptr,
return Stride;
}
+std::optional<uint64_t> llvm::getBoundedAccessBound(const SCEV *PtrSCEV,
+ Type *AccessTy,
+ const Loop *L,
+ ScalarEvolution &SE) {
+ if (AccessTy->isScalableTy())
+ return std::nullopt;
+
+ // `A[i % 2^N]` is `Base + ElemSize * zext({0,+,1}<iN>)`. For a byte
+ // element (ElemSize == 1) the multiply folds away.
+ const SCEV *Base, *Start;
+ const APInt *Scale = nullptr;
+ auto Index = m_scev_ZExt(
+ m_scev_AffineAddRec(m_SCEV(Start), m_scev_One(), m_SpecificLoop(L)));
+ if (!match(PtrSCEV, m_scev_Add(m_scev_Mul(m_scev_APInt(Scale), Index),
+ m_SCEV(Base))) &&
+ !match(PtrSCEV, m_scev_Add(Index, m_SCEV(Base))))
+ return std::nullopt;
+
+ uint64_t AllocSize = L->getHeader()
+ ->getDataLayout()
+ .getTypeAllocSize(AccessTy)
+ .getFixedValue();
+ if (!Start->isZero() || !SE.isLoopInvariant(Base, L) ||
+ (Scale ? *Scale != AllocSize : AllocSize != 1))
+ return std::nullopt;
+
+ unsigned NarrowWidth = SE.getTypeSizeInBits(Start->getType());
+ if (NarrowWidth == 0 || NarrowWidth >= 64)
+ return std::nullopt;
+ return uint64_t(1) << NarrowWidth;
+}
+
std::optional<int64_t> llvm::getPointersDiff(Type *ElemTyA, Value *PtrA,
Type *ElemTyB, Value *PtrB,
const DataLayout &DL,
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
index 8d875b2b6e492..2fe01360c7104 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
@@ -437,9 +437,14 @@ void LoopVectorizationLegality::collectUnitStridePredicates() const {
return;
for (BasicBlock *BB : TheLoop->blocks())
- for (Instruction &I : *BB)
+ for (Instruction &I : *BB) {
+ // Bounded loads use the fast path; skip to avoid the wrap predicate
+ // getPtrStride would register.
+ if (getBoundedLoadBound(&I))
+ continue;
if (Value *Ptr = getLoadStorePointerOperand(&I))
isConsecutivePtr(getLoadStoreType(&I), Ptr);
+ }
}
int LoopVectorizationLegality::isConsecutivePtr(Type *AccessTy,
@@ -461,6 +466,16 @@ int LoopVectorizationLegality::isConsecutivePtr(Type *AccessTy,
return 0;
}
+std::optional<uint64_t>
+LoopVectorizationLegality::getBoundedLoadBound(Instruction *I) const {
+ auto *LI = dyn_cast<LoadInst>(I);
+ if (!LI || LAI->getNumStores() != 0)
+ return std::nullopt;
+ Value *Ptr = LI->getPointerOperand();
+ return llvm::getBoundedAccessBound(PSE.getSCEV(Ptr), LI->getType(), TheLoop,
+ *PSE.getSE());
+}
+
bool LoopVectorizationLegality::isInvariant(Value *V) const {
return LAI->isInvariant(V);
}
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index aa099b84ed61b..f9e0e5228c85d 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -875,6 +875,7 @@ class LoopVectorizationCostModel {
enum InstWidening {
CM_Unknown,
CM_Widen, // For consecutive accesses with stride +1.
+ CM_Widen_Bounded, // For bounded (i % 2^N) loads in read-only loops.
CM_Widen_Reverse, // For consecutive accesses with stride -1.
CM_Interleave,
CM_GatherScatter,
@@ -1048,8 +1049,8 @@ class LoopVectorizationCostModel {
getDivRemSpeculationCost(Instruction *I, ElementCount VF);
/// If \p I is a memory instruction with a consecutive pointer that can be
- /// widened, returns the widening kind (CM_Widen or CM_Widen_Reverse) and
- /// std::nullopt otherwise.
+ /// widened, returns the widening kind (CM_Widen, CM_Widen_Reverse,
+ /// CM_Widen_Bounded) and std::nullopt otherwise.
std::optional<InstWidening> memoryInstructionCanBeWidened(Instruction *I,
ElementCount VF);
@@ -2427,8 +2428,10 @@ bool LoopVectorizationCostModel::isScalarWithPredication(Instruction *I,
}
case Instruction::Load:
case Instruction::Store: {
- bool IsConsecutive = Legal->isConsecutivePtr(getLoadStoreType(I),
- getLoadStorePointerOperand(I));
+ bool IsConsecutive =
+ Legal->getBoundedLoadBound(I).has_value() ||
+ Legal->isConsecutivePtr(getLoadStoreType(I),
+ getLoadStorePointerOperand(I)) != 0;
return !(IsConsecutive && isLegalMaskedLoadOrStore(I, VF)) &&
!Config.isLegalGatherOrScatter(I, VF);
}
@@ -2668,20 +2671,27 @@ LoopVectorizationCostModel::memoryInstructionCanBeWidened(Instruction *I,
auto *Ptr = getLoadStorePointerOperand(I);
auto *ScalarTy = getLoadStoreType(I);
- // In order to be widened, the pointer should be consecutive, first of all.
- int Stride = Legal->isConsecutivePtr(ScalarTy, Ptr);
- if (!Stride)
+ // If the instruction's allocated size doesn't equal it's type size, it
+ // requires padding and will be scalarized.
+ auto &DL = I->getDataLayout();
+ if (hasIrregularType(ScalarTy, DL))
return std::nullopt;
- // If the instruction is a store located in a predicated block, it will be
- // scalarized.
+ // If the instruction is located in a predicated block, it will be scalarized.
if (isScalarWithPredication(I, VF))
return std::nullopt;
- // If the instruction's allocated size doesn't equal it's type size, it
- // requires padding and will be scalarized.
- auto &DL = I->getDataLayout();
- if (hasIrregularType(ScalarTy, DL))
+ // Widen a bounded (i % 2^N) load in a read-only loop as a consecutive
+ // vector load when VF divides the bound.
+ if (std::optional<uint64_t> Bound = Legal->getBoundedLoadBound(I);
+ Bound && VF.isFixed()) {
+ if (VF.getFixedValue() <= *Bound && *Bound % VF.getFixedValue() == 0)
+ return CM_Widen_Bounded;
+ return std::nullopt;
+ }
+
+ int Stride = Legal->isConsecutivePtr(ScalarTy, Ptr);
+ if (!Stride)
return std::nullopt;
return Stride == 1 ? CM_Widen : CM_Widen_Reverse;
@@ -2778,6 +2788,7 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) {
return true;
return (WideningDecision == CM_Widen ||
+ WideningDecision == CM_Widen_Bounded ||
WideningDecision == CM_Widen_Reverse ||
WideningDecision == CM_Interleave);
};
@@ -4294,7 +4305,8 @@ LoopVectorizationCostModel::getMemInstScalarizationCost(Instruction *I,
InstructionCost LoopVectorizationCostModel::getConsecutiveMemOpCost(
Instruction *I, ElementCount VF, InstWidening Kind) {
- assert((Kind == CM_Widen || Kind == CM_Widen_Reverse) &&
+ assert((Kind == CM_Widen || Kind == CM_Widen_Reverse ||
+ Kind == CM_Widen_Bounded) &&
"Expected a consecutive widening decision");
Type *ValTy = getLoadStoreType(I);
auto *VectorTy = cast<VectorType>(toVectorTy(ValTy, VF));
@@ -4866,7 +4878,8 @@ void LoopVectorizationCostModel::setCostBasedWideningDecision(ElementCount VF) {
// instead changed here when we know this is the case.
InstWidening Decision = getWideningDecision(I, VF);
if (!isPredicatedInst(I) &&
- (Decision == CM_Widen || Decision == CM_Widen_Reverse ||
+ (Decision == CM_Widen || Decision == CM_Widen_Bounded ||
+ Decision == CM_Widen_Reverse ||
(!isUniformMemOp(*I, VF) && Decision == CM_Scalarize))) {
// Scalarize a widened load of address or update the cost of a scalar
// load of an address.
@@ -5277,6 +5290,7 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I,
return TTI::CastContextHint::Interleave;
case LoopVectorizationCostModel::CM_Scalarize:
case LoopVectorizationCostModel::CM_Widen:
+ case LoopVectorizationCostModel::CM_Widen_Bounded:
return isPredicatedInst(I) ? TTI::CastContextHint::Masked
: TTI::CastContextHint::Normal;
case LoopVectorizationCostModel::CM_Widen_Reverse:
@@ -6207,6 +6221,8 @@ VPRecipeBase *VPRecipeBuilder::tryToWidenMemory(VPInstruction *VPI,
// reverse consecutive.
LoopVectorizationCostModel::InstWidening Decision =
CM.getWideningDecision(I, Range.Start);
+ assert(Decision != LoopVectorizationCostModel::CM_Widen_Bounded &&
+ "bounded loads must be widened in makeMemOpWideningDecisions");
bool Reverse = Decision == LoopVectorizationCostModel::CM_Widen_Reverse;
bool Consecutive =
Reverse || Decision == LoopVectorizationCostModel::CM_Widen;
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index e5035c4e7767f..a956a283c32b0 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -5345,6 +5345,35 @@ void VPlanTransforms::createPartialReductions(VPlan &Plan,
transformToPartialReduction(Chain, Plan, Phi);
}
+/// Check if \p VPI is a bounded (i % 2^N) load we can widen. This requires the
+/// vector factor to divide the bound, so that each VF-wide load stays within a
+/// single 2^N window.
+static bool canCreateBoundedLoad(VPInstruction *VPI, VFRange &Range,
+ VPCostContext &Ctx) {
+ if (VPI->getOpcode() != Instruction::Load)
+ return false;
+
+ Type *ScalarTy = VPI->getScalarType();
+ if (hasIrregularType(ScalarTy, Ctx.L->getHeader()->getDataLayout()))
+ return false;
+
+ const SCEV *PtrSCEV =
+ vputils::getSCEVExprForVPValue(VPI->getOperand(0), Ctx.PSE, Ctx.L);
+ std::optional<uint64_t> Bound =
+ getBoundedAccessBound(PtrSCEV, ScalarTy, Ctx.L, *Ctx.PSE.getSE());
+ if (!Bound)
+ return false;
+
+ // Only widen for VFs that divide the bound, so each VF-wide load stays within
+ // a single window and does not wrap.
+ auto DividesBound = [&](ElementCount VF) {
+ return VF.isFixed() && VF.getFixedValue() <= *Bound &&
+ *Bound % VF.getFixedValue() == 0;
+ };
+ return LoopVectorizationPlanner::getDecisionAndClampRange(DividesBound,
+ Range);
+}
+
void VPlanTransforms::makeMemOpWideningDecisions(VPlan &Plan, VFRange &Range,
VPRecipeBuilder &RecipeBuilder,
VPCostContext &CostCtx) {
@@ -5366,6 +5395,9 @@ void VPlanTransforms::makeMemOpWideningDecisions(VPlan &Plan, VFRange &Range,
// Few helpers to process different kinds of memory operations.
+ bool LoopHasStore = any_of(
+ MemOps, [](VPInstruction *VPI) { return VPI->mayWriteToMemory(); });
+
// To be used as argument to `VPlanTransforms::runPass` which explicitly
// specified pass name, hence `VPlan &` parameter.
auto ProcessSubset = [&](VPlan &, auto ProcessVPInst) {
@@ -5464,6 +5496,15 @@ void VPlanTransforms::makeMemOpWideningDecisions(VPlan &Plan, VFRange &Range,
"widenConsecutiveMemOps", ProcessSubset, Plan, [&](VPInstruction *VPI) {
Instruction *I = VPI->getUnderlyingInstr();
bool IsLoad = VPI->getOpcode() == Instruction::Load;
+ if (IsLoad && !LoopHasStore &&
+ canCreateBoundedLoad(VPI, Range, CostCtx)) {
+ auto *Load = cast<LoadInst>(VPI->getUnderlyingInstr());
+ VPSingleDefRecipe *LoadR = VPBuilder(VPI).createWidenLoad(
+ *Load, VPI->getOperand(0), /*Mask=*/nullptr,
+ /*Consecutive=*/true, *VPI, Load->getDebugLoc());
+ return ReplaceWith(VPI, LoadR);
+ }
+
VPValue *Ptr = VPI->getOperand(!IsLoad);
Type *ScalarTy =
IsLoad ? VPI->getScalarType() : VPI->getOperand(0)->getScalarType();
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll b/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
index 2e0f55236f65b..557ccdb1f465d 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
@@ -6,98 +6,64 @@ target triple = "arm64-apple-macosx"
define i32 @bounded_load_reduction_bound2(ptr %A, i32 %N) {
; CHECK-LABEL: define i32 @bounded_load_reduction_bound2(
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
-; CHECK-NEXT: [[ITER_CHECK:.*]]:
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i1
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i32 [[TMP0]], 1
-; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: br i1 [[TMP3]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
-; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
-; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 16
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 8
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 16
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 8
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP4:%.*]] = urem i32 [[INDEX]], 2
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 -3
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 -7
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 -11
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 -15
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4
-; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4
-; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP8]], align 4
-; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i32>, ptr [[TMP9]], align 4
-; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[REVERSE8:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD5]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[REVERSE9:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD6]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[REVERSE10:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD7]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[TMP10]] = add <4 x i32> [[VEC_PHI]], [[REVERSE]]
-; CHECK-NEXT: [[TMP11]] = add <4 x i32> [[VEC_PHI2]], [[REVERSE8]]
-; CHECK-NEXT: [[TMP12]] = add <4 x i32> [[VEC_PHI3]], [[REVERSE9]]
-; CHECK-NEXT: [[TMP13]] = add <4 x i32> [[VEC_PHI4]], [[REVERSE10]]
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
-; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[INDEX]], 2
+; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[INDEX]], 6
+; CHECK-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 2
+; CHECK-NEXT: [[TMP4:%.*]] = urem i32 [[TMP7]], 2
+; CHECK-NEXT: [[TMP5:%.*]] = urem i32 [[TMP11]], 2
+; CHECK-NEXT: [[TMP6:%.*]] = urem i32 [[TMP15]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP4]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP6]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4
+; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <2 x i32>, ptr [[TMP8]], align 4
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x i32>, ptr [[TMP9]], align 4
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i32>, ptr [[TMP10]], align 4
+; CHECK-NEXT: [[TMP2]] = add <2 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP12]] = add <2 x i32> [[VEC_PHI1]], [[WIDE_LOAD4]]
+; CHECK-NEXT: [[TMP13]] = add <2 x i32> [[VEC_PHI2]], [[WIDE_LOAD5]]
+; CHECK-NEXT: [[TMP14]] = add <2 x i32> [[VEC_PHI3]], [[WIDE_LOAD6]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP11]], [[TMP10]]
-; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP12]], [[BIN_RDX]]
-; CHECK-NEXT: [[BIN_RDX12:%.*]] = add <4 x i32> [[TMP13]], [[BIN_RDX11]]
-; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX12]])
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[TMP12]], [[TMP2]]
+; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <2 x i32> [[TMP13]], [[BIN_RDX]]
+; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <2 x i32> [[TMP14]], [[BIN_RDX7]]
+; CHECK-NEXT: [[TMP16:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX8]])
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
-; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
-; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF]], 4
-; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
-; CHECK: [[VEC_EPILOG_PH]]:
-; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP15]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
-; CHECK-NEXT: [[N_MOD_VF13:%.*]] = urem i32 [[N]], 4
-; CHECK-NEXT: [[N_VEC14:%.*]] = sub i32 [[N]], [[N_MOD_VF13]]
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i32> zeroinitializer, i32 [[BC_MERGE_RDX]], i32 0
-; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]
-; CHECK: [[VEC_EPILOG_VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX15:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT19:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI16:%.*]] = phi <4 x i32> [ [[TMP16]], %[[VEC_EPILOG_PH]] ], [ [[TMP20:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP17:%.*]] = urem i32 [[INDEX15]], 2
-; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP17]]
-; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i64 -3
-; CHECK-NEXT: [[WIDE_LOAD17:%.*]] = load <4 x i32>, ptr [[TMP19]], align 4
-; CHECK-NEXT: [[REVERSE18:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD17]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[TMP20]] = add <4 x i32> [[VEC_PHI16]], [[REVERSE18]]
-; CHECK-NEXT: [[INDEX_NEXT19]] = add nuw i32 [[INDEX15]], 4
-; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[INDEX_NEXT19]], [[N_VEC14]]
-; CHECK-NEXT: br i1 [[TMP21]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
-; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[TMP22:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP20]])
-; CHECK-NEXT: [[CMP_N20:%.*]] = icmp eq i32 [[N]], [[N_VEC14]]
-; CHECK-NEXT: br i1 [[CMP_N20]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
-; CHECK: [[VEC_EPILOG_SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC14]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX21:%.*]] = phi i32 [ [[TMP22]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP15]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP16]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX21]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 2
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[GEP]], align 4
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP15]], %[[MIDDLE_BLOCK]] ], [ [[TMP22]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP16]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i32 [[R]]
;
entry:
@@ -124,11 +90,7 @@ define i32 @bounded_load_reduction_bound4(ptr %A, i32 %N) {
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ITER_CHECK:.*]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
@@ -142,11 +104,17 @@ define i32 @bounded_load_reduction_bound4(ptr %A, i32 %N) {
; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; CHECK-NEXT: [[TMP19:%.*]] = add i32 [[INDEX]], 12
; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP20:%.*]] = urem i32 [[TMP0]], 4
+; CHECK-NEXT: [[TMP21:%.*]] = urem i32 [[TMP1]], 4
+; CHECK-NEXT: [[TMP22:%.*]] = urem i32 [[TMP19]], 4
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 4
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 8
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 12
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP20]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP21]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP22]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4
; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4
; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4
@@ -157,7 +125,7 @@ define i32 @bounded_load_reduction_bound4(ptr %A, i32 %N) {
; CHECK-NEXT: [[TMP10]] = add <4 x i32> [[VEC_PHI4]], [[WIDE_LOAD7]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP8]], [[TMP7]]
; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[TMP9]], [[BIN_RDX]]
@@ -167,7 +135,7 @@ define i32 @bounded_load_reduction_bound4(ptr %A, i32 %N) {
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF]], 4
-; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3]]
+; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF5:![0-9]+]]
; CHECK: [[VEC_EPILOG_PH]]:
; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP12]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
@@ -184,14 +152,14 @@ define i32 @bounded_load_reduction_bound4(ptr %A, i32 %N) {
; CHECK-NEXT: [[TMP16]] = add <4 x i32> [[VEC_PHI13]], [[WIDE_LOAD14]]
; CHECK-NEXT: [[INDEX_NEXT15]] = add nuw i32 [[INDEX12]], 4
; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT15]], [[N_VEC11]]
-; CHECK-NEXT: br i1 [[TMP17]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP17]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:
; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP16]])
; CHECK-NEXT: [[CMP_N16:%.*]] = icmp eq i32 [[N]], [[N_VEC11]]
; CHECK-NEXT: br i1 [[CMP_N16]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
; CHECK: [[VEC_EPILOG_SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC11]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX17:%.*]] = phi i32 [ [[TMP18]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP12]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC11]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX17:%.*]] = phi i32 [ [[TMP18]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP12]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
@@ -202,7 +170,7 @@ define i32 @bounded_load_reduction_bound4(ptr %A, i32 %N) {
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP12]], %[[MIDDLE_BLOCK]] ], [ [[TMP18]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i32 [[R]]
@@ -231,11 +199,7 @@ define i16 @bounded_load_reduction_bound4_i16(ptr %A, i32 %N) {
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ITER_CHECK:.*]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
@@ -245,29 +209,45 @@ define i16 @bounded_load_reduction_bound4_i16(ptr %A, i32 %N) {
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <8 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <8 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i16> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[INDEX]], 12
; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP4:%.*]] = urem i32 [[TMP0]], 4
+; CHECK-NEXT: [[TMP5:%.*]] = urem i32 [[TMP1]], 4
+; CHECK-NEXT: [[TMP6:%.*]] = urem i32 [[TMP20]], 4
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 8
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[TMP3]], align 2
-; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i16>, ptr [[TMP4]], align 2
-; CHECK-NEXT: [[TMP5]] = add <8 x i16> [[VEC_PHI]], [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP6]] = add <8 x i16> [[VEC_PHI2]], [[WIDE_LOAD3]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP4]]
+; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[TMP6]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[TMP3]], align 2
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i16>, ptr [[TMP8]], align 2
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i16>, ptr [[TMP21]], align 2
+; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i16>, ptr [[TMP22]], align 2
+; CHECK-NEXT: [[TMP15]] = add <4 x i16> [[VEC_PHI]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP17]] = add <4 x i16> [[VEC_PHI2]], [[WIDE_LOAD5]]
+; CHECK-NEXT: [[TMP18]] = add <4 x i16> [[VEC_PHI3]], [[WIDE_LOAD6]]
+; CHECK-NEXT: [[TMP19]] = add <4 x i16> [[VEC_PHI4]], [[WIDE_LOAD7]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <8 x i16> [[TMP6]], [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[BIN_RDX]])
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i16> [[TMP17]], [[TMP15]]
+; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i16> [[TMP18]], [[BIN_RDX]]
+; CHECK-NEXT: [[BIN_RDX9:%.*]] = add <4 x i16> [[TMP19]], [[BIN_RDX8]]
+; CHECK-NEXT: [[TMP16:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[BIN_RDX9]])
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF]], 4
-; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3]]
+; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF5]]
; CHECK: [[VEC_EPILOG_PH]]:
; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP8]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP16]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
; CHECK-NEXT: [[N_MOD_VF4:%.*]] = urem i32 [[N]], 4
; CHECK-NEXT: [[N_VEC5:%.*]] = sub i32 [[N]], [[N_MOD_VF4]]
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i16> zeroinitializer, i16 [[BC_MERGE_RDX]], i32 0
@@ -281,27 +261,27 @@ define i16 @bounded_load_reduction_bound4_i16(ptr %A, i32 %N) {
; CHECK-NEXT: [[TMP12]] = add <4 x i16> [[VEC_PHI7]], [[WIDE_LOAD8]]
; CHECK-NEXT: [[INDEX_NEXT9]] = add nuw i32 [[INDEX6]], 4
; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT9]], [[N_VEC5]]
-; CHECK-NEXT: br i1 [[TMP13]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP13]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:
; CHECK-NEXT: [[TMP14:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[TMP12]])
; CHECK-NEXT: [[CMP_N10:%.*]] = icmp eq i32 [[N]], [[N_VEC5]]
; CHECK-NEXT: br i1 [[CMP_N10]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
; CHECK: [[VEC_EPILOG_SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC5]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX11:%.*]] = phi i16 [ [[TMP14]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP8]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC5]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX17:%.*]] = phi i16 [ [[TMP14]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP16]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i16 [ [[BC_MERGE_RDX11]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i16 [ [[BC_MERGE_RDX17]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 [[BOUNDED]]
; CHECK-NEXT: [[LV:%.*]] = load i16, ptr [[GEP]], align 2
; CHECK-NEXT: [[SUM_NEXT]] = add i16 [[SUM]], [[LV]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[R:%.*]] = phi i16 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP8]], %[[MIDDLE_BLOCK]] ], [ [[TMP14]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[R:%.*]] = phi i16 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP16]], %[[MIDDLE_BLOCK]] ], [ [[TMP14]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i16 [[R]]
;
entry:
@@ -329,11 +309,7 @@ define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 32
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 32
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -348,15 +324,29 @@ define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; CHECK-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[INDEX]], 12
+; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[INDEX]], 16
+; CHECK-NEXT: [[TMP23:%.*]] = add i32 [[INDEX]], 20
+; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[INDEX]], 24
+; CHECK-NEXT: [[TMP25:%.*]] = add i32 [[INDEX]], 28
; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP26:%.*]] = urem i32 [[TMP0]], 4
+; CHECK-NEXT: [[TMP27:%.*]] = urem i32 [[TMP1]], 4
+; CHECK-NEXT: [[TMP28:%.*]] = urem i32 [[TMP21]], 4
+; CHECK-NEXT: [[TMP29:%.*]] = urem i32 [[TMP22]], 4
+; CHECK-NEXT: [[TMP30:%.*]] = urem i32 [[TMP23]], 4
+; CHECK-NEXT: [[TMP31:%.*]] = urem i32 [[TMP24]], 4
+; CHECK-NEXT: [[TMP32:%.*]] = urem i32 [[TMP25]], 4
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 4
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 8
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 12
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 16
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 20
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 24
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 28
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP26]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP27]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP28]]
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP29]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP30]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP31]]
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP32]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4
; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4
; CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4
@@ -375,7 +365,7 @@ define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; CHECK-NEXT: [[TMP18]] = add <4 x i32> [[VEC_PHI7]], [[WIDE_LOAD14]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 32
; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP12]], [[TMP11]]
; CHECK-NEXT: [[BIN_RDX15:%.*]] = add <4 x i32> [[TMP13]], [[BIN_RDX]]
@@ -388,8 +378,8 @@ define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP20]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP20]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
@@ -400,7 +390,7 @@ define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP20]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i32 [[SUM_NEXT_LCSSA]]
@@ -464,7 +454,7 @@ define i32 @scalable_vf_rejected(ptr %A, i64 %N) #0 {
; CHECK-NEXT: [[TMP16]] = add <vscale x 4 x i32> [[VEC_PHI3]], [[WIDE_LOAD6]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]]
; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[BIN_RDX:%.*]] = add <vscale x 4 x i32> [[TMP14]], [[TMP13]]
; CHECK-NEXT: [[BIN_RDX7:%.*]] = add <vscale x 4 x i32> [[TMP15]], [[BIN_RDX]]
@@ -485,7 +475,7 @@ define i32 @scalable_vf_rejected(ptr %A, i64 %N) #0 {
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP15:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP18]], %[[MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i32 [[R]]
@@ -526,11 +516,8 @@ define i32 @reverse_load_with_bounded(ptr %A, ptr %B, i32 %N) {
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 3
; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 1, [[N]]
-; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: br i1 [[TMP3]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; CHECK-NEXT: br i1 [[TMP2]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK2:%.*]] = icmp ult i32 [[N]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK2]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
@@ -544,11 +531,17 @@ define i32 @reverse_load_with_bounded(ptr %A, ptr %B, i32 %N) {
; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP35:%.*]] = add i32 [[INDEX]], 8
+; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[INDEX]], 12
; CHECK-NEXT: [[TMP4:%.*]] = urem i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP36:%.*]] = urem i32 [[TMP1]], 4
+; CHECK-NEXT: [[TMP37:%.*]] = urem i32 [[TMP35]], 4
+; CHECK-NEXT: [[TMP38:%.*]] = urem i32 [[TMP3]], 4
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 4
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 8
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i64 12
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP36]]
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP37]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP38]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4
; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4
; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4
@@ -577,7 +570,7 @@ define i32 @reverse_load_with_bounded(ptr %A, ptr %B, i32 %N) {
; CHECK-NEXT: [[TMP22]] = add <4 x i32> [[VEC_PHI5]], [[TMP18]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP20]], [[TMP19]]
; CHECK-NEXT: [[BIN_RDX16:%.*]] = add <4 x i32> [[TMP21]], [[BIN_RDX]]
@@ -587,7 +580,7 @@ define i32 @reverse_load_with_bounded(ptr %A, ptr %B, i32 %N) {
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[N_MOD_VF]], 4
-; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3]]
+; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF5]]
; CHECK: [[VEC_EPILOG_PH]]:
; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP24]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
@@ -610,18 +603,18 @@ define i32 @reverse_load_with_bounded(ptr %A, ptr %B, i32 %N) {
; CHECK-NEXT: [[TMP32]] = add <4 x i32> [[VEC_PHI21]], [[TMP31]]
; CHECK-NEXT: [[INDEX_NEXT25]] = add nuw i32 [[INDEX20]], 4
; CHECK-NEXT: [[TMP33:%.*]] = icmp eq i32 [[INDEX_NEXT25]], [[N_VEC19]]
-; CHECK-NEXT: br i1 [[TMP33]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP33]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:
; CHECK-NEXT: [[TMP34:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP32]])
; CHECK-NEXT: [[CMP_N26:%.*]] = icmp eq i32 [[N]], [[N_VEC19]]
; CHECK-NEXT: br i1 [[CMP_N26]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
; CHECK: [[VEC_EPILOG_SCALAR_PH]]:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC19]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX27:%.*]] = phi i32 [ [[TMP34]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP24]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX26:%.*]] = phi i32 [ [[TMP34]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP24]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[ITER_CHECK]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX27]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[BC_MERGE_RDX26]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
; CHECK-NEXT: [[LV1:%.*]] = load i32, ptr [[GEP1]], align 4
@@ -632,7 +625,7 @@ define i32 @reverse_load_with_bounded(ptr %A, ptr %B, i32 %N) {
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[ADD]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP18:![0-9]+]]
+; CHECK-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP17:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ], [ [[TMP24]], %[[MIDDLE_BLOCK]] ], [ [[TMP34]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ]
; CHECK-NEXT: ret i32 [[R]]
diff --git a/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll b/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll
index 0c1f159ac6129..9c83cc110e555 100644
--- a/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll
+++ b/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll
@@ -13,11 +13,7 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 127
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -80,8 +76,8 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP31]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP31]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -108,11 +104,7 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC4-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; IC4-NEXT: [[ENTRY:.*]]:
; IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 16
-; IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; IC4: [[VECTOR_SCEVCHECK]]:
-; IC4-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; IC4-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 127
-; IC4-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC4: [[VECTOR_PH]]:
; IC4-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 16
; IC4-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -319,8 +311,8 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC4-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC4: [[SCALAR_PH]]:
-; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP115]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP115]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC4-NEXT: br label %[[LOOP:.*]]
; IC4: [[LOOP]]:
; IC4-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -347,11 +339,7 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC8-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; IC8-NEXT: [[ENTRY:.*]]:
; IC8-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 32
-; IC8-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; IC8: [[VECTOR_SCEVCHECK]]:
-; IC8-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; IC8-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 127
-; IC8-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; IC8-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC8: [[VECTOR_PH]]:
; IC8-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 32
; IC8-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -750,8 +738,8 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC8-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; IC8-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC8: [[SCALAR_PH]]:
-; IC8-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; IC8-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP227]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; IC8-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC8-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP227]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC8-NEXT: br label %[[LOOP:.*]]
; IC8: [[LOOP]]:
; IC8-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -814,11 +802,7 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 15
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -881,8 +865,8 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP31]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP31]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -909,11 +893,7 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC4-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; IC4-NEXT: [[ENTRY:.*]]:
; IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 16
-; IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; IC4: [[VECTOR_SCEVCHECK]]:
-; IC4-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; IC4-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 15
-; IC4-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC4: [[VECTOR_PH]]:
; IC4-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 16
; IC4-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -1120,8 +1100,8 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC4-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC4: [[SCALAR_PH]]:
-; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP115]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP115]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC4-NEXT: br label %[[LOOP:.*]]
; IC4: [[LOOP]]:
; IC4-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -1148,11 +1128,7 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC8-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; IC8-NEXT: [[ENTRY:.*]]:
; IC8-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 32
-; IC8-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; IC8: [[VECTOR_SCEVCHECK]]:
-; IC8-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; IC8-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 15
-; IC8-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; IC8-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC8: [[VECTOR_PH]]:
; IC8-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 32
; IC8-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -1551,8 +1527,8 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC8-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; IC8-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC8: [[SCALAR_PH]]:
-; IC8-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; IC8-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP227]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; IC8-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC8-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP227]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC8-NEXT: br label %[[LOOP:.*]]
; IC8: [[LOOP]]:
; IC8-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
@@ -1605,21 +1581,21 @@ exit:
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
-; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
;.
; IC4: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; IC4: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
; IC4: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; IC4: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+; IC4: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
; IC4: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
-; IC4: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; IC4: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
;.
; IC8: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; IC8: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
; IC8: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; IC8: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+; IC8: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
; IC8: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
-; IC8: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; IC8: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
;.
diff --git a/llvm/test/Transforms/LoopVectorize/bounded-load-user-ic.ll b/llvm/test/Transforms/LoopVectorize/bounded-load-user-ic.ll
index 280613d6b04ec..9e380d5fb65f3 100644
--- a/llvm/test/Transforms/LoopVectorize/bounded-load-user-ic.ll
+++ b/llvm/test/Transforms/LoopVectorize/bounded-load-user-ic.ll
@@ -2,16 +2,17 @@
; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=4 -S %s | FileCheck %s --check-prefix=IC4
; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=3 -S %s | FileCheck %s --check-prefix=IC3
+; A user-forced interleave count is honored in full for bounded (i % 2^N) loads,
+; even when VF * IC exceeds the window (here VF=4, IC=4, window=8 => VF*IC=16).
+; This is safe without a cap: each unrolled part re-derives its address as
+; A[(i + Part * VF) % 8], which is a multiple of VF in [0, 8), so no part ever
+; reads past the window regardless of the interleave count.
define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; IC4-LABEL: define i32 @bounded_user_ic_exceeds_window(
; IC4-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; IC4-NEXT: [[ENTRY:.*]]:
; IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 16
-; IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; IC4: [[VECTOR_SCEVCHECK]]:
-; IC4-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; IC4-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 7
-; IC4-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC4: [[VECTOR_PH]]:
; IC4-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 16
; IC4-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -22,11 +23,17 @@ define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
; IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
; IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; IC4-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; IC4-NEXT: [[TMP13:%.*]] = add i32 [[INDEX]], 12
; IC4-NEXT: [[TMP2:%.*]] = urem i32 [[INDEX]], 8
+; IC4-NEXT: [[TMP14:%.*]] = urem i32 [[TMP0]], 8
+; IC4-NEXT: [[TMP15:%.*]] = urem i32 [[TMP1]], 8
+; IC4-NEXT: [[TMP16:%.*]] = urem i32 [[TMP13]], 8
; IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP2]]
-; IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 4
-; IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 8
-; IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 12
+; IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP14]]
+; IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP15]]
+; IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP16]]
; IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4
; IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4
; IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4
@@ -46,8 +53,8 @@ define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; IC4-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC4: [[SCALAR_PH]]:
-; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP12]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP12]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC4-NEXT: br label %[[LOOP:.*]]
; IC4: [[LOOP]]:
; IC4-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
@@ -67,11 +74,7 @@ define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; IC3-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; IC3-NEXT: [[ENTRY:.*]]:
; IC3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 12
-; IC3-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; IC3: [[VECTOR_SCEVCHECK]]:
-; IC3-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; IC3-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 7
-; IC3-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; IC3-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC3: [[VECTOR_PH]]:
; IC3-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 12
; IC3-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -81,10 +84,14 @@ define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; IC3-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
; IC3-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
; IC3-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
+; IC3-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; IC3-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
; IC3-NEXT: [[TMP2:%.*]] = urem i32 [[INDEX]], 8
+; IC3-NEXT: [[TMP11:%.*]] = urem i32 [[TMP0]], 8
+; IC3-NEXT: [[TMP12:%.*]] = urem i32 [[TMP1]], 8
; IC3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP2]]
-; IC3-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 4
-; IC3-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 8
+; IC3-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP11]]
+; IC3-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP12]]
; IC3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4
; IC3-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4
; IC3-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4
@@ -101,8 +108,8 @@ define i32 @bounded_user_ic_exceeds_window(ptr %A, i32 %N) {
; IC3-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; IC3-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC3: [[SCALAR_PH]]:
-; IC3-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; IC3-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; IC3-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC3-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC3-NEXT: br label %[[LOOP:.*]]
; IC3: [[LOOP]]:
; IC3-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/bounded-load-vf-ranges.ll b/llvm/test/Transforms/LoopVectorize/bounded-load-vf-ranges.ll
index adeed75278ba6..d8e0998a1c4d4 100644
--- a/llvm/test/Transforms/LoopVectorize/bounded-load-vf-ranges.ll
+++ b/llvm/test/Transforms/LoopVectorize/bounded-load-vf-ranges.ll
@@ -6,57 +6,101 @@
define i32 @bounded_load_reduction_bound4(ptr %A) {
; VF2-LABEL: define i32 @bounded_load_reduction_bound4(
; VF2-SAME: ptr [[A:%.*]]) {
-; VF2-NEXT: [[ENTRY:.*]]:
-; VF2-NEXT: br label %[[LOOP:.*]]
-; VF2: [[LOOP]]:
-; VF2-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
-; VF2-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF2-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF2-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF2-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF2-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF2-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF2-NEXT: [[ENTRY:.*:]]
+; VF2-NEXT: br label %[[VECTOR_PH:.*]]
+; VF2: [[VECTOR_PH]]:
+; VF2-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF2: [[VECTOR_BODY]]:
+; VF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 4
+; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4
+; VF2-NEXT: [[TMP2]] = add <2 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
+; VF2-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF2-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF2: [[MIDDLE_BLOCK]]:
+; VF2-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP2]])
+; VF2-NEXT: br label %[[EXIT:.*]]
; VF2: [[EXIT]]:
-; VF2-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF2-NEXT: ret i32 [[R]]
+; VF2-NEXT: ret i32 [[TMP4]]
;
; VF4-LABEL: define i32 @bounded_load_reduction_bound4(
; VF4-SAME: ptr [[A:%.*]]) {
-; VF4-NEXT: [[ENTRY:.*]]:
-; VF4-NEXT: br label %[[LOOP:.*]]
-; VF4: [[LOOP]]:
-; VF4-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
-; VF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF4-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF4-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF4-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF4-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF4-NEXT: [[ENTRY:.*:]]
+; VF4-NEXT: br label %[[VECTOR_PH:.*]]
+; VF4: [[VECTOR_PH]]:
+; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF4: [[VECTOR_BODY]]:
+; VF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 4
+; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
+; VF4-NEXT: [[TMP2]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; VF4-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF4-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF4: [[MIDDLE_BLOCK]]:
+; VF4-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
+; VF4-NEXT: br label %[[EXIT:.*]]
; VF4: [[EXIT]]:
-; VF4-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF4-NEXT: ret i32 [[R]]
+; VF4-NEXT: ret i32 [[TMP4]]
;
; VF8-LABEL: define i32 @bounded_load_reduction_bound4(
; VF8-SAME: ptr [[A:%.*]]) {
-; VF8-NEXT: [[ENTRY:.*]]:
-; VF8-NEXT: br label %[[LOOP:.*]]
-; VF8: [[LOOP]]:
-; VF8-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 4
-; VF8-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF8-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF8-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF8-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF8-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF8-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF8-NEXT: [[ENTRY:.*:]]
+; VF8-NEXT: br label %[[VECTOR_PH:.*]]
+; VF8: [[VECTOR_PH]]:
+; VF8-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF8: [[VECTOR_BODY]]:
+; VF8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[VEC_IND:%.*]] = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP33:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[TMP0:%.*]] = urem <8 x i32> [[VEC_IND]], splat (i32 4)
+; VF8-NEXT: [[TMP1:%.*]] = extractelement <8 x i32> [[TMP0]], i64 0
+; VF8-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP1]]
+; VF8-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[TMP0]], i64 1
+; VF8-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP2]]
+; VF8-NEXT: [[TMP3:%.*]] = extractelement <8 x i32> [[TMP0]], i64 2
+; VF8-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP3]]
+; VF8-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP0]], i64 3
+; VF8-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP4]]
+; VF8-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP0]], i64 4
+; VF8-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP5]]
+; VF8-NEXT: [[TMP6:%.*]] = extractelement <8 x i32> [[TMP0]], i64 5
+; VF8-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP6]]
+; VF8-NEXT: [[TMP7:%.*]] = extractelement <8 x i32> [[TMP0]], i64 6
+; VF8-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP7]]
+; VF8-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP0]], i64 7
+; VF8-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP8]]
+; VF8-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP9]], align 4
+; VF8-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP10]], align 4
+; VF8-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP11]], align 4
+; VF8-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP12]], align 4
+; VF8-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP13]], align 4
+; VF8-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP14]], align 4
+; VF8-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP15]], align 4
+; VF8-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP16]], align 4
+; VF8-NEXT: [[TMP25:%.*]] = insertelement <8 x i32> poison, i32 [[TMP17]], i32 0
+; VF8-NEXT: [[TMP26:%.*]] = insertelement <8 x i32> [[TMP25]], i32 [[TMP18]], i32 1
+; VF8-NEXT: [[TMP27:%.*]] = insertelement <8 x i32> [[TMP26]], i32 [[TMP19]], i32 2
+; VF8-NEXT: [[TMP28:%.*]] = insertelement <8 x i32> [[TMP27]], i32 [[TMP20]], i32 3
+; VF8-NEXT: [[TMP29:%.*]] = insertelement <8 x i32> [[TMP28]], i32 [[TMP21]], i32 4
+; VF8-NEXT: [[TMP30:%.*]] = insertelement <8 x i32> [[TMP29]], i32 [[TMP22]], i32 5
+; VF8-NEXT: [[TMP31:%.*]] = insertelement <8 x i32> [[TMP30]], i32 [[TMP23]], i32 6
+; VF8-NEXT: [[TMP32:%.*]] = insertelement <8 x i32> [[TMP31]], i32 [[TMP24]], i32 7
+; VF8-NEXT: [[TMP33]] = add <8 x i32> [[VEC_PHI]], [[TMP32]]
+; VF8-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; VF8-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <8 x i32> [[VEC_IND]], splat (i32 8)
+; VF8-NEXT: [[TMP34:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF8-NEXT: br i1 [[TMP34]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF8: [[MIDDLE_BLOCK]]:
+; VF8-NEXT: [[TMP35:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP33]])
+; VF8-NEXT: br label %[[EXIT:.*]]
; VF8: [[EXIT]]:
-; VF8-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF8-NEXT: ret i32 [[R]]
+; VF8-NEXT: ret i32 [[TMP35]]
;
entry:
br label %loop
@@ -80,57 +124,69 @@ exit:
define i32 @bounded_load_reduction_bound8(ptr %A) {
; VF2-LABEL: define i32 @bounded_load_reduction_bound8(
; VF2-SAME: ptr [[A:%.*]]) {
-; VF2-NEXT: [[ENTRY:.*]]:
-; VF2-NEXT: br label %[[LOOP:.*]]
-; VF2: [[LOOP]]:
-; VF2-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF2-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF2-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF2-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF2-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF2-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF2-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF2-NEXT: [[ENTRY:.*:]]
+; VF2-NEXT: br label %[[VECTOR_PH:.*]]
+; VF2: [[VECTOR_PH]]:
+; VF2-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF2: [[VECTOR_BODY]]:
+; VF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4
+; VF2-NEXT: [[TMP2]] = add <2 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
+; VF2-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF2-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF2: [[MIDDLE_BLOCK]]:
+; VF2-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP2]])
+; VF2-NEXT: br label %[[EXIT:.*]]
; VF2: [[EXIT]]:
-; VF2-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF2-NEXT: ret i32 [[R]]
+; VF2-NEXT: ret i32 [[TMP4]]
;
; VF4-LABEL: define i32 @bounded_load_reduction_bound8(
; VF4-SAME: ptr [[A:%.*]]) {
-; VF4-NEXT: [[ENTRY:.*]]:
-; VF4-NEXT: br label %[[LOOP:.*]]
-; VF4: [[LOOP]]:
-; VF4-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF4-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF4-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF4-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF4-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF4-NEXT: [[ENTRY:.*:]]
+; VF4-NEXT: br label %[[VECTOR_PH:.*]]
+; VF4: [[VECTOR_PH]]:
+; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF4: [[VECTOR_BODY]]:
+; VF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
+; VF4-NEXT: [[TMP2]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; VF4-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF4-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF4: [[MIDDLE_BLOCK]]:
+; VF4-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
+; VF4-NEXT: br label %[[EXIT:.*]]
; VF4: [[EXIT]]:
-; VF4-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF4-NEXT: ret i32 [[R]]
+; VF4-NEXT: ret i32 [[TMP4]]
;
; VF8-LABEL: define i32 @bounded_load_reduction_bound8(
; VF8-SAME: ptr [[A:%.*]]) {
-; VF8-NEXT: [[ENTRY:.*]]:
-; VF8-NEXT: br label %[[LOOP:.*]]
-; VF8: [[LOOP]]:
-; VF8-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF8-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; VF8-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; VF8-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; VF8-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF8-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF8-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF8-NEXT: [[ENTRY:.*:]]
+; VF8-NEXT: br label %[[VECTOR_PH:.*]]
+; VF8: [[VECTOR_PH]]:
+; VF8-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF8: [[VECTOR_BODY]]:
+; VF8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF8-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; VF8-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[TMP1]], align 4
+; VF8-NEXT: [[TMP2]] = add <8 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; VF8-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; VF8-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF8-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF8: [[MIDDLE_BLOCK]]:
+; VF8-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP2]])
+; VF8-NEXT: br label %[[EXIT:.*]]
; VF8: [[EXIT]]:
-; VF8-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF8-NEXT: ret i32 [[R]]
+; VF8-NEXT: ret i32 [[TMP4]]
;
entry:
br label %loop
@@ -154,60 +210,72 @@ exit:
define i32 @bounded_load_reduction_bound8_i8(ptr %A) {
; VF2-LABEL: define i32 @bounded_load_reduction_bound8_i8(
; VF2-SAME: ptr [[A:%.*]]) {
-; VF2-NEXT: [[ENTRY:.*]]:
-; VF2-NEXT: br label %[[LOOP:.*]]
-; VF2: [[LOOP]]:
-; VF2-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF2-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF2-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[BOUNDED]]
-; VF2-NEXT: [[LV:%.*]] = load i8, ptr [[GEP_A]], align 1
-; VF2-NEXT: [[EXT:%.*]] = zext i8 [[LV]] to i32
-; VF2-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[EXT]]
-; VF2-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF2-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF2-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF2-NEXT: [[ENTRY:.*:]]
+; VF2-NEXT: br label %[[VECTOR_PH:.*]]
+; VF2: [[VECTOR_PH]]:
+; VF2-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF2: [[VECTOR_BODY]]:
+; VF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; VF2-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[TMP0]]
+; VF2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP1]], align 1
+; VF2-NEXT: [[TMP2:%.*]] = zext <2 x i8> [[WIDE_LOAD]] to <2 x i32>
+; VF2-NEXT: [[TMP3]] = add <2 x i32> [[VEC_PHI]], [[TMP2]]
+; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
+; VF2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF2-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; VF2: [[MIDDLE_BLOCK]]:
+; VF2-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP3]])
+; VF2-NEXT: br label %[[EXIT:.*]]
; VF2: [[EXIT]]:
-; VF2-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF2-NEXT: ret i32 [[R]]
+; VF2-NEXT: ret i32 [[TMP5]]
;
; VF4-LABEL: define i32 @bounded_load_reduction_bound8_i8(
; VF4-SAME: ptr [[A:%.*]]) {
-; VF4-NEXT: [[ENTRY:.*]]:
-; VF4-NEXT: br label %[[LOOP:.*]]
-; VF4: [[LOOP]]:
-; VF4-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF4-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[BOUNDED]]
-; VF4-NEXT: [[LV:%.*]] = load i8, ptr [[GEP_A]], align 1
-; VF4-NEXT: [[EXT:%.*]] = zext i8 [[LV]] to i32
-; VF4-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[EXT]]
-; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF4-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF4-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF4-NEXT: [[ENTRY:.*:]]
+; VF4-NEXT: br label %[[VECTOR_PH:.*]]
+; VF4: [[VECTOR_PH]]:
+; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF4: [[VECTOR_BODY]]:
+; VF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; VF4-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[TMP0]]
+; VF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1
+; VF4-NEXT: [[TMP2:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i32>
+; VF4-NEXT: [[TMP3]] = add <4 x i32> [[VEC_PHI]], [[TMP2]]
+; VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; VF4-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF4-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; VF4: [[MIDDLE_BLOCK]]:
+; VF4-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])
+; VF4-NEXT: br label %[[EXIT:.*]]
; VF4: [[EXIT]]:
-; VF4-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF4-NEXT: ret i32 [[R]]
+; VF4-NEXT: ret i32 [[TMP5]]
;
; VF8-LABEL: define i32 @bounded_load_reduction_bound8_i8(
; VF8-SAME: ptr [[A:%.*]]) {
-; VF8-NEXT: [[ENTRY:.*]]:
-; VF8-NEXT: br label %[[LOOP:.*]]
-; VF8: [[LOOP]]:
-; VF8-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; VF8-NEXT: [[BOUNDED:%.*]] = urem i32 [[IV]], 8
-; VF8-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[BOUNDED]]
-; VF8-NEXT: [[LV:%.*]] = load i8, ptr [[GEP_A]], align 1
-; VF8-NEXT: [[EXT:%.*]] = zext i8 [[LV]] to i32
-; VF8-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[EXT]]
-; VF8-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; VF8-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; VF8-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; VF8-NEXT: [[ENTRY:.*:]]
+; VF8-NEXT: br label %[[VECTOR_PH:.*]]
+; VF8: [[VECTOR_PH]]:
+; VF8-NEXT: br label %[[VECTOR_BODY:.*]]
+; VF8: [[VECTOR_BODY]]:
+; VF8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; VF8-NEXT: [[TMP0:%.*]] = urem i32 [[INDEX]], 8
+; VF8-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[TMP0]]
+; VF8-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP1]], align 1
+; VF8-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[WIDE_LOAD]] to <8 x i32>
+; VF8-NEXT: [[TMP3]] = add <8 x i32> [[VEC_PHI]], [[TMP2]]
+; VF8-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; VF8-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; VF8-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; VF8: [[MIDDLE_BLOCK]]:
+; VF8-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP3]])
+; VF8-NEXT: br label %[[EXIT:.*]]
; VF8: [[EXIT]]:
-; VF8-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; VF8-NEXT: ret i32 [[R]]
+; VF8-NEXT: ret i32 [[TMP5]]
;
entry:
br label %loop
@@ -257,7 +325,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF2-NEXT: store <2 x i32> [[TMP5]], ptr [[TMP3]], align 4
; VF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
; VF2-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; VF2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; VF2: [[MIDDLE_BLOCK]]:
; VF2-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; VF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
@@ -275,7 +343,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF2-NEXT: store i32 [[SUM]], ptr [[GEP_A]], align 4
; VF2-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; VF2-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; VF2-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF2-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; VF2: [[EXIT]]:
; VF2-NEXT: ret void
;
@@ -303,7 +371,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF4-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP3]], align 4
; VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; VF4-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; VF4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; VF4: [[MIDDLE_BLOCK]]:
; VF4-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; VF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
@@ -321,7 +389,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF4-NEXT: store i32 [[SUM]], ptr [[GEP_A]], align 4
; VF4-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; VF4-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; VF4-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF4-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; VF4: [[EXIT]]:
; VF4-NEXT: ret void
;
@@ -349,7 +417,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF8-NEXT: store <8 x i32> [[TMP5]], ptr [[TMP3]], align 4
; VF8-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
; VF8-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; VF8-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; VF8-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; VF8: [[MIDDLE_BLOCK]]:
; VF8-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; VF8-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
@@ -367,7 +435,7 @@ define void @bounded_rmw_vf_capped(ptr noalias %A, ptr noalias %B, i32 %n) {
; VF8-NEXT: store i32 [[SUM]], ptr [[GEP_A]], align 4
; VF8-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; VF8-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; VF8-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; VF8-NEXT: br i1 [[COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
; VF8: [[EXIT]]:
; VF8-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LoopVectorize/bounded-load.ll b/llvm/test/Transforms/LoopVectorize/bounded-load.ll
index 3a4860b3bcd01..31db4c1476bb1 100644
--- a/llvm/test/Transforms/LoopVectorize/bounded-load.ll
+++ b/llvm/test/Transforms/LoopVectorize/bounded-load.ll
@@ -6,21 +6,41 @@ target datalayout = "e-m:o-p:64:64-p1:128:128-n8:16:32:64-S128"
define i24 @bounded_load_i24_alloc_size(ptr %A) {
; CHECK-LABEL: define i24 @bounded_load_i24_alloc_size(
; CHECK-SAME: ptr [[A:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: br label %[[LOOP:.*]]
-; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i24 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[BOUNDED:%.*]] = urem i64 [[IV]], 4
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i24, ptr [[A]], i64 [[BOUNDED]]
-; CHECK-NEXT: [[LV:%.*]] = load i24, ptr [[GEP]], align 4
-; CHECK-NEXT: [[SUM_NEXT]] = add i24 [[SUM]], [[LV]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IV_NEXT]], 128
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i24> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = urem <4 x i64> [[VEC_IND]], splat (i64 4)
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i64> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i24, ptr [[A]], i64 [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i24, ptr [[A]], i64 [[TMP2]]
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP0]], i64 2
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i24, ptr [[A]], i64 [[TMP3]]
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i64> [[TMP0]], i64 3
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i24, ptr [[A]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP9:%.*]] = load i24, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i24, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = load i24, ptr [[TMP7]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = load i24, ptr [[TMP8]], align 4
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i24> poison, i24 [[TMP9]], i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i24> [[TMP13]], i24 [[TMP10]], i32 1
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i24> [[TMP14]], i24 [[TMP11]], i32 2
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i24> [[TMP15]], i24 [[TMP12]], i32 3
+; CHECK-NEXT: [[TMP17]] = add <4 x i24> [[VEC_PHI]], [[TMP16]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
+; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 128
+; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP19:%.*]] = call i24 @llvm.vector.reduce.add.v4i24(<4 x i24> [[TMP17]])
+; CHECK-NEXT: br label %[[EXIT:.*]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i24 [ [[SUM_NEXT]], %[[LOOP]] ]
-; CHECK-NEXT: ret i24 [[SUM_NEXT_LCSSA]]
+; CHECK-NEXT: ret i24 [[TMP19]]
;
entry:
br label %loop
@@ -72,7 +92,7 @@ define i32 @bounded_load_non_pow2_modulus(ptr %A) {
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 4)
; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
-; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[TMP19:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP17]])
; CHECK-NEXT: br label %[[EXIT:.*]]
@@ -141,21 +161,25 @@ exit:
define i32 @bounded_load_srem_nonneg(ptr %A) {
; CHECK-LABEL: define i32 @bounded_load_srem_nonneg(
; CHECK-SAME: ptr [[A:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: br label %[[LOOP:.*]]
-; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[SUM_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[BOUNDED:%.*]] = srem i32 [[IV]], 4
-; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[BOUNDED]]
-; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_A]], align 4
-; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[LV]]
-; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
-; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], 128
-; CHECK-NEXT: br i1 [[COND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = srem i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP0]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
+; CHECK-NEXT: [[TMP2]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
+; CHECK-NEXT: br label %[[EXIT:.*]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[SUM_NEXT]], %[[LOOP]] ]
-; CHECK-NEXT: ret i32 [[R]]
+; CHECK-NEXT: ret i32 [[TMP4]]
;
entry:
br label %loop
@@ -211,7 +235,7 @@ define i32 @bounded_load_srem_maybe_negative(ptr %A, i32 %n) {
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 4)
; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], 128
-; CHECK-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[TMP20:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP18]])
; CHECK-NEXT: br label %[[EXIT:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-check-small-bounded-ranges.ll b/llvm/test/Transforms/LoopVectorize/runtime-check-small-bounded-ranges.ll
index 1eba63048137c..bca186d2b3580 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-check-small-bounded-ranges.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-check-small-bounded-ranges.ll
@@ -90,11 +90,7 @@ define i32 @bounded_load_reduction(ptr %A, i32 %N) {
; CHECK-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
-; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
@@ -114,8 +110,8 @@ define i32 @bounded_load_reduction(ptr %A, i32 %N) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
-; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
>From bc110483418363d809098f5b2aef3d81bf106cd3 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Fri, 24 Jul 2026 10:23:53 +0100
Subject: [PATCH 2/3] !fixup address comments
---
.../llvm/Analysis/LoopAccessAnalysis.h | 10 +-
.../Vectorize/LoopVectorizationLegality.h | 4 +-
llvm/lib/Analysis/LoopAccessAnalysis.cpp | 22 +-
.../Vectorize/LoopVectorizationLegality.cpp | 12 +-
.../Transforms/Vectorize/LoopVectorize.cpp | 35 +-
.../Transforms/Vectorize/VPlanTransforms.cpp | 14 +-
.../LoopVectorize/bounded-load-predicated.ll | 1188 ++---------------
7 files changed, 155 insertions(+), 1130 deletions(-)
diff --git a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
index 05a9d606e96a2..33a264a3aabc9 100644
--- a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
+++ b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
@@ -921,11 +921,11 @@ getPtrStride(PredicatedScalarEvolution &PSE, Type *AccessTy, Value *Ptr,
/// If \p PtrSCEV is a bounded access of the form `Base + ElemSize * (i % 2^N)`
/// where Base is loop invariant in \p L and ElemSize equals the allocation size
-/// of \p AccessTy, returns the bound 2^N.
-LLVM_ABI std::optional<uint64_t> getBoundedAccessBound(const SCEV *PtrSCEV,
- Type *AccessTy,
- const Loop *L,
- ScalarEvolution &SE);
+/// of \p AccessTy, returns the bound 2^N. Returns 0 if \p PtrSCEV is not such a
+/// bounded access; a valid bound is always >= 2.
+LLVM_ABI uint64_t getBoundForConsecutiveLoad(const SCEV *PtrSCEV,
+ Type *AccessTy, const Loop *L,
+ ScalarEvolution &SE);
/// Returns the distance between the pointers \p PtrA and \p PtrB iff they are
/// compatible and it is possible to calculate the distance between them. This
diff --git a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
index 4ea0c037e4489..8877ef6352925 100644
--- a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+++ b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
@@ -390,8 +390,8 @@ class LoopVectorizationLegality {
LLVM_ABI int isConsecutivePtr(Type *AccessTy, Value *Ptr) const;
/// If \p I is a bounded (i % 2^N) load in a read-only loop, returns its
- /// bound (2^N).
- LLVM_ABI std::optional<uint64_t> getBoundedLoadBound(Instruction *I) const;
+ /// bound (2^N). Returns 0 otherwise; a valid bound is always >= 2.
+ LLVM_ABI uint64_t getBoundForConsecutiveLoad(Instruction *I) const;
/// Returns true if \p V is invariant across all loop iterations according to
/// SCEV.
diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
index 1674610925784..dd996fe0e4382 100644
--- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
+++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
@@ -1708,12 +1708,10 @@ llvm::getPtrStride(PredicatedScalarEvolution &PSE, Type *AccessTy, Value *Ptr,
return Stride;
}
-std::optional<uint64_t> llvm::getBoundedAccessBound(const SCEV *PtrSCEV,
- Type *AccessTy,
- const Loop *L,
- ScalarEvolution &SE) {
+uint64_t llvm::getBoundForConsecutiveLoad(const SCEV *PtrSCEV, Type *AccessTy,
+ const Loop *L, ScalarEvolution &SE) {
if (AccessTy->isScalableTy())
- return std::nullopt;
+ return 0;
// `A[i % 2^N]` is `Base + ElemSize * zext({0,+,1}<iN>)`. For a byte
// element (ElemSize == 1) the multiply folds away.
@@ -1724,19 +1722,17 @@ std::optional<uint64_t> llvm::getBoundedAccessBound(const SCEV *PtrSCEV,
if (!match(PtrSCEV, m_scev_Add(m_scev_Mul(m_scev_APInt(Scale), Index),
m_SCEV(Base))) &&
!match(PtrSCEV, m_scev_Add(Index, m_SCEV(Base))))
- return std::nullopt;
+ return 0;
- uint64_t AllocSize = L->getHeader()
- ->getDataLayout()
- .getTypeAllocSize(AccessTy)
- .getFixedValue();
+ uint64_t AllocSize =
+ SE.getDataLayout().getTypeAllocSize(AccessTy).getFixedValue();
if (!Start->isZero() || !SE.isLoopInvariant(Base, L) ||
(Scale ? *Scale != AllocSize : AllocSize != 1))
- return std::nullopt;
+ return 0;
unsigned NarrowWidth = SE.getTypeSizeInBits(Start->getType());
- if (NarrowWidth == 0 || NarrowWidth >= 64)
- return std::nullopt;
+ if (NarrowWidth >= 64)
+ return 0;
return uint64_t(1) << NarrowWidth;
}
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
index 2fe01360c7104..2e62417811c06 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
@@ -440,7 +440,7 @@ void LoopVectorizationLegality::collectUnitStridePredicates() const {
for (Instruction &I : *BB) {
// Bounded loads use the fast path; skip to avoid the wrap predicate
// getPtrStride would register.
- if (getBoundedLoadBound(&I))
+ if (getBoundForConsecutiveLoad(&I))
continue;
if (Value *Ptr = getLoadStorePointerOperand(&I))
isConsecutivePtr(getLoadStoreType(&I), Ptr);
@@ -466,14 +466,14 @@ int LoopVectorizationLegality::isConsecutivePtr(Type *AccessTy,
return 0;
}
-std::optional<uint64_t>
-LoopVectorizationLegality::getBoundedLoadBound(Instruction *I) const {
+uint64_t
+LoopVectorizationLegality::getBoundForConsecutiveLoad(Instruction *I) const {
auto *LI = dyn_cast<LoadInst>(I);
if (!LI || LAI->getNumStores() != 0)
- return std::nullopt;
+ return 0;
Value *Ptr = LI->getPointerOperand();
- return llvm::getBoundedAccessBound(PSE.getSCEV(Ptr), LI->getType(), TheLoop,
- *PSE.getSE());
+ return llvm::getBoundForConsecutiveLoad(PSE.getSCEV(Ptr), LI->getType(),
+ TheLoop, *PSE.getSE());
}
bool LoopVectorizationLegality::isInvariant(Value *V) const {
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index f9e0e5228c85d..7d9a9cbabdf7d 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -874,8 +874,8 @@ class LoopVectorizationCostModel {
/// Decision that was taken during cost calculation for memory instruction.
enum InstWidening {
CM_Unknown,
- CM_Widen, // For consecutive accesses with stride +1.
- CM_Widen_Bounded, // For bounded (i % 2^N) loads in read-only loops.
+ CM_Widen, // For consecutive accesses with stride +1 and bounded
+ // (i % 2^N) loads in read-only loops.
CM_Widen_Reverse, // For consecutive accesses with stride -1.
CM_Interleave,
CM_GatherScatter,
@@ -1049,8 +1049,8 @@ class LoopVectorizationCostModel {
getDivRemSpeculationCost(Instruction *I, ElementCount VF);
/// If \p I is a memory instruction with a consecutive pointer that can be
- /// widened, returns the widening kind (CM_Widen, CM_Widen_Reverse,
- /// CM_Widen_Bounded) and std::nullopt otherwise.
+ /// widened, returns the widening kind (CM_Widen or CM_Widen_Reverse) and
+ /// std::nullopt otherwise.
std::optional<InstWidening> memoryInstructionCanBeWidened(Instruction *I,
ElementCount VF);
@@ -2429,7 +2429,7 @@ bool LoopVectorizationCostModel::isScalarWithPredication(Instruction *I,
case Instruction::Load:
case Instruction::Store: {
bool IsConsecutive =
- Legal->getBoundedLoadBound(I).has_value() ||
+ Legal->getBoundForConsecutiveLoad(I) != 0 ||
Legal->isConsecutivePtr(getLoadStoreType(I),
getLoadStorePointerOperand(I)) != 0;
return !(IsConsecutive && isLegalMaskedLoadOrStore(I, VF)) &&
@@ -2682,13 +2682,13 @@ LoopVectorizationCostModel::memoryInstructionCanBeWidened(Instruction *I,
return std::nullopt;
// Widen a bounded (i % 2^N) load in a read-only loop as a consecutive
- // vector load when VF divides the bound.
- if (std::optional<uint64_t> Bound = Legal->getBoundedLoadBound(I);
- Bound && VF.isFixed()) {
- if (VF.getFixedValue() <= *Bound && *Bound % VF.getFixedValue() == 0)
- return CM_Widen_Bounded;
- return std::nullopt;
- }
+ // vector load when VF divides the bound, so each VF-wide load stays within a
+ // single window and does not wrap.
+ uint64_t Bound = Legal->getBoundForConsecutiveLoad(I);
+ if (Bound != 0 && VF.isFixed())
+ return ElementCount::getFixed(Bound).isKnownMultipleOf(VF)
+ ? std::optional(CM_Widen)
+ : std::nullopt;
int Stride = Legal->isConsecutivePtr(ScalarTy, Ptr);
if (!Stride)
@@ -2788,7 +2788,6 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) {
return true;
return (WideningDecision == CM_Widen ||
- WideningDecision == CM_Widen_Bounded ||
WideningDecision == CM_Widen_Reverse ||
WideningDecision == CM_Interleave);
};
@@ -4305,8 +4304,7 @@ LoopVectorizationCostModel::getMemInstScalarizationCost(Instruction *I,
InstructionCost LoopVectorizationCostModel::getConsecutiveMemOpCost(
Instruction *I, ElementCount VF, InstWidening Kind) {
- assert((Kind == CM_Widen || Kind == CM_Widen_Reverse ||
- Kind == CM_Widen_Bounded) &&
+ assert((Kind == CM_Widen || Kind == CM_Widen_Reverse) &&
"Expected a consecutive widening decision");
Type *ValTy = getLoadStoreType(I);
auto *VectorTy = cast<VectorType>(toVectorTy(ValTy, VF));
@@ -4878,8 +4876,7 @@ void LoopVectorizationCostModel::setCostBasedWideningDecision(ElementCount VF) {
// instead changed here when we know this is the case.
InstWidening Decision = getWideningDecision(I, VF);
if (!isPredicatedInst(I) &&
- (Decision == CM_Widen || Decision == CM_Widen_Bounded ||
- Decision == CM_Widen_Reverse ||
+ (Decision == CM_Widen || Decision == CM_Widen_Reverse ||
(!isUniformMemOp(*I, VF) && Decision == CM_Scalarize))) {
// Scalarize a widened load of address or update the cost of a scalar
// load of an address.
@@ -5290,7 +5287,6 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I,
return TTI::CastContextHint::Interleave;
case LoopVectorizationCostModel::CM_Scalarize:
case LoopVectorizationCostModel::CM_Widen:
- case LoopVectorizationCostModel::CM_Widen_Bounded:
return isPredicatedInst(I) ? TTI::CastContextHint::Masked
: TTI::CastContextHint::Normal;
case LoopVectorizationCostModel::CM_Widen_Reverse:
@@ -6221,7 +6217,8 @@ VPRecipeBase *VPRecipeBuilder::tryToWidenMemory(VPInstruction *VPI,
// reverse consecutive.
LoopVectorizationCostModel::InstWidening Decision =
CM.getWideningDecision(I, Range.Start);
- assert(Decision != LoopVectorizationCostModel::CM_Widen_Bounded &&
+ assert(!(Legal->getBoundForConsecutiveLoad(I) &&
+ Decision == LoopVectorizationCostModel::CM_Widen) &&
"bounded loads must be widened in makeMemOpWideningDecisions");
bool Reverse = Decision == LoopVectorizationCostModel::CM_Widen_Reverse;
bool Consecutive =
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index a956a283c32b0..297492ef426ef 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -5359,16 +5359,15 @@ static bool canCreateBoundedLoad(VPInstruction *VPI, VFRange &Range,
const SCEV *PtrSCEV =
vputils::getSCEVExprForVPValue(VPI->getOperand(0), Ctx.PSE, Ctx.L);
- std::optional<uint64_t> Bound =
- getBoundedAccessBound(PtrSCEV, ScalarTy, Ctx.L, *Ctx.PSE.getSE());
- if (!Bound)
+ uint64_t Bound =
+ getBoundForConsecutiveLoad(PtrSCEV, ScalarTy, Ctx.L, *Ctx.PSE.getSE());
+ if (Bound == 0)
return false;
// Only widen for VFs that divide the bound, so each VF-wide load stays within
// a single window and does not wrap.
auto DividesBound = [&](ElementCount VF) {
- return VF.isFixed() && VF.getFixedValue() <= *Bound &&
- *Bound % VF.getFixedValue() == 0;
+ return ElementCount::getFixed(Bound).isKnownMultipleOf(VF);
};
return LoopVectorizationPlanner::getDecisionAndClampRange(DividesBound,
Range);
@@ -5495,11 +5494,13 @@ void VPlanTransforms::makeMemOpWideningDecisions(VPlan &Plan, VFRange &Range,
VPlanTransforms::runPass(
"widenConsecutiveMemOps", ProcessSubset, Plan, [&](VPInstruction *VPI) {
Instruction *I = VPI->getUnderlyingInstr();
+
+ VPBuilder Builder(VPI);
bool IsLoad = VPI->getOpcode() == Instruction::Load;
if (IsLoad && !LoopHasStore &&
canCreateBoundedLoad(VPI, Range, CostCtx)) {
auto *Load = cast<LoadInst>(VPI->getUnderlyingInstr());
- VPSingleDefRecipe *LoadR = VPBuilder(VPI).createWidenLoad(
+ auto *LoadR = Builder.createWidenLoad(
*Load, VPI->getOperand(0), /*Mask=*/nullptr,
/*Consecutive=*/true, *VPI, Load->getDebugLoc());
return ReplaceWith(VPI, LoadR);
@@ -5523,7 +5524,6 @@ void VPlanTransforms::makeMemOpWideningDecisions(VPlan &Plan, VFRange &Range,
getLoadStoreAddressSpace(I)))
return false;
- VPBuilder Builder(VPI);
VPSingleDefRecipe *VectorPtr = Builder.createConsecutiveVectorPointer(
Ptr, ScalarTy, Reverse, VPI->getDebugLoc());
diff --git a/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll b/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll
index 9c83cc110e555..92fe0b0567465 100644
--- a/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll
+++ b/llvm/test/Transforms/LoopVectorize/bounded-load-predicated.ll
@@ -19,52 +19,14 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]
-; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[VEC_IND]], splat (i32 1)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <4 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = urem <4 x i32> [[VEC_IND]], splat (i32 128)
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP3]], i64 0
-; CHECK-NEXT: br i1 [[TMP5]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
-; CHECK: [[PRED_LOAD_IF]]:
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i64 0
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> poison, i32 [[TMP8]], i64 0
-; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]
-; CHECK: [[PRED_LOAD_CONTINUE]]:
-; CHECK-NEXT: [[TMP10:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP9]], %[[PRED_LOAD_IF]] ]
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP3]], i64 1
-; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]
-; CHECK: [[PRED_LOAD_IF1]]:
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP4]], i64 1
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP12]]
-; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP14]], i64 1
-; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE2]]
-; CHECK: [[PRED_LOAD_CONTINUE2]]:
-; CHECK-NEXT: [[TMP16:%.*]] = phi <4 x i32> [ [[TMP10]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP15]], %[[PRED_LOAD_IF1]] ]
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i1> [[TMP3]], i64 2
-; CHECK-NEXT: br i1 [[TMP17]], label %[[PRED_LOAD_IF3:.*]], label %[[PRED_LOAD_CONTINUE4:.*]]
-; CHECK: [[PRED_LOAD_IF3]]:
-; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i32> [[TMP4]], i64 2
-; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP18]]
-; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> [[TMP16]], i32 [[TMP20]], i64 2
-; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE4]]
-; CHECK: [[PRED_LOAD_CONTINUE4]]:
-; CHECK-NEXT: [[TMP22:%.*]] = phi <4 x i32> [ [[TMP16]], %[[PRED_LOAD_CONTINUE2]] ], [ [[TMP21]], %[[PRED_LOAD_IF3]] ]
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i1> [[TMP3]], i64 3
-; CHECK-NEXT: br i1 [[TMP23]], label %[[PRED_LOAD_IF5:.*]], label %[[PRED_LOAD_CONTINUE6]]
-; CHECK: [[PRED_LOAD_IF5]]:
-; CHECK-NEXT: [[TMP24:%.*]] = extractelement <4 x i32> [[TMP4]], i64 3
+; CHECK-NEXT: [[TMP24:%.*]] = urem i32 [[INDEX]], 128
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i32> [[TMP22]], i32 [[TMP26]], i64 3
-; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE6]]
-; CHECK: [[PRED_LOAD_CONTINUE6]]:
-; CHECK-NEXT: [[TMP28:%.*]] = phi <4 x i32> [ [[TMP22]], %[[PRED_LOAD_CONTINUE4]] ], [ [[TMP27]], %[[PRED_LOAD_IF5]] ]
+; CHECK-NEXT: [[TMP28:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4
; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP28]], <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP29]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
@@ -110,15 +72,18 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC4-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; IC4-NEXT: br label %[[VECTOR_BODY:.*]]
; IC4: [[VECTOR_BODY]]:
-; IC4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33:.*]] ]
-; IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP110:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP111:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP112:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP113:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP110:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP111:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP112:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP113:%.*]], %[[VECTOR_BODY]] ]
; IC4-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i32> [[VEC_IND]], splat (i32 4)
; IC4-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i32> [[STEP_ADD]], splat (i32 4)
; IC4-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i32> [[STEP_ADD_2]], splat (i32 4)
+; IC4-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; IC4-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; IC4-NEXT: [[TMP10:%.*]] = add i32 [[INDEX]], 12
; IC4-NEXT: [[TMP2:%.*]] = and <4 x i32> [[VEC_IND]], splat (i32 1)
; IC4-NEXT: [[TMP3:%.*]] = and <4 x i32> [[STEP_ADD]], splat (i32 1)
; IC4-NEXT: [[TMP4:%.*]] = and <4 x i32> [[STEP_ADD_2]], splat (i32 1)
@@ -127,170 +92,18 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC4-NEXT: [[TMP7:%.*]] = icmp eq <4 x i32> [[TMP3]], zeroinitializer
; IC4-NEXT: [[TMP8:%.*]] = icmp eq <4 x i32> [[TMP4]], zeroinitializer
; IC4-NEXT: [[TMP9:%.*]] = icmp eq <4 x i32> [[TMP5]], zeroinitializer
-; IC4-NEXT: [[TMP10:%.*]] = urem <4 x i32> [[VEC_IND]], splat (i32 128)
-; IC4-NEXT: [[TMP11:%.*]] = urem <4 x i32> [[STEP_ADD]], splat (i32 128)
-; IC4-NEXT: [[TMP12:%.*]] = urem <4 x i32> [[STEP_ADD_2]], splat (i32 128)
-; IC4-NEXT: [[TMP13:%.*]] = urem <4 x i32> [[STEP_ADD_3]], splat (i32 128)
-; IC4-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP6]], i64 0
-; IC4-NEXT: br i1 [[TMP14]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
-; IC4: [[PRED_LOAD_IF]]:
-; IC4-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP10]], i64 0
-; IC4-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP15]]
-; IC4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
-; IC4-NEXT: [[TMP18:%.*]] = insertelement <4 x i32> poison, i32 [[TMP17]], i64 0
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE]]
-; IC4: [[PRED_LOAD_CONTINUE]]:
-; IC4-NEXT: [[TMP19:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP18]], %[[PRED_LOAD_IF]] ]
-; IC4-NEXT: [[TMP20:%.*]] = extractelement <4 x i1> [[TMP6]], i64 1
-; IC4-NEXT: br i1 [[TMP20]], label %[[PRED_LOAD_IF4:.*]], label %[[PRED_LOAD_CONTINUE5:.*]]
-; IC4: [[PRED_LOAD_IF4]]:
-; IC4-NEXT: [[TMP21:%.*]] = extractelement <4 x i32> [[TMP10]], i64 1
-; IC4-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP21]]
-; IC4-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; IC4-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> [[TMP19]], i32 [[TMP23]], i64 1
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE5]]
-; IC4: [[PRED_LOAD_CONTINUE5]]:
-; IC4-NEXT: [[TMP25:%.*]] = phi <4 x i32> [ [[TMP19]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP24]], %[[PRED_LOAD_IF4]] ]
-; IC4-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[TMP6]], i64 2
-; IC4-NEXT: br i1 [[TMP26]], label %[[PRED_LOAD_IF6:.*]], label %[[PRED_LOAD_CONTINUE7:.*]]
-; IC4: [[PRED_LOAD_IF6]]:
-; IC4-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP10]], i64 2
-; IC4-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP27]]
-; IC4-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
-; IC4-NEXT: [[TMP30:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP29]], i64 2
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE7]]
-; IC4: [[PRED_LOAD_CONTINUE7]]:
-; IC4-NEXT: [[TMP31:%.*]] = phi <4 x i32> [ [[TMP25]], %[[PRED_LOAD_CONTINUE5]] ], [ [[TMP30]], %[[PRED_LOAD_IF6]] ]
-; IC4-NEXT: [[TMP32:%.*]] = extractelement <4 x i1> [[TMP6]], i64 3
-; IC4-NEXT: br i1 [[TMP32]], label %[[PRED_LOAD_IF8:.*]], label %[[PRED_LOAD_CONTINUE9:.*]]
-; IC4: [[PRED_LOAD_IF8]]:
-; IC4-NEXT: [[TMP33:%.*]] = extractelement <4 x i32> [[TMP10]], i64 3
-; IC4-NEXT: [[TMP34:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP33]]
-; IC4-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4
-; IC4-NEXT: [[TMP36:%.*]] = insertelement <4 x i32> [[TMP31]], i32 [[TMP35]], i64 3
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE9]]
-; IC4: [[PRED_LOAD_CONTINUE9]]:
-; IC4-NEXT: [[TMP37:%.*]] = phi <4 x i32> [ [[TMP31]], %[[PRED_LOAD_CONTINUE7]] ], [ [[TMP36]], %[[PRED_LOAD_IF8]] ]
-; IC4-NEXT: [[TMP38:%.*]] = extractelement <4 x i1> [[TMP7]], i64 0
-; IC4-NEXT: br i1 [[TMP38]], label %[[PRED_LOAD_IF10:.*]], label %[[PRED_LOAD_CONTINUE11:.*]]
-; IC4: [[PRED_LOAD_IF10]]:
-; IC4-NEXT: [[TMP39:%.*]] = extractelement <4 x i32> [[TMP11]], i64 0
-; IC4-NEXT: [[TMP40:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP39]]
-; IC4-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-; IC4-NEXT: [[TMP42:%.*]] = insertelement <4 x i32> poison, i32 [[TMP41]], i64 0
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE11]]
-; IC4: [[PRED_LOAD_CONTINUE11]]:
-; IC4-NEXT: [[TMP43:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE9]] ], [ [[TMP42]], %[[PRED_LOAD_IF10]] ]
-; IC4-NEXT: [[TMP44:%.*]] = extractelement <4 x i1> [[TMP7]], i64 1
-; IC4-NEXT: br i1 [[TMP44]], label %[[PRED_LOAD_IF12:.*]], label %[[PRED_LOAD_CONTINUE13:.*]]
-; IC4: [[PRED_LOAD_IF12]]:
-; IC4-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[TMP11]], i64 1
-; IC4-NEXT: [[TMP46:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP45]]
-; IC4-NEXT: [[TMP47:%.*]] = load i32, ptr [[TMP46]], align 4
-; IC4-NEXT: [[TMP48:%.*]] = insertelement <4 x i32> [[TMP43]], i32 [[TMP47]], i64 1
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE13]]
-; IC4: [[PRED_LOAD_CONTINUE13]]:
-; IC4-NEXT: [[TMP49:%.*]] = phi <4 x i32> [ [[TMP43]], %[[PRED_LOAD_CONTINUE11]] ], [ [[TMP48]], %[[PRED_LOAD_IF12]] ]
-; IC4-NEXT: [[TMP50:%.*]] = extractelement <4 x i1> [[TMP7]], i64 2
-; IC4-NEXT: br i1 [[TMP50]], label %[[PRED_LOAD_IF14:.*]], label %[[PRED_LOAD_CONTINUE15:.*]]
-; IC4: [[PRED_LOAD_IF14]]:
-; IC4-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[TMP11]], i64 2
-; IC4-NEXT: [[TMP52:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP51]]
-; IC4-NEXT: [[TMP53:%.*]] = load i32, ptr [[TMP52]], align 4
-; IC4-NEXT: [[TMP54:%.*]] = insertelement <4 x i32> [[TMP49]], i32 [[TMP53]], i64 2
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE15]]
-; IC4: [[PRED_LOAD_CONTINUE15]]:
-; IC4-NEXT: [[TMP55:%.*]] = phi <4 x i32> [ [[TMP49]], %[[PRED_LOAD_CONTINUE13]] ], [ [[TMP54]], %[[PRED_LOAD_IF14]] ]
-; IC4-NEXT: [[TMP56:%.*]] = extractelement <4 x i1> [[TMP7]], i64 3
-; IC4-NEXT: br i1 [[TMP56]], label %[[PRED_LOAD_IF16:.*]], label %[[PRED_LOAD_CONTINUE17:.*]]
-; IC4: [[PRED_LOAD_IF16]]:
-; IC4-NEXT: [[TMP57:%.*]] = extractelement <4 x i32> [[TMP11]], i64 3
-; IC4-NEXT: [[TMP58:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP57]]
-; IC4-NEXT: [[TMP59:%.*]] = load i32, ptr [[TMP58]], align 4
-; IC4-NEXT: [[TMP60:%.*]] = insertelement <4 x i32> [[TMP55]], i32 [[TMP59]], i64 3
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE17]]
-; IC4: [[PRED_LOAD_CONTINUE17]]:
-; IC4-NEXT: [[TMP61:%.*]] = phi <4 x i32> [ [[TMP55]], %[[PRED_LOAD_CONTINUE15]] ], [ [[TMP60]], %[[PRED_LOAD_IF16]] ]
-; IC4-NEXT: [[TMP62:%.*]] = extractelement <4 x i1> [[TMP8]], i64 0
-; IC4-NEXT: br i1 [[TMP62]], label %[[PRED_LOAD_IF18:.*]], label %[[PRED_LOAD_CONTINUE19:.*]]
-; IC4: [[PRED_LOAD_IF18]]:
-; IC4-NEXT: [[TMP63:%.*]] = extractelement <4 x i32> [[TMP12]], i64 0
-; IC4-NEXT: [[TMP64:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP63]]
-; IC4-NEXT: [[TMP65:%.*]] = load i32, ptr [[TMP64]], align 4
-; IC4-NEXT: [[TMP66:%.*]] = insertelement <4 x i32> poison, i32 [[TMP65]], i64 0
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE19]]
-; IC4: [[PRED_LOAD_CONTINUE19]]:
-; IC4-NEXT: [[TMP67:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE17]] ], [ [[TMP66]], %[[PRED_LOAD_IF18]] ]
-; IC4-NEXT: [[TMP68:%.*]] = extractelement <4 x i1> [[TMP8]], i64 1
-; IC4-NEXT: br i1 [[TMP68]], label %[[PRED_LOAD_IF20:.*]], label %[[PRED_LOAD_CONTINUE21:.*]]
-; IC4: [[PRED_LOAD_IF20]]:
-; IC4-NEXT: [[TMP69:%.*]] = extractelement <4 x i32> [[TMP12]], i64 1
-; IC4-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP69]]
-; IC4-NEXT: [[TMP71:%.*]] = load i32, ptr [[TMP70]], align 4
-; IC4-NEXT: [[TMP72:%.*]] = insertelement <4 x i32> [[TMP67]], i32 [[TMP71]], i64 1
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE21]]
-; IC4: [[PRED_LOAD_CONTINUE21]]:
-; IC4-NEXT: [[TMP73:%.*]] = phi <4 x i32> [ [[TMP67]], %[[PRED_LOAD_CONTINUE19]] ], [ [[TMP72]], %[[PRED_LOAD_IF20]] ]
-; IC4-NEXT: [[TMP74:%.*]] = extractelement <4 x i1> [[TMP8]], i64 2
-; IC4-NEXT: br i1 [[TMP74]], label %[[PRED_LOAD_IF22:.*]], label %[[PRED_LOAD_CONTINUE23:.*]]
-; IC4: [[PRED_LOAD_IF22]]:
-; IC4-NEXT: [[TMP75:%.*]] = extractelement <4 x i32> [[TMP12]], i64 2
-; IC4-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP75]]
-; IC4-NEXT: [[TMP77:%.*]] = load i32, ptr [[TMP76]], align 4
-; IC4-NEXT: [[TMP78:%.*]] = insertelement <4 x i32> [[TMP73]], i32 [[TMP77]], i64 2
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE23]]
-; IC4: [[PRED_LOAD_CONTINUE23]]:
-; IC4-NEXT: [[TMP79:%.*]] = phi <4 x i32> [ [[TMP73]], %[[PRED_LOAD_CONTINUE21]] ], [ [[TMP78]], %[[PRED_LOAD_IF22]] ]
-; IC4-NEXT: [[TMP80:%.*]] = extractelement <4 x i1> [[TMP8]], i64 3
-; IC4-NEXT: br i1 [[TMP80]], label %[[PRED_LOAD_IF24:.*]], label %[[PRED_LOAD_CONTINUE25:.*]]
-; IC4: [[PRED_LOAD_IF24]]:
-; IC4-NEXT: [[TMP81:%.*]] = extractelement <4 x i32> [[TMP12]], i64 3
-; IC4-NEXT: [[TMP82:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP81]]
-; IC4-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP82]], align 4
-; IC4-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> [[TMP79]], i32 [[TMP83]], i64 3
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE25]]
-; IC4: [[PRED_LOAD_CONTINUE25]]:
-; IC4-NEXT: [[TMP85:%.*]] = phi <4 x i32> [ [[TMP79]], %[[PRED_LOAD_CONTINUE23]] ], [ [[TMP84]], %[[PRED_LOAD_IF24]] ]
-; IC4-NEXT: [[TMP86:%.*]] = extractelement <4 x i1> [[TMP9]], i64 0
-; IC4-NEXT: br i1 [[TMP86]], label %[[PRED_LOAD_IF26:.*]], label %[[PRED_LOAD_CONTINUE27:.*]]
-; IC4: [[PRED_LOAD_IF26]]:
-; IC4-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[TMP13]], i64 0
+; IC4-NEXT: [[TMP87:%.*]] = urem i32 [[INDEX]], 128
+; IC4-NEXT: [[TMP93:%.*]] = urem i32 [[TMP0]], 128
+; IC4-NEXT: [[TMP99:%.*]] = urem i32 [[TMP1]], 128
+; IC4-NEXT: [[TMP105:%.*]] = urem i32 [[TMP10]], 128
; IC4-NEXT: [[TMP88:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP87]]
-; IC4-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP88]], align 4
-; IC4-NEXT: [[TMP90:%.*]] = insertelement <4 x i32> poison, i32 [[TMP89]], i64 0
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE27]]
-; IC4: [[PRED_LOAD_CONTINUE27]]:
-; IC4-NEXT: [[TMP91:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE25]] ], [ [[TMP90]], %[[PRED_LOAD_IF26]] ]
-; IC4-NEXT: [[TMP92:%.*]] = extractelement <4 x i1> [[TMP9]], i64 1
-; IC4-NEXT: br i1 [[TMP92]], label %[[PRED_LOAD_IF28:.*]], label %[[PRED_LOAD_CONTINUE29:.*]]
-; IC4: [[PRED_LOAD_IF28]]:
-; IC4-NEXT: [[TMP93:%.*]] = extractelement <4 x i32> [[TMP13]], i64 1
; IC4-NEXT: [[TMP94:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP93]]
-; IC4-NEXT: [[TMP95:%.*]] = load i32, ptr [[TMP94]], align 4
-; IC4-NEXT: [[TMP96:%.*]] = insertelement <4 x i32> [[TMP91]], i32 [[TMP95]], i64 1
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE29]]
-; IC4: [[PRED_LOAD_CONTINUE29]]:
-; IC4-NEXT: [[TMP97:%.*]] = phi <4 x i32> [ [[TMP91]], %[[PRED_LOAD_CONTINUE27]] ], [ [[TMP96]], %[[PRED_LOAD_IF28]] ]
-; IC4-NEXT: [[TMP98:%.*]] = extractelement <4 x i1> [[TMP9]], i64 2
-; IC4-NEXT: br i1 [[TMP98]], label %[[PRED_LOAD_IF30:.*]], label %[[PRED_LOAD_CONTINUE31:.*]]
-; IC4: [[PRED_LOAD_IF30]]:
-; IC4-NEXT: [[TMP99:%.*]] = extractelement <4 x i32> [[TMP13]], i64 2
; IC4-NEXT: [[TMP100:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP99]]
-; IC4-NEXT: [[TMP101:%.*]] = load i32, ptr [[TMP100]], align 4
-; IC4-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP97]], i32 [[TMP101]], i64 2
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE31]]
-; IC4: [[PRED_LOAD_CONTINUE31]]:
-; IC4-NEXT: [[TMP103:%.*]] = phi <4 x i32> [ [[TMP97]], %[[PRED_LOAD_CONTINUE29]] ], [ [[TMP102]], %[[PRED_LOAD_IF30]] ]
-; IC4-NEXT: [[TMP104:%.*]] = extractelement <4 x i1> [[TMP9]], i64 3
-; IC4-NEXT: br i1 [[TMP104]], label %[[PRED_LOAD_IF32:.*]], label %[[PRED_LOAD_CONTINUE33]]
-; IC4: [[PRED_LOAD_IF32]]:
-; IC4-NEXT: [[TMP105:%.*]] = extractelement <4 x i32> [[TMP13]], i64 3
; IC4-NEXT: [[TMP106:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP105]]
-; IC4-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP106]], align 4
-; IC4-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> [[TMP103]], i32 [[TMP107]], i64 3
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE33]]
-; IC4: [[PRED_LOAD_CONTINUE33]]:
-; IC4-NEXT: [[TMP109:%.*]] = phi <4 x i32> [ [[TMP103]], %[[PRED_LOAD_CONTINUE31]] ], [ [[TMP108]], %[[PRED_LOAD_IF32]] ]
+; IC4-NEXT: [[TMP37:%.*]] = load <4 x i32>, ptr [[TMP88]], align 4
+; IC4-NEXT: [[TMP61:%.*]] = load <4 x i32>, ptr [[TMP94]], align 4
+; IC4-NEXT: [[TMP85:%.*]] = load <4 x i32>, ptr [[TMP100]], align 4
+; IC4-NEXT: [[TMP109:%.*]] = load <4 x i32>, ptr [[TMP106]], align 4
; IC4-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[TMP37]], <4 x i32> zeroinitializer
; IC4-NEXT: [[PREDPHI34:%.*]] = select <4 x i1> [[TMP7]], <4 x i32> [[TMP61]], <4 x i32> zeroinitializer
; IC4-NEXT: [[PREDPHI35:%.*]] = select <4 x i1> [[TMP8]], <4 x i32> [[TMP85]], <4 x i32> zeroinitializer
@@ -345,16 +158,16 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC8-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; IC8-NEXT: br label %[[VECTOR_BODY:.*]]
; IC8: [[VECTOR_BODY]]:
-; IC8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69:.*]] ]
-; IC8-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP218:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP219:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP220:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP221:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP222:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP223:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP224:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP225:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP218:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP219:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP220:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP221:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP222:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP223:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP224:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP225:%.*]], %[[VECTOR_BODY]] ]
; IC8-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i32> [[VEC_IND]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i32> [[STEP_ADD]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i32> [[STEP_ADD_2]], splat (i32 4)
@@ -362,6 +175,13 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC8-NEXT: [[STEP_ADD_5:%.*]] = add nuw <4 x i32> [[STEP_ADD_4]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_6:%.*]] = add nuw <4 x i32> [[STEP_ADD_5]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_7:%.*]] = add nuw <4 x i32> [[STEP_ADD_6]], splat (i32 4)
+; IC8-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; IC8-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; IC8-NEXT: [[TMP18:%.*]] = add i32 [[INDEX]], 12
+; IC8-NEXT: [[TMP19:%.*]] = add i32 [[INDEX]], 16
+; IC8-NEXT: [[TMP20:%.*]] = add i32 [[INDEX]], 20
+; IC8-NEXT: [[TMP21:%.*]] = add i32 [[INDEX]], 24
+; IC8-NEXT: [[TMP22:%.*]] = add i32 [[INDEX]], 28
; IC8-NEXT: [[TMP2:%.*]] = and <4 x i32> [[VEC_IND]], splat (i32 1)
; IC8-NEXT: [[TMP3:%.*]] = and <4 x i32> [[STEP_ADD]], splat (i32 1)
; IC8-NEXT: [[TMP4:%.*]] = and <4 x i32> [[STEP_ADD_2]], splat (i32 1)
@@ -378,334 +198,30 @@ define i32 @clamped_load_predicated(ptr %A, i32 %n) {
; IC8-NEXT: [[TMP15:%.*]] = icmp eq <4 x i32> [[TMP7]], zeroinitializer
; IC8-NEXT: [[TMP16:%.*]] = icmp eq <4 x i32> [[TMP8]], zeroinitializer
; IC8-NEXT: [[TMP17:%.*]] = icmp eq <4 x i32> [[TMP9]], zeroinitializer
-; IC8-NEXT: [[TMP18:%.*]] = urem <4 x i32> [[VEC_IND]], splat (i32 128)
-; IC8-NEXT: [[TMP19:%.*]] = urem <4 x i32> [[STEP_ADD]], splat (i32 128)
-; IC8-NEXT: [[TMP20:%.*]] = urem <4 x i32> [[STEP_ADD_2]], splat (i32 128)
-; IC8-NEXT: [[TMP21:%.*]] = urem <4 x i32> [[STEP_ADD_3]], splat (i32 128)
-; IC8-NEXT: [[TMP22:%.*]] = urem <4 x i32> [[STEP_ADD_4]], splat (i32 128)
-; IC8-NEXT: [[TMP23:%.*]] = urem <4 x i32> [[STEP_ADD_5]], splat (i32 128)
-; IC8-NEXT: [[TMP24:%.*]] = urem <4 x i32> [[STEP_ADD_6]], splat (i32 128)
-; IC8-NEXT: [[TMP25:%.*]] = urem <4 x i32> [[STEP_ADD_7]], splat (i32 128)
-; IC8-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[TMP10]], i64 0
-; IC8-NEXT: br i1 [[TMP26]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
-; IC8: [[PRED_LOAD_IF]]:
-; IC8-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP18]], i64 0
-; IC8-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP27]]
-; IC8-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
-; IC8-NEXT: [[TMP30:%.*]] = insertelement <4 x i32> poison, i32 [[TMP29]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE]]
-; IC8: [[PRED_LOAD_CONTINUE]]:
-; IC8-NEXT: [[TMP31:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP30]], %[[PRED_LOAD_IF]] ]
-; IC8-NEXT: [[TMP32:%.*]] = extractelement <4 x i1> [[TMP10]], i64 1
-; IC8-NEXT: br i1 [[TMP32]], label %[[PRED_LOAD_IF8:.*]], label %[[PRED_LOAD_CONTINUE9:.*]]
-; IC8: [[PRED_LOAD_IF8]]:
-; IC8-NEXT: [[TMP33:%.*]] = extractelement <4 x i32> [[TMP18]], i64 1
-; IC8-NEXT: [[TMP34:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP33]]
-; IC8-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4
-; IC8-NEXT: [[TMP36:%.*]] = insertelement <4 x i32> [[TMP31]], i32 [[TMP35]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE9]]
-; IC8: [[PRED_LOAD_CONTINUE9]]:
-; IC8-NEXT: [[TMP37:%.*]] = phi <4 x i32> [ [[TMP31]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP36]], %[[PRED_LOAD_IF8]] ]
-; IC8-NEXT: [[TMP38:%.*]] = extractelement <4 x i1> [[TMP10]], i64 2
-; IC8-NEXT: br i1 [[TMP38]], label %[[PRED_LOAD_IF10:.*]], label %[[PRED_LOAD_CONTINUE11:.*]]
-; IC8: [[PRED_LOAD_IF10]]:
-; IC8-NEXT: [[TMP39:%.*]] = extractelement <4 x i32> [[TMP18]], i64 2
-; IC8-NEXT: [[TMP40:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP39]]
-; IC8-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-; IC8-NEXT: [[TMP42:%.*]] = insertelement <4 x i32> [[TMP37]], i32 [[TMP41]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE11]]
-; IC8: [[PRED_LOAD_CONTINUE11]]:
-; IC8-NEXT: [[TMP43:%.*]] = phi <4 x i32> [ [[TMP37]], %[[PRED_LOAD_CONTINUE9]] ], [ [[TMP42]], %[[PRED_LOAD_IF10]] ]
-; IC8-NEXT: [[TMP44:%.*]] = extractelement <4 x i1> [[TMP10]], i64 3
-; IC8-NEXT: br i1 [[TMP44]], label %[[PRED_LOAD_IF12:.*]], label %[[PRED_LOAD_CONTINUE13:.*]]
-; IC8: [[PRED_LOAD_IF12]]:
-; IC8-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[TMP18]], i64 3
-; IC8-NEXT: [[TMP46:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP45]]
-; IC8-NEXT: [[TMP47:%.*]] = load i32, ptr [[TMP46]], align 4
-; IC8-NEXT: [[TMP48:%.*]] = insertelement <4 x i32> [[TMP43]], i32 [[TMP47]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE13]]
-; IC8: [[PRED_LOAD_CONTINUE13]]:
-; IC8-NEXT: [[TMP49:%.*]] = phi <4 x i32> [ [[TMP43]], %[[PRED_LOAD_CONTINUE11]] ], [ [[TMP48]], %[[PRED_LOAD_IF12]] ]
-; IC8-NEXT: [[TMP50:%.*]] = extractelement <4 x i1> [[TMP11]], i64 0
-; IC8-NEXT: br i1 [[TMP50]], label %[[PRED_LOAD_IF14:.*]], label %[[PRED_LOAD_CONTINUE15:.*]]
-; IC8: [[PRED_LOAD_IF14]]:
-; IC8-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[TMP19]], i64 0
-; IC8-NEXT: [[TMP52:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP51]]
-; IC8-NEXT: [[TMP53:%.*]] = load i32, ptr [[TMP52]], align 4
-; IC8-NEXT: [[TMP54:%.*]] = insertelement <4 x i32> poison, i32 [[TMP53]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE15]]
-; IC8: [[PRED_LOAD_CONTINUE15]]:
-; IC8-NEXT: [[TMP55:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE13]] ], [ [[TMP54]], %[[PRED_LOAD_IF14]] ]
-; IC8-NEXT: [[TMP56:%.*]] = extractelement <4 x i1> [[TMP11]], i64 1
-; IC8-NEXT: br i1 [[TMP56]], label %[[PRED_LOAD_IF16:.*]], label %[[PRED_LOAD_CONTINUE17:.*]]
-; IC8: [[PRED_LOAD_IF16]]:
-; IC8-NEXT: [[TMP57:%.*]] = extractelement <4 x i32> [[TMP19]], i64 1
-; IC8-NEXT: [[TMP58:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP57]]
-; IC8-NEXT: [[TMP59:%.*]] = load i32, ptr [[TMP58]], align 4
-; IC8-NEXT: [[TMP60:%.*]] = insertelement <4 x i32> [[TMP55]], i32 [[TMP59]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE17]]
-; IC8: [[PRED_LOAD_CONTINUE17]]:
-; IC8-NEXT: [[TMP61:%.*]] = phi <4 x i32> [ [[TMP55]], %[[PRED_LOAD_CONTINUE15]] ], [ [[TMP60]], %[[PRED_LOAD_IF16]] ]
-; IC8-NEXT: [[TMP62:%.*]] = extractelement <4 x i1> [[TMP11]], i64 2
-; IC8-NEXT: br i1 [[TMP62]], label %[[PRED_LOAD_IF18:.*]], label %[[PRED_LOAD_CONTINUE19:.*]]
-; IC8: [[PRED_LOAD_IF18]]:
-; IC8-NEXT: [[TMP63:%.*]] = extractelement <4 x i32> [[TMP19]], i64 2
-; IC8-NEXT: [[TMP64:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP63]]
-; IC8-NEXT: [[TMP65:%.*]] = load i32, ptr [[TMP64]], align 4
-; IC8-NEXT: [[TMP66:%.*]] = insertelement <4 x i32> [[TMP61]], i32 [[TMP65]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE19]]
-; IC8: [[PRED_LOAD_CONTINUE19]]:
-; IC8-NEXT: [[TMP67:%.*]] = phi <4 x i32> [ [[TMP61]], %[[PRED_LOAD_CONTINUE17]] ], [ [[TMP66]], %[[PRED_LOAD_IF18]] ]
-; IC8-NEXT: [[TMP68:%.*]] = extractelement <4 x i1> [[TMP11]], i64 3
-; IC8-NEXT: br i1 [[TMP68]], label %[[PRED_LOAD_IF20:.*]], label %[[PRED_LOAD_CONTINUE21:.*]]
-; IC8: [[PRED_LOAD_IF20]]:
-; IC8-NEXT: [[TMP69:%.*]] = extractelement <4 x i32> [[TMP19]], i64 3
-; IC8-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP69]]
-; IC8-NEXT: [[TMP71:%.*]] = load i32, ptr [[TMP70]], align 4
-; IC8-NEXT: [[TMP72:%.*]] = insertelement <4 x i32> [[TMP67]], i32 [[TMP71]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE21]]
-; IC8: [[PRED_LOAD_CONTINUE21]]:
-; IC8-NEXT: [[TMP73:%.*]] = phi <4 x i32> [ [[TMP67]], %[[PRED_LOAD_CONTINUE19]] ], [ [[TMP72]], %[[PRED_LOAD_IF20]] ]
-; IC8-NEXT: [[TMP74:%.*]] = extractelement <4 x i1> [[TMP12]], i64 0
-; IC8-NEXT: br i1 [[TMP74]], label %[[PRED_LOAD_IF22:.*]], label %[[PRED_LOAD_CONTINUE23:.*]]
-; IC8: [[PRED_LOAD_IF22]]:
-; IC8-NEXT: [[TMP75:%.*]] = extractelement <4 x i32> [[TMP20]], i64 0
-; IC8-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP75]]
-; IC8-NEXT: [[TMP77:%.*]] = load i32, ptr [[TMP76]], align 4
-; IC8-NEXT: [[TMP78:%.*]] = insertelement <4 x i32> poison, i32 [[TMP77]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE23]]
-; IC8: [[PRED_LOAD_CONTINUE23]]:
-; IC8-NEXT: [[TMP79:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE21]] ], [ [[TMP78]], %[[PRED_LOAD_IF22]] ]
-; IC8-NEXT: [[TMP80:%.*]] = extractelement <4 x i1> [[TMP12]], i64 1
-; IC8-NEXT: br i1 [[TMP80]], label %[[PRED_LOAD_IF24:.*]], label %[[PRED_LOAD_CONTINUE25:.*]]
-; IC8: [[PRED_LOAD_IF24]]:
-; IC8-NEXT: [[TMP81:%.*]] = extractelement <4 x i32> [[TMP20]], i64 1
-; IC8-NEXT: [[TMP82:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP81]]
-; IC8-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP82]], align 4
-; IC8-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> [[TMP79]], i32 [[TMP83]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE25]]
-; IC8: [[PRED_LOAD_CONTINUE25]]:
-; IC8-NEXT: [[TMP85:%.*]] = phi <4 x i32> [ [[TMP79]], %[[PRED_LOAD_CONTINUE23]] ], [ [[TMP84]], %[[PRED_LOAD_IF24]] ]
-; IC8-NEXT: [[TMP86:%.*]] = extractelement <4 x i1> [[TMP12]], i64 2
-; IC8-NEXT: br i1 [[TMP86]], label %[[PRED_LOAD_IF26:.*]], label %[[PRED_LOAD_CONTINUE27:.*]]
-; IC8: [[PRED_LOAD_IF26]]:
-; IC8-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[TMP20]], i64 2
-; IC8-NEXT: [[TMP88:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP87]]
-; IC8-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP88]], align 4
-; IC8-NEXT: [[TMP90:%.*]] = insertelement <4 x i32> [[TMP85]], i32 [[TMP89]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE27]]
-; IC8: [[PRED_LOAD_CONTINUE27]]:
-; IC8-NEXT: [[TMP91:%.*]] = phi <4 x i32> [ [[TMP85]], %[[PRED_LOAD_CONTINUE25]] ], [ [[TMP90]], %[[PRED_LOAD_IF26]] ]
-; IC8-NEXT: [[TMP92:%.*]] = extractelement <4 x i1> [[TMP12]], i64 3
-; IC8-NEXT: br i1 [[TMP92]], label %[[PRED_LOAD_IF28:.*]], label %[[PRED_LOAD_CONTINUE29:.*]]
-; IC8: [[PRED_LOAD_IF28]]:
-; IC8-NEXT: [[TMP93:%.*]] = extractelement <4 x i32> [[TMP20]], i64 3
-; IC8-NEXT: [[TMP94:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP93]]
-; IC8-NEXT: [[TMP95:%.*]] = load i32, ptr [[TMP94]], align 4
-; IC8-NEXT: [[TMP96:%.*]] = insertelement <4 x i32> [[TMP91]], i32 [[TMP95]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE29]]
-; IC8: [[PRED_LOAD_CONTINUE29]]:
-; IC8-NEXT: [[TMP97:%.*]] = phi <4 x i32> [ [[TMP91]], %[[PRED_LOAD_CONTINUE27]] ], [ [[TMP96]], %[[PRED_LOAD_IF28]] ]
-; IC8-NEXT: [[TMP98:%.*]] = extractelement <4 x i1> [[TMP13]], i64 0
-; IC8-NEXT: br i1 [[TMP98]], label %[[PRED_LOAD_IF30:.*]], label %[[PRED_LOAD_CONTINUE31:.*]]
-; IC8: [[PRED_LOAD_IF30]]:
-; IC8-NEXT: [[TMP99:%.*]] = extractelement <4 x i32> [[TMP21]], i64 0
-; IC8-NEXT: [[TMP100:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP99]]
-; IC8-NEXT: [[TMP101:%.*]] = load i32, ptr [[TMP100]], align 4
-; IC8-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> poison, i32 [[TMP101]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE31]]
-; IC8: [[PRED_LOAD_CONTINUE31]]:
-; IC8-NEXT: [[TMP103:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE29]] ], [ [[TMP102]], %[[PRED_LOAD_IF30]] ]
-; IC8-NEXT: [[TMP104:%.*]] = extractelement <4 x i1> [[TMP13]], i64 1
-; IC8-NEXT: br i1 [[TMP104]], label %[[PRED_LOAD_IF32:.*]], label %[[PRED_LOAD_CONTINUE33:.*]]
-; IC8: [[PRED_LOAD_IF32]]:
-; IC8-NEXT: [[TMP105:%.*]] = extractelement <4 x i32> [[TMP21]], i64 1
-; IC8-NEXT: [[TMP106:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP105]]
-; IC8-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP106]], align 4
-; IC8-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> [[TMP103]], i32 [[TMP107]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE33]]
-; IC8: [[PRED_LOAD_CONTINUE33]]:
-; IC8-NEXT: [[TMP109:%.*]] = phi <4 x i32> [ [[TMP103]], %[[PRED_LOAD_CONTINUE31]] ], [ [[TMP108]], %[[PRED_LOAD_IF32]] ]
-; IC8-NEXT: [[TMP110:%.*]] = extractelement <4 x i1> [[TMP13]], i64 2
-; IC8-NEXT: br i1 [[TMP110]], label %[[PRED_LOAD_IF34:.*]], label %[[PRED_LOAD_CONTINUE35:.*]]
-; IC8: [[PRED_LOAD_IF34]]:
-; IC8-NEXT: [[TMP111:%.*]] = extractelement <4 x i32> [[TMP21]], i64 2
-; IC8-NEXT: [[TMP112:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP111]]
-; IC8-NEXT: [[TMP113:%.*]] = load i32, ptr [[TMP112]], align 4
-; IC8-NEXT: [[TMP114:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP113]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE35]]
-; IC8: [[PRED_LOAD_CONTINUE35]]:
-; IC8-NEXT: [[TMP115:%.*]] = phi <4 x i32> [ [[TMP109]], %[[PRED_LOAD_CONTINUE33]] ], [ [[TMP114]], %[[PRED_LOAD_IF34]] ]
-; IC8-NEXT: [[TMP116:%.*]] = extractelement <4 x i1> [[TMP13]], i64 3
-; IC8-NEXT: br i1 [[TMP116]], label %[[PRED_LOAD_IF36:.*]], label %[[PRED_LOAD_CONTINUE37:.*]]
-; IC8: [[PRED_LOAD_IF36]]:
-; IC8-NEXT: [[TMP117:%.*]] = extractelement <4 x i32> [[TMP21]], i64 3
-; IC8-NEXT: [[TMP118:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP117]]
-; IC8-NEXT: [[TMP119:%.*]] = load i32, ptr [[TMP118]], align 4
-; IC8-NEXT: [[TMP120:%.*]] = insertelement <4 x i32> [[TMP115]], i32 [[TMP119]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE37]]
-; IC8: [[PRED_LOAD_CONTINUE37]]:
-; IC8-NEXT: [[TMP121:%.*]] = phi <4 x i32> [ [[TMP115]], %[[PRED_LOAD_CONTINUE35]] ], [ [[TMP120]], %[[PRED_LOAD_IF36]] ]
-; IC8-NEXT: [[TMP122:%.*]] = extractelement <4 x i1> [[TMP14]], i64 0
-; IC8-NEXT: br i1 [[TMP122]], label %[[PRED_LOAD_IF38:.*]], label %[[PRED_LOAD_CONTINUE39:.*]]
-; IC8: [[PRED_LOAD_IF38]]:
-; IC8-NEXT: [[TMP123:%.*]] = extractelement <4 x i32> [[TMP22]], i64 0
-; IC8-NEXT: [[TMP124:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP123]]
-; IC8-NEXT: [[TMP125:%.*]] = load i32, ptr [[TMP124]], align 4
-; IC8-NEXT: [[TMP126:%.*]] = insertelement <4 x i32> poison, i32 [[TMP125]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE39]]
-; IC8: [[PRED_LOAD_CONTINUE39]]:
-; IC8-NEXT: [[TMP127:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE37]] ], [ [[TMP126]], %[[PRED_LOAD_IF38]] ]
-; IC8-NEXT: [[TMP128:%.*]] = extractelement <4 x i1> [[TMP14]], i64 1
-; IC8-NEXT: br i1 [[TMP128]], label %[[PRED_LOAD_IF40:.*]], label %[[PRED_LOAD_CONTINUE41:.*]]
-; IC8: [[PRED_LOAD_IF40]]:
-; IC8-NEXT: [[TMP129:%.*]] = extractelement <4 x i32> [[TMP22]], i64 1
-; IC8-NEXT: [[TMP130:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP129]]
-; IC8-NEXT: [[TMP131:%.*]] = load i32, ptr [[TMP130]], align 4
-; IC8-NEXT: [[TMP132:%.*]] = insertelement <4 x i32> [[TMP127]], i32 [[TMP131]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE41]]
-; IC8: [[PRED_LOAD_CONTINUE41]]:
-; IC8-NEXT: [[TMP133:%.*]] = phi <4 x i32> [ [[TMP127]], %[[PRED_LOAD_CONTINUE39]] ], [ [[TMP132]], %[[PRED_LOAD_IF40]] ]
-; IC8-NEXT: [[TMP134:%.*]] = extractelement <4 x i1> [[TMP14]], i64 2
-; IC8-NEXT: br i1 [[TMP134]], label %[[PRED_LOAD_IF42:.*]], label %[[PRED_LOAD_CONTINUE43:.*]]
-; IC8: [[PRED_LOAD_IF42]]:
-; IC8-NEXT: [[TMP135:%.*]] = extractelement <4 x i32> [[TMP22]], i64 2
-; IC8-NEXT: [[TMP136:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP135]]
-; IC8-NEXT: [[TMP137:%.*]] = load i32, ptr [[TMP136]], align 4
-; IC8-NEXT: [[TMP138:%.*]] = insertelement <4 x i32> [[TMP133]], i32 [[TMP137]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE43]]
-; IC8: [[PRED_LOAD_CONTINUE43]]:
-; IC8-NEXT: [[TMP139:%.*]] = phi <4 x i32> [ [[TMP133]], %[[PRED_LOAD_CONTINUE41]] ], [ [[TMP138]], %[[PRED_LOAD_IF42]] ]
-; IC8-NEXT: [[TMP140:%.*]] = extractelement <4 x i1> [[TMP14]], i64 3
-; IC8-NEXT: br i1 [[TMP140]], label %[[PRED_LOAD_IF44:.*]], label %[[PRED_LOAD_CONTINUE45:.*]]
-; IC8: [[PRED_LOAD_IF44]]:
-; IC8-NEXT: [[TMP141:%.*]] = extractelement <4 x i32> [[TMP22]], i64 3
-; IC8-NEXT: [[TMP142:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP141]]
-; IC8-NEXT: [[TMP143:%.*]] = load i32, ptr [[TMP142]], align 4
-; IC8-NEXT: [[TMP144:%.*]] = insertelement <4 x i32> [[TMP139]], i32 [[TMP143]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE45]]
-; IC8: [[PRED_LOAD_CONTINUE45]]:
-; IC8-NEXT: [[TMP145:%.*]] = phi <4 x i32> [ [[TMP139]], %[[PRED_LOAD_CONTINUE43]] ], [ [[TMP144]], %[[PRED_LOAD_IF44]] ]
-; IC8-NEXT: [[TMP146:%.*]] = extractelement <4 x i1> [[TMP15]], i64 0
-; IC8-NEXT: br i1 [[TMP146]], label %[[PRED_LOAD_IF46:.*]], label %[[PRED_LOAD_CONTINUE47:.*]]
-; IC8: [[PRED_LOAD_IF46]]:
-; IC8-NEXT: [[TMP147:%.*]] = extractelement <4 x i32> [[TMP23]], i64 0
-; IC8-NEXT: [[TMP148:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP147]]
-; IC8-NEXT: [[TMP149:%.*]] = load i32, ptr [[TMP148]], align 4
-; IC8-NEXT: [[TMP150:%.*]] = insertelement <4 x i32> poison, i32 [[TMP149]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE47]]
-; IC8: [[PRED_LOAD_CONTINUE47]]:
-; IC8-NEXT: [[TMP151:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE45]] ], [ [[TMP150]], %[[PRED_LOAD_IF46]] ]
-; IC8-NEXT: [[TMP152:%.*]] = extractelement <4 x i1> [[TMP15]], i64 1
-; IC8-NEXT: br i1 [[TMP152]], label %[[PRED_LOAD_IF48:.*]], label %[[PRED_LOAD_CONTINUE49:.*]]
-; IC8: [[PRED_LOAD_IF48]]:
-; IC8-NEXT: [[TMP153:%.*]] = extractelement <4 x i32> [[TMP23]], i64 1
-; IC8-NEXT: [[TMP154:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP153]]
-; IC8-NEXT: [[TMP155:%.*]] = load i32, ptr [[TMP154]], align 4
-; IC8-NEXT: [[TMP156:%.*]] = insertelement <4 x i32> [[TMP151]], i32 [[TMP155]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE49]]
-; IC8: [[PRED_LOAD_CONTINUE49]]:
-; IC8-NEXT: [[TMP157:%.*]] = phi <4 x i32> [ [[TMP151]], %[[PRED_LOAD_CONTINUE47]] ], [ [[TMP156]], %[[PRED_LOAD_IF48]] ]
-; IC8-NEXT: [[TMP158:%.*]] = extractelement <4 x i1> [[TMP15]], i64 2
-; IC8-NEXT: br i1 [[TMP158]], label %[[PRED_LOAD_IF50:.*]], label %[[PRED_LOAD_CONTINUE51:.*]]
-; IC8: [[PRED_LOAD_IF50]]:
-; IC8-NEXT: [[TMP159:%.*]] = extractelement <4 x i32> [[TMP23]], i64 2
-; IC8-NEXT: [[TMP160:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP159]]
-; IC8-NEXT: [[TMP161:%.*]] = load i32, ptr [[TMP160]], align 4
-; IC8-NEXT: [[TMP162:%.*]] = insertelement <4 x i32> [[TMP157]], i32 [[TMP161]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE51]]
-; IC8: [[PRED_LOAD_CONTINUE51]]:
-; IC8-NEXT: [[TMP163:%.*]] = phi <4 x i32> [ [[TMP157]], %[[PRED_LOAD_CONTINUE49]] ], [ [[TMP162]], %[[PRED_LOAD_IF50]] ]
-; IC8-NEXT: [[TMP164:%.*]] = extractelement <4 x i1> [[TMP15]], i64 3
-; IC8-NEXT: br i1 [[TMP164]], label %[[PRED_LOAD_IF52:.*]], label %[[PRED_LOAD_CONTINUE53:.*]]
-; IC8: [[PRED_LOAD_IF52]]:
-; IC8-NEXT: [[TMP165:%.*]] = extractelement <4 x i32> [[TMP23]], i64 3
-; IC8-NEXT: [[TMP166:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP165]]
-; IC8-NEXT: [[TMP167:%.*]] = load i32, ptr [[TMP166]], align 4
-; IC8-NEXT: [[TMP168:%.*]] = insertelement <4 x i32> [[TMP163]], i32 [[TMP167]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE53]]
-; IC8: [[PRED_LOAD_CONTINUE53]]:
-; IC8-NEXT: [[TMP169:%.*]] = phi <4 x i32> [ [[TMP163]], %[[PRED_LOAD_CONTINUE51]] ], [ [[TMP168]], %[[PRED_LOAD_IF52]] ]
-; IC8-NEXT: [[TMP170:%.*]] = extractelement <4 x i1> [[TMP16]], i64 0
-; IC8-NEXT: br i1 [[TMP170]], label %[[PRED_LOAD_IF54:.*]], label %[[PRED_LOAD_CONTINUE55:.*]]
-; IC8: [[PRED_LOAD_IF54]]:
-; IC8-NEXT: [[TMP171:%.*]] = extractelement <4 x i32> [[TMP24]], i64 0
+; IC8-NEXT: [[TMP171:%.*]] = urem i32 [[INDEX]], 128
+; IC8-NEXT: [[TMP177:%.*]] = urem i32 [[TMP0]], 128
+; IC8-NEXT: [[TMP183:%.*]] = urem i32 [[TMP1]], 128
+; IC8-NEXT: [[TMP189:%.*]] = urem i32 [[TMP18]], 128
+; IC8-NEXT: [[TMP195:%.*]] = urem i32 [[TMP19]], 128
+; IC8-NEXT: [[TMP201:%.*]] = urem i32 [[TMP20]], 128
+; IC8-NEXT: [[TMP207:%.*]] = urem i32 [[TMP21]], 128
+; IC8-NEXT: [[TMP213:%.*]] = urem i32 [[TMP22]], 128
; IC8-NEXT: [[TMP172:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP171]]
-; IC8-NEXT: [[TMP173:%.*]] = load i32, ptr [[TMP172]], align 4
-; IC8-NEXT: [[TMP174:%.*]] = insertelement <4 x i32> poison, i32 [[TMP173]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE55]]
-; IC8: [[PRED_LOAD_CONTINUE55]]:
-; IC8-NEXT: [[TMP175:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE53]] ], [ [[TMP174]], %[[PRED_LOAD_IF54]] ]
-; IC8-NEXT: [[TMP176:%.*]] = extractelement <4 x i1> [[TMP16]], i64 1
-; IC8-NEXT: br i1 [[TMP176]], label %[[PRED_LOAD_IF56:.*]], label %[[PRED_LOAD_CONTINUE57:.*]]
-; IC8: [[PRED_LOAD_IF56]]:
-; IC8-NEXT: [[TMP177:%.*]] = extractelement <4 x i32> [[TMP24]], i64 1
; IC8-NEXT: [[TMP178:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP177]]
-; IC8-NEXT: [[TMP179:%.*]] = load i32, ptr [[TMP178]], align 4
-; IC8-NEXT: [[TMP180:%.*]] = insertelement <4 x i32> [[TMP175]], i32 [[TMP179]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE57]]
-; IC8: [[PRED_LOAD_CONTINUE57]]:
-; IC8-NEXT: [[TMP181:%.*]] = phi <4 x i32> [ [[TMP175]], %[[PRED_LOAD_CONTINUE55]] ], [ [[TMP180]], %[[PRED_LOAD_IF56]] ]
-; IC8-NEXT: [[TMP182:%.*]] = extractelement <4 x i1> [[TMP16]], i64 2
-; IC8-NEXT: br i1 [[TMP182]], label %[[PRED_LOAD_IF58:.*]], label %[[PRED_LOAD_CONTINUE59:.*]]
-; IC8: [[PRED_LOAD_IF58]]:
-; IC8-NEXT: [[TMP183:%.*]] = extractelement <4 x i32> [[TMP24]], i64 2
; IC8-NEXT: [[TMP184:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP183]]
-; IC8-NEXT: [[TMP185:%.*]] = load i32, ptr [[TMP184]], align 4
-; IC8-NEXT: [[TMP186:%.*]] = insertelement <4 x i32> [[TMP181]], i32 [[TMP185]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE59]]
-; IC8: [[PRED_LOAD_CONTINUE59]]:
-; IC8-NEXT: [[TMP187:%.*]] = phi <4 x i32> [ [[TMP181]], %[[PRED_LOAD_CONTINUE57]] ], [ [[TMP186]], %[[PRED_LOAD_IF58]] ]
-; IC8-NEXT: [[TMP188:%.*]] = extractelement <4 x i1> [[TMP16]], i64 3
-; IC8-NEXT: br i1 [[TMP188]], label %[[PRED_LOAD_IF60:.*]], label %[[PRED_LOAD_CONTINUE61:.*]]
-; IC8: [[PRED_LOAD_IF60]]:
-; IC8-NEXT: [[TMP189:%.*]] = extractelement <4 x i32> [[TMP24]], i64 3
; IC8-NEXT: [[TMP190:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP189]]
-; IC8-NEXT: [[TMP191:%.*]] = load i32, ptr [[TMP190]], align 4
-; IC8-NEXT: [[TMP192:%.*]] = insertelement <4 x i32> [[TMP187]], i32 [[TMP191]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE61]]
-; IC8: [[PRED_LOAD_CONTINUE61]]:
-; IC8-NEXT: [[TMP193:%.*]] = phi <4 x i32> [ [[TMP187]], %[[PRED_LOAD_CONTINUE59]] ], [ [[TMP192]], %[[PRED_LOAD_IF60]] ]
-; IC8-NEXT: [[TMP194:%.*]] = extractelement <4 x i1> [[TMP17]], i64 0
-; IC8-NEXT: br i1 [[TMP194]], label %[[PRED_LOAD_IF62:.*]], label %[[PRED_LOAD_CONTINUE63:.*]]
-; IC8: [[PRED_LOAD_IF62]]:
-; IC8-NEXT: [[TMP195:%.*]] = extractelement <4 x i32> [[TMP25]], i64 0
; IC8-NEXT: [[TMP196:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP195]]
-; IC8-NEXT: [[TMP197:%.*]] = load i32, ptr [[TMP196]], align 4
-; IC8-NEXT: [[TMP198:%.*]] = insertelement <4 x i32> poison, i32 [[TMP197]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE63]]
-; IC8: [[PRED_LOAD_CONTINUE63]]:
-; IC8-NEXT: [[TMP199:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE61]] ], [ [[TMP198]], %[[PRED_LOAD_IF62]] ]
-; IC8-NEXT: [[TMP200:%.*]] = extractelement <4 x i1> [[TMP17]], i64 1
-; IC8-NEXT: br i1 [[TMP200]], label %[[PRED_LOAD_IF64:.*]], label %[[PRED_LOAD_CONTINUE65:.*]]
-; IC8: [[PRED_LOAD_IF64]]:
-; IC8-NEXT: [[TMP201:%.*]] = extractelement <4 x i32> [[TMP25]], i64 1
; IC8-NEXT: [[TMP202:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP201]]
-; IC8-NEXT: [[TMP203:%.*]] = load i32, ptr [[TMP202]], align 4
-; IC8-NEXT: [[TMP204:%.*]] = insertelement <4 x i32> [[TMP199]], i32 [[TMP203]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE65]]
-; IC8: [[PRED_LOAD_CONTINUE65]]:
-; IC8-NEXT: [[TMP205:%.*]] = phi <4 x i32> [ [[TMP199]], %[[PRED_LOAD_CONTINUE63]] ], [ [[TMP204]], %[[PRED_LOAD_IF64]] ]
-; IC8-NEXT: [[TMP206:%.*]] = extractelement <4 x i1> [[TMP17]], i64 2
-; IC8-NEXT: br i1 [[TMP206]], label %[[PRED_LOAD_IF66:.*]], label %[[PRED_LOAD_CONTINUE67:.*]]
-; IC8: [[PRED_LOAD_IF66]]:
-; IC8-NEXT: [[TMP207:%.*]] = extractelement <4 x i32> [[TMP25]], i64 2
; IC8-NEXT: [[TMP208:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP207]]
-; IC8-NEXT: [[TMP209:%.*]] = load i32, ptr [[TMP208]], align 4
-; IC8-NEXT: [[TMP210:%.*]] = insertelement <4 x i32> [[TMP205]], i32 [[TMP209]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE67]]
-; IC8: [[PRED_LOAD_CONTINUE67]]:
-; IC8-NEXT: [[TMP211:%.*]] = phi <4 x i32> [ [[TMP205]], %[[PRED_LOAD_CONTINUE65]] ], [ [[TMP210]], %[[PRED_LOAD_IF66]] ]
-; IC8-NEXT: [[TMP212:%.*]] = extractelement <4 x i1> [[TMP17]], i64 3
-; IC8-NEXT: br i1 [[TMP212]], label %[[PRED_LOAD_IF68:.*]], label %[[PRED_LOAD_CONTINUE69]]
-; IC8: [[PRED_LOAD_IF68]]:
-; IC8-NEXT: [[TMP213:%.*]] = extractelement <4 x i32> [[TMP25]], i64 3
; IC8-NEXT: [[TMP214:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP213]]
-; IC8-NEXT: [[TMP215:%.*]] = load i32, ptr [[TMP214]], align 4
-; IC8-NEXT: [[TMP216:%.*]] = insertelement <4 x i32> [[TMP211]], i32 [[TMP215]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE69]]
-; IC8: [[PRED_LOAD_CONTINUE69]]:
-; IC8-NEXT: [[TMP217:%.*]] = phi <4 x i32> [ [[TMP211]], %[[PRED_LOAD_CONTINUE67]] ], [ [[TMP216]], %[[PRED_LOAD_IF68]] ]
+; IC8-NEXT: [[TMP49:%.*]] = load <4 x i32>, ptr [[TMP172]], align 4
+; IC8-NEXT: [[TMP73:%.*]] = load <4 x i32>, ptr [[TMP178]], align 4
+; IC8-NEXT: [[TMP97:%.*]] = load <4 x i32>, ptr [[TMP184]], align 4
+; IC8-NEXT: [[TMP121:%.*]] = load <4 x i32>, ptr [[TMP190]], align 4
+; IC8-NEXT: [[TMP145:%.*]] = load <4 x i32>, ptr [[TMP196]], align 4
+; IC8-NEXT: [[TMP169:%.*]] = load <4 x i32>, ptr [[TMP202]], align 4
+; IC8-NEXT: [[TMP193:%.*]] = load <4 x i32>, ptr [[TMP208]], align 4
+; IC8-NEXT: [[TMP217:%.*]] = load <4 x i32>, ptr [[TMP214]], align 4
; IC8-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP10]], <4 x i32> [[TMP49]], <4 x i32> zeroinitializer
; IC8-NEXT: [[PREDPHI70:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP73]], <4 x i32> zeroinitializer
; IC8-NEXT: [[PREDPHI71:%.*]] = select <4 x i1> [[TMP12]], <4 x i32> [[TMP97]], <4 x i32> zeroinitializer
@@ -808,52 +324,14 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]
-; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[PRED_LOAD_CONTINUE6]] ]
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[VEC_IND]], splat (i32 1)
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <4 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = urem <4 x i32> [[VEC_IND]], splat (i32 16)
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP3]], i64 0
-; CHECK-NEXT: br i1 [[TMP5]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
-; CHECK: [[PRED_LOAD_IF]]:
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i64 0
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> poison, i32 [[TMP8]], i64 0
-; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]
-; CHECK: [[PRED_LOAD_CONTINUE]]:
-; CHECK-NEXT: [[TMP10:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP9]], %[[PRED_LOAD_IF]] ]
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP3]], i64 1
-; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]
-; CHECK: [[PRED_LOAD_IF1]]:
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP4]], i64 1
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP12]]
-; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP14]], i64 1
-; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE2]]
-; CHECK: [[PRED_LOAD_CONTINUE2]]:
-; CHECK-NEXT: [[TMP16:%.*]] = phi <4 x i32> [ [[TMP10]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP15]], %[[PRED_LOAD_IF1]] ]
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i1> [[TMP3]], i64 2
-; CHECK-NEXT: br i1 [[TMP17]], label %[[PRED_LOAD_IF3:.*]], label %[[PRED_LOAD_CONTINUE4:.*]]
-; CHECK: [[PRED_LOAD_IF3]]:
-; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i32> [[TMP4]], i64 2
-; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP18]]
-; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> [[TMP16]], i32 [[TMP20]], i64 2
-; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE4]]
-; CHECK: [[PRED_LOAD_CONTINUE4]]:
-; CHECK-NEXT: [[TMP22:%.*]] = phi <4 x i32> [ [[TMP16]], %[[PRED_LOAD_CONTINUE2]] ], [ [[TMP21]], %[[PRED_LOAD_IF3]] ]
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i1> [[TMP3]], i64 3
-; CHECK-NEXT: br i1 [[TMP23]], label %[[PRED_LOAD_IF5:.*]], label %[[PRED_LOAD_CONTINUE6]]
-; CHECK: [[PRED_LOAD_IF5]]:
-; CHECK-NEXT: [[TMP24:%.*]] = extractelement <4 x i32> [[TMP4]], i64 3
+; CHECK-NEXT: [[TMP24:%.*]] = urem i32 [[INDEX]], 16
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i32> [[TMP22]], i32 [[TMP26]], i64 3
-; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE6]]
-; CHECK: [[PRED_LOAD_CONTINUE6]]:
-; CHECK-NEXT: [[TMP28:%.*]] = phi <4 x i32> [ [[TMP22]], %[[PRED_LOAD_CONTINUE4]] ], [ [[TMP27]], %[[PRED_LOAD_IF5]] ]
+; CHECK-NEXT: [[TMP28:%.*]] = load <4 x i32>, ptr [[TMP25]], align 4
; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP28]], <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP29]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
@@ -899,15 +377,18 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC4-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; IC4-NEXT: br label %[[VECTOR_BODY:.*]]
; IC4: [[VECTOR_BODY]]:
-; IC4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33:.*]] ]
-; IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP110:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP111:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP112:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
-; IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP113:%.*]], %[[PRED_LOAD_CONTINUE33]] ]
+; IC4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP110:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP111:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP112:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP113:%.*]], %[[VECTOR_BODY]] ]
; IC4-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i32> [[VEC_IND]], splat (i32 4)
; IC4-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i32> [[STEP_ADD]], splat (i32 4)
; IC4-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i32> [[STEP_ADD_2]], splat (i32 4)
+; IC4-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; IC4-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; IC4-NEXT: [[TMP10:%.*]] = add i32 [[INDEX]], 12
; IC4-NEXT: [[TMP2:%.*]] = and <4 x i32> [[VEC_IND]], splat (i32 1)
; IC4-NEXT: [[TMP3:%.*]] = and <4 x i32> [[STEP_ADD]], splat (i32 1)
; IC4-NEXT: [[TMP4:%.*]] = and <4 x i32> [[STEP_ADD_2]], splat (i32 1)
@@ -916,170 +397,18 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC4-NEXT: [[TMP7:%.*]] = icmp eq <4 x i32> [[TMP3]], zeroinitializer
; IC4-NEXT: [[TMP8:%.*]] = icmp eq <4 x i32> [[TMP4]], zeroinitializer
; IC4-NEXT: [[TMP9:%.*]] = icmp eq <4 x i32> [[TMP5]], zeroinitializer
-; IC4-NEXT: [[TMP10:%.*]] = urem <4 x i32> [[VEC_IND]], splat (i32 16)
-; IC4-NEXT: [[TMP11:%.*]] = urem <4 x i32> [[STEP_ADD]], splat (i32 16)
-; IC4-NEXT: [[TMP12:%.*]] = urem <4 x i32> [[STEP_ADD_2]], splat (i32 16)
-; IC4-NEXT: [[TMP13:%.*]] = urem <4 x i32> [[STEP_ADD_3]], splat (i32 16)
-; IC4-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP6]], i64 0
-; IC4-NEXT: br i1 [[TMP14]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
-; IC4: [[PRED_LOAD_IF]]:
-; IC4-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP10]], i64 0
-; IC4-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP15]]
-; IC4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
-; IC4-NEXT: [[TMP18:%.*]] = insertelement <4 x i32> poison, i32 [[TMP17]], i64 0
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE]]
-; IC4: [[PRED_LOAD_CONTINUE]]:
-; IC4-NEXT: [[TMP19:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP18]], %[[PRED_LOAD_IF]] ]
-; IC4-NEXT: [[TMP20:%.*]] = extractelement <4 x i1> [[TMP6]], i64 1
-; IC4-NEXT: br i1 [[TMP20]], label %[[PRED_LOAD_IF4:.*]], label %[[PRED_LOAD_CONTINUE5:.*]]
-; IC4: [[PRED_LOAD_IF4]]:
-; IC4-NEXT: [[TMP21:%.*]] = extractelement <4 x i32> [[TMP10]], i64 1
-; IC4-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP21]]
-; IC4-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
-; IC4-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> [[TMP19]], i32 [[TMP23]], i64 1
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE5]]
-; IC4: [[PRED_LOAD_CONTINUE5]]:
-; IC4-NEXT: [[TMP25:%.*]] = phi <4 x i32> [ [[TMP19]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP24]], %[[PRED_LOAD_IF4]] ]
-; IC4-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[TMP6]], i64 2
-; IC4-NEXT: br i1 [[TMP26]], label %[[PRED_LOAD_IF6:.*]], label %[[PRED_LOAD_CONTINUE7:.*]]
-; IC4: [[PRED_LOAD_IF6]]:
-; IC4-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP10]], i64 2
-; IC4-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP27]]
-; IC4-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
-; IC4-NEXT: [[TMP30:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP29]], i64 2
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE7]]
-; IC4: [[PRED_LOAD_CONTINUE7]]:
-; IC4-NEXT: [[TMP31:%.*]] = phi <4 x i32> [ [[TMP25]], %[[PRED_LOAD_CONTINUE5]] ], [ [[TMP30]], %[[PRED_LOAD_IF6]] ]
-; IC4-NEXT: [[TMP32:%.*]] = extractelement <4 x i1> [[TMP6]], i64 3
-; IC4-NEXT: br i1 [[TMP32]], label %[[PRED_LOAD_IF8:.*]], label %[[PRED_LOAD_CONTINUE9:.*]]
-; IC4: [[PRED_LOAD_IF8]]:
-; IC4-NEXT: [[TMP33:%.*]] = extractelement <4 x i32> [[TMP10]], i64 3
-; IC4-NEXT: [[TMP34:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP33]]
-; IC4-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4
-; IC4-NEXT: [[TMP36:%.*]] = insertelement <4 x i32> [[TMP31]], i32 [[TMP35]], i64 3
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE9]]
-; IC4: [[PRED_LOAD_CONTINUE9]]:
-; IC4-NEXT: [[TMP37:%.*]] = phi <4 x i32> [ [[TMP31]], %[[PRED_LOAD_CONTINUE7]] ], [ [[TMP36]], %[[PRED_LOAD_IF8]] ]
-; IC4-NEXT: [[TMP38:%.*]] = extractelement <4 x i1> [[TMP7]], i64 0
-; IC4-NEXT: br i1 [[TMP38]], label %[[PRED_LOAD_IF10:.*]], label %[[PRED_LOAD_CONTINUE11:.*]]
-; IC4: [[PRED_LOAD_IF10]]:
-; IC4-NEXT: [[TMP39:%.*]] = extractelement <4 x i32> [[TMP11]], i64 0
-; IC4-NEXT: [[TMP40:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP39]]
-; IC4-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-; IC4-NEXT: [[TMP42:%.*]] = insertelement <4 x i32> poison, i32 [[TMP41]], i64 0
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE11]]
-; IC4: [[PRED_LOAD_CONTINUE11]]:
-; IC4-NEXT: [[TMP43:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE9]] ], [ [[TMP42]], %[[PRED_LOAD_IF10]] ]
-; IC4-NEXT: [[TMP44:%.*]] = extractelement <4 x i1> [[TMP7]], i64 1
-; IC4-NEXT: br i1 [[TMP44]], label %[[PRED_LOAD_IF12:.*]], label %[[PRED_LOAD_CONTINUE13:.*]]
-; IC4: [[PRED_LOAD_IF12]]:
-; IC4-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[TMP11]], i64 1
-; IC4-NEXT: [[TMP46:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP45]]
-; IC4-NEXT: [[TMP47:%.*]] = load i32, ptr [[TMP46]], align 4
-; IC4-NEXT: [[TMP48:%.*]] = insertelement <4 x i32> [[TMP43]], i32 [[TMP47]], i64 1
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE13]]
-; IC4: [[PRED_LOAD_CONTINUE13]]:
-; IC4-NEXT: [[TMP49:%.*]] = phi <4 x i32> [ [[TMP43]], %[[PRED_LOAD_CONTINUE11]] ], [ [[TMP48]], %[[PRED_LOAD_IF12]] ]
-; IC4-NEXT: [[TMP50:%.*]] = extractelement <4 x i1> [[TMP7]], i64 2
-; IC4-NEXT: br i1 [[TMP50]], label %[[PRED_LOAD_IF14:.*]], label %[[PRED_LOAD_CONTINUE15:.*]]
-; IC4: [[PRED_LOAD_IF14]]:
-; IC4-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[TMP11]], i64 2
-; IC4-NEXT: [[TMP52:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP51]]
-; IC4-NEXT: [[TMP53:%.*]] = load i32, ptr [[TMP52]], align 4
-; IC4-NEXT: [[TMP54:%.*]] = insertelement <4 x i32> [[TMP49]], i32 [[TMP53]], i64 2
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE15]]
-; IC4: [[PRED_LOAD_CONTINUE15]]:
-; IC4-NEXT: [[TMP55:%.*]] = phi <4 x i32> [ [[TMP49]], %[[PRED_LOAD_CONTINUE13]] ], [ [[TMP54]], %[[PRED_LOAD_IF14]] ]
-; IC4-NEXT: [[TMP56:%.*]] = extractelement <4 x i1> [[TMP7]], i64 3
-; IC4-NEXT: br i1 [[TMP56]], label %[[PRED_LOAD_IF16:.*]], label %[[PRED_LOAD_CONTINUE17:.*]]
-; IC4: [[PRED_LOAD_IF16]]:
-; IC4-NEXT: [[TMP57:%.*]] = extractelement <4 x i32> [[TMP11]], i64 3
-; IC4-NEXT: [[TMP58:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP57]]
-; IC4-NEXT: [[TMP59:%.*]] = load i32, ptr [[TMP58]], align 4
-; IC4-NEXT: [[TMP60:%.*]] = insertelement <4 x i32> [[TMP55]], i32 [[TMP59]], i64 3
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE17]]
-; IC4: [[PRED_LOAD_CONTINUE17]]:
-; IC4-NEXT: [[TMP61:%.*]] = phi <4 x i32> [ [[TMP55]], %[[PRED_LOAD_CONTINUE15]] ], [ [[TMP60]], %[[PRED_LOAD_IF16]] ]
-; IC4-NEXT: [[TMP62:%.*]] = extractelement <4 x i1> [[TMP8]], i64 0
-; IC4-NEXT: br i1 [[TMP62]], label %[[PRED_LOAD_IF18:.*]], label %[[PRED_LOAD_CONTINUE19:.*]]
-; IC4: [[PRED_LOAD_IF18]]:
-; IC4-NEXT: [[TMP63:%.*]] = extractelement <4 x i32> [[TMP12]], i64 0
-; IC4-NEXT: [[TMP64:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP63]]
-; IC4-NEXT: [[TMP65:%.*]] = load i32, ptr [[TMP64]], align 4
-; IC4-NEXT: [[TMP66:%.*]] = insertelement <4 x i32> poison, i32 [[TMP65]], i64 0
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE19]]
-; IC4: [[PRED_LOAD_CONTINUE19]]:
-; IC4-NEXT: [[TMP67:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE17]] ], [ [[TMP66]], %[[PRED_LOAD_IF18]] ]
-; IC4-NEXT: [[TMP68:%.*]] = extractelement <4 x i1> [[TMP8]], i64 1
-; IC4-NEXT: br i1 [[TMP68]], label %[[PRED_LOAD_IF20:.*]], label %[[PRED_LOAD_CONTINUE21:.*]]
-; IC4: [[PRED_LOAD_IF20]]:
-; IC4-NEXT: [[TMP69:%.*]] = extractelement <4 x i32> [[TMP12]], i64 1
-; IC4-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP69]]
-; IC4-NEXT: [[TMP71:%.*]] = load i32, ptr [[TMP70]], align 4
-; IC4-NEXT: [[TMP72:%.*]] = insertelement <4 x i32> [[TMP67]], i32 [[TMP71]], i64 1
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE21]]
-; IC4: [[PRED_LOAD_CONTINUE21]]:
-; IC4-NEXT: [[TMP73:%.*]] = phi <4 x i32> [ [[TMP67]], %[[PRED_LOAD_CONTINUE19]] ], [ [[TMP72]], %[[PRED_LOAD_IF20]] ]
-; IC4-NEXT: [[TMP74:%.*]] = extractelement <4 x i1> [[TMP8]], i64 2
-; IC4-NEXT: br i1 [[TMP74]], label %[[PRED_LOAD_IF22:.*]], label %[[PRED_LOAD_CONTINUE23:.*]]
-; IC4: [[PRED_LOAD_IF22]]:
-; IC4-NEXT: [[TMP75:%.*]] = extractelement <4 x i32> [[TMP12]], i64 2
-; IC4-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP75]]
-; IC4-NEXT: [[TMP77:%.*]] = load i32, ptr [[TMP76]], align 4
-; IC4-NEXT: [[TMP78:%.*]] = insertelement <4 x i32> [[TMP73]], i32 [[TMP77]], i64 2
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE23]]
-; IC4: [[PRED_LOAD_CONTINUE23]]:
-; IC4-NEXT: [[TMP79:%.*]] = phi <4 x i32> [ [[TMP73]], %[[PRED_LOAD_CONTINUE21]] ], [ [[TMP78]], %[[PRED_LOAD_IF22]] ]
-; IC4-NEXT: [[TMP80:%.*]] = extractelement <4 x i1> [[TMP8]], i64 3
-; IC4-NEXT: br i1 [[TMP80]], label %[[PRED_LOAD_IF24:.*]], label %[[PRED_LOAD_CONTINUE25:.*]]
-; IC4: [[PRED_LOAD_IF24]]:
-; IC4-NEXT: [[TMP81:%.*]] = extractelement <4 x i32> [[TMP12]], i64 3
-; IC4-NEXT: [[TMP82:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP81]]
-; IC4-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP82]], align 4
-; IC4-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> [[TMP79]], i32 [[TMP83]], i64 3
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE25]]
-; IC4: [[PRED_LOAD_CONTINUE25]]:
-; IC4-NEXT: [[TMP85:%.*]] = phi <4 x i32> [ [[TMP79]], %[[PRED_LOAD_CONTINUE23]] ], [ [[TMP84]], %[[PRED_LOAD_IF24]] ]
-; IC4-NEXT: [[TMP86:%.*]] = extractelement <4 x i1> [[TMP9]], i64 0
-; IC4-NEXT: br i1 [[TMP86]], label %[[PRED_LOAD_IF26:.*]], label %[[PRED_LOAD_CONTINUE27:.*]]
-; IC4: [[PRED_LOAD_IF26]]:
-; IC4-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[TMP13]], i64 0
+; IC4-NEXT: [[TMP87:%.*]] = urem i32 [[INDEX]], 16
+; IC4-NEXT: [[TMP93:%.*]] = urem i32 [[TMP0]], 16
+; IC4-NEXT: [[TMP99:%.*]] = urem i32 [[TMP1]], 16
+; IC4-NEXT: [[TMP105:%.*]] = urem i32 [[TMP10]], 16
; IC4-NEXT: [[TMP88:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP87]]
-; IC4-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP88]], align 4
-; IC4-NEXT: [[TMP90:%.*]] = insertelement <4 x i32> poison, i32 [[TMP89]], i64 0
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE27]]
-; IC4: [[PRED_LOAD_CONTINUE27]]:
-; IC4-NEXT: [[TMP91:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE25]] ], [ [[TMP90]], %[[PRED_LOAD_IF26]] ]
-; IC4-NEXT: [[TMP92:%.*]] = extractelement <4 x i1> [[TMP9]], i64 1
-; IC4-NEXT: br i1 [[TMP92]], label %[[PRED_LOAD_IF28:.*]], label %[[PRED_LOAD_CONTINUE29:.*]]
-; IC4: [[PRED_LOAD_IF28]]:
-; IC4-NEXT: [[TMP93:%.*]] = extractelement <4 x i32> [[TMP13]], i64 1
; IC4-NEXT: [[TMP94:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP93]]
-; IC4-NEXT: [[TMP95:%.*]] = load i32, ptr [[TMP94]], align 4
-; IC4-NEXT: [[TMP96:%.*]] = insertelement <4 x i32> [[TMP91]], i32 [[TMP95]], i64 1
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE29]]
-; IC4: [[PRED_LOAD_CONTINUE29]]:
-; IC4-NEXT: [[TMP97:%.*]] = phi <4 x i32> [ [[TMP91]], %[[PRED_LOAD_CONTINUE27]] ], [ [[TMP96]], %[[PRED_LOAD_IF28]] ]
-; IC4-NEXT: [[TMP98:%.*]] = extractelement <4 x i1> [[TMP9]], i64 2
-; IC4-NEXT: br i1 [[TMP98]], label %[[PRED_LOAD_IF30:.*]], label %[[PRED_LOAD_CONTINUE31:.*]]
-; IC4: [[PRED_LOAD_IF30]]:
-; IC4-NEXT: [[TMP99:%.*]] = extractelement <4 x i32> [[TMP13]], i64 2
; IC4-NEXT: [[TMP100:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP99]]
-; IC4-NEXT: [[TMP101:%.*]] = load i32, ptr [[TMP100]], align 4
-; IC4-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP97]], i32 [[TMP101]], i64 2
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE31]]
-; IC4: [[PRED_LOAD_CONTINUE31]]:
-; IC4-NEXT: [[TMP103:%.*]] = phi <4 x i32> [ [[TMP97]], %[[PRED_LOAD_CONTINUE29]] ], [ [[TMP102]], %[[PRED_LOAD_IF30]] ]
-; IC4-NEXT: [[TMP104:%.*]] = extractelement <4 x i1> [[TMP9]], i64 3
-; IC4-NEXT: br i1 [[TMP104]], label %[[PRED_LOAD_IF32:.*]], label %[[PRED_LOAD_CONTINUE33]]
-; IC4: [[PRED_LOAD_IF32]]:
-; IC4-NEXT: [[TMP105:%.*]] = extractelement <4 x i32> [[TMP13]], i64 3
; IC4-NEXT: [[TMP106:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP105]]
-; IC4-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP106]], align 4
-; IC4-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> [[TMP103]], i32 [[TMP107]], i64 3
-; IC4-NEXT: br label %[[PRED_LOAD_CONTINUE33]]
-; IC4: [[PRED_LOAD_CONTINUE33]]:
-; IC4-NEXT: [[TMP109:%.*]] = phi <4 x i32> [ [[TMP103]], %[[PRED_LOAD_CONTINUE31]] ], [ [[TMP108]], %[[PRED_LOAD_IF32]] ]
+; IC4-NEXT: [[TMP37:%.*]] = load <4 x i32>, ptr [[TMP88]], align 4
+; IC4-NEXT: [[TMP61:%.*]] = load <4 x i32>, ptr [[TMP94]], align 4
+; IC4-NEXT: [[TMP85:%.*]] = load <4 x i32>, ptr [[TMP100]], align 4
+; IC4-NEXT: [[TMP109:%.*]] = load <4 x i32>, ptr [[TMP106]], align 4
; IC4-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[TMP37]], <4 x i32> zeroinitializer
; IC4-NEXT: [[PREDPHI34:%.*]] = select <4 x i1> [[TMP7]], <4 x i32> [[TMP61]], <4 x i32> zeroinitializer
; IC4-NEXT: [[PREDPHI35:%.*]] = select <4 x i1> [[TMP8]], <4 x i32> [[TMP85]], <4 x i32> zeroinitializer
@@ -1134,16 +463,16 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC8-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
; IC8-NEXT: br label %[[VECTOR_BODY:.*]]
; IC8: [[VECTOR_BODY]]:
-; IC8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69:.*]] ]
-; IC8-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP218:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP219:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP220:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP221:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP222:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP223:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP224:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
-; IC8-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP225:%.*]], %[[PRED_LOAD_CONTINUE69]] ]
+; IC8-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP218:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP219:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP220:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP221:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP222:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP223:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP224:%.*]], %[[VECTOR_BODY]] ]
+; IC8-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP225:%.*]], %[[VECTOR_BODY]] ]
; IC8-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i32> [[VEC_IND]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i32> [[STEP_ADD]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i32> [[STEP_ADD_2]], splat (i32 4)
@@ -1151,6 +480,13 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC8-NEXT: [[STEP_ADD_5:%.*]] = add nuw <4 x i32> [[STEP_ADD_4]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_6:%.*]] = add nuw <4 x i32> [[STEP_ADD_5]], splat (i32 4)
; IC8-NEXT: [[STEP_ADD_7:%.*]] = add nuw <4 x i32> [[STEP_ADD_6]], splat (i32 4)
+; IC8-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 4
+; IC8-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 8
+; IC8-NEXT: [[TMP18:%.*]] = add i32 [[INDEX]], 12
+; IC8-NEXT: [[TMP19:%.*]] = add i32 [[INDEX]], 16
+; IC8-NEXT: [[TMP20:%.*]] = add i32 [[INDEX]], 20
+; IC8-NEXT: [[TMP21:%.*]] = add i32 [[INDEX]], 24
+; IC8-NEXT: [[TMP22:%.*]] = add i32 [[INDEX]], 28
; IC8-NEXT: [[TMP2:%.*]] = and <4 x i32> [[VEC_IND]], splat (i32 1)
; IC8-NEXT: [[TMP3:%.*]] = and <4 x i32> [[STEP_ADD]], splat (i32 1)
; IC8-NEXT: [[TMP4:%.*]] = and <4 x i32> [[STEP_ADD_2]], splat (i32 1)
@@ -1167,334 +503,30 @@ define i32 @clamped_load_predicated_ic_capped(ptr %A, i32 %n) {
; IC8-NEXT: [[TMP15:%.*]] = icmp eq <4 x i32> [[TMP7]], zeroinitializer
; IC8-NEXT: [[TMP16:%.*]] = icmp eq <4 x i32> [[TMP8]], zeroinitializer
; IC8-NEXT: [[TMP17:%.*]] = icmp eq <4 x i32> [[TMP9]], zeroinitializer
-; IC8-NEXT: [[TMP18:%.*]] = urem <4 x i32> [[VEC_IND]], splat (i32 16)
-; IC8-NEXT: [[TMP19:%.*]] = urem <4 x i32> [[STEP_ADD]], splat (i32 16)
-; IC8-NEXT: [[TMP20:%.*]] = urem <4 x i32> [[STEP_ADD_2]], splat (i32 16)
-; IC8-NEXT: [[TMP21:%.*]] = urem <4 x i32> [[STEP_ADD_3]], splat (i32 16)
-; IC8-NEXT: [[TMP22:%.*]] = urem <4 x i32> [[STEP_ADD_4]], splat (i32 16)
-; IC8-NEXT: [[TMP23:%.*]] = urem <4 x i32> [[STEP_ADD_5]], splat (i32 16)
-; IC8-NEXT: [[TMP24:%.*]] = urem <4 x i32> [[STEP_ADD_6]], splat (i32 16)
-; IC8-NEXT: [[TMP25:%.*]] = urem <4 x i32> [[STEP_ADD_7]], splat (i32 16)
-; IC8-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[TMP10]], i64 0
-; IC8-NEXT: br i1 [[TMP26]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
-; IC8: [[PRED_LOAD_IF]]:
-; IC8-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP18]], i64 0
-; IC8-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP27]]
-; IC8-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
-; IC8-NEXT: [[TMP30:%.*]] = insertelement <4 x i32> poison, i32 [[TMP29]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE]]
-; IC8: [[PRED_LOAD_CONTINUE]]:
-; IC8-NEXT: [[TMP31:%.*]] = phi <4 x i32> [ poison, %[[VECTOR_BODY]] ], [ [[TMP30]], %[[PRED_LOAD_IF]] ]
-; IC8-NEXT: [[TMP32:%.*]] = extractelement <4 x i1> [[TMP10]], i64 1
-; IC8-NEXT: br i1 [[TMP32]], label %[[PRED_LOAD_IF8:.*]], label %[[PRED_LOAD_CONTINUE9:.*]]
-; IC8: [[PRED_LOAD_IF8]]:
-; IC8-NEXT: [[TMP33:%.*]] = extractelement <4 x i32> [[TMP18]], i64 1
-; IC8-NEXT: [[TMP34:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP33]]
-; IC8-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4
-; IC8-NEXT: [[TMP36:%.*]] = insertelement <4 x i32> [[TMP31]], i32 [[TMP35]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE9]]
-; IC8: [[PRED_LOAD_CONTINUE9]]:
-; IC8-NEXT: [[TMP37:%.*]] = phi <4 x i32> [ [[TMP31]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP36]], %[[PRED_LOAD_IF8]] ]
-; IC8-NEXT: [[TMP38:%.*]] = extractelement <4 x i1> [[TMP10]], i64 2
-; IC8-NEXT: br i1 [[TMP38]], label %[[PRED_LOAD_IF10:.*]], label %[[PRED_LOAD_CONTINUE11:.*]]
-; IC8: [[PRED_LOAD_IF10]]:
-; IC8-NEXT: [[TMP39:%.*]] = extractelement <4 x i32> [[TMP18]], i64 2
-; IC8-NEXT: [[TMP40:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP39]]
-; IC8-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-; IC8-NEXT: [[TMP42:%.*]] = insertelement <4 x i32> [[TMP37]], i32 [[TMP41]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE11]]
-; IC8: [[PRED_LOAD_CONTINUE11]]:
-; IC8-NEXT: [[TMP43:%.*]] = phi <4 x i32> [ [[TMP37]], %[[PRED_LOAD_CONTINUE9]] ], [ [[TMP42]], %[[PRED_LOAD_IF10]] ]
-; IC8-NEXT: [[TMP44:%.*]] = extractelement <4 x i1> [[TMP10]], i64 3
-; IC8-NEXT: br i1 [[TMP44]], label %[[PRED_LOAD_IF12:.*]], label %[[PRED_LOAD_CONTINUE13:.*]]
-; IC8: [[PRED_LOAD_IF12]]:
-; IC8-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[TMP18]], i64 3
-; IC8-NEXT: [[TMP46:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP45]]
-; IC8-NEXT: [[TMP47:%.*]] = load i32, ptr [[TMP46]], align 4
-; IC8-NEXT: [[TMP48:%.*]] = insertelement <4 x i32> [[TMP43]], i32 [[TMP47]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE13]]
-; IC8: [[PRED_LOAD_CONTINUE13]]:
-; IC8-NEXT: [[TMP49:%.*]] = phi <4 x i32> [ [[TMP43]], %[[PRED_LOAD_CONTINUE11]] ], [ [[TMP48]], %[[PRED_LOAD_IF12]] ]
-; IC8-NEXT: [[TMP50:%.*]] = extractelement <4 x i1> [[TMP11]], i64 0
-; IC8-NEXT: br i1 [[TMP50]], label %[[PRED_LOAD_IF14:.*]], label %[[PRED_LOAD_CONTINUE15:.*]]
-; IC8: [[PRED_LOAD_IF14]]:
-; IC8-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[TMP19]], i64 0
-; IC8-NEXT: [[TMP52:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP51]]
-; IC8-NEXT: [[TMP53:%.*]] = load i32, ptr [[TMP52]], align 4
-; IC8-NEXT: [[TMP54:%.*]] = insertelement <4 x i32> poison, i32 [[TMP53]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE15]]
-; IC8: [[PRED_LOAD_CONTINUE15]]:
-; IC8-NEXT: [[TMP55:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE13]] ], [ [[TMP54]], %[[PRED_LOAD_IF14]] ]
-; IC8-NEXT: [[TMP56:%.*]] = extractelement <4 x i1> [[TMP11]], i64 1
-; IC8-NEXT: br i1 [[TMP56]], label %[[PRED_LOAD_IF16:.*]], label %[[PRED_LOAD_CONTINUE17:.*]]
-; IC8: [[PRED_LOAD_IF16]]:
-; IC8-NEXT: [[TMP57:%.*]] = extractelement <4 x i32> [[TMP19]], i64 1
-; IC8-NEXT: [[TMP58:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP57]]
-; IC8-NEXT: [[TMP59:%.*]] = load i32, ptr [[TMP58]], align 4
-; IC8-NEXT: [[TMP60:%.*]] = insertelement <4 x i32> [[TMP55]], i32 [[TMP59]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE17]]
-; IC8: [[PRED_LOAD_CONTINUE17]]:
-; IC8-NEXT: [[TMP61:%.*]] = phi <4 x i32> [ [[TMP55]], %[[PRED_LOAD_CONTINUE15]] ], [ [[TMP60]], %[[PRED_LOAD_IF16]] ]
-; IC8-NEXT: [[TMP62:%.*]] = extractelement <4 x i1> [[TMP11]], i64 2
-; IC8-NEXT: br i1 [[TMP62]], label %[[PRED_LOAD_IF18:.*]], label %[[PRED_LOAD_CONTINUE19:.*]]
-; IC8: [[PRED_LOAD_IF18]]:
-; IC8-NEXT: [[TMP63:%.*]] = extractelement <4 x i32> [[TMP19]], i64 2
-; IC8-NEXT: [[TMP64:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP63]]
-; IC8-NEXT: [[TMP65:%.*]] = load i32, ptr [[TMP64]], align 4
-; IC8-NEXT: [[TMP66:%.*]] = insertelement <4 x i32> [[TMP61]], i32 [[TMP65]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE19]]
-; IC8: [[PRED_LOAD_CONTINUE19]]:
-; IC8-NEXT: [[TMP67:%.*]] = phi <4 x i32> [ [[TMP61]], %[[PRED_LOAD_CONTINUE17]] ], [ [[TMP66]], %[[PRED_LOAD_IF18]] ]
-; IC8-NEXT: [[TMP68:%.*]] = extractelement <4 x i1> [[TMP11]], i64 3
-; IC8-NEXT: br i1 [[TMP68]], label %[[PRED_LOAD_IF20:.*]], label %[[PRED_LOAD_CONTINUE21:.*]]
-; IC8: [[PRED_LOAD_IF20]]:
-; IC8-NEXT: [[TMP69:%.*]] = extractelement <4 x i32> [[TMP19]], i64 3
-; IC8-NEXT: [[TMP70:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP69]]
-; IC8-NEXT: [[TMP71:%.*]] = load i32, ptr [[TMP70]], align 4
-; IC8-NEXT: [[TMP72:%.*]] = insertelement <4 x i32> [[TMP67]], i32 [[TMP71]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE21]]
-; IC8: [[PRED_LOAD_CONTINUE21]]:
-; IC8-NEXT: [[TMP73:%.*]] = phi <4 x i32> [ [[TMP67]], %[[PRED_LOAD_CONTINUE19]] ], [ [[TMP72]], %[[PRED_LOAD_IF20]] ]
-; IC8-NEXT: [[TMP74:%.*]] = extractelement <4 x i1> [[TMP12]], i64 0
-; IC8-NEXT: br i1 [[TMP74]], label %[[PRED_LOAD_IF22:.*]], label %[[PRED_LOAD_CONTINUE23:.*]]
-; IC8: [[PRED_LOAD_IF22]]:
-; IC8-NEXT: [[TMP75:%.*]] = extractelement <4 x i32> [[TMP20]], i64 0
-; IC8-NEXT: [[TMP76:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP75]]
-; IC8-NEXT: [[TMP77:%.*]] = load i32, ptr [[TMP76]], align 4
-; IC8-NEXT: [[TMP78:%.*]] = insertelement <4 x i32> poison, i32 [[TMP77]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE23]]
-; IC8: [[PRED_LOAD_CONTINUE23]]:
-; IC8-NEXT: [[TMP79:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE21]] ], [ [[TMP78]], %[[PRED_LOAD_IF22]] ]
-; IC8-NEXT: [[TMP80:%.*]] = extractelement <4 x i1> [[TMP12]], i64 1
-; IC8-NEXT: br i1 [[TMP80]], label %[[PRED_LOAD_IF24:.*]], label %[[PRED_LOAD_CONTINUE25:.*]]
-; IC8: [[PRED_LOAD_IF24]]:
-; IC8-NEXT: [[TMP81:%.*]] = extractelement <4 x i32> [[TMP20]], i64 1
-; IC8-NEXT: [[TMP82:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP81]]
-; IC8-NEXT: [[TMP83:%.*]] = load i32, ptr [[TMP82]], align 4
-; IC8-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> [[TMP79]], i32 [[TMP83]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE25]]
-; IC8: [[PRED_LOAD_CONTINUE25]]:
-; IC8-NEXT: [[TMP85:%.*]] = phi <4 x i32> [ [[TMP79]], %[[PRED_LOAD_CONTINUE23]] ], [ [[TMP84]], %[[PRED_LOAD_IF24]] ]
-; IC8-NEXT: [[TMP86:%.*]] = extractelement <4 x i1> [[TMP12]], i64 2
-; IC8-NEXT: br i1 [[TMP86]], label %[[PRED_LOAD_IF26:.*]], label %[[PRED_LOAD_CONTINUE27:.*]]
-; IC8: [[PRED_LOAD_IF26]]:
-; IC8-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[TMP20]], i64 2
-; IC8-NEXT: [[TMP88:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP87]]
-; IC8-NEXT: [[TMP89:%.*]] = load i32, ptr [[TMP88]], align 4
-; IC8-NEXT: [[TMP90:%.*]] = insertelement <4 x i32> [[TMP85]], i32 [[TMP89]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE27]]
-; IC8: [[PRED_LOAD_CONTINUE27]]:
-; IC8-NEXT: [[TMP91:%.*]] = phi <4 x i32> [ [[TMP85]], %[[PRED_LOAD_CONTINUE25]] ], [ [[TMP90]], %[[PRED_LOAD_IF26]] ]
-; IC8-NEXT: [[TMP92:%.*]] = extractelement <4 x i1> [[TMP12]], i64 3
-; IC8-NEXT: br i1 [[TMP92]], label %[[PRED_LOAD_IF28:.*]], label %[[PRED_LOAD_CONTINUE29:.*]]
-; IC8: [[PRED_LOAD_IF28]]:
-; IC8-NEXT: [[TMP93:%.*]] = extractelement <4 x i32> [[TMP20]], i64 3
-; IC8-NEXT: [[TMP94:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP93]]
-; IC8-NEXT: [[TMP95:%.*]] = load i32, ptr [[TMP94]], align 4
-; IC8-NEXT: [[TMP96:%.*]] = insertelement <4 x i32> [[TMP91]], i32 [[TMP95]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE29]]
-; IC8: [[PRED_LOAD_CONTINUE29]]:
-; IC8-NEXT: [[TMP97:%.*]] = phi <4 x i32> [ [[TMP91]], %[[PRED_LOAD_CONTINUE27]] ], [ [[TMP96]], %[[PRED_LOAD_IF28]] ]
-; IC8-NEXT: [[TMP98:%.*]] = extractelement <4 x i1> [[TMP13]], i64 0
-; IC8-NEXT: br i1 [[TMP98]], label %[[PRED_LOAD_IF30:.*]], label %[[PRED_LOAD_CONTINUE31:.*]]
-; IC8: [[PRED_LOAD_IF30]]:
-; IC8-NEXT: [[TMP99:%.*]] = extractelement <4 x i32> [[TMP21]], i64 0
-; IC8-NEXT: [[TMP100:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP99]]
-; IC8-NEXT: [[TMP101:%.*]] = load i32, ptr [[TMP100]], align 4
-; IC8-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> poison, i32 [[TMP101]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE31]]
-; IC8: [[PRED_LOAD_CONTINUE31]]:
-; IC8-NEXT: [[TMP103:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE29]] ], [ [[TMP102]], %[[PRED_LOAD_IF30]] ]
-; IC8-NEXT: [[TMP104:%.*]] = extractelement <4 x i1> [[TMP13]], i64 1
-; IC8-NEXT: br i1 [[TMP104]], label %[[PRED_LOAD_IF32:.*]], label %[[PRED_LOAD_CONTINUE33:.*]]
-; IC8: [[PRED_LOAD_IF32]]:
-; IC8-NEXT: [[TMP105:%.*]] = extractelement <4 x i32> [[TMP21]], i64 1
-; IC8-NEXT: [[TMP106:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP105]]
-; IC8-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP106]], align 4
-; IC8-NEXT: [[TMP108:%.*]] = insertelement <4 x i32> [[TMP103]], i32 [[TMP107]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE33]]
-; IC8: [[PRED_LOAD_CONTINUE33]]:
-; IC8-NEXT: [[TMP109:%.*]] = phi <4 x i32> [ [[TMP103]], %[[PRED_LOAD_CONTINUE31]] ], [ [[TMP108]], %[[PRED_LOAD_IF32]] ]
-; IC8-NEXT: [[TMP110:%.*]] = extractelement <4 x i1> [[TMP13]], i64 2
-; IC8-NEXT: br i1 [[TMP110]], label %[[PRED_LOAD_IF34:.*]], label %[[PRED_LOAD_CONTINUE35:.*]]
-; IC8: [[PRED_LOAD_IF34]]:
-; IC8-NEXT: [[TMP111:%.*]] = extractelement <4 x i32> [[TMP21]], i64 2
-; IC8-NEXT: [[TMP112:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP111]]
-; IC8-NEXT: [[TMP113:%.*]] = load i32, ptr [[TMP112]], align 4
-; IC8-NEXT: [[TMP114:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP113]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE35]]
-; IC8: [[PRED_LOAD_CONTINUE35]]:
-; IC8-NEXT: [[TMP115:%.*]] = phi <4 x i32> [ [[TMP109]], %[[PRED_LOAD_CONTINUE33]] ], [ [[TMP114]], %[[PRED_LOAD_IF34]] ]
-; IC8-NEXT: [[TMP116:%.*]] = extractelement <4 x i1> [[TMP13]], i64 3
-; IC8-NEXT: br i1 [[TMP116]], label %[[PRED_LOAD_IF36:.*]], label %[[PRED_LOAD_CONTINUE37:.*]]
-; IC8: [[PRED_LOAD_IF36]]:
-; IC8-NEXT: [[TMP117:%.*]] = extractelement <4 x i32> [[TMP21]], i64 3
-; IC8-NEXT: [[TMP118:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP117]]
-; IC8-NEXT: [[TMP119:%.*]] = load i32, ptr [[TMP118]], align 4
-; IC8-NEXT: [[TMP120:%.*]] = insertelement <4 x i32> [[TMP115]], i32 [[TMP119]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE37]]
-; IC8: [[PRED_LOAD_CONTINUE37]]:
-; IC8-NEXT: [[TMP121:%.*]] = phi <4 x i32> [ [[TMP115]], %[[PRED_LOAD_CONTINUE35]] ], [ [[TMP120]], %[[PRED_LOAD_IF36]] ]
-; IC8-NEXT: [[TMP122:%.*]] = extractelement <4 x i1> [[TMP14]], i64 0
-; IC8-NEXT: br i1 [[TMP122]], label %[[PRED_LOAD_IF38:.*]], label %[[PRED_LOAD_CONTINUE39:.*]]
-; IC8: [[PRED_LOAD_IF38]]:
-; IC8-NEXT: [[TMP123:%.*]] = extractelement <4 x i32> [[TMP22]], i64 0
-; IC8-NEXT: [[TMP124:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP123]]
-; IC8-NEXT: [[TMP125:%.*]] = load i32, ptr [[TMP124]], align 4
-; IC8-NEXT: [[TMP126:%.*]] = insertelement <4 x i32> poison, i32 [[TMP125]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE39]]
-; IC8: [[PRED_LOAD_CONTINUE39]]:
-; IC8-NEXT: [[TMP127:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE37]] ], [ [[TMP126]], %[[PRED_LOAD_IF38]] ]
-; IC8-NEXT: [[TMP128:%.*]] = extractelement <4 x i1> [[TMP14]], i64 1
-; IC8-NEXT: br i1 [[TMP128]], label %[[PRED_LOAD_IF40:.*]], label %[[PRED_LOAD_CONTINUE41:.*]]
-; IC8: [[PRED_LOAD_IF40]]:
-; IC8-NEXT: [[TMP129:%.*]] = extractelement <4 x i32> [[TMP22]], i64 1
-; IC8-NEXT: [[TMP130:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP129]]
-; IC8-NEXT: [[TMP131:%.*]] = load i32, ptr [[TMP130]], align 4
-; IC8-NEXT: [[TMP132:%.*]] = insertelement <4 x i32> [[TMP127]], i32 [[TMP131]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE41]]
-; IC8: [[PRED_LOAD_CONTINUE41]]:
-; IC8-NEXT: [[TMP133:%.*]] = phi <4 x i32> [ [[TMP127]], %[[PRED_LOAD_CONTINUE39]] ], [ [[TMP132]], %[[PRED_LOAD_IF40]] ]
-; IC8-NEXT: [[TMP134:%.*]] = extractelement <4 x i1> [[TMP14]], i64 2
-; IC8-NEXT: br i1 [[TMP134]], label %[[PRED_LOAD_IF42:.*]], label %[[PRED_LOAD_CONTINUE43:.*]]
-; IC8: [[PRED_LOAD_IF42]]:
-; IC8-NEXT: [[TMP135:%.*]] = extractelement <4 x i32> [[TMP22]], i64 2
-; IC8-NEXT: [[TMP136:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP135]]
-; IC8-NEXT: [[TMP137:%.*]] = load i32, ptr [[TMP136]], align 4
-; IC8-NEXT: [[TMP138:%.*]] = insertelement <4 x i32> [[TMP133]], i32 [[TMP137]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE43]]
-; IC8: [[PRED_LOAD_CONTINUE43]]:
-; IC8-NEXT: [[TMP139:%.*]] = phi <4 x i32> [ [[TMP133]], %[[PRED_LOAD_CONTINUE41]] ], [ [[TMP138]], %[[PRED_LOAD_IF42]] ]
-; IC8-NEXT: [[TMP140:%.*]] = extractelement <4 x i1> [[TMP14]], i64 3
-; IC8-NEXT: br i1 [[TMP140]], label %[[PRED_LOAD_IF44:.*]], label %[[PRED_LOAD_CONTINUE45:.*]]
-; IC8: [[PRED_LOAD_IF44]]:
-; IC8-NEXT: [[TMP141:%.*]] = extractelement <4 x i32> [[TMP22]], i64 3
-; IC8-NEXT: [[TMP142:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP141]]
-; IC8-NEXT: [[TMP143:%.*]] = load i32, ptr [[TMP142]], align 4
-; IC8-NEXT: [[TMP144:%.*]] = insertelement <4 x i32> [[TMP139]], i32 [[TMP143]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE45]]
-; IC8: [[PRED_LOAD_CONTINUE45]]:
-; IC8-NEXT: [[TMP145:%.*]] = phi <4 x i32> [ [[TMP139]], %[[PRED_LOAD_CONTINUE43]] ], [ [[TMP144]], %[[PRED_LOAD_IF44]] ]
-; IC8-NEXT: [[TMP146:%.*]] = extractelement <4 x i1> [[TMP15]], i64 0
-; IC8-NEXT: br i1 [[TMP146]], label %[[PRED_LOAD_IF46:.*]], label %[[PRED_LOAD_CONTINUE47:.*]]
-; IC8: [[PRED_LOAD_IF46]]:
-; IC8-NEXT: [[TMP147:%.*]] = extractelement <4 x i32> [[TMP23]], i64 0
-; IC8-NEXT: [[TMP148:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP147]]
-; IC8-NEXT: [[TMP149:%.*]] = load i32, ptr [[TMP148]], align 4
-; IC8-NEXT: [[TMP150:%.*]] = insertelement <4 x i32> poison, i32 [[TMP149]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE47]]
-; IC8: [[PRED_LOAD_CONTINUE47]]:
-; IC8-NEXT: [[TMP151:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE45]] ], [ [[TMP150]], %[[PRED_LOAD_IF46]] ]
-; IC8-NEXT: [[TMP152:%.*]] = extractelement <4 x i1> [[TMP15]], i64 1
-; IC8-NEXT: br i1 [[TMP152]], label %[[PRED_LOAD_IF48:.*]], label %[[PRED_LOAD_CONTINUE49:.*]]
-; IC8: [[PRED_LOAD_IF48]]:
-; IC8-NEXT: [[TMP153:%.*]] = extractelement <4 x i32> [[TMP23]], i64 1
-; IC8-NEXT: [[TMP154:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP153]]
-; IC8-NEXT: [[TMP155:%.*]] = load i32, ptr [[TMP154]], align 4
-; IC8-NEXT: [[TMP156:%.*]] = insertelement <4 x i32> [[TMP151]], i32 [[TMP155]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE49]]
-; IC8: [[PRED_LOAD_CONTINUE49]]:
-; IC8-NEXT: [[TMP157:%.*]] = phi <4 x i32> [ [[TMP151]], %[[PRED_LOAD_CONTINUE47]] ], [ [[TMP156]], %[[PRED_LOAD_IF48]] ]
-; IC8-NEXT: [[TMP158:%.*]] = extractelement <4 x i1> [[TMP15]], i64 2
-; IC8-NEXT: br i1 [[TMP158]], label %[[PRED_LOAD_IF50:.*]], label %[[PRED_LOAD_CONTINUE51:.*]]
-; IC8: [[PRED_LOAD_IF50]]:
-; IC8-NEXT: [[TMP159:%.*]] = extractelement <4 x i32> [[TMP23]], i64 2
-; IC8-NEXT: [[TMP160:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP159]]
-; IC8-NEXT: [[TMP161:%.*]] = load i32, ptr [[TMP160]], align 4
-; IC8-NEXT: [[TMP162:%.*]] = insertelement <4 x i32> [[TMP157]], i32 [[TMP161]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE51]]
-; IC8: [[PRED_LOAD_CONTINUE51]]:
-; IC8-NEXT: [[TMP163:%.*]] = phi <4 x i32> [ [[TMP157]], %[[PRED_LOAD_CONTINUE49]] ], [ [[TMP162]], %[[PRED_LOAD_IF50]] ]
-; IC8-NEXT: [[TMP164:%.*]] = extractelement <4 x i1> [[TMP15]], i64 3
-; IC8-NEXT: br i1 [[TMP164]], label %[[PRED_LOAD_IF52:.*]], label %[[PRED_LOAD_CONTINUE53:.*]]
-; IC8: [[PRED_LOAD_IF52]]:
-; IC8-NEXT: [[TMP165:%.*]] = extractelement <4 x i32> [[TMP23]], i64 3
-; IC8-NEXT: [[TMP166:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP165]]
-; IC8-NEXT: [[TMP167:%.*]] = load i32, ptr [[TMP166]], align 4
-; IC8-NEXT: [[TMP168:%.*]] = insertelement <4 x i32> [[TMP163]], i32 [[TMP167]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE53]]
-; IC8: [[PRED_LOAD_CONTINUE53]]:
-; IC8-NEXT: [[TMP169:%.*]] = phi <4 x i32> [ [[TMP163]], %[[PRED_LOAD_CONTINUE51]] ], [ [[TMP168]], %[[PRED_LOAD_IF52]] ]
-; IC8-NEXT: [[TMP170:%.*]] = extractelement <4 x i1> [[TMP16]], i64 0
-; IC8-NEXT: br i1 [[TMP170]], label %[[PRED_LOAD_IF54:.*]], label %[[PRED_LOAD_CONTINUE55:.*]]
-; IC8: [[PRED_LOAD_IF54]]:
-; IC8-NEXT: [[TMP171:%.*]] = extractelement <4 x i32> [[TMP24]], i64 0
+; IC8-NEXT: [[TMP171:%.*]] = urem i32 [[INDEX]], 16
+; IC8-NEXT: [[TMP177:%.*]] = urem i32 [[TMP0]], 16
+; IC8-NEXT: [[TMP183:%.*]] = urem i32 [[TMP1]], 16
+; IC8-NEXT: [[TMP189:%.*]] = urem i32 [[TMP18]], 16
+; IC8-NEXT: [[TMP195:%.*]] = urem i32 [[TMP19]], 16
+; IC8-NEXT: [[TMP201:%.*]] = urem i32 [[TMP20]], 16
+; IC8-NEXT: [[TMP207:%.*]] = urem i32 [[TMP21]], 16
+; IC8-NEXT: [[TMP213:%.*]] = urem i32 [[TMP22]], 16
; IC8-NEXT: [[TMP172:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP171]]
-; IC8-NEXT: [[TMP173:%.*]] = load i32, ptr [[TMP172]], align 4
-; IC8-NEXT: [[TMP174:%.*]] = insertelement <4 x i32> poison, i32 [[TMP173]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE55]]
-; IC8: [[PRED_LOAD_CONTINUE55]]:
-; IC8-NEXT: [[TMP175:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE53]] ], [ [[TMP174]], %[[PRED_LOAD_IF54]] ]
-; IC8-NEXT: [[TMP176:%.*]] = extractelement <4 x i1> [[TMP16]], i64 1
-; IC8-NEXT: br i1 [[TMP176]], label %[[PRED_LOAD_IF56:.*]], label %[[PRED_LOAD_CONTINUE57:.*]]
-; IC8: [[PRED_LOAD_IF56]]:
-; IC8-NEXT: [[TMP177:%.*]] = extractelement <4 x i32> [[TMP24]], i64 1
; IC8-NEXT: [[TMP178:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP177]]
-; IC8-NEXT: [[TMP179:%.*]] = load i32, ptr [[TMP178]], align 4
-; IC8-NEXT: [[TMP180:%.*]] = insertelement <4 x i32> [[TMP175]], i32 [[TMP179]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE57]]
-; IC8: [[PRED_LOAD_CONTINUE57]]:
-; IC8-NEXT: [[TMP181:%.*]] = phi <4 x i32> [ [[TMP175]], %[[PRED_LOAD_CONTINUE55]] ], [ [[TMP180]], %[[PRED_LOAD_IF56]] ]
-; IC8-NEXT: [[TMP182:%.*]] = extractelement <4 x i1> [[TMP16]], i64 2
-; IC8-NEXT: br i1 [[TMP182]], label %[[PRED_LOAD_IF58:.*]], label %[[PRED_LOAD_CONTINUE59:.*]]
-; IC8: [[PRED_LOAD_IF58]]:
-; IC8-NEXT: [[TMP183:%.*]] = extractelement <4 x i32> [[TMP24]], i64 2
; IC8-NEXT: [[TMP184:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP183]]
-; IC8-NEXT: [[TMP185:%.*]] = load i32, ptr [[TMP184]], align 4
-; IC8-NEXT: [[TMP186:%.*]] = insertelement <4 x i32> [[TMP181]], i32 [[TMP185]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE59]]
-; IC8: [[PRED_LOAD_CONTINUE59]]:
-; IC8-NEXT: [[TMP187:%.*]] = phi <4 x i32> [ [[TMP181]], %[[PRED_LOAD_CONTINUE57]] ], [ [[TMP186]], %[[PRED_LOAD_IF58]] ]
-; IC8-NEXT: [[TMP188:%.*]] = extractelement <4 x i1> [[TMP16]], i64 3
-; IC8-NEXT: br i1 [[TMP188]], label %[[PRED_LOAD_IF60:.*]], label %[[PRED_LOAD_CONTINUE61:.*]]
-; IC8: [[PRED_LOAD_IF60]]:
-; IC8-NEXT: [[TMP189:%.*]] = extractelement <4 x i32> [[TMP24]], i64 3
; IC8-NEXT: [[TMP190:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP189]]
-; IC8-NEXT: [[TMP191:%.*]] = load i32, ptr [[TMP190]], align 4
-; IC8-NEXT: [[TMP192:%.*]] = insertelement <4 x i32> [[TMP187]], i32 [[TMP191]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE61]]
-; IC8: [[PRED_LOAD_CONTINUE61]]:
-; IC8-NEXT: [[TMP193:%.*]] = phi <4 x i32> [ [[TMP187]], %[[PRED_LOAD_CONTINUE59]] ], [ [[TMP192]], %[[PRED_LOAD_IF60]] ]
-; IC8-NEXT: [[TMP194:%.*]] = extractelement <4 x i1> [[TMP17]], i64 0
-; IC8-NEXT: br i1 [[TMP194]], label %[[PRED_LOAD_IF62:.*]], label %[[PRED_LOAD_CONTINUE63:.*]]
-; IC8: [[PRED_LOAD_IF62]]:
-; IC8-NEXT: [[TMP195:%.*]] = extractelement <4 x i32> [[TMP25]], i64 0
; IC8-NEXT: [[TMP196:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP195]]
-; IC8-NEXT: [[TMP197:%.*]] = load i32, ptr [[TMP196]], align 4
-; IC8-NEXT: [[TMP198:%.*]] = insertelement <4 x i32> poison, i32 [[TMP197]], i64 0
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE63]]
-; IC8: [[PRED_LOAD_CONTINUE63]]:
-; IC8-NEXT: [[TMP199:%.*]] = phi <4 x i32> [ poison, %[[PRED_LOAD_CONTINUE61]] ], [ [[TMP198]], %[[PRED_LOAD_IF62]] ]
-; IC8-NEXT: [[TMP200:%.*]] = extractelement <4 x i1> [[TMP17]], i64 1
-; IC8-NEXT: br i1 [[TMP200]], label %[[PRED_LOAD_IF64:.*]], label %[[PRED_LOAD_CONTINUE65:.*]]
-; IC8: [[PRED_LOAD_IF64]]:
-; IC8-NEXT: [[TMP201:%.*]] = extractelement <4 x i32> [[TMP25]], i64 1
; IC8-NEXT: [[TMP202:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP201]]
-; IC8-NEXT: [[TMP203:%.*]] = load i32, ptr [[TMP202]], align 4
-; IC8-NEXT: [[TMP204:%.*]] = insertelement <4 x i32> [[TMP199]], i32 [[TMP203]], i64 1
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE65]]
-; IC8: [[PRED_LOAD_CONTINUE65]]:
-; IC8-NEXT: [[TMP205:%.*]] = phi <4 x i32> [ [[TMP199]], %[[PRED_LOAD_CONTINUE63]] ], [ [[TMP204]], %[[PRED_LOAD_IF64]] ]
-; IC8-NEXT: [[TMP206:%.*]] = extractelement <4 x i1> [[TMP17]], i64 2
-; IC8-NEXT: br i1 [[TMP206]], label %[[PRED_LOAD_IF66:.*]], label %[[PRED_LOAD_CONTINUE67:.*]]
-; IC8: [[PRED_LOAD_IF66]]:
-; IC8-NEXT: [[TMP207:%.*]] = extractelement <4 x i32> [[TMP25]], i64 2
; IC8-NEXT: [[TMP208:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP207]]
-; IC8-NEXT: [[TMP209:%.*]] = load i32, ptr [[TMP208]], align 4
-; IC8-NEXT: [[TMP210:%.*]] = insertelement <4 x i32> [[TMP205]], i32 [[TMP209]], i64 2
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE67]]
-; IC8: [[PRED_LOAD_CONTINUE67]]:
-; IC8-NEXT: [[TMP211:%.*]] = phi <4 x i32> [ [[TMP205]], %[[PRED_LOAD_CONTINUE65]] ], [ [[TMP210]], %[[PRED_LOAD_IF66]] ]
-; IC8-NEXT: [[TMP212:%.*]] = extractelement <4 x i1> [[TMP17]], i64 3
-; IC8-NEXT: br i1 [[TMP212]], label %[[PRED_LOAD_IF68:.*]], label %[[PRED_LOAD_CONTINUE69]]
-; IC8: [[PRED_LOAD_IF68]]:
-; IC8-NEXT: [[TMP213:%.*]] = extractelement <4 x i32> [[TMP25]], i64 3
; IC8-NEXT: [[TMP214:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[TMP213]]
-; IC8-NEXT: [[TMP215:%.*]] = load i32, ptr [[TMP214]], align 4
-; IC8-NEXT: [[TMP216:%.*]] = insertelement <4 x i32> [[TMP211]], i32 [[TMP215]], i64 3
-; IC8-NEXT: br label %[[PRED_LOAD_CONTINUE69]]
-; IC8: [[PRED_LOAD_CONTINUE69]]:
-; IC8-NEXT: [[TMP217:%.*]] = phi <4 x i32> [ [[TMP211]], %[[PRED_LOAD_CONTINUE67]] ], [ [[TMP216]], %[[PRED_LOAD_IF68]] ]
+; IC8-NEXT: [[TMP49:%.*]] = load <4 x i32>, ptr [[TMP172]], align 4
+; IC8-NEXT: [[TMP73:%.*]] = load <4 x i32>, ptr [[TMP178]], align 4
+; IC8-NEXT: [[TMP97:%.*]] = load <4 x i32>, ptr [[TMP184]], align 4
+; IC8-NEXT: [[TMP121:%.*]] = load <4 x i32>, ptr [[TMP190]], align 4
+; IC8-NEXT: [[TMP145:%.*]] = load <4 x i32>, ptr [[TMP196]], align 4
+; IC8-NEXT: [[TMP169:%.*]] = load <4 x i32>, ptr [[TMP202]], align 4
+; IC8-NEXT: [[TMP193:%.*]] = load <4 x i32>, ptr [[TMP208]], align 4
+; IC8-NEXT: [[TMP217:%.*]] = load <4 x i32>, ptr [[TMP214]], align 4
; IC8-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP10]], <4 x i32> [[TMP49]], <4 x i32> zeroinitializer
; IC8-NEXT: [[PREDPHI70:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP73]], <4 x i32> zeroinitializer
; IC8-NEXT: [[PREDPHI71:%.*]] = select <4 x i1> [[TMP12]], <4 x i32> [[TMP97]], <4 x i32> zeroinitializer
>From c54d9e90157791057fc202eee114e041411c9ac2 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Mon, 27 Jul 2026 10:54:59 +0100
Subject: [PATCH 3/3] !fixup address comments, thanks
---
llvm/lib/Analysis/LoopAccessAnalysis.cpp | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
index dd996fe0e4382..d6455b6cd9ac7 100644
--- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
+++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
@@ -1713,15 +1713,17 @@ uint64_t llvm::getBoundForConsecutiveLoad(const SCEV *PtrSCEV, Type *AccessTy,
if (AccessTy->isScalableTy())
return 0;
- // `A[i % 2^N]` is `Base + ElemSize * zext({0,+,1}<iN>)`. For a byte
- // element (ElemSize == 1) the multiply folds away.
+ // `A[i % 2^N]` is modeled as `Base + ElemSize * zext({0,+,1}<iN>)`by SCEV,
+ // with N being the bitwidth of the induction. For a byte element (ElemSize ==
+ // 1) the multiply folds away.
const SCEV *Base, *Start;
const APInt *Scale = nullptr;
auto Index = m_scev_ZExt(
m_scev_AffineAddRec(m_SCEV(Start), m_scev_One(), m_SpecificLoop(L)));
- if (!match(PtrSCEV, m_scev_Add(m_scev_Mul(m_scev_APInt(Scale), Index),
- m_SCEV(Base))) &&
- !match(PtrSCEV, m_scev_Add(Index, m_SCEV(Base))))
+ if (!match(
+ PtrSCEV,
+ m_scev_Add(m_CombineOr(Index, m_scev_Mul(m_scev_APInt(Scale), Index)),
+ m_SCEV(Base))))
return 0;
uint64_t AllocSize =
More information about the llvm-commits
mailing list