[llvm] afd4c46 - [AArch64] Preserve store memoperand (#210936)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 30 21:51:31 PDT 2026
Author: Kamlesh Kumar
Date: 2026-07-31T05:51:26+01:00
New Revision: afd4c46353bf77b9f4ebfde664e4fcf8d2ef2fc8
URL: https://github.com/llvm/llvm-project/commit/afd4c46353bf77b9f4ebfde664e4fcf8d2ef2fc8
DIFF: https://github.com/llvm/llvm-project/commit/afd4c46353bf77b9f4ebfde664e4fcf8d2ef2fc8.diff
LOG: [AArch64] Preserve store memoperand (#210936)
Added:
llvm/test/CodeGen/AArch64/sve-structured-store-memoperands.ll
Modified:
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 4ade8a4a51c91..f6b90594b064e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -2617,6 +2617,10 @@ void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs,
N->getOperand(0)}; // chain
SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
+ // Transfer memoperands.
+ MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
+ CurDAG->setNodeMemRefs(cast<MachineSDNode>(St), {MemOp});
+
ReplaceNode(N, St);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 492ebdb7aace0..f1a91a5537ee0 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18431,6 +18431,14 @@ setInfoSVEStN(const AArch64TargetLowering &TLI, const DataLayout &DL,
EC * NumVecs);
Info.ptrVal = CI.getArgOperand(CI.arg_size() - 1);
Info.offset = 0;
+ // Unless all predicate lanes are known to be active, the full scalable
+ // vector size is only an upper bound on the memory accessed, which
+ // MachineMemOperand cannot represent so set it unknown.
+ // `NumVecs` used in operand below because predicate is after
+ // all vector i.e. stN(vec0, ..., vecN-1, predicate, pointer)
+ const auto *Pred = dyn_cast<Constant>(CI.getArgOperand(NumVecs));
+ if (!Pred || !Pred->isAllOnesValue())
+ Info.size = MemoryLocation::UnknownSize;
Info.align.reset();
Info.flags = MachineMemOperand::MOStore;
}
@@ -18445,14 +18453,17 @@ void AArch64TargetLowering::getTgtMemIntrinsic(
auto &DL = I.getDataLayout();
switch (Intrinsic) {
case Intrinsic::aarch64_sve_st2:
+ case Intrinsic::aarch64_sve_st2q:
setInfoSVEStN<2>(*this, DL, Info, I);
Infos.push_back(Info);
return;
case Intrinsic::aarch64_sve_st3:
+ case Intrinsic::aarch64_sve_st3q:
setInfoSVEStN<3>(*this, DL, Info, I);
Infos.push_back(Info);
return;
case Intrinsic::aarch64_sve_st4:
+ case Intrinsic::aarch64_sve_st4q:
setInfoSVEStN<4>(*this, DL, Info, I);
Infos.push_back(Info);
return;
@@ -34431,7 +34442,8 @@ SDValue AArch64TargetLowering::LowerVECTOR_INTERLEAVE(SDValue Op,
Align Alignment = DAG.getReducedAlign(OpVT, /*UseABI=*/false);
SDValue StackPtr =
DAG.CreateStackTemporary(OpVT.getStoreSize() * 3, Alignment);
-
+ MachinePointerInfo StackPtrInfo = MachinePointerInfo::getFixedStack(
+ DAG.getMachineFunction(), cast<FrameIndexSDNode>(StackPtr)->getIndex());
SmallVector<SDValue, 6> Ops;
Ops.push_back(DAG.getEntryNode());
Ops.push_back(
@@ -34445,7 +34457,7 @@ SDValue AArch64TargetLowering::LowerVECTOR_INTERLEAVE(SDValue Op,
OpVT.getVectorNumElements() * 3);
SDValue Chain = DAG.getMemIntrinsicNode(
ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), Ops, TripleOpVT,
- MachinePointerInfo(), Alignment, MachineMemOperand::MOStore);
+ StackPtrInfo, Alignment, MachineMemOperand::MOStore);
SmallVector<SDValue, 3> Results;
for (unsigned I = 0; I < 3; ++I) {
@@ -34467,6 +34479,8 @@ SDValue AArch64TargetLowering::LowerVECTOR_INTERLEAVE(SDValue Op,
Align Alignment = DAG.getReducedAlign(PackedVT, /*UseABI=*/false);
SDValue StackPtr =
DAG.CreateStackTemporary(PackedVT.getStoreSize() * 3, Alignment);
+ MachinePointerInfo StackPtrInfo = MachinePointerInfo::getFixedStack(
+ DAG.getMachineFunction(), cast<FrameIndexSDNode>(StackPtr)->getIndex());
Intrinsic::ID IntID = Intrinsic::aarch64_sve_st3;
EVT PredVT = PackedVT.changeVectorElementType(*DAG.getContext(), MVT::i1);
@@ -34479,7 +34493,12 @@ SDValue AArch64TargetLowering::LowerVECTOR_INTERLEAVE(SDValue Op,
Ops.push_back(StackPtr);
// Interleave operands and store.
- SDValue Chain = DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops);
+ EVT TriplePackedVT =
+ EVT::getVectorVT(*DAG.getContext(), PackedVT.getVectorElementType(),
+ PackedVT.getVectorElementCount() * 3);
+ SDValue Chain = DAG.getMemIntrinsicNode(
+ ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), Ops, TriplePackedVT,
+ StackPtrInfo, Alignment, MachineMemOperand::MOStore);
// Read back the interleaved data.
SmallVector<SDValue, 3> Results;
diff --git a/llvm/test/CodeGen/AArch64/sve-structured-store-memoperands.ll b/llvm/test/CodeGen/AArch64/sve-structured-store-memoperands.ll
new file mode 100644
index 0000000000000..cc8648737dfee
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-structured-store-memoperands.ll
@@ -0,0 +1,199 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=aarch64-isel -verify-machineinstrs -o - < %s | FileCheck %s
+
+define void @st2b_imm_mmo(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1,
+ ; CHECK-LABEL: name: st2b_imm_mmo
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $z0, $z1, $p0, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z1
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY $z0
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:zpr2 = REG_SEQUENCE [[COPY3]], %subreg.zsub0, [[COPY2]], %subreg.zsub1
+ ; CHECK-NEXT: ST2B_IMM killed [[REG_SEQUENCE]], [[COPY1]], [[COPY]], 1 :: (store unknown-size into %ir.base, align 32)
+ ; CHECK-NEXT: RET_ReallyLR
+ <vscale x 16 x i1> %pred, ptr %addr) {
+ %base = getelementptr <vscale x 16 x i8>, ptr %addr, i64 2, i64 0
+ call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
+ <vscale x 16 x i8> %v1,
+ <vscale x 16 x i1> %pred,
+ ptr %base)
+ ret void
+}
+
+define void @st2b_reg_mmo(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1,
+ ; CHECK-LABEL: name: st2b_reg_mmo
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $z0, $z1, $p0, $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY $p0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY $z1
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY $z0
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:zpr2 = REG_SEQUENCE [[COPY4]], %subreg.zsub0, [[COPY3]], %subreg.zsub1
+ ; CHECK-NEXT: [[RDVLI_XI:%[0-9]+]]:gpr64 = RDVLI_XI 1, implicit $vg
+ ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64common = MADDXrrr [[COPY]], killed [[RDVLI_XI]], $xzr
+ ; CHECK-NEXT: ST2B killed [[REG_SEQUENCE]], [[COPY2]], [[COPY1]], killed [[MADDXrrr]] :: (store unknown-size into %ir.base, align 32)
+ ; CHECK-NEXT: RET_ReallyLR
+ <vscale x 16 x i1> %pred, ptr %addr,
+ i64 %offset) {
+ %base = getelementptr <vscale x 16 x i8>, ptr %addr, i64 %offset, i64 0
+ call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
+ <vscale x 16 x i8> %v1,
+ <vscale x 16 x i1> %pred,
+ ptr %base)
+ ret void
+}
+
+define void @masked_store_mmo(<vscale x 16 x i8> %v,
+ ; CHECK-LABEL: name: masked_store_mmo
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $z0, $p0, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z0
+ ; CHECK-NEXT: ST1B_IMM [[COPY2]], [[COPY1]], [[COPY]], 0 :: (store unknown-size into %ir.addr, align 1)
+ ; CHECK-NEXT: RET_ReallyLR
+ <vscale x 16 x i1> %pred, ptr %addr) {
+ call void @llvm.masked.store.nxv16i8.p0(<vscale x 16 x i8> %v,
+ ptr align 1 %addr,
+ <vscale x 16 x i1> %pred)
+ ret void
+}
+
+define void @unpredicated_store_mmo(<vscale x 16 x i8> %v, ptr %addr) {
+ ; CHECK-LABEL: name: unpredicated_store_mmo
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $z0, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
+ ; CHECK-NEXT: STR_ZXI [[COPY1]], [[COPY]], 0 :: (store (<vscale x 1 x s128>) into %ir.addr, align 1)
+ ; CHECK-NEXT: RET_ReallyLR
+ store <vscale x 16 x i8> %v, ptr %addr, align 1
+ ret void
+}
+
+define void @st2b_ptrue_mmo(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, ptr %addr) {
+ ; CHECK-LABEL: name: st2b_ptrue_mmo
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $z0, $z1, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z0
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:zpr2 = REG_SEQUENCE [[COPY2]], %subreg.zsub0, [[COPY1]], %subreg.zsub1
+ ; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
+ ; CHECK-NEXT: ST2B_IMM killed [[REG_SEQUENCE]], killed [[PTRUE_B]], [[COPY]], 0 :: (store (<vscale x 1 x s256>) into %ir.addr)
+ ; CHECK-NEXT: RET_ReallyLR
+ call void @llvm.aarch64.sve.st2.nxv16i8(
+ <vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1,
+ <vscale x 16 x i1> splat (i1 true), ptr %addr)
+ ret void
+}
+
+define void @st2q_mmo(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1,
+ ; CHECK-LABEL: name: st2q_mmo
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $z0, $z1, $p0, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z1
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY $z0
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:zpr2 = REG_SEQUENCE [[COPY3]], %subreg.zsub0, [[COPY2]], %subreg.zsub1
+ ; CHECK-NEXT: ST2Q_IMM killed [[REG_SEQUENCE]], [[COPY1]], [[COPY]], 0 :: (store unknown-size into %ir.addr, align 32)
+ ; CHECK-NEXT: RET_ReallyLR
+ <vscale x 16 x i1> %pred, ptr %addr) {
+ call void @llvm.aarch64.sve.st2q.nxv16i8(<vscale x 16 x i8> %v0,
+ <vscale x 16 x i8> %v1,
+ <vscale x 16 x i1> %pred,
+ ptr %addr)
+ ret void
+}
+
+define void @st3q_mmo(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1,
+ ; CHECK-LABEL: name: st3q_mmo
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $z0, $z1, $z2, $p0, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY $z1
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY $z0
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:zpr3 = REG_SEQUENCE [[COPY4]], %subreg.zsub0, [[COPY3]], %subreg.zsub1, [[COPY2]], %subreg.zsub2
+ ; CHECK-NEXT: ST3Q_IMM killed [[REG_SEQUENCE]], [[COPY1]], [[COPY]], 0 :: (store unknown-size into %ir.addr, align 64)
+ ; CHECK-NEXT: RET_ReallyLR
+ <vscale x 16 x i8> %v2,
+ <vscale x 16 x i1> %pred, ptr %addr) {
+ call void @llvm.aarch64.sve.st3q.nxv16i8(<vscale x 16 x i8> %v0,
+ <vscale x 16 x i8> %v1,
+ <vscale x 16 x i8> %v2,
+ <vscale x 16 x i1> %pred,
+ ptr %addr)
+ ret void
+}
+
+define void @st4q_mmo(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1,
+ ; CHECK-LABEL: name: st4q_mmo
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $z0, $z1, $z2, $z3, $p0, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z3
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY $z2
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY $z1
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY $z0
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:zpr4 = REG_SEQUENCE [[COPY5]], %subreg.zsub0, [[COPY4]], %subreg.zsub1, [[COPY3]], %subreg.zsub2, [[COPY2]], %subreg.zsub3
+ ; CHECK-NEXT: ST4Q_IMM killed [[REG_SEQUENCE]], [[COPY1]], [[COPY]], 0 :: (store unknown-size into %ir.addr, align 64)
+ ; CHECK-NEXT: RET_ReallyLR
+ <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3,
+ <vscale x 16 x i1> %pred, ptr %addr) {
+ call void @llvm.aarch64.sve.st4q.nxv16i8(<vscale x 16 x i8> %v0,
+ <vscale x 16 x i8> %v1,
+ <vscale x 16 x i8> %v2,
+ <vscale x 16 x i8> %v3,
+ <vscale x 16 x i1> %pred,
+ ptr %addr)
+ ret void
+}
+
+define <vscale x 6 x half> @interleave3_nxv6f16_mmo(<vscale x 2 x half> %v0,
+ ; CHECK-LABEL: name: interleave3_nxv6f16_mmo
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $z0, $z1, $z2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z2
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY [[COPY]]
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY2]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:zpr3 = REG_SEQUENCE killed [[COPY5]], %subreg.zsub0, killed [[COPY4]], %subreg.zsub1, killed [[COPY3]], %subreg.zsub2
+ ; CHECK-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
+ ; CHECK-NEXT: ST3D_IMM killed [[REG_SEQUENCE]], killed [[PTRUE_D]], %stack.0, 0 :: (store (<vscale x 1 x s384>) into %stack.0, align 16)
+ ; CHECK-NEXT: [[LDR_ZXI:%[0-9]+]]:zpr = LDR_ZXI %stack.0, 2 :: (load (<vscale x 1 x s128>))
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:zpr = COPY killed [[LDR_ZXI]]
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:zpr = IMPLICIT_DEF
+ ; CHECK-NEXT: [[UZP1_ZZZ_S:%[0-9]+]]:zpr = UZP1_ZZZ_S killed [[COPY6]], killed [[DEF]]
+ ; CHECK-NEXT: [[LDR_ZXI1:%[0-9]+]]:zpr = LDR_ZXI %stack.0, 1 :: (load (<vscale x 1 x s128>))
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:zpr = COPY killed [[LDR_ZXI1]]
+ ; CHECK-NEXT: [[LDR_ZXI2:%[0-9]+]]:zpr = LDR_ZXI %stack.0, 0 :: (load (<vscale x 1 x s128>) from %stack.0)
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:zpr = COPY killed [[LDR_ZXI2]]
+ ; CHECK-NEXT: [[UZP1_ZZZ_S1:%[0-9]+]]:zpr = UZP1_ZZZ_S killed [[COPY8]], killed [[COPY7]]
+ ; CHECK-NEXT: [[UZP1_ZZZ_H:%[0-9]+]]:zpr = UZP1_ZZZ_H killed [[UZP1_ZZZ_S1]], killed [[UZP1_ZZZ_S]]
+ ; CHECK-NEXT: $z0 = COPY [[UZP1_ZZZ_H]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $z0
+ <vscale x 2 x half> %v1,
+ <vscale x 2 x half> %v2) {
+ %interleaved = call <vscale x 6 x half>
+ @llvm.vector.interleave3.nxv6f16(<vscale x 2 x half> %v0,
+ <vscale x 2 x half> %v1,
+ <vscale x 2 x half> %v2)
+ ret <vscale x 6 x half> %interleaved
+}
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll b/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
index 81a0cc242fc11..c497ba6f7008b 100644
--- a/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
@@ -876,8 +876,8 @@ define <vscale x 12 x i64> @interleave6_nxv12i64(<vscale x 2 x i64> %vec0, <vsca
; SME2-NEXT: mov z3.d, z7.d
; SME2-NEXT: ptrue p0.d
; SME2-NEXT: st3d { z4.d - z6.d }, p0, [sp]
-; SME2-NEXT: st3d { z1.d - z3.d }, p0, [sp, #3, mul vl]
; SME2-NEXT: ldr z0, [sp]
+; SME2-NEXT: st3d { z1.d - z3.d }, p0, [sp, #3, mul vl]
; SME2-NEXT: ldr z1, [sp, #1, mul vl]
; SME2-NEXT: ldr z2, [sp, #2, mul vl]
; SME2-NEXT: ldr z3, [sp, #3, mul vl]
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