[llvm] [X86] Match ENDBR immediates in little-endian order (PR #208754)

[Phoebe Wang via llvm-commits]

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@@ -966,30 +974,34 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
     // opcode matches in the binary
     // Here’s an example:
     // If the compiler had to generate asm for the following code:
-    // a = 0xF30F1EFA
+    // a = 0xFA1E0FF3
     // it could, for example, generate:
-    // mov 0xF30F1EFA, dword ptr[a]
+    // mov 0xFA1E0FF3, dword ptr[a]
     // In such a case, the binary would include a gadget that starts
     // with a fake ENDBR64 opcode. Therefore, we split such generation
     // into multiple operations, let it not shows in the binary
     if (N->getOpcode() == ISD::Constant) {
       MVT VT = N->getSimpleValueType(0);
-      int64_t Imm = cast<ConstantSDNode>(N)->getSExtValue();
-      int32_t EndbrImm = Subtarget->is64Bit() ? 0xF30F1EFA : 0xF30F1EFB;
-      if (Imm == EndbrImm || isEndbrImm64(Imm)) {
-        // Check that the cf-protection-branch is enabled.
-        Metadata *CFProtectionBranch =
-            MF->getFunction().getParent()->getModuleFlag(
-                "cf-protection-branch");
-        if (CFProtectionBranch || IndirectBranchTracking) {
-          SDLoc dl(N);
-          SDValue Complement = CurDAG->getConstant(~Imm, dl, VT, false, true);
-          Complement = CurDAG->getNOT(dl, Complement, VT);
-          --I;
-          CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Complement);
-          ++I;
-          MadeChange = true;
-          continue;
+      if (VT.isScalarInteger()) {
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phoebewang wrote:

Is it possible a FP constant? If not, assert for future change.

https://github.com/llvm/llvm-project/pull/208754