[llvm] 8b04cf3 - [AMDGPU] Rename packed 64-bit features to include SingleSGPR. NFCI. (#212891)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 30 19:10:52 PDT 2026
Author: Stanislav Mekhanoshin
Date: 2026-07-30T19:10:47-07:00
New Revision: 8b04cf374d4ac63edf973eb23b0566c21b6f638f
URL: https://github.com/llvm/llvm-project/commit/8b04cf374d4ac63edf973eb23b0566c21b6f638f
DIFF: https://github.com/llvm/llvm-project/commit/8b04cf374d4ac63edf973eb23b0566c21b6f638f.diff
LOG: [AMDGPU] Rename packed 64-bit features to include SingleSGPR. NFCI. (#212891)
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
llvm/lib/Target/AMDGPU/GCNSubtarget.h
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/SOPInstructions.td
llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index cd644bb993d87..2346bbb7e63c2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -749,12 +749,12 @@ defm PackedFP32SingleSGPROps : AMDGPUSubtargetFeature<"packed-fp32-single-sgpr-o
"Support packed fp32 instructions with SGPR operands propagating low to high 32 bit"
>;
-defm PackedFP64Ops : AMDGPUSubtargetFeature<"packed-fp64-ops",
- "Support packed fp64 instructions"
+defm PackedFP64SingleSGPROps : AMDGPUSubtargetFeature<"packed-fp64-single-sgpr-ops",
+ "Support packed fp64 instructions with SGPR operands propagating low to high 64 bit"
>;
-defm PackedU64Ops : AMDGPUSubtargetFeature<"packed-u64-ops",
- "Support packed uint64 instructions"
+defm PackedU64SingleSGPROps : AMDGPUSubtargetFeature<"packed-u64-single-sgpr-ops",
+ "Support packed uint64 instructions with SGPR operands propagating low to high 64 bit"
>;
defm R128A16 : AMDGPUSubtargetFeature<"r128-a16",
@@ -2355,8 +2355,8 @@ def FeatureISAVersion12_51 : FeatureSet<
FeatureFullRate64Ops,
FeatureVOP3PX2IncrementsVaVdstTwice,
FeatureDPALU_DPP,
- FeaturePackedFP64Ops,
- FeaturePackedU64Ops,
+ FeaturePackedFP64SingleSGPROps,
+ FeaturePackedU64SingleSGPROps,
FeatureGFX1251GEMMInsts,
FeatureGFX125xLowestRateWMMA,
FeatureCubeInsts,
@@ -2985,6 +2985,12 @@ def NotHasIEEEMinimumMaximumInsts : Predicate<"!Subtarget->hasIEEEMinimumMaximum
def HasAnyPackedFP32Ops : Predicate<"Subtarget->hasAnyPackedFP32Ops()">,
AssemblerPredicate<(any_of FeaturePackedFP32Ops, FeaturePackedFP32SingleSGPROps)>;
+def HasAnyPackedFP64Ops : Predicate<"Subtarget->hasAnyPackedFP64Ops()">,
+ AssemblerPredicate<(any_of FeaturePackedFP64SingleSGPROps)>;
+
+def HasAnyPackedU64Ops : Predicate<"Subtarget->hasAnyPackedU64Ops()">,
+ AssemblerPredicate<(any_of FeaturePackedU64SingleSGPROps)>;
+
def NeedsAlignedVGPRs : Predicate<"Subtarget->needsAlignedVGPRs()">,
AssemblerPredicate<(all_of FeatureRequiresAlignedVGPRs)>;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 48dbc3325ba03..6bf05f9808d78 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -770,7 +770,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
if (ST.hasVOP3PInsts() && ST.hasAddNoCarryInsts() && ST.hasIntClamp()) {
// Full set of gfx9 features.
- if (ST.hasPackedU64Ops()) {
+ if (ST.hasAnyPackedU64Ops()) {
getActionDefinitionsBuilder({G_ADD, G_SUB})
.legalFor({S64, S32, S16, V2S16, V2S64})
.clampMaxNumElementsStrict(0, S16, 2)
@@ -1009,12 +1009,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
FPOpActions.clampMaxNumElementsStrict(0, F32, 2);
}
- if (ST.hasPackedFP64Ops()) {
+ if (ST.hasAnyPackedFP64Ops()) {
FPOpActions.legalFor({V2F64});
FPOpActions.clampMaxNumElementsStrict(0, F64, 2);
}
- if (ST.hasPackedFP64Ops()) {
+ if (ST.hasAnyPackedFP64Ops()) {
FPOpActions.legalFor({V2F64});
FPOpActions.clampMaxNumElementsStrict(0, F64, 2);
}
@@ -1039,7 +1039,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
auto &MinNumMaxNum = getActionDefinitionsBuilder(
{G_FMINNUM, G_FMAXNUM, G_FMINIMUMNUM, G_FMAXIMUMNUM});
- if (ST.hasPackedFP64Ops()) {
+ if (ST.hasAnyPackedFP64Ops()) {
MinNumMaxNum.customFor(FPTypesPK16_64)
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
.clampMaxNumElements(0, S16, 2)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 4d906a7a376a6..9f2d3af93b02d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -4069,7 +4069,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
unsigned Size = Ty.getSizeInBits();
// Packed add and sub are VALU only.
- if (Subtarget.hasPackedU64Ops() && Ty.isVector() && Size == 128)
+ if (Subtarget.hasAnyPackedU64Ops() && Ty.isVector() && Size == 128)
return getDefaultMappingVOP(MI);
return getDefaultMappingSOP(MI);
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index 5fc7ef1b8bac2..231f19747092b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -315,10 +315,10 @@ GCNTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
case TargetTransformInfo::RGK_Scalar:
return TypeSize::getFixed(32);
case TargetTransformInfo::RGK_FixedWidthVector:
- return TypeSize::getFixed((ST->hasPackedFP64Ops() || ST->hasPackedU64Ops())
- ? 128
- : ST->hasAnyPackedFP32Ops() ? 64
- : 32);
+ return TypeSize::getFixed(
+ (ST->hasAnyPackedFP64Ops() || ST->hasAnyPackedU64Ops()) ? 128
+ : ST->hasAnyPackedFP32Ops() ? 64
+ : 32);
case TargetTransformInfo::RGK_ScalableVector:
return TypeSize::getScalable(0);
}
@@ -338,7 +338,7 @@ unsigned GCNTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
: (ElemWidth == 16 && ST->has16BitInsts()) ? 2
: (ElemWidth == 32 && ST->hasAnyPackedFP32Ops()) ? 2
: (ElemWidth == 64 &&
- (ST->hasPackedFP64Ops() || ST->hasPackedU64Ops()))
+ (ST->hasAnyPackedFP64Ops() || ST->hasAnyPackedU64Ops()))
? 2
: 1;
}
@@ -554,7 +554,7 @@ InstructionCost GCNTTIImpl::getArithmeticInstrCost(
return getFullRateInstrCost() * LT.first * NElts;
case ISD::ADD:
case ISD::SUB:
- if (SLT == MVT::i64 && ST->hasPackedU64Ops())
+ if (SLT == MVT::i64 && ST->hasAnyPackedU64Ops())
NElts = (NElts + 1) / 2;
[[fallthrough]];
case ISD::AND:
@@ -610,7 +610,7 @@ InstructionCost GCNTTIImpl::getArithmeticInstrCost(
if (ST->hasBF16PackedInsts() && SLT == MVT::bf16)
NElts = (NElts + 1) / 2;
if (SLT == MVT::f64) {
- if (ST->hasPackedFP64Ops())
+ if (ST->hasAnyPackedFP64Ops())
NElts = (NElts + 1) / 2;
return LT.first * NElts * get64BitInstrCost(CostKind);
}
@@ -876,8 +876,8 @@ GCNTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
if ((ST->hasVOP3PInsts() &&
(SLT == MVT::f16 || SLT == MVT::i16 ||
(SLT == MVT::bf16 && ST->hasBF16PackedInsts()))) ||
- (ST->hasPackedFP64Ops() && SLT == MVT::f64) ||
- (ST->hasPackedU64Ops() && SLT == MVT::i64)) {
+ (ST->hasAnyPackedFP64Ops() && SLT == MVT::f64) ||
+ (ST->hasAnyPackedU64Ops() && SLT == MVT::i64)) {
NElts = (NElts + 1) / 2;
} else if (SLT == MVT::f32) {
bool HasPk2FP32Op = ST->hasAnyPackedFP32Ops() &&
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 03638802ca6d0..c42ca8e19ef9c 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -753,6 +753,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return hasPackedFP32Ops() || hasPackedFP32SingleSGPROps();
};
+ bool hasAnyPackedFP64Ops() const { return hasPackedFP64SingleSGPROps(); };
+
+ bool hasAnyPackedU64Ops() const { return hasPackedU64SingleSGPROps(); };
+
/// \returns SGPR allocation granularity supported by the subtarget.
unsigned getSGPRAllocGranule() const {
return AMDGPU::getSGPRAllocGranule(getTargetID().getGPUKind());
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 5237aff2d21fc..b5e2a36ad9f19 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -915,7 +915,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
{MVT::v4f32, MVT::v8f32, MVT::v16f32, MVT::v32f32},
Custom);
}
- if (Subtarget->hasPackedFP64Ops()) {
+ if (Subtarget->hasAnyPackedFP64Ops()) {
setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG,
ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
ISD::FCANONICALIZE, ISD::BUILD_VECTOR},
@@ -930,7 +930,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
{MVT::v4f64, MVT::v8f64, MVT::v16f64, MVT::v32f64}, Custom);
}
- if (Subtarget->hasPackedU64Ops()) {
+ if (Subtarget->hasAnyPackedU64Ops()) {
setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::BUILD_VECTOR},
MVT::v2i64, Legal);
setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL},
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 0153b24cda286..36cacfd47f62c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2405,7 +2405,7 @@ def : GCNPat <
(V_PK_ADD_F64 !or(SRCMODS.NEG, SRCMODS.NEG_HI), VReg_128:$src,
!or(SRCMODS.NEG, SRCMODS.NEG_HI), (v2i64 (as_i64imm (i32 0))))
> {
- let SubtargetPredicate = HasPackedFP64Ops;
+ let SubtargetPredicate = HasPackedFP64SingleSGPROps;
}
foreach fp16vt = [f16, bf16] in {
@@ -3904,7 +3904,7 @@ multiclass SelectCanonicalizeAsMax<
def : GCNPat<
(fcanonicalize (v2f64 (VOP3PMods v2f64:$src, i32:$src_mods))),
(V_PK_MAX_NUM_F64 $src_mods, $src, $src_mods, $src)> {
- let OtherPredicates = !listconcat(f64_preds, [HasPackedFP64Ops]);
+ let OtherPredicates = !listconcat(f64_preds, [HasPackedFP64SingleSGPROps]);
}
}
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index f82ca6397c006..2c5a2b1f7d0d7 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -2148,7 +2148,7 @@ def : GCNPat<
}
// v2i64 shl is legal, we need a way to select scalar code
-let SubtargetPredicate = HasPackedU64Ops in {
+let SubtargetPredicate = HasAnyPackedU64Ops in {
def : GCNPat<
(v2i64 (UniformBinFrag<cshl_64> v2i64:$src0, v2i64:$src1)),
(v2i64 (REG_SEQUENCE SReg_128,
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index cb0e1369f94a1..8728e70ea351f 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -184,12 +184,12 @@ defm V_PK_MIN_U16 : VOP3PInst<"v_pk_min_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I1
defm V_PK_MAX_I16 : VOP3PInst<"v_pk_max_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, smax>;
defm V_PK_MAX_U16 : VOP3PInst<"v_pk_max_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, umax>;
-let SubtargetPredicate = HasPackedFP64Ops, SchedRW = [WriteDouble] in {
+let SubtargetPredicate = HasPackedFP64SingleSGPROps, SchedRW = [WriteDouble] in {
defm V_PK_MAX_NUM_F64 : VOP3PInst<"v_pk_max_num_f64", V_PK_VOP2_F64_Profile, fmaxnum_like>;
defm V_PK_MIN_NUM_F64 : VOP3PInst<"v_pk_min_num_f64", V_PK_VOP2_F64_Profile, fminnum_like>;
}
-let SubtargetPredicate = HasPackedU64Ops, SchedRW = [Write64Bit] in
+let SubtargetPredicate = HasPackedU64SingleSGPROps, SchedRW = [Write64Bit] in
defm V_PK_ADD_NC_U64 : VOP3PInst<"v_pk_add_nc_u64", V_PK_VOP2_I64_Profile, add>;
let SubtargetPredicate = HasIEEEMinimumMaximumInsts, ReadsModeReg = 0 in {
@@ -205,10 +205,10 @@ defm V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_lshlrev_b16", VOP3P_Profile<VOP_V2I16_V2
defm V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, cashr_rev_16>;
defm V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, clshr_rev_16>;
-let SubtargetPredicate = HasPackedU64Ops, SchedRW = [Write64Bit] in {
+let SubtargetPredicate = HasPackedU64SingleSGPROps, SchedRW = [Write64Bit] in {
defm V_PK_SUB_NC_U64 : VOP3PInst<"v_pk_sub_nc_u64", V_PK_VOP2_I64_Profile, sub>;
defm V_PK_LSHL_ADD_U64 : VOP3PInst<"v_pk_lshl_add_u64", V_PK_LSHL_ADD_U64_Profile>;
-} // End SubtargetPredicate = HasPackedU64Ops, , SchedRW = [Write64Bit]
+} // End SubtargetPredicate = HasPackedU64SingleSGPROps, , SchedRW = [Write64Bit]
} // End isReMaterializable = 1
let SubtargetPredicate = HasVOP3PInsts in {
@@ -571,7 +571,7 @@ def : ThreeOp_OpSelClampPats<smin, smin, V_PK_MIN3_I16>;
def : ThreeOp_OpSelClampPats<umin, umin, V_PK_MIN3_U16>;
}
-let SubtargetPredicate = HasPackedU64Ops in {
+let SubtargetPredicate = HasPackedU64SingleSGPROps in {
let AddedComplexity = 5 in
def : GCNPat<
(v2i64 (DivergentBinFrag<shl_0_to_4> (v2i64 (VOP3PMods v2i64:$src0, i32:$src0_mods)),
@@ -604,7 +604,7 @@ def : GCNPat<
(i32 (EXTRACT_SUBREG $src1, sub2)), sub1)),
$src2_mods, VSrc_v2b64:$src2)
>;
-} // End SubtargetPredicate = HasPackedU64Ops
+} // End SubtargetPredicate = HasPackedU64SingleSGPROps
// Defines patterns that extract signed 4bit from each Idx[0].
foreach Idx = [[0,28],[4,24],[8,20],[12,16],[16,12],[20,8],[24,4]] in
@@ -1473,11 +1473,11 @@ let isCommutable = 1, isReMaterializable = 1 in {
defm V_MAX_BF16_PSEUDO : VOP3Inst <"v_max_bf16", VOP_BF16_BF16_BF16>;
}
- let SubtargetPredicate = HasPackedFP64Ops, SchedRW = [WriteDouble] in {
+ let SubtargetPredicate = HasPackedFP64SingleSGPROps, SchedRW = [WriteDouble] in {
defm V_PK_FMA_F64 : VOP3PInst<"v_pk_fma_f64", V_PK_VOP3_F64_Profile, any_fma>;
defm V_PK_MUL_F64 : VOP3PInst<"v_pk_mul_f64", V_PK_VOP2_F64_Profile, any_fmul>;
defm V_PK_ADD_F64 : VOP3PInst<"v_pk_add_f64", V_PK_VOP2_F64_Profile, any_fadd>;
- } // End SubtargetPredicate = HasPackedFP64Ops, SchedRW = [WriteDouble]
+ } // End SubtargetPredicate = HasPackedFP64SingleSGPROps, SchedRW = [WriteDouble]
} // End isCommutable = 1, isReMaterializable = 1
def : AMDGPUMnemonicAlias<"v_accvgpr_read", "v_accvgpr_read_b32">;
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