[llvm] AMDGPU/GlobalISel: Switch more FP opcodes to extended LLTs (part 3) (PR #213135)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 30 13:46:12 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: vangthao95
<details>
<summary>Changes</summary>
Migrate trigonometric, division, remainder, multiply-add, and min/max opcodes to extended floating-point LLTs.
Remove redundant scalar clamps that request unsupported f128-to-f64 narrowing, while retaining required f16-to-f32 widening.
Also update the relevant MIR tests.
---
Patch is 873.15 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213135.diff
11 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+44-50)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir (+383-383)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir (+1139-1149)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir (+779-779)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir (+469-439)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir (+52-52)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaximum.mir (+147-147)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir (+609-609)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminimum.mir (+147-147)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir (+609-609)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir (+383-383)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index cfd913cea86de..840e4924c21a1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -736,8 +736,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
S32, S64, S16, V2S16
};
- const std::initializer_list<LLT> FPTypesPK16_64 = {S32, S64, S16, V2S16,
- V2S64};
+ const std::initializer_list<LLT> ExtendedFPTypesBase = {F32, F64};
+ const std::initializer_list<LLT> ExtendedFPTypes16 = {F32, F64, F16};
+ const std::initializer_list<LLT> ExtendedFPTypesPK16 = {F32, F64, F16, V2F16};
+ const std::initializer_list<LLT> ExtendedFPTypesPK16_64 = {F32, F64, F16,
+ V2F16, V2F64};
const LLT MinScalarFPTy = ST.has16BitInsts() ? S16 : S32;
const LLT MinExtendedFPTy = ST.has16BitInsts() ? F16 : F32;
@@ -989,10 +992,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
getActionDefinitionsBuilder({G_FADD, G_FMUL, G_FMA, G_FCANONICALIZE,
G_STRICT_FADD, G_STRICT_FMUL, G_STRICT_FMA})
.legalFor({F32, F64});
- auto &TrigActions = getActionDefinitionsBuilder({G_FSIN, G_FCOS})
- .customFor({S32, S64});
- auto &FDIVActions = getActionDefinitionsBuilder(G_FDIV)
- .customFor({S32, S64});
+ auto &TrigActions =
+ getActionDefinitionsBuilder({G_FSIN, G_FCOS}).customFor({F32, F64});
+ auto &FDIVActions = getActionDefinitionsBuilder(G_FDIV).customFor({F32, F64});
if (ST.has16BitInsts()) {
if (ST.hasVOP3PInsts())
@@ -1000,8 +1002,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
else
FPOpActions.legalFor({F16});
- TrigActions.customFor({S16});
- FDIVActions.customFor({S16});
+ TrigActions.customFor({F16});
+ FDIVActions.customFor({F16});
}
if (ST.hasPackedFP32Ops()) {
@@ -1023,59 +1025,52 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
getActionDefinitionsBuilder({G_FMINNUM_IEEE, G_FMAXNUM_IEEE});
if (ST.hasVOP3PInsts()) {
- MinNumMaxNumIeee.legalFor(FPTypesPK16)
+ MinNumMaxNumIeee.legalFor(ExtendedFPTypesPK16)
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
- .clampMaxNumElements(0, S16, 2)
- .clampScalar(0, S16, S64)
+ .clampMaxNumElements(0, F16, 2)
.scalarize(0);
} else if (ST.has16BitInsts()) {
- MinNumMaxNumIeee.legalFor(FPTypes16).clampScalar(0, S16, S64).scalarize(0);
+ MinNumMaxNumIeee.legalFor(ExtendedFPTypes16).scalarize(0);
} else {
- MinNumMaxNumIeee.legalFor(FPTypesBase)
- .clampScalar(0, S32, S64)
- .scalarize(0);
+ MinNumMaxNumIeee.legalFor(ExtendedFPTypesBase).scalarize(0);
}
auto &MinNumMaxNum = getActionDefinitionsBuilder(
{G_FMINNUM, G_FMAXNUM, G_FMINIMUMNUM, G_FMAXIMUMNUM});
if (ST.hasPackedFP64Ops()) {
- MinNumMaxNum.customFor(FPTypesPK16_64)
+ MinNumMaxNum.customFor(ExtendedFPTypesPK16_64)
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
- .clampMaxNumElements(0, S16, 2)
- .clampMaxNumElements(0, S64, 2)
- .clampScalar(0, S16, S64)
+ .clampMaxNumElements(0, F16, 2)
+ .clampMaxNumElements(0, F64, 2)
.scalarize(0);
} else if (ST.hasVOP3PInsts()) {
- MinNumMaxNum.customFor(FPTypesPK16)
- .moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
- .clampMaxNumElements(0, S16, 2)
- .clampScalar(0, S16, S64)
- .scalarize(0);
+ MinNumMaxNum.customFor(ExtendedFPTypesPK16)
+ .moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
+ .clampMaxNumElements(0, F16, 2)
+ .scalarize(0);
} else if (ST.has16BitInsts()) {
- MinNumMaxNum.customFor(FPTypes16)
- .clampScalar(0, S16, S64)
- .scalarize(0);
+ MinNumMaxNum.customFor(ExtendedFPTypes16).scalarize(0);
} else {
- MinNumMaxNum.customFor(FPTypesBase)
- .clampScalar(0, S32, S64)
- .scalarize(0);
+ MinNumMaxNum.customFor(ExtendedFPTypesBase).scalarize(0);
+ }
+
+ if (!ST.has16BitInsts()) {
+ MinNumMaxNumIeee.minScalar(0, F32);
+ MinNumMaxNum.minScalar(0, F32);
}
if (ST.hasVOP3PInsts())
FPOpActions.clampMaxNumElementsStrict(0, F16, 2);
FPOpActions.scalarize(0);
- if (!ST.has16BitInsts())
+ TrigActions.scalarize(0);
+ FDIVActions.scalarize(0);
+ if (!ST.has16BitInsts()) {
FPOpActions.minScalar(0, F32);
-
- TrigActions
- .scalarize(0)
- .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64);
-
- FDIVActions
- .scalarize(0)
- .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64);
+ TrigActions.minScalar(0, F32);
+ FDIVActions.minScalar(0, F32);
+ }
auto &FNegAbs = getActionDefinitionsBuilder({G_FNEG, G_FABS});
FNegAbs.legalFor(FPTypesPK16)
@@ -1191,20 +1186,19 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
// Whether this is legal depends on the floating point mode for the function.
auto &FMad = getActionDefinitionsBuilder(G_FMAD);
if (ST.hasMadF16() && ST.hasMadMacF32Insts())
- FMad.customFor({S32, S16});
+ FMad.customFor({F32, F16});
else if (ST.hasMadMacF32Insts())
- FMad.customFor({S32});
+ FMad.customFor({F32});
else if (ST.hasMadF16())
- FMad.customFor({S16});
+ FMad.customFor({F16});
FMad.scalarize(0)
.lower();
auto &FRem = getActionDefinitionsBuilder(G_FREM);
if (ST.has16BitInsts()) {
- FRem.customFor({S16, S32, S64});
+ FRem.customFor({F16, F32, F64});
} else {
- FRem.minScalar(0, S32)
- .customFor({S32, S64});
+ FRem.minScalar(0, F32).customFor({F32, F64});
}
FRem.scalarize(0);
@@ -2270,19 +2264,19 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
if (ST.hasIEEEMinimumMaximumInsts()) {
getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM})
- .legalFor(FPTypesPK16)
- .clampMaxNumElements(0, S16, 2)
+ .legalFor(ExtendedFPTypesPK16)
+ .clampMaxNumElements(0, F16, 2)
.scalarize(0);
} else if (ST.hasVOP3PInsts()) {
getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM})
- .lowerFor({V2S16})
- .clampMaxNumElementsStrict(0, S16, 2)
+ .lowerFor({V2F16})
+ .clampMaxNumElementsStrict(0, F16, 2)
.scalarize(0)
.lower();
} else {
getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM})
.scalarize(0)
- .clampScalar(0, S32, S64)
+ .clampScalar(0, F32, F64)
.lower();
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
index 1970f01423c48..d33766b79f38a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
@@ -14,33 +14,33 @@ body: |
; SI-LABEL: name: test_fcos_s32
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: $vgpr0 = COPY [[INT1]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: $vgpr0 = COPY [[INT1]](f32)
;
; VI-LABEL: name: test_fcos_s32
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; VI-NEXT: $vgpr0 = COPY [[INT1]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; VI-NEXT: $vgpr0 = COPY [[INT1]](f32)
;
; GFX9-LABEL: name: test_fcos_s32
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
- ; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = G_FCOS %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f32)
+ ; GFX9-NEXT: $vgpr0 = COPY [[INT]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = G_FCOS %0
$vgpr0 = COPY %1
...
@@ -53,33 +53,33 @@ body: |
; SI-LABEL: name: test_fcos_s64
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f64)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](f64)
;
; VI-LABEL: name: test_fcos_s64
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](s64)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f64)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f64)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](f64)
;
; GFX9-LABEL: name: test_fcos_s64
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double f0x3FC45F306DC9C883
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s64)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_FCOS %0
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f64) = G_FCONSTANT double f0x3FC45F306DC9C883
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f64) = G_FMUL [[COPY]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f64)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = G_FCOS %0
$vgpr0_vgpr1 = COPY %1
...
---
@@ -91,43 +91,43 @@ body: |
; SI-LABEL: name: test_fcos_s16
; SI: liveins: $vgpr0
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[FPEXT]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[INT1]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; VI-LABEL: name: test_fcos_s16
; VI: liveins: $vgpr0
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s16)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s16)
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f16)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f16)
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT1]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
; GFX9-LABEL: name: test_fcos_s16
; GFX9: liveins: $vgpr0
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 1.591800e-01
- ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[TRUNC]], [[C]]
- ; GFX9-NEXT: [[INT:%[0-9]+]]:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s16)
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FCOS %1
- %3:_(s32) = G_ANYEXT %2
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[C:%[0-9]+]]:_(f16) = G_FCONSTANT half 1.591800e-01
+ ; GFX9-NEXT: [[FMUL:%[0-9]+]]:_(f16) = G_FMUL [[TRUNC]], [[C]]
+ ; GFX9-NEXT: [[INT:%[0-9]+]]:_(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](f16)
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[INT]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(f16) = G_TRUNC %0
+ %2:_(f16) = G_FCOS %1
+ %3:_(i32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
@@ -140,47 +140,47 @@ body: |
; SI-LABEL: name: test_fcos_v2s32
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; SI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; SI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; SI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; SI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; SI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; SI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; SI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; SI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; SI-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](f32)
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[INT1]](f32), [[INT3]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
; VI-LABEL: name: test_fcos_v2s32
; VI: liveins: $vgpr0_vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x3E22F983
- ; VI-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[UV]], [[C]]
- ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
- ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
- ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[UV1]], [[C]]
- ; VI-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](s32)
- ; VI-NEXT: [[INT3:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT2]](s32)
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[INT1]](s32), [[INT3]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x3E22F983
+ ; VI-NEXT: [[FMUL:%[0-9]+]]:_(f32) = G_FMUL [[UV]], [[C]]
+ ; VI-NEXT: [[INT:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](f32)
+ ; VI-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](f32)
+ ; VI-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[C]]
+ ; VI-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL1]](f32)
+ ; VI-NEXT: [[INT3:...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/213135
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