[llvm] [DAGCombiner] Expose CSE for shifts of logic operations (PR #213091)

[Matt Arsenault via llvm-commits]

================
@@ -10776,6 +10777,119 @@ static SDValue combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) {
                      LogicOp->getFlags());
 }
 
+static bool matchLogicWithConstant(SDValue V, SDValue &X, SDValue &C) {
+  if (V.getOpcode() != ISD::AND && V.getOpcode() != ISD::OR &&
+      V.getOpcode() != ISD::XOR)
+    return false;
+
+  X = V.getOperand(0);
+  C = V.getOperand(1);
+  ConstantSDNode *Constant = isConstOrConstSplat(C);
----------------
arsenm wrote:

Use sd_match? 

https://github.com/llvm/llvm-project/pull/213091