[llvm] [GlobalISel] LegalizationArtifactCombiner for merge-unmerge->unmerge where src and dst of result would be different scalar/vector types (PR #213086)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 30 10:46:44 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Madhur Kumar (MadhurKumar004)
<details>
<summary>Changes</summary>
fixes: https://github.com/llvm/llvm-project/issues/177416
---
Patch is 30.56 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213086.diff
8 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h (+12-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll (+5-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir (+129)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir (+8-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll (+18-34)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll (+4-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll (-6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll (+18-34)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index d8d7ccc0bd7a7..96403a443f70f 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -1006,7 +1006,8 @@ class LegalizationArtifactCombiner {
}
// Recognize UnmergeSrc that can be unmerged to DstTy directly.
- // Types have to be either both vector or both non-vector types.
+ // Types have to be either both vector or both non-vector types, or
+ // UnmergeSrcTy is vector and DstTy is scalar.
// In case of vector types, the scalar elements need to match.
// Merge-like opcodes are combined one at the time. First one creates new
// unmerge, following should use the same unmerge (builder performs CSE).
@@ -1016,14 +1017,22 @@ class LegalizationArtifactCombiner {
// %AnotherDst:_(DstTy) = G_merge_like_opcode %2:_(EltTy), %3
//
// %Dst:_(DstTy), %AnotherDst = G_UNMERGE_VALUES %UnmergeSrc
- if (((!DstTy.isVector() && !UnmergeSrcTy.isVector()) ||
- (DstTy.isVector() && UnmergeSrcTy.isVector() &&
+ if ((!DstTy.isVector() ||
+ (UnmergeSrcTy.isVector() &&
DstTy.getScalarType() == UnmergeSrcTy.getScalarType())) &&
(Elt0UnmergeIdx % NumMIElts == 0) &&
+ (DstTy.getSizeInBits() < UnmergeSrcTy.getSizeInBits()) &&
getCoverTy(UnmergeSrcTy, DstTy) == UnmergeSrcTy) {
if (!isSequenceFromUnmerge(MI, 0, Unmerge, Elt0UnmergeIdx, NumMIElts,
EltSize, false))
return false;
+ if(!DstTy.isVector() && UnmergeSrcTy.isVector()){
+ LegalizeActionStep ActionStep = LI.getAction(
+ {TargetOpcode::G_UNMERGE_VALUES, {DstTy, UnmergeSrcTy}});
+ if(ActionStep.Action != LegalizeAction::Legal){
+ return false;
+ }
+ }
MIB.setInstrAndDebugLoc(MI);
auto NewUnmerge = MIB.buildUnmerge(DstTy, Unmerge->getSourceReg());
unsigned DstIdx = (Elt0UnmergeIdx * EltSize) / DstTy.getSizeInBits();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
index d553f16d49013..239dfa9698192 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
@@ -750,8 +750,6 @@ define amdgpu_ps i48 @s_andn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1
; GFX11-TRUE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]
; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: s_andn2_v3i16:
@@ -824,8 +822,6 @@ define amdgpu_ps i48 @s_andn2_v3i16_commute(<3 x i16> inreg %src0, <3 x i16> inr
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1
; GFX11-TRUE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1]
; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: s_andn2_v3i16_commute:
@@ -913,10 +909,7 @@ define amdgpu_ps { i48, i48 } @s_andn2_v3i16_multi_use(<3 x i16> inreg %src0, <3
; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1
; GFX11-TRUE16-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1]
; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5]
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s4, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s4, s3
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -953,20 +946,16 @@ define <3 x i16> @v_andn2_v3i16(<3 x i16> %src0, <3 x i16> %src1) {
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v5
+; GFX6-NEXT: v_xor_b32_e32 v3, 0xfff5, v3
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_xor_b32_e32 v3, 0xfff5, v3
-; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_and_b32_e32 v1, v1, v3
-; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
index 9f0ef53b922a0..b49d2abeb39c9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
@@ -1611,3 +1611,132 @@ body: |
$vgpr0 = COPY %4
$vgpr1 = COPY %5
...
+
+# Vector to scalar unmerge + merge combine tests.
+# G_UNMERGE_VALUES of a vector feeding G_MERGE_VALUES into a scalar
+# should fold to direct G_UNMERGE_VALUES of the source vector.
+
+---
+name: vector_to_scalar_merge_values
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: vector_to_scalar_merge_values
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK-NEXT: $vgpr1 = COPY [[UV3]](s32)
+ %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
+ %1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %0:_(<4 x s16>)
+ %5:_(s32) = G_MERGE_VALUES %1:_(s16), %2:_(s16)
+ %6:_(s32) = G_MERGE_VALUES %3:_(s16), %4:_(s16)
+ $vgpr0 = COPY %5:_(s32)
+ $vgpr1 = COPY %6:_(s32)
+...
+---
+name: vector_to_scalar_build_vector
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: vector_to_scalar_build_vector
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV]](<2 x s16>)
+ ; CHECK-NEXT: $vgpr1 = COPY [[UV3]](<2 x s16>)
+ %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
+ %1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %0:_(<4 x s16>)
+ %5:_(<2 x s16>) = G_BUILD_VECTOR %1:_(s16), %2:_(s16)
+ %6:_(<2 x s16>) = G_BUILD_VECTOR %3:_(s16), %4:_(s16)
+ $vgpr0 = COPY %5:_(<2 x s16>)
+ $vgpr1 = COPY %6:_(<2 x s16>)
+...
+---
+name: scalar_to_vector_no_fold
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: scalar_to_vector_no_fold
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64)
+ %3:_(<2 x s32>) = G_BUILD_VECTOR %1:_(s32), %2:_(s32)
+ $vgpr0_vgpr1 = COPY %3:_(<2 x s32>)
+...
+---
+name: equal_size_no_fold
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: equal_size_no_fold
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(<2 x s32>)
+ %3:_(s64) = G_MERGE_VALUES %1:_(s32), %2:_(s32)
+ $vgpr0_vgpr1 = COPY %3:_(s64)
+...
+---
+name: vector_to_scalar_eight_s16
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: vector_to_scalar_eight_s16
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
+ ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
+ ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
+ ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK-NEXT: $vgpr1 = COPY [[UV5]](s32)
+ ; CHECK-NEXT: $vgpr2 = COPY [[UV10]](s32)
+ ; CHECK-NEXT: $vgpr3 = COPY [[UV15]](s32)
+ %0:_(<8 x s16>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16), %5:_(s16), %6:_(s16), %7:_(s16), %8:_(s16) = G_UNMERGE_VALUES %0:_(<8 x s16>)
+ %9:_(s32) = G_MERGE_VALUES %1:_(s16), %2:_(s16)
+ %10:_(s32) = G_MERGE_VALUES %3:_(s16), %4:_(s16)
+ %11:_(s32) = G_MERGE_VALUES %5:_(s16), %6:_(s16)
+ %12:_(s32) = G_MERGE_VALUES %7:_(s16), %8:_(s16)
+ $vgpr0 = COPY %9:_(s32)
+ $vgpr1 = COPY %10:_(s32)
+ $vgpr2 = COPY %11:_(s32)
+ $vgpr3 = COPY %12:_(s32)
+...
+---
+name: non_zero_start_index
+body: |
+ bb.0.entry:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: non_zero_start_index
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: $vgpr0 = COPY [[UV1]](s32)
+ %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
+ %1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %0:_(<4 x s16>)
+ %5:_(s32) = G_MERGE_VALUES %3:_(s16), %4:_(s16)
+ $vgpr0 = COPY %5:_(s32)
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
index ef6699139ca7d..f4b3947616e0e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -414,9 +414,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV]](s64)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = G_EXTRACT %0, 0
$vgpr0_vgpr1 = COPY %1
@@ -450,9 +449,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV1]](s64)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s64) = G_EXTRACT %0, 64
$vgpr0_vgpr1 = COPY %1
@@ -467,9 +465,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p0)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV]](p0)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = G_EXTRACT %0, 0
$vgpr0_vgpr1 = COPY %1
@@ -503,9 +500,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
- ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32)
- ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](p0)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[UV1]](p0)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(p0) = G_EXTRACT %0, 64
$vgpr0_vgpr1 = COPY %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index 1d0ae809d3707..9bf7f0288cf30 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -51,14 +51,11 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_flat(i32 %node_ptr, float
define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> inreg %tdescr) {
; GFX10-LABEL: image_bvh_intersect_ray_a16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v5
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff, v7
+; GFX10-NEXT: v_and_b32_e32 v9, 0xffff, v7
; GFX10-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX10-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; GFX10-NEXT: v_and_or_b32 v5, 0xffff, v5, v9
-; GFX10-NEXT: v_and_or_b32 v6, 0xffff, v6, v10
+; GFX10-NEXT: v_and_or_b32 v6, 0xffff, v6, v9
; GFX10-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
@@ -126,14 +123,11 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_flat(<2 x i32> %node_ptr
define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> inreg %tdescr) {
; GFX10-LABEL: image_bvh64_intersect_ray_a16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v6
-; GFX10-NEXT: v_and_b32_e32 v11, 0xffff, v8
+; GFX10-NEXT: v_and_b32_e32 v10, 0xffff, v8
; GFX10-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX10-NEXT: v_alignbit_b32 v8, v9, v8, 16
-; GFX10-NEXT: v_and_or_b32 v6, 0xffff, v6, v10
-; GFX10-NEXT: v_and_or_b32 v7, 0xffff, v7, v11
+; GFX10-NEXT: v_and_or_b32 v7, 0xffff, v7, v10
; GFX10-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
@@ -279,19 +273,17 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
; GFX1030-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1030: ; %bb.0:
; GFX1030-NEXT: v_mov_b32_e32 v13, v0
+; GFX1030-NEXT: v_and_b32_e32 v0, 0xffff, v7
; GFX1030-NEXT: v_mov_b32_e32 v14, v1
-; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v7
+; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v8
; GFX1030-NEXT: v_mov_b32_e32 v15, v2
-; GFX1030-NEXT: v_and_b32_e32 v2, 0xffff, v8
; GFX1030-NEXT: v_mov_b32_e32 v16, v3
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1030-NEXT: v_mov_b32_e32 v17, v4
-; GFX1030-NEXT: v_alignbit_b32 v20, v2, v7, 16
+; GFX1030-NEXT: v_mov_b32_e32 v18, v5
+; GFX1030-NEXT: v_alignbit_b32 v20, v1, v7, 16
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
-; GFX1030-NEXT: v_and_or_b32 v18, 0xffff, v5, v0
-; GFX1030-NEXT: v_and_or_b32 v19, 0xffff, v6, v1
+; GFX1030-NEXT: v_and_or_b32 v19, 0xffff, v6, v0
; GFX1030-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v9
; GFX1030-NEXT: v_readfirstlane_b32 s5, v10
@@ -321,15 +313,12 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16_vgpr_descr(i32 %node_p
;
; GFX1013-LABEL: image_bvh_intersect_ray_a16_vgpr_descr:
; GFX1013: ; %bb.0:
-; GFX1013-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX1013-NEXT: v_and_b32_e32 v14, 0xffff, v7
+; GFX1013-NEXT: v_and_b32_e32 v13, 0xffff, v7
; GFX1013-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX1013-NEXT: s_mov_b32 s1, exec_lo
; GFX1013-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX1013-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX1013-NEXT: v_alignbit_b32 v7, v8, v7, 16
-; GFX1013-NEXT: v_and_or_b32 v5, 0xffff, v5, v13
-; GFX1013-NEXT: v_and_or_b32 v6, 0xffff, v6, v14
+; GFX1013-NEXT: v_and_or_b32 v6, 0xffff, v6, v13
; GFX1013-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1
; GFX1013-NEXT: v_readfirstlane_b32 s4, v9
; GFX1013-NEXT: v_readfirstlane_b32 s5, v10
@@ -546,19 +535,17 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16_vgpr_descr(i64 %node
; GFX1030-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr:
; GFX1030: ; %bb.0:
; GFX1030-NEXT: v_mov_b32_e32 v14, v0
+; GFX1030-NEXT: v_and_b32_e32 v0, 0xffff, v8
; GFX1030-NEXT: v_mov_b32_e32 v15, v1
-; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v6
-; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v8
+; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v9
; GFX1030-NEXT: v_mov_b32_e32 v16, v2
-; GFX1030-NEXT: v_and_b32_e32 v2, 0xffff, v9
; GFX1030-NEXT: v_mov_b32_e32 v17, v3
; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1030-NEXT: v_mov_b32_e32 v18, v4
; GFX1030-NEXT: v_mov_b32_e32 v19, v5
-; GFX1030-NEXT: v_alignbit_b32 v22, v2, v8, 16
-; GFX1030-NEXT: v_and_or_b32 v20, 0xffff, v6, v0
-; GFX1030-NEXT: v_and_or_b32 v21, 0xffff, v7, v1
+; GFX1030-NEXT: v_mov_b32_e32 v20, v6
+; GFX1030-NEXT: v_alignbit_b32 v22, v1, v8, 16
+; GFX1030-NEXT: v_and_or_b32 v21, 0xffff, v7, v0
; GFX1030-NEXT: s_mov_b32 s1, exec_lo
; GFX1030-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
; GFX1030-NEXT: v_readfirstlane_b32 s4, v10
@@ -590,15 +577,12 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16_vgpr_descr(i64 %node
;
; GFX1013-LABEL: image_bvh64_intersect_ray_a16_vgpr_descr:
; GFX1013: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/213086
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