[llvm] [AArch64][SVE] Allow scalable factor-3 interleaved accesses (PR #200424)

[Harry Ramsey via llvm-commits]

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@@ -27682,7 +27717,12 @@ performInterleavedStoreCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
       return SDValue();
   } else if (!isSplatVectorInterleaveOps(DAG, DL, WideValue,
                                          ValueInterleaveOps)) {
-    return SDValue();
+    // A vector.interleave3 defined in another basic block is unknown here
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Harry-Ramsey wrote:

Across blocks, we cannot see the original DAG node. I believe for 2 and 4 we can use the power-of-two to identify if it is compatible. We do not have that with factor of 3, so I have had to implement `deinterleaveInterleavedValueForSVESt3` as a way to help with that.

That is why this test is only for factors of 3.

https://github.com/llvm/llvm-project/pull/200424