[llvm] [M68k] Prevent COPY instruction from killing live condition flags (PR #168485)
Dan Salvato via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 30 08:49:11 PDT 2026
https://github.com/dansalvato updated https://github.com/llvm/llvm-project/pull/168485
>From 4de373e07591fdb1810851a673f01f1f63aa8d42 Mon Sep 17 00:00:00 2001
From: Dan Salvato <dan at teamsalvato.com>
Date: Sun, 20 Jul 2025 17:34:07 -0600
Subject: [PATCH 1/6] [M68k] Fix COPY instruction killing live condition flags
During PHI node elimination, a COPY instruction is inserted that is not
known to kill condition flags until after it is lowered by
`copyPhysReg()`. To mitigate this, `copyPhysReg()` now has logic to
determine whether the CCR is live, and if so, will back it up and
restore it after the COPY.
---
llvm/lib/Target/M68k/M68kInstrData.td | 14 +-
llvm/lib/Target/M68k/M68kInstrInfo.cpp | 105 +-
llvm/lib/Target/M68k/M68kInstrInfo.td | 3 +
llvm/lib/Target/M68k/M68kSubtarget.h | 1 +
llvm/test/CodeGen/M68k/Atomics/rmw.ll | 730 +++++---
.../M68k/CodeModel/Large/Atomics/rmw.ll | 1490 +++++++++++------
6 files changed, 1566 insertions(+), 777 deletions(-)
diff --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td
index fd654be09dc97..b7b2d0ac48519 100644
--- a/llvm/lib/Target/M68k/M68kInstrData.td
+++ b/llvm/lib/Target/M68k/M68kInstrData.td
@@ -395,7 +395,6 @@ def MOVM32mp_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.POp>;
/// | EFFECTIVE ADDRESS
/// 0 1 0 0 0 1 0 0 1 1 | MODE | REG
/// --------------------------------------------------
-let Defs = [CCR] in {
class MxMoveToCCR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
: MxInst<(outs CCRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
let Inst = (ascend
@@ -406,7 +405,6 @@ class MxMoveToCCR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
class MxMoveToCCRPseudo<MxOperand MEMOp>
: MxPseudo<(outs CCRC:$dst), (ins MEMOp:$src)>;
-} // let Defs = [CCR]
let mayLoad = 1 in
foreach AM = MxMoveSrcAMs in {
@@ -425,7 +423,6 @@ def MOV16cd : MxMoveToCCR<MxOp16AddrMode_d.Op, MxMoveSrcOpEnc_d>;
/// | EFFECTIVE ADDRESS
/// 0 1 0 0 0 0 1 0 1 1 | MODE | REG
/// --------------------------------------------------
-let Uses = [CCR] in {
class MxMoveFromCCR_R
: MxInst<(outs MxDRD16:$dst), (ins CCRC:$src), "move.w\t$src, $dst", []>,
Requires<[ AtLeastM68010 ]> {
@@ -445,7 +442,6 @@ class MxMoveFromCCRPseudo<MxOperand MEMOp>
: MxPseudo<(outs), (ins MEMOp:$dst, CCRC:$src)>;
class MxMoveFromCCR_RPseudo<MxOperand MEMOp>
: MxPseudo<(outs MEMOp:$dst), (ins CCRC:$src)>;
-} // let Uses = [CCR]
let mayStore = 1 in
foreach AM = MxMoveDstAMs in {
@@ -466,7 +462,6 @@ def MOV16dc : MxMoveFromCCR_R;
/// | EFFECTIVE ADDRESS
/// 0 1 0 0 0 1 1 0 1 1 | MODE | REG
/// --------------------------------------------------
-let Defs = [SR] in {
class MxMoveToSR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
: MxInst<(outs SRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
let Inst = (ascend
@@ -474,7 +469,6 @@ class MxMoveToSR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
SRC_ENC.Supplement
);
}
-} // let Defs = [SR]
let mayLoad = 1 in
foreach AM = MxMoveSrcAMs in {
@@ -491,20 +485,20 @@ def MOV16sd : MxMoveToSR<MxOp16AddrMode_d.Op, MxMoveSrcOpEnc_d>;
/// | EFFECTIVE ADDRESS
/// 0 1 0 0 0 0 0 0 1 1 | MODE | REG
/// --------------------------------------------------
-let Uses = [SR] in {
class MxMoveFromSR_R
- : MxInst<(outs MxDRD16:$dst), (ins SRC:$src), "move.w\t$src, $dst", []> {
+ : MxInst<(outs MxDRD16:$dst), (ins SRC:$src), "move.w\t$src, $dst", []>,
+ Requires<[ IsM68000 ]> {
let Inst = (descend 0b0100000011, MxEncAddrMode_d<"dst">.EA);
}
class MxMoveFromSR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
- : MxInst<(outs), (ins MEMOp:$dst, SRC:$src), "move.w\t$src, $dst", []> {
+ : MxInst<(outs), (ins MEMOp:$dst, SRC:$src), "move.w\t$src, $dst", []>,
+ Requires<[ IsM68000 ]> {
let Inst = (ascend
(descend 0b0100000011, DST_ENC.EA),
DST_ENC.Supplement
);
}
-} // let Uses = [SR]
let mayStore = 1 in
foreach AM = MxMoveDstAMs in {
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 0c4708eb98daa..8d9ccd887b680 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -690,6 +690,8 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
bool RenamableDest, bool RenamableSrc) const {
const auto &Subtarget = MBB.getParent()->getSubtarget<M68kSubtarget>();
unsigned Opc = 0;
+ MachineFunction &MF = *MBB.getParent();
+ const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
// First deal with the normal symmetric copies.
if (M68k::XR32RegClass.contains(DstReg, SrcReg))
@@ -699,20 +701,13 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
else if (M68k::DR8RegClass.contains(DstReg, SrcReg))
Opc = M68k::MOV8dd;
- if (Opc) {
- BuildMI(MBB, MI, DL, get(Opc), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
-
// Now deal with asymmetrically sized copies. The cases that follow are upcast
// moves.
//
// NOTE
// These moves are not aware of type nature of these values and thus
// won't do any SExt or ZExt and upper bits will basically contain garbage.
- MachineInstrBuilder MIB(*MBB.getParent(), MI);
- if (M68k::DR8RegClass.contains(SrcReg)) {
+ else if (M68k::DR8RegClass.contains(SrcReg)) {
if (M68k::XR16RegClass.contains(DstReg))
Opc = M68k::MOVXd16d8;
else if (M68k::XR32RegClass.contains(DstReg))
@@ -721,31 +716,18 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
M68k::XR32RegClass.contains(DstReg))
Opc = M68k::MOVXd32d16;
- if (Opc) {
- BuildMI(MBB, MI, DL, get(Opc), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
-
- bool FromCCR = SrcReg == M68k::CCR;
- bool FromSR = SrcReg == M68k::SR;
- bool ToCCR = DstReg == M68k::CCR;
- bool ToSR = DstReg == M68k::SR;
-
- if (FromCCR) {
- Opc = M68k::MOV16dc;
- if (!Subtarget.atLeastM68010()) {
- Opc = M68k::MOV16ds;
- SrcReg = M68k::SR;
- }
- if (!M68k::DR8RegClass.contains(DstReg) &&
- !M68k::DR16RegClass.contains(DstReg) &&
- !M68k::DR32RegClass.contains(DstReg)) {
+ else if (SrcReg == M68k::CCR) {
+ if (M68k::DR8RegClass.contains(DstReg)) {
+ Opc = M68k::MOV8dc;
+ } else if (M68k::DR16RegClass.contains(DstReg)) {
+ Opc = STI.isM68000() ? M68k::MOV16ds : M68k::MOV16dc;
+ } else if (M68k::DR32RegClass.contains(DstReg)) {
+ Opc = STI.isM68000() ? M68k::MOV16ds : M68k::MOV16dc;
+ } else {
LLVM_DEBUG(dbgs() << "Cannot copy CCR to " << RI.getName(DstReg) << '\n');
llvm_unreachable("Invalid register for MOVE from CCR");
}
- } else if (ToCCR) {
- Opc = M68k::MOV16cd;
+ } else if (DstReg == M68k::CCR) {
if (M68k::DR8RegClass.contains(SrcReg)) {
// Promote used register to the next class
SrcReg = getRegisterInfo().getMatchingSuperReg(
@@ -755,19 +737,72 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to CCR\n");
llvm_unreachable("Invalid register for MOVE to CCR");
}
- } else if (FromSR || ToSR) {
+ } else if (SrcReg == M68k::SR || DstReg == M68k::SR)
llvm_unreachable("Cannot emit SR copy instruction");
}
- if (Opc) {
+ if (!Opc) {
+ LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
+ << RI.getName(DstReg) << '\n');
+ llvm_unreachable("Cannot emit physreg copy instruction");
+ }
+
+ unsigned CCRSrcReg = STI.isM68000() ? M68k::SR : M68k::CCR;
+
+ // Get the live registers right before the COPY instruction. If CCR is
+ // live, the MOVE is going to kill it, so we will need to preserve it.
+ LiveRegUnits UsedRegs(RI);
+ UsedRegs.addLiveOuts(MBB);
+ auto InstUpToI = MBB.end();
+ while (InstUpToI != MI) {
+ UsedRegs.stepBackward(*--InstUpToI);
+ }
+
+ if (SrcReg == M68k::CCR) {
+ BuildMI(MBB, MI, DL, get(Opc), DstReg).addReg(CCRSrcReg);
+ return;
+ }
+ if (DstReg == M68k::CCR) {
+ BuildMI(MBB, MI, DL, get(Opc), M68k::CCR)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
+ if (UsedRegs.available(M68k::CCR)) {
BuildMI(MBB, MI, DL, get(Opc), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc));
return;
}
- LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
- << RI.getName(DstReg) << '\n');
- llvm_unreachable("Cannot emit physreg copy instruction");
+ // CCR is live, so we must restore it after the copy. Prepare push/pop ops.
+ // 68000 must use MOVE from SR, 68010+ must use MOVE from CCR. In either
+ // case, MOVE to CCR masks out the upper byte.
+
+ // Look for an available data register for the CCR, or push to stack if
+ // there are none
+ BitVector Allocatable =
+ RI.getAllocatableSet(MF, RI.getRegClass(M68k::DR16RegClassID));
+ for (Register Reg : Allocatable.set_bits()) {
+ if (!RI.regsOverlap(DstReg, Reg) && (UsedRegs.available(Reg))) {
+ unsigned CCRPushOp = STI.isM68000() ? M68k::MOV16ds : M68k::MOV16dc;
+ unsigned CCRPopOp = M68k::MOV16cd;
+ BuildMI(MBB, MI, DL, get(CCRPushOp), Reg).addReg(CCRSrcReg);
+ BuildMI(MBB, MI, DL, get(Opc), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ BuildMI(MBB, MI, DL, get(CCRPopOp), M68k::CCR).addReg(Reg);
+ return;
+ }
+ }
+
+ unsigned CCRPushOp = STI.isM68000() ? M68k::MOV16es : M68k::MOV16ec;
+ unsigned CCRPopOp = M68k::MOV16co;
+
+ BuildMI(MBB, MI, DL, get(CCRPushOp))
+ .addReg(RI.getStackRegister())
+ .addReg(CCRSrcReg);
+ BuildMI(MBB, MI, DL, get(Opc), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ BuildMI(MBB, MI, DL, get(CCRPopOp), M68k::CCR).addReg(RI.getStackRegister());
+ return;
}
namespace {
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index 422b737721e2b..7804a24f30948 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -490,6 +490,9 @@ def IsPIC : Predicate<"TM.isPositionIndependent()">;
def IsNotPIC : Predicate<"!TM.isPositionIndependent()">;
// ISA versions
+def IsM68000 : Predicate<"Subtarget->isM68000()">,
+ AssemblerPredicate<(all_of FeatureISA00)>;
+
foreach i = [0,1,2,4,6] in
def AtLeastM680 # i # "0" : Predicate<"Subtarget->atLeastM680"#i#"0()">,
AssemblerPredicate<(all_of
diff --git a/llvm/lib/Target/M68k/M68kSubtarget.h b/llvm/lib/Target/M68k/M68kSubtarget.h
index 4f9685814d9a9..0a46f3b8e371f 100644
--- a/llvm/lib/Target/M68k/M68kSubtarget.h
+++ b/llvm/lib/Target/M68k/M68kSubtarget.h
@@ -82,6 +82,7 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
/// of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
+ bool isM68000() const { return SubtargetKind == M00; }
bool atLeastM68000() const { return SubtargetKind >= M00; }
bool atLeastM68010() const { return SubtargetKind >= M10; }
bool atLeastM68020() const { return SubtargetKind >= M20; }
diff --git a/llvm/test/CodeGen/M68k/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/Atomics/rmw.ll
index 8549524836a78..ffd53ee157047 100644
--- a/llvm/test/CodeGen/M68k/Atomics/rmw.ll
+++ b/llvm/test/CodeGen/M68k/Atomics/rmw.ll
@@ -1,24 +1,36 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs | FileCheck %s --check-prefix=NO-ATOMIC
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs | FileCheck %s --check-prefix=NO-ATOMIC
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs | FileCheck %s --check-prefix=NO-ATOMIC-000
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs | FileCheck %s --check-prefix=NO-ATOMIC-010
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68020 -verify-machineinstrs | FileCheck %s --check-prefix=ATOMIC
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68030 -verify-machineinstrs | FileCheck %s --check-prefix=ATOMIC
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68040 -verify-machineinstrs | FileCheck %s --check-prefix=ATOMIC
define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_add_i8:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_add_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_add_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_add_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_add_i8:
; ATOMIC: .cfi_startproc
@@ -40,7 +52,9 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB0_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -51,19 +65,31 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
}
define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i16:
; ATOMIC: .cfi_startproc
@@ -85,7 +111,9 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB1_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -96,18 +124,27 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
}
define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_and_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_and_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_and_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_and_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_and_i32:
; ATOMIC: .cfi_startproc
@@ -129,7 +166,9 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB2_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -140,21 +179,31 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
}
define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xor_i64:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #20, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -24
-; NO-ATOMIC-NEXT: move.l (28,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (32,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-NEXT: jsr __atomic_fetch_xor_8
-; NO-ATOMIC-NEXT: adda.l #20, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #20, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-000-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-000-NEXT: move.l (28,%sp), (8,%sp)
+; NO-ATOMIC-000-NEXT: move.l (24,%sp), (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (32,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __atomic_fetch_xor_8
+; NO-ATOMIC-000-NEXT: adda.l #20, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #20, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-010-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-010-NEXT: move.l (28,%sp), (8,%sp)
+; NO-ATOMIC-010-NEXT: move.l (24,%sp), (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (32,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __atomic_fetch_xor_8
+; NO-ATOMIC-010-NEXT: adda.l #20, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xor_i64:
; ATOMIC: .cfi_startproc
@@ -176,19 +225,31 @@ define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
}
define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_or_i8:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_or_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_or_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_or_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_or_i8:
; ATOMIC: .cfi_startproc
@@ -210,7 +271,9 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB4_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -221,23 +284,39 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
}
define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atmoicrmw_nand_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d2
-; NO-ATOMIC-NEXT: move.l %d2, %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_nand_2
-; NO-ATOMIC-NEXT: move.w %d2, %d0
-; NO-ATOMIC-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-000-NEXT: move.l %d2, %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_nand_2
+; NO-ATOMIC-000-NEXT: move.w %d2, %d0
+; NO-ATOMIC-000-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-010-NEXT: move.l %d2, %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_nand_2
+; NO-ATOMIC-010-NEXT: move.w %d2, %d0
+; NO-ATOMIC-010-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atmoicrmw_nand_i16:
; ATOMIC: .cfi_startproc
@@ -260,7 +339,9 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d1, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB5_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -271,18 +352,27 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
}
define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_min_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_min_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_min_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_min_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_min_i32:
; ATOMIC: .cfi_startproc
@@ -303,13 +393,17 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB6_4
; ATOMIC-NEXT: .LBB6_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d2, %d0
; ATOMIC-NEXT: sub.l %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.l %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: ble .LBB6_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB6_1 Depth=1
@@ -324,54 +418,105 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
}
define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_max_i64:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #52, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-NEXT: move.l (64,%sp), %d3
-; NO-ATOMIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-NEXT: move.l #0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (60,%sp), %d4
-; NO-ATOMIC-NEXT: move.l (56,%sp), %d5
-; NO-ATOMIC-NEXT: jsr __atomic_load_8
-; NO-ATOMIC-NEXT: lea (24,%sp), %a2
-; NO-ATOMIC-NEXT: bra .LBB7_1
-; NO-ATOMIC-NEXT: .LBB7_3: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-NEXT: move.l %d1, (12,%sp)
-; NO-ATOMIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-NEXT: move.l #5, (20,%sp)
-; NO-ATOMIC-NEXT: move.l #5, (16,%sp)
-; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_8
-; NO-ATOMIC-NEXT: move.b %d0, %d2
-; NO-ATOMIC-NEXT: move.l (28,%sp), %d1
-; NO-ATOMIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-NEXT: bne .LBB7_4
-; NO-ATOMIC-NEXT: .LBB7_1: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
-; NO-ATOMIC-NEXT: move.l %d0, (24,%sp)
-; NO-ATOMIC-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-NEXT: move.l %a2, (4,%sp)
-; NO-ATOMIC-NEXT: move.l %d4, %d2
-; NO-ATOMIC-NEXT: sub.l %d1, %d2
-; NO-ATOMIC-NEXT: move.l %d5, %d2
-; NO-ATOMIC-NEXT: subx.l %d0, %d2
-; NO-ATOMIC-NEXT: slt %d2
-; NO-ATOMIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-NEXT: bne .LBB7_3
-; NO-ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-NEXT: move.l %d4, %d1
-; NO-ATOMIC-NEXT: move.l %d5, %d0
-; NO-ATOMIC-NEXT: bra .LBB7_3
-; NO-ATOMIC-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
-; NO-ATOMIC-NEXT: adda.l #52, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #52, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-000-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-000-NEXT: move.l (60,%sp), %d3
+; NO-ATOMIC-000-NEXT: move.l (56,%sp), %d4
+; NO-ATOMIC-000-NEXT: move.l (64,%sp), %a2
+; NO-ATOMIC-000-NEXT: move.l (4,%a2), %d1
+; NO-ATOMIC-000-NEXT: move.l (%a2), %d0
+; NO-ATOMIC-000-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-000-NEXT: bra .LBB7_1
+; NO-ATOMIC-000-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-000-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-000-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-000-NEXT: jsr __atomic_compare_exchange_8
+; NO-ATOMIC-000-NEXT: move.b %d0, %d2
+; NO-ATOMIC-000-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-000-NEXT: bne .LBB7_4
+; NO-ATOMIC-000-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-000-NEXT: move.l %a2, (%sp)
+; NO-ATOMIC-000-NEXT: move.l %a3, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d3, %d2
+; NO-ATOMIC-000-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-000-NEXT: move.w %sr, -(%sp)
+; NO-ATOMIC-000-NEXT: move.l %d4, %d2
+; NO-ATOMIC-000-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-000-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-000-NEXT: slt %d2
+; NO-ATOMIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-000-NEXT: bne .LBB7_3
+; NO-ATOMIC-000-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d3, %d1
+; NO-ATOMIC-000-NEXT: move.l %d4, %d0
+; NO-ATOMIC-000-NEXT: bra .LBB7_3
+; NO-ATOMIC-000-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-000-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-000-NEXT: adda.l #52, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #52, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-010-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-010-NEXT: move.l (60,%sp), %d3
+; NO-ATOMIC-010-NEXT: move.l (56,%sp), %d4
+; NO-ATOMIC-010-NEXT: move.l (64,%sp), %a2
+; NO-ATOMIC-010-NEXT: move.l (4,%a2), %d1
+; NO-ATOMIC-010-NEXT: move.l (%a2), %d0
+; NO-ATOMIC-010-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-010-NEXT: bra .LBB7_1
+; NO-ATOMIC-010-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-010-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-010-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-010-NEXT: jsr __atomic_compare_exchange_8
+; NO-ATOMIC-010-NEXT: move.b %d0, %d2
+; NO-ATOMIC-010-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-010-NEXT: bne .LBB7_4
+; NO-ATOMIC-010-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-010-NEXT: move.l %a2, (%sp)
+; NO-ATOMIC-010-NEXT: move.l %a3, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d3, %d2
+; NO-ATOMIC-010-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-010-NEXT: move.w %ccr, -(%sp)
+; NO-ATOMIC-010-NEXT: move.l %d4, %d2
+; NO-ATOMIC-010-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-010-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-010-NEXT: slt %d2
+; NO-ATOMIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-010-NEXT: bne .LBB7_3
+; NO-ATOMIC-010-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d3, %d1
+; NO-ATOMIC-010-NEXT: move.l %d4, %d0
+; NO-ATOMIC-010-NEXT: bra .LBB7_3
+; NO-ATOMIC-010-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-010-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-010-NEXT: adda.l #52, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_max_i64:
; ATOMIC: .cfi_startproc
@@ -403,11 +548,13 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d0, (24,%sp)
; ATOMIC-NEXT: move.l %d1, (28,%sp)
-; ATOMIC-NEXT: move.l %d3, (%sp)
-; ATOMIC-NEXT: move.l %a2, (4,%sp)
-; ATOMIC-NEXT: move.l %d4, %d2
+; ATOMIC-NEXT: move.l %a2, (%sp)
+; ATOMIC-NEXT: move.l %a3, (4,%sp)
+; ATOMIC-NEXT: move.l %d3, %d2
; ATOMIC-NEXT: sub.l %d1, %d2
-; ATOMIC-NEXT: move.l %d5, %d2
+; ATOMIC-NEXT: move.w %ccr, -(%sp)
+; ATOMIC-NEXT: move.l %d4, %d2
+; ATOMIC-NEXT: move.w (%sp)+, %ccr
; ATOMIC-NEXT: subx.l %d0, %d2
; ATOMIC-NEXT: slt %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
@@ -426,19 +573,31 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
}
define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_i8_umin:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_umin_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umin_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umin_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_i8_umin:
; ATOMIC: .cfi_startproc
@@ -459,13 +618,17 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB8_4
; ATOMIC-NEXT: .LBB8_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.b %d2, %d0
; ATOMIC-NEXT: sub.b %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.b %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: bls .LBB8_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB8_1 Depth=1
@@ -480,19 +643,31 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
}
define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_umax_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_umax_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umax_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umax_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_umax_i16:
; ATOMIC: .cfi_startproc
@@ -513,13 +688,17 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB9_4
; ATOMIC-NEXT: .LBB9_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.w %d2, %d0
; ATOMIC-NEXT: sub.w %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.w %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: bhi .LBB9_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB9_1 Depth=1
@@ -534,19 +713,31 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
}
define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xchg_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_lock_test_and_set_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xchg_i16:
; ATOMIC: .cfi_startproc
@@ -566,7 +757,9 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB10_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -578,18 +771,27 @@ entry:
}
define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xchg_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_lock_test_and_set_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xchg_i32:
; ATOMIC: .cfi_startproc
@@ -609,7 +811,9 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB11_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -621,19 +825,33 @@ entry:
}
define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i8_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i8_arid:
; ATOMIC: .cfi_startproc
@@ -655,7 +873,9 @@ define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.b %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB12_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -669,19 +889,33 @@ start:
}
define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i16_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i16_arid:
; ATOMIC: .cfi_startproc
@@ -703,7 +937,9 @@ define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.w %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB13_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -717,19 +953,33 @@ start:
}
define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i32_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i32_arid:
; ATOMIC: .cfi_startproc
@@ -751,7 +1001,9 @@ define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.l %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB14_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
index 9009d5a53e2a6..78b011e39465b 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=NO-ATOMIC
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=NO-ATOMIC
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs --code-model=large --relocation-model=pic | FileCheck %s --check-prefix=NO-ATOMIC-PIC
-; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs --code-model=large --relocation-model=pic | FileCheck %s --check-prefix=NO-ATOMIC-PIC
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=NO-ATOMIC-000
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=NO-ATOMIC-010
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 -verify-machineinstrs --code-model=large --relocation-model=pic | FileCheck %s --check-prefix=NO-ATOMIC-PIC-000
+; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 -verify-machineinstrs --code-model=large --relocation-model=pic | FileCheck %s --check-prefix=NO-ATOMIC-PIC-010
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68020 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=ATOMIC
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68030 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=ATOMIC
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68040 -verify-machineinstrs --code-model=large | FileCheck %s --check-prefix=ATOMIC
@@ -11,33 +11,57 @@
; RUN: llc %s -o - -mtriple=m68k -mcpu=M68040 -verify-machineinstrs --code-model=large --relocation-model=pic | FileCheck %s --check-prefix=ATOMIC-PIC
define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_add_i8:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_add_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_add_i8:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_add_1 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_add_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_add_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_add_1 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_add_i8:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_add_1 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_add_i8:
; ATOMIC: .cfi_startproc
@@ -59,7 +83,9 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB0_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -86,7 +112,9 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.b %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB0_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -97,33 +125,57 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
}
define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_sub_i16:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_sub_i16:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i16:
; ATOMIC: .cfi_startproc
@@ -145,7 +197,9 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB1_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -172,7 +226,9 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.w %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB1_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -183,31 +239,49 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
}
define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_and_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_and_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_and_i32:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_and_4 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_and_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_and_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_and_4 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_and_i32:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_and_4 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_and_i32:
; ATOMIC: .cfi_startproc
@@ -229,7 +303,9 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB2_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -256,7 +332,9 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.l %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB2_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -267,37 +345,57 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
}
define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xor_i64:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #20, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -24
-; NO-ATOMIC-NEXT: move.l (28,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (32,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-NEXT: jsr __atomic_fetch_xor_8
-; NO-ATOMIC-NEXT: adda.l #20, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_xor_i64:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #20, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -24
-; NO-ATOMIC-PIC-NEXT: move.l (28,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (32,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__atomic_fetch_xor_8 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #20, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #20, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-000-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-000-NEXT: move.l (28,%sp), (8,%sp)
+; NO-ATOMIC-000-NEXT: move.l (24,%sp), (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (32,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __atomic_fetch_xor_8
+; NO-ATOMIC-000-NEXT: adda.l #20, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #20, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-010-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-010-NEXT: move.l (28,%sp), (8,%sp)
+; NO-ATOMIC-010-NEXT: move.l (24,%sp), (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (32,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __atomic_fetch_xor_8
+; NO-ATOMIC-010-NEXT: adda.l #20, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #20, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-PIC-000-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (28,%sp), (8,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (24,%sp), (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (32,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__atomic_fetch_xor_8 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #20, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_xor_i64:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #20, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-PIC-010-NEXT: move.l #3, (12,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (28,%sp), (8,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (24,%sp), (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (32,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__atomic_fetch_xor_8 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #20, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xor_i64:
; ATOMIC: .cfi_startproc
@@ -335,33 +433,57 @@ define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
}
define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_or_i8:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_or_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_or_i8:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_or_1 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_or_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_or_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_or_1 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_or_i8:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_or_1 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_or_i8:
; ATOMIC: .cfi_startproc
@@ -383,7 +505,9 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB4_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -410,7 +534,9 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.b %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB4_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -421,41 +547,73 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
}
define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atmoicrmw_nand_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d2
-; NO-ATOMIC-NEXT: move.l %d2, %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_nand_2
-; NO-ATOMIC-NEXT: move.w %d2, %d0
-; NO-ATOMIC-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atmoicrmw_nand_i16:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
-; NO-ATOMIC-PIC-NEXT: move.w (18,%sp), %d2
-; NO-ATOMIC-PIC-NEXT: move.l %d2, %d0
-; NO-ATOMIC-PIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_nand_2 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: move.w %d2, %d0
-; NO-ATOMIC-PIC-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-000-NEXT: move.l %d2, %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_nand_2
+; NO-ATOMIC-000-NEXT: move.w %d2, %d0
+; NO-ATOMIC-000-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-010-NEXT: move.l %d2, %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_nand_2
+; NO-ATOMIC-010-NEXT: move.w %d2, %d0
+; NO-ATOMIC-010-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-PIC-000-NEXT: move.l %d2, %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_nand_2 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: move.w %d2, %d0
+; NO-ATOMIC-PIC-000-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atmoicrmw_nand_i16:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: movem.l %d2, (8,%sp) ; 8-byte Folded Spill
+; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d2
+; NO-ATOMIC-PIC-010-NEXT: move.l %d2, %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_nand_2 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: move.w %d2, %d0
+; NO-ATOMIC-PIC-010-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atmoicrmw_nand_i16:
; ATOMIC: .cfi_startproc
@@ -478,7 +636,9 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d1, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB5_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -506,7 +666,9 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.w %d1, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB5_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -517,31 +679,49 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
}
define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_min_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_min_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_min_i32:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_min_4 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_min_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_min_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_min_4 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_min_i32:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_min_4 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_min_i32:
; ATOMIC: .cfi_startproc
@@ -562,13 +742,17 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB6_4
; ATOMIC-NEXT: .LBB6_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d2, %d0
; ATOMIC-NEXT: sub.l %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.l %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: ble .LBB6_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB6_1 Depth=1
@@ -598,13 +782,17 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.l %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: bne .LBB6_4
; ATOMIC-PIC-NEXT: .LBB6_1: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.l %d2, %d0
; ATOMIC-PIC-NEXT: sub.l %d1, %d0
+; ATOMIC-PIC-NEXT: move.w %ccr, %d0
; ATOMIC-PIC-NEXT: move.l %d2, %d3
+; ATOMIC-PIC-NEXT: move.w %d0, %ccr
; ATOMIC-PIC-NEXT: ble .LBB6_3
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; in Loop: Header=BB6_1 Depth=1
@@ -619,103 +807,205 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
}
define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_max_i64:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #52, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-NEXT: move.l (64,%sp), %d3
-; NO-ATOMIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-NEXT: move.l #0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (60,%sp), %d4
-; NO-ATOMIC-NEXT: move.l (56,%sp), %d5
-; NO-ATOMIC-NEXT: jsr __atomic_load_8
-; NO-ATOMIC-NEXT: lea (24,%sp), %a2
-; NO-ATOMIC-NEXT: bra .LBB7_1
-; NO-ATOMIC-NEXT: .LBB7_3: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-NEXT: move.l %d1, (12,%sp)
-; NO-ATOMIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-NEXT: move.l #5, (20,%sp)
-; NO-ATOMIC-NEXT: move.l #5, (16,%sp)
-; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_8
-; NO-ATOMIC-NEXT: move.b %d0, %d2
-; NO-ATOMIC-NEXT: move.l (28,%sp), %d1
-; NO-ATOMIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-NEXT: bne .LBB7_4
-; NO-ATOMIC-NEXT: .LBB7_1: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
-; NO-ATOMIC-NEXT: move.l %d0, (24,%sp)
-; NO-ATOMIC-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-NEXT: move.l %a2, (4,%sp)
-; NO-ATOMIC-NEXT: move.l %d4, %d2
-; NO-ATOMIC-NEXT: sub.l %d1, %d2
-; NO-ATOMIC-NEXT: move.l %d5, %d2
-; NO-ATOMIC-NEXT: subx.l %d0, %d2
-; NO-ATOMIC-NEXT: slt %d2
-; NO-ATOMIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-NEXT: bne .LBB7_3
-; NO-ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
-; NO-ATOMIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-NEXT: move.l %d4, %d1
-; NO-ATOMIC-NEXT: move.l %d5, %d0
-; NO-ATOMIC-NEXT: bra .LBB7_3
-; NO-ATOMIC-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
-; NO-ATOMIC-NEXT: adda.l #52, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_max_i64:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #52, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-PIC-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-PIC-NEXT: move.l (64,%sp), %d3
-; NO-ATOMIC-PIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (60,%sp), %d4
-; NO-ATOMIC-PIC-NEXT: move.l (56,%sp), %d5
-; NO-ATOMIC-PIC-NEXT: jsr (__atomic_load_8 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: lea (24,%sp), %a2
-; NO-ATOMIC-PIC-NEXT: bra .LBB7_1
-; NO-ATOMIC-PIC-NEXT: .LBB7_3: ; %atomicrmw.start
-; NO-ATOMIC-PIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-PIC-NEXT: move.l %d1, (12,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (8,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #5, (20,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #5, (16,%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__atomic_compare_exchange_8 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: move.b %d0, %d2
-; NO-ATOMIC-PIC-NEXT: move.l (28,%sp), %d1
-; NO-ATOMIC-PIC-NEXT: move.l (24,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-PIC-NEXT: bne .LBB7_4
-; NO-ATOMIC-PIC-NEXT: .LBB7_1: ; %atomicrmw.start
-; NO-ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (24,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l %d3, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l %a2, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l %d4, %d2
-; NO-ATOMIC-PIC-NEXT: sub.l %d1, %d2
-; NO-ATOMIC-PIC-NEXT: move.l %d5, %d2
-; NO-ATOMIC-PIC-NEXT: subx.l %d0, %d2
-; NO-ATOMIC-PIC-NEXT: slt %d2
-; NO-ATOMIC-PIC-NEXT: cmpi.b #0, %d2
-; NO-ATOMIC-PIC-NEXT: bne .LBB7_3
-; NO-ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.start
-; NO-ATOMIC-PIC-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-PIC-NEXT: move.l %d4, %d1
-; NO-ATOMIC-PIC-NEXT: move.l %d5, %d0
-; NO-ATOMIC-PIC-NEXT: bra .LBB7_3
-; NO-ATOMIC-PIC-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-PIC-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
-; NO-ATOMIC-PIC-NEXT: adda.l #52, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #52, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-000-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-000-NEXT: move.l (60,%sp), %d3
+; NO-ATOMIC-000-NEXT: move.l (56,%sp), %d4
+; NO-ATOMIC-000-NEXT: move.l (64,%sp), %a2
+; NO-ATOMIC-000-NEXT: move.l (4,%a2), %d1
+; NO-ATOMIC-000-NEXT: move.l (%a2), %d0
+; NO-ATOMIC-000-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-000-NEXT: bra .LBB7_1
+; NO-ATOMIC-000-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-000-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-000-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-000-NEXT: jsr __atomic_compare_exchange_8
+; NO-ATOMIC-000-NEXT: move.b %d0, %d2
+; NO-ATOMIC-000-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-000-NEXT: bne .LBB7_4
+; NO-ATOMIC-000-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-000-NEXT: move.l %a2, (%sp)
+; NO-ATOMIC-000-NEXT: move.l %a3, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d3, %d2
+; NO-ATOMIC-000-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-000-NEXT: move.w %sr, -(%sp)
+; NO-ATOMIC-000-NEXT: move.l %d4, %d2
+; NO-ATOMIC-000-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-000-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-000-NEXT: slt %d2
+; NO-ATOMIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-000-NEXT: bne .LBB7_3
+; NO-ATOMIC-000-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-000-NEXT: move.l %d3, %d1
+; NO-ATOMIC-000-NEXT: move.l %d4, %d0
+; NO-ATOMIC-000-NEXT: bra .LBB7_3
+; NO-ATOMIC-000-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-000-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-000-NEXT: adda.l #52, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #52, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-010-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-010-NEXT: move.l (60,%sp), %d3
+; NO-ATOMIC-010-NEXT: move.l (56,%sp), %d4
+; NO-ATOMIC-010-NEXT: move.l (64,%sp), %a2
+; NO-ATOMIC-010-NEXT: move.l (4,%a2), %d1
+; NO-ATOMIC-010-NEXT: move.l (%a2), %d0
+; NO-ATOMIC-010-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-010-NEXT: bra .LBB7_1
+; NO-ATOMIC-010-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-010-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-010-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-010-NEXT: jsr __atomic_compare_exchange_8
+; NO-ATOMIC-010-NEXT: move.b %d0, %d2
+; NO-ATOMIC-010-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-010-NEXT: bne .LBB7_4
+; NO-ATOMIC-010-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-010-NEXT: move.l %a2, (%sp)
+; NO-ATOMIC-010-NEXT: move.l %a3, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d3, %d2
+; NO-ATOMIC-010-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-010-NEXT: move.w %ccr, -(%sp)
+; NO-ATOMIC-010-NEXT: move.l %d4, %d2
+; NO-ATOMIC-010-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-010-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-010-NEXT: slt %d2
+; NO-ATOMIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-010-NEXT: bne .LBB7_3
+; NO-ATOMIC-010-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-010-NEXT: move.l %d3, %d1
+; NO-ATOMIC-010-NEXT: move.l %d4, %d0
+; NO-ATOMIC-010-NEXT: bra .LBB7_3
+; NO-ATOMIC-010-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-010-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-010-NEXT: adda.l #52, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #52, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-PIC-000-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-PIC-000-NEXT: move.l (60,%sp), %d3
+; NO-ATOMIC-PIC-000-NEXT: move.l (56,%sp), %d4
+; NO-ATOMIC-PIC-000-NEXT: move.l (64,%sp), %a2
+; NO-ATOMIC-PIC-000-NEXT: move.l (4,%a2), %d1
+; NO-ATOMIC-PIC-000-NEXT: move.l (%a2), %d0
+; NO-ATOMIC-PIC-000-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-PIC-000-NEXT: bra .LBB7_1
+; NO-ATOMIC-PIC-000-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-PIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-PIC-000-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__atomic_compare_exchange_8 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: move.b %d0, %d2
+; NO-ATOMIC-PIC-000-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-PIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-PIC-000-NEXT: bne .LBB7_4
+; NO-ATOMIC-PIC-000-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-PIC-000-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %a2, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %a3, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %d3, %d2
+; NO-ATOMIC-PIC-000-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-PIC-000-NEXT: move.w %sr, -(%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %d4, %d2
+; NO-ATOMIC-PIC-000-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-PIC-000-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-PIC-000-NEXT: slt %d2
+; NO-ATOMIC-PIC-000-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-PIC-000-NEXT: bne .LBB7_3
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-PIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-PIC-000-NEXT: move.l %d3, %d1
+; NO-ATOMIC-PIC-000-NEXT: move.l %d4, %d0
+; NO-ATOMIC-PIC-000-NEXT: bra .LBB7_3
+; NO-ATOMIC-PIC-000-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-PIC-000-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-PIC-000-NEXT: adda.l #52, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_max_i64:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #52, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -56
+; NO-ATOMIC-PIC-010-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-PIC-010-NEXT: move.l (60,%sp), %d3
+; NO-ATOMIC-PIC-010-NEXT: move.l (56,%sp), %d4
+; NO-ATOMIC-PIC-010-NEXT: move.l (64,%sp), %a2
+; NO-ATOMIC-PIC-010-NEXT: move.l (4,%a2), %d1
+; NO-ATOMIC-PIC-010-NEXT: move.l (%a2), %d0
+; NO-ATOMIC-PIC-010-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-PIC-010-NEXT: bra .LBB7_1
+; NO-ATOMIC-PIC-010-NEXT: .LBB7_3: ; %atomicrmw.start
+; NO-ATOMIC-PIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-PIC-010-NEXT: move.l %d1, (12,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #5, (20,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #5, (16,%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__atomic_compare_exchange_8 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: move.b %d0, %d2
+; NO-ATOMIC-PIC-010-NEXT: move.l (28,%sp), %d1
+; NO-ATOMIC-PIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-PIC-010-NEXT: bne .LBB7_4
+; NO-ATOMIC-PIC-010-NEXT: .LBB7_1: ; %atomicrmw.start
+; NO-ATOMIC-PIC-010-NEXT: ; =>This Inner Loop Header: Depth=1
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (24,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %d1, (28,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %a2, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %a3, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %d3, %d2
+; NO-ATOMIC-PIC-010-NEXT: sub.l %d1, %d2
+; NO-ATOMIC-PIC-010-NEXT: move.w %ccr, -(%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %d4, %d2
+; NO-ATOMIC-PIC-010-NEXT: move.w (%sp)+, %ccr
+; NO-ATOMIC-PIC-010-NEXT: subx.l %d0, %d2
+; NO-ATOMIC-PIC-010-NEXT: slt %d2
+; NO-ATOMIC-PIC-010-NEXT: cmpi.b #0, %d2
+; NO-ATOMIC-PIC-010-NEXT: bne .LBB7_3
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.2: ; %atomicrmw.start
+; NO-ATOMIC-PIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
+; NO-ATOMIC-PIC-010-NEXT: move.l %d3, %d1
+; NO-ATOMIC-PIC-010-NEXT: move.l %d4, %d0
+; NO-ATOMIC-PIC-010-NEXT: bra .LBB7_3
+; NO-ATOMIC-PIC-010-NEXT: .LBB7_4: ; %atomicrmw.end
+; NO-ATOMIC-PIC-010-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-PIC-010-NEXT: adda.l #52, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_max_i64:
; ATOMIC: .cfi_startproc
@@ -747,11 +1037,13 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d0, (24,%sp)
; ATOMIC-NEXT: move.l %d1, (28,%sp)
-; ATOMIC-NEXT: move.l %d3, (%sp)
-; ATOMIC-NEXT: move.l %a2, (4,%sp)
-; ATOMIC-NEXT: move.l %d4, %d2
+; ATOMIC-NEXT: move.l %a2, (%sp)
+; ATOMIC-NEXT: move.l %a3, (4,%sp)
+; ATOMIC-NEXT: move.l %d3, %d2
; ATOMIC-NEXT: sub.l %d1, %d2
-; ATOMIC-NEXT: move.l %d5, %d2
+; ATOMIC-NEXT: move.w %ccr, -(%sp)
+; ATOMIC-NEXT: move.l %d4, %d2
+; ATOMIC-NEXT: move.w (%sp)+, %ccr
; ATOMIC-NEXT: subx.l %d0, %d2
; ATOMIC-NEXT: slt %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
@@ -796,11 +1088,13 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.l %d0, (24,%sp)
; ATOMIC-PIC-NEXT: move.l %d1, (28,%sp)
-; ATOMIC-PIC-NEXT: move.l %d3, (%sp)
-; ATOMIC-PIC-NEXT: move.l %a2, (4,%sp)
-; ATOMIC-PIC-NEXT: move.l %d4, %d2
+; ATOMIC-PIC-NEXT: move.l %a2, (%sp)
+; ATOMIC-PIC-NEXT: move.l %a3, (4,%sp)
+; ATOMIC-PIC-NEXT: move.l %d3, %d2
; ATOMIC-PIC-NEXT: sub.l %d1, %d2
-; ATOMIC-PIC-NEXT: move.l %d5, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, -(%sp)
+; ATOMIC-PIC-NEXT: move.l %d4, %d2
+; ATOMIC-PIC-NEXT: move.w (%sp)+, %ccr
; ATOMIC-PIC-NEXT: subx.l %d0, %d2
; ATOMIC-PIC-NEXT: slt %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
@@ -819,33 +1113,57 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
}
define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_i8_umin:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_umin_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_i8_umin:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.b (19,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #255, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_umin_1 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umin_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umin_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_umin_1 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_i8_umin:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.b (19,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #255, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_umin_1 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_i8_umin:
; ATOMIC: .cfi_startproc
@@ -866,13 +1184,17 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.b %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB8_4
; ATOMIC-NEXT: .LBB8_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.b %d2, %d0
; ATOMIC-NEXT: sub.b %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.b %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: bls .LBB8_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB8_1 Depth=1
@@ -902,13 +1224,17 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.b %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: bne .LBB8_4
; ATOMIC-PIC-NEXT: .LBB8_1: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.b %d2, %d0
; ATOMIC-PIC-NEXT: sub.b %d1, %d0
+; ATOMIC-PIC-NEXT: move.w %ccr, %d0
; ATOMIC-PIC-NEXT: move.b %d2, %d3
+; ATOMIC-PIC-NEXT: move.w %d0, %ccr
; ATOMIC-PIC-NEXT: bls .LBB8_3
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; in Loop: Header=BB8_1 Depth=1
@@ -923,33 +1249,57 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
}
define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_umax_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0:
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_umax_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_umax_i16:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0:
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_umax_2 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umax_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umax_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_umax_2 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_umax_i16:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_umax_2 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_umax_i16:
; ATOMIC: .cfi_startproc
@@ -970,13 +1320,17 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: bne .LBB9_4
; ATOMIC-NEXT: .LBB9_1: ; %atomicrmw.start
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.w %d2, %d0
; ATOMIC-NEXT: sub.w %d1, %d0
+; ATOMIC-NEXT: move.w %ccr, %d0
; ATOMIC-NEXT: move.w %d2, %d3
+; ATOMIC-NEXT: move.w %d0, %ccr
; ATOMIC-NEXT: bhi .LBB9_3
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-NEXT: ; in Loop: Header=BB9_1 Depth=1
@@ -1006,13 +1360,17 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.w %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: bne .LBB9_4
; ATOMIC-PIC-NEXT: .LBB9_1: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.w %d2, %d0
; ATOMIC-PIC-NEXT: sub.w %d1, %d0
+; ATOMIC-PIC-NEXT: move.w %ccr, %d0
; ATOMIC-PIC-NEXT: move.w %d2, %d3
+; ATOMIC-PIC-NEXT: move.w %d0, %ccr
; ATOMIC-PIC-NEXT: bhi .LBB9_3
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.start
; ATOMIC-PIC-NEXT: ; in Loop: Header=BB9_1 Depth=1
@@ -1027,33 +1385,57 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
}
define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xchg_i16:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_lock_test_and_set_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_xchg_i16:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.w (18,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: and.l #65535, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_lock_test_and_set_2 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_lock_test_and_set_2 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_xchg_i16:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_lock_test_and_set_2 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xchg_i16:
; ATOMIC: .cfi_startproc
@@ -1073,7 +1455,9 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.w %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB10_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -1098,7 +1482,9 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.w %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB10_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -1110,31 +1496,49 @@ entry:
}
define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
-; NO-ATOMIC-LABEL: atomicrmw_xchg_i32:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: jsr __sync_lock_test_and_set_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_xchg_i32:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0: ; %entry
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: move.l (20,%sp), %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_lock_test_and_set_4 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_lock_test_and_set_4 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_xchg_i32:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %entry
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_lock_test_and_set_4 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_xchg_i32:
; ATOMIC: .cfi_startproc
@@ -1154,7 +1558,9 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; ATOMIC-NEXT: seq %d2
; ATOMIC-NEXT: and.b #1, %d2
; ATOMIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-NEXT: move.w %ccr, %d3
; ATOMIC-NEXT: move.l %d0, %d2
+; ATOMIC-NEXT: move.w %d3, %ccr
; ATOMIC-NEXT: beq .LBB11_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -1179,7 +1585,9 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: seq %d2
; ATOMIC-PIC-NEXT: and.b #1, %d2
; ATOMIC-PIC-NEXT: cmpi.b #0, %d2
+; ATOMIC-PIC-NEXT: move.w %ccr, %d3
; ATOMIC-PIC-NEXT: move.l %d0, %d2
+; ATOMIC-PIC-NEXT: move.w %d3, %ccr
; ATOMIC-PIC-NEXT: beq .LBB11_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
@@ -1191,33 +1599,61 @@ entry:
}
define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i8_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_1
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_sub_i8_arid:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-PIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-PIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_sub_1 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_1
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_1
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_sub_1 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_sub_i8_arid:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_sub_1 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i8_arid:
; ATOMIC: .cfi_startproc
@@ -1239,7 +1675,9 @@ define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.b %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB12_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -1266,7 +1704,9 @@ define i8 @atomicrmw_sub_i8_arid(ptr align 2 %self) {
; ATOMIC-PIC-NEXT: seq %d1
; ATOMIC-PIC-NEXT: and.b #1, %d1
; ATOMIC-PIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-PIC-NEXT: move.w %ccr, %d2
; ATOMIC-PIC-NEXT: move.b %d0, %d1
+; ATOMIC-PIC-NEXT: move.w %d2, %ccr
; ATOMIC-PIC-NEXT: beq .LBB12_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -1280,33 +1720,61 @@ start:
}
define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i16_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_2
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_sub_i16_arid:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-PIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-PIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_2
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_sub_i16_arid:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i16_arid:
; ATOMIC: .cfi_startproc
@@ -1328,7 +1796,9 @@ define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.w %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB13_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -1355,7 +1825,9 @@ define i16 @atomicrmw_sub_i16_arid(ptr align 2 %self) {
; ATOMIC-PIC-NEXT: seq %d1
; ATOMIC-PIC-NEXT: and.b #1, %d1
; ATOMIC-PIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-PIC-NEXT: move.w %ccr, %d2
; ATOMIC-PIC-NEXT: move.w %d0, %d1
+; ATOMIC-PIC-NEXT: move.w %d2, %ccr
; ATOMIC-PIC-NEXT: beq .LBB13_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -1369,33 +1841,61 @@ start:
}
define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
-; NO-ATOMIC-LABEL: atomicrmw_sub_i32_arid:
-; NO-ATOMIC: .cfi_startproc
-; NO-ATOMIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-NEXT: jsr __sync_fetch_and_sub_4
-; NO-ATOMIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-NEXT: rts
-;
-; NO-ATOMIC-PIC-LABEL: atomicrmw_sub_i32_arid:
-; NO-ATOMIC-PIC: .cfi_startproc
-; NO-ATOMIC-PIC-NEXT: ; %bb.0: ; %start
-; NO-ATOMIC-PIC-NEXT: suba.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-NEXT: move.l (16,%sp), %a0
-; NO-ATOMIC-PIC-NEXT: move.l (%a0), %d0
-; NO-ATOMIC-PIC-NEXT: add.l #4, %d0
-; NO-ATOMIC-PIC-NEXT: move.l %d0, (%sp)
-; NO-ATOMIC-PIC-NEXT: move.l #1, (4,%sp)
-; NO-ATOMIC-PIC-NEXT: jsr (__sync_fetch_and_sub_4 at PLT,%pc)
-; NO-ATOMIC-PIC-NEXT: adda.l #12, %sp
-; NO-ATOMIC-PIC-NEXT: rts
+; NO-ATOMIC-000-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-000: .cfi_startproc
+; NO-ATOMIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_4
+; NO-ATOMIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-000-NEXT: rts
+;
+; NO-ATOMIC-010-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-010: .cfi_startproc
+; NO-ATOMIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_4
+; NO-ATOMIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-010-NEXT: rts
+;
+; NO-ATOMIC-PIC-000-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-PIC-000: .cfi_startproc
+; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-000-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-000-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_sub_4 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-000-NEXT: rts
+;
+; NO-ATOMIC-PIC-010-LABEL: atomicrmw_sub_i32_arid:
+; NO-ATOMIC-PIC-010: .cfi_startproc
+; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %start
+; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %a0
+; NO-ATOMIC-PIC-010-NEXT: move.l (%a0), %d0
+; NO-ATOMIC-PIC-010-NEXT: add.l #4, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #1, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_sub_4 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
+; NO-ATOMIC-PIC-010-NEXT: rts
;
; ATOMIC-LABEL: atomicrmw_sub_i32_arid:
; ATOMIC: .cfi_startproc
@@ -1417,7 +1917,9 @@ define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
; ATOMIC-NEXT: seq %d1
; ATOMIC-NEXT: and.b #1, %d1
; ATOMIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-NEXT: move.w %ccr, %d2
; ATOMIC-NEXT: move.l %d0, %d1
+; ATOMIC-NEXT: move.w %d2, %ccr
; ATOMIC-NEXT: beq .LBB14_1
; ATOMIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
@@ -1444,7 +1946,9 @@ define i32 @atomicrmw_sub_i32_arid(ptr align 2 %self) {
; ATOMIC-PIC-NEXT: seq %d1
; ATOMIC-PIC-NEXT: and.b #1, %d1
; ATOMIC-PIC-NEXT: cmpi.b #0, %d1
+; ATOMIC-PIC-NEXT: move.w %ccr, %d2
; ATOMIC-PIC-NEXT: move.l %d0, %d1
+; ATOMIC-PIC-NEXT: move.w %d2, %ccr
; ATOMIC-PIC-NEXT: beq .LBB14_1
; ATOMIC-PIC-NEXT: ; %bb.2: ; %atomicrmw.end
; ATOMIC-PIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
>From 5b720061b6a49342014ec78f4cabffa2cf1c1d7e Mon Sep 17 00:00:00 2001
From: Dan Salvato <dan at teamsalvato.com>
Date: Thu, 26 Mar 2026 12:59:48 -0400
Subject: [PATCH 2/6] Remove obsolete usage of `MOV8dc`
---
llvm/lib/Target/M68k/M68kInstrInfo.cpp | 67 ++++++++++++++------------
1 file changed, 36 insertions(+), 31 deletions(-)
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 8d9ccd887b680..1d9d0d85142eb 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -688,59 +688,64 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
const DebugLoc &DL, Register DstReg,
Register SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
- const auto &Subtarget = MBB.getParent()->getSubtarget<M68kSubtarget>();
unsigned Opc = 0;
MachineFunction &MF = *MBB.getParent();
const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
- // First deal with the normal symmetric copies.
- if (M68k::XR32RegClass.contains(DstReg, SrcReg))
+ // Symmetric register copies
+ if (M68k::XR32RegClass.contains(DstReg, SrcReg)) {
Opc = M68k::MOV32rr;
- else if (M68k::XR16RegClass.contains(DstReg, SrcReg))
+ } else if (M68k::XR16RegClass.contains(DstReg, SrcReg)) {
Opc = M68k::MOV16rr;
- else if (M68k::DR8RegClass.contains(DstReg, SrcReg))
+ } else if (M68k::DR8RegClass.contains(DstReg, SrcReg)) {
Opc = M68k::MOV8dd;
+ }
- // Now deal with asymmetrically sized copies. The cases that follow are upcast
- // moves.
- //
- // NOTE
- // These moves are not aware of type nature of these values and thus
- // won't do any SExt or ZExt and upper bits will basically contain garbage.
- else if (M68k::DR8RegClass.contains(SrcReg)) {
- if (M68k::XR16RegClass.contains(DstReg))
- Opc = M68k::MOVXd16d8;
- else if (M68k::XR32RegClass.contains(DstReg))
- Opc = M68k::MOVXd32d8;
+ // Asymmetric register copies
+ // 8 -> 16
+ else if (M68k::DR8RegClass.contains(SrcReg) &&
+ M68k::XR16RegClass.contains(DstReg)) {
+ Opc = M68k::MOVXd16d8;
+ // 8 -> 32
+ } else if (M68k::DR8RegClass.contains(SrcReg) &&
+ M68k::XR32RegClass.contains(DstReg)) {
+ Opc = M68k::MOVXd32d8;
+ // 16 -> 32
} else if (M68k::XR16RegClass.contains(SrcReg) &&
- M68k::XR32RegClass.contains(DstReg))
+ M68k::XR32RegClass.contains(DstReg)) {
Opc = M68k::MOVXd32d16;
+ }
+ // Copy from CCR
+ // NOTE: M68000 uses MOVE from SR to copy from CCR, all other variants use
else if (SrcReg == M68k::CCR) {
- if (M68k::DR8RegClass.contains(DstReg)) {
- Opc = M68k::MOV8dc;
- } else if (M68k::DR16RegClass.contains(DstReg)) {
- Opc = STI.isM68000() ? M68k::MOV16ds : M68k::MOV16dc;
- } else if (M68k::DR32RegClass.contains(DstReg)) {
+ if (M68k::DR8RegClass.contains(DstReg) ||
+ M68k::DR16RegClass.contains(DstReg) ||
+ M68k::DR32RegClass.contains(DstReg)) {
Opc = STI.isM68000() ? M68k::MOV16ds : M68k::MOV16dc;
} else {
LLVM_DEBUG(dbgs() << "Cannot copy CCR to " << RI.getName(DstReg) << '\n');
llvm_unreachable("Invalid register for MOVE from CCR");
}
- } else if (DstReg == M68k::CCR) {
- if (M68k::DR8RegClass.contains(SrcReg)) {
- // Promote used register to the next class
- SrcReg = getRegisterInfo().getMatchingSuperReg(
- SrcReg, M68k::MxSubRegIndex8Lo, &M68k::DR16RegClass);
- } else if (!M68k::DR16RegClass.contains(SrcReg) &&
- !M68k::DR32RegClass.contains(SrcReg)) {
+ }
+
+ // Copy to CCR
+ else if (DstReg == M68k::CCR) {
+ if (M68k::DR8RegClass.contains(SrcReg) ||
+ M68k::DR16RegClass.contains(SrcReg) ||
+ M68k::DR32RegClass.contains(SrcReg)) {
+ Opc = M68k::MOV16cd;
+ } else {
LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to CCR\n");
llvm_unreachable("Invalid register for MOVE to CCR");
}
- } else if (SrcReg == M68k::SR || DstReg == M68k::SR)
- llvm_unreachable("Cannot emit SR copy instruction");
}
+ // SR should never be a valid register for copying
+ else if (SrcReg == M68k::SR || DstReg == M68k::SR)
+ llvm_unreachable("Cannot explicitly copy to/from SR");
+
+ // We should now have our opcode
if (!Opc) {
LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
<< RI.getName(DstReg) << '\n');
>From fb2d154f713d62066cd11b166347d2e6d3dba799 Mon Sep 17 00:00:00 2001
From: Dan Salvato <dan at teamsalvato.com>
Date: Thu, 26 Mar 2026 13:18:19 -0400
Subject: [PATCH 3/6] Fix tests
---
llvm/test/CodeGen/M68k/Atomics/rmw.ll | 96 ++++++---
.../M68k/CodeModel/Large/Atomics/rmw.ll | 192 ++++++++++++------
2 files changed, 192 insertions(+), 96 deletions(-)
diff --git a/llvm/test/CodeGen/M68k/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/Atomics/rmw.ll
index ffd53ee157047..34dbb72f8ff0a 100644
--- a/llvm/test/CodeGen/M68k/Atomics/rmw.ll
+++ b/llvm/test/CodeGen/M68k/Atomics/rmw.ll
@@ -14,7 +14,8 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #255, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_add_1
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -27,7 +28,8 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #255, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_add_1
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -73,7 +75,8 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_2
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -86,7 +89,8 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_2
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -129,8 +133,10 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-000-NEXT: suba.l #12, %sp
; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_and_4
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -140,8 +146,10 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-010-NEXT: suba.l #12, %sp
; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_and_4
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -184,10 +192,13 @@ define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-000-NEXT: suba.l #20, %sp
; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-000-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-000-NEXT: move.l (28,%sp), (8,%sp)
-; NO-ATOMIC-000-NEXT: move.l (24,%sp), (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (32,%sp), (%sp)
; NO-ATOMIC-000-NEXT: jsr __atomic_fetch_xor_8
; NO-ATOMIC-000-NEXT: adda.l #20, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -197,10 +208,13 @@ define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-010-NEXT: suba.l #20, %sp
; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-010-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-010-NEXT: move.l (28,%sp), (8,%sp)
-; NO-ATOMIC-010-NEXT: move.l (24,%sp), (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (32,%sp), (%sp)
; NO-ATOMIC-010-NEXT: jsr __atomic_fetch_xor_8
; NO-ATOMIC-010-NEXT: adda.l #20, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -233,7 +247,8 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #255, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_or_1
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -246,7 +261,8 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #255, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_or_1
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -294,7 +310,8 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.l %d2, %d0
; NO-ATOMIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_nand_2
; NO-ATOMIC-000-NEXT: move.w %d2, %d0
; NO-ATOMIC-000-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
@@ -311,7 +328,8 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.l %d2, %d0
; NO-ATOMIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_nand_2
; NO-ATOMIC-010-NEXT: move.w %d2, %d0
; NO-ATOMIC-010-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
@@ -357,8 +375,10 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-000-NEXT: suba.l #12, %sp
; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_min_4
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -368,8 +388,10 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-010-NEXT: suba.l #12, %sp
; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_min_4
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -581,7 +603,8 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #255, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umin_1
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -594,7 +617,8 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #255, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umin_1
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -651,7 +675,8 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umax_2
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -664,7 +689,8 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umax_2
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -721,7 +747,8 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_2
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -734,7 +761,8 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_2
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -776,8 +804,10 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; %bb.0: ; %entry
; NO-ATOMIC-000-NEXT: suba.l #12, %sp
; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_4
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -787,8 +817,10 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; %bb.0: ; %entry
; NO-ATOMIC-010-NEXT: suba.l #12, %sp
; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_4
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
diff --git a/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
index 78b011e39465b..db59f986d11fd 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
@@ -19,7 +19,8 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #255, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_add_1
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -32,7 +33,8 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #255, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_add_1
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -45,7 +47,8 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-PIC-000-NEXT: and.l #255, %d0
; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_add_1 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
@@ -58,7 +61,8 @@ define i8 @atomicrmw_add_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-PIC-010-NEXT: and.l #255, %d0
; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_add_1 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
@@ -133,7 +137,8 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_sub_2
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -146,7 +151,8 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_sub_2
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -159,7 +165,8 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
@@ -172,7 +179,8 @@ define i16 @atomicrmw_sub_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_sub_2 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
@@ -244,8 +252,10 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-000-NEXT: suba.l #12, %sp
; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_and_4
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -255,8 +265,10 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-010-NEXT: suba.l #12, %sp
; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_and_4
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -266,8 +278,10 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_and_4 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
@@ -277,8 +291,10 @@ define i32 @atomicrmw_and_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_and_4 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
@@ -350,10 +366,13 @@ define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-000-NEXT: suba.l #20, %sp
; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-000-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-000-NEXT: move.l (28,%sp), (8,%sp)
-; NO-ATOMIC-000-NEXT: move.l (24,%sp), (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (32,%sp), (%sp)
; NO-ATOMIC-000-NEXT: jsr __atomic_fetch_xor_8
; NO-ATOMIC-000-NEXT: adda.l #20, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -363,10 +382,13 @@ define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-010-NEXT: suba.l #20, %sp
; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-010-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-010-NEXT: move.l (28,%sp), (8,%sp)
-; NO-ATOMIC-010-NEXT: move.l (24,%sp), (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (32,%sp), (%sp)
; NO-ATOMIC-010-NEXT: jsr __atomic_fetch_xor_8
; NO-ATOMIC-010-NEXT: adda.l #20, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -376,10 +398,13 @@ define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-PIC-000-NEXT: suba.l #20, %sp
; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-PIC-000-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (28,%sp), (8,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (24,%sp), (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (32,%sp), (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__atomic_fetch_xor_8 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: adda.l #20, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
@@ -389,10 +414,13 @@ define i64 @atomicrmw_xor_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-PIC-010-NEXT: suba.l #20, %sp
; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -24
+; NO-ATOMIC-PIC-010-NEXT: move.l (28,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (8,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (24,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (32,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: move.l #3, (12,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (28,%sp), (8,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (24,%sp), (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (32,%sp), (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__atomic_fetch_xor_8 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: adda.l #20, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
@@ -441,7 +469,8 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #255, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_or_1
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -454,7 +483,8 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #255, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_or_1
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -467,7 +497,8 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-PIC-000-NEXT: and.l #255, %d0
; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_or_1 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
@@ -480,7 +511,8 @@ define i8 @atomicrmw_or_i8(i8 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-PIC-010-NEXT: and.l #255, %d0
; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_or_1 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
@@ -557,7 +589,8 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.l %d2, %d0
; NO-ATOMIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_nand_2
; NO-ATOMIC-000-NEXT: move.w %d2, %d0
; NO-ATOMIC-000-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
@@ -574,7 +607,8 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.l %d2, %d0
; NO-ATOMIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_nand_2
; NO-ATOMIC-010-NEXT: move.w %d2, %d0
; NO-ATOMIC-010-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
@@ -591,7 +625,8 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: move.l %d2, %d0
; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_nand_2 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: move.w %d2, %d0
; NO-ATOMIC-PIC-000-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
@@ -608,7 +643,8 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: move.l %d2, %d0
; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_nand_2 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: move.w %d2, %d0
; NO-ATOMIC-PIC-010-NEXT: movem.l (8,%sp), %d2 ; 8-byte Folded Reload
@@ -684,8 +720,10 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-000-NEXT: suba.l #12, %sp
; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_min_4
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -695,8 +733,10 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-010-NEXT: suba.l #12, %sp
; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_min_4
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -706,8 +746,10 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_min_4 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
@@ -717,8 +759,10 @@ define i32 @atomicrmw_min_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_min_4 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
@@ -1121,7 +1165,8 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #255, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umin_1
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -1134,7 +1179,8 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #255, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umin_1
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -1147,7 +1193,8 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-PIC-000-NEXT: and.l #255, %d0
; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_umin_1 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
@@ -1160,7 +1207,8 @@ define i8 @atomicrmw_i8_umin(i8 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: move.b (19,%sp), %d0
; NO-ATOMIC-PIC-010-NEXT: and.l #255, %d0
; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_umin_1 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
@@ -1257,7 +1305,8 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_fetch_and_umax_2
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -1270,7 +1319,8 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_fetch_and_umax_2
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -1283,7 +1333,8 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_fetch_and_umax_2 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
@@ -1296,7 +1347,8 @@ define i16 @atomicrmw_umax_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_fetch_and_umax_2 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
@@ -1393,7 +1445,8 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_2
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -1406,7 +1459,8 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_2
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -1419,7 +1473,8 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-PIC-000-NEXT: and.l #65535, %d0
; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_lock_test_and_set_2 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
@@ -1432,7 +1487,8 @@ define i16 @atomicrmw_xchg_i16(i16 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: move.w (18,%sp), %d0
; NO-ATOMIC-PIC-010-NEXT: and.l #65535, %d0
; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_lock_test_and_set_2 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
@@ -1501,8 +1557,10 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; %bb.0: ; %entry
; NO-ATOMIC-000-NEXT: suba.l #12, %sp
; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-000-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-000-NEXT: jsr __sync_lock_test_and_set_4
; NO-ATOMIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-000-NEXT: rts
@@ -1512,8 +1570,10 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; %bb.0: ; %entry
; NO-ATOMIC-010-NEXT: suba.l #12, %sp
; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-010-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-010-NEXT: jsr __sync_lock_test_and_set_4
; NO-ATOMIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-010-NEXT: rts
@@ -1523,8 +1583,10 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: ; %bb.0: ; %entry
; NO-ATOMIC-PIC-000-NEXT: suba.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-000-NEXT: jsr (__sync_lock_test_and_set_4 at PLT,%pc)
; NO-ATOMIC-PIC-000-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
@@ -1534,8 +1596,10 @@ define i32 @atomicrmw_xchg_i32(i32 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: ; %bb.0: ; %entry
; NO-ATOMIC-PIC-010-NEXT: suba.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -16
-; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (16,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (20,%sp), %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (%sp)
; NO-ATOMIC-PIC-010-NEXT: jsr (__sync_lock_test_and_set_4 at PLT,%pc)
; NO-ATOMIC-PIC-010-NEXT: adda.l #12, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
>From 237de8a0d83fafe687b5d4f71acde82f000b992f Mon Sep 17 00:00:00 2001
From: Dan Salvato <dan at teamsalvato.com>
Date: Thu, 26 Mar 2026 13:41:33 -0400
Subject: [PATCH 4/6] Fix code formatting
---
llvm/lib/Target/M68k/M68kInstrInfo.cpp | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 1d9d0d85142eb..d8ee37daf6a9e 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -704,13 +704,13 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// Asymmetric register copies
// 8 -> 16
else if (M68k::DR8RegClass.contains(SrcReg) &&
- M68k::XR16RegClass.contains(DstReg)) {
+ M68k::XR16RegClass.contains(DstReg)) {
Opc = M68k::MOVXd16d8;
- // 8 -> 32
+ // 8 -> 32
} else if (M68k::DR8RegClass.contains(SrcReg) &&
M68k::XR32RegClass.contains(DstReg)) {
Opc = M68k::MOVXd32d8;
- // 16 -> 32
+ // 16 -> 32
} else if (M68k::XR16RegClass.contains(SrcReg) &&
M68k::XR32RegClass.contains(DstReg)) {
Opc = M68k::MOVXd32d16;
@@ -720,8 +720,8 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// NOTE: M68000 uses MOVE from SR to copy from CCR, all other variants use
else if (SrcReg == M68k::CCR) {
if (M68k::DR8RegClass.contains(DstReg) ||
- M68k::DR16RegClass.contains(DstReg) ||
- M68k::DR32RegClass.contains(DstReg)) {
+ M68k::DR16RegClass.contains(DstReg) ||
+ M68k::DR32RegClass.contains(DstReg)) {
Opc = STI.isM68000() ? M68k::MOV16ds : M68k::MOV16dc;
} else {
LLVM_DEBUG(dbgs() << "Cannot copy CCR to " << RI.getName(DstReg) << '\n');
@@ -732,8 +732,8 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// Copy to CCR
else if (DstReg == M68k::CCR) {
if (M68k::DR8RegClass.contains(SrcReg) ||
- M68k::DR16RegClass.contains(SrcReg) ||
- M68k::DR32RegClass.contains(SrcReg)) {
+ M68k::DR16RegClass.contains(SrcReg) ||
+ M68k::DR32RegClass.contains(SrcReg)) {
Opc = M68k::MOV16cd;
} else {
LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to CCR\n");
>From 3413d4212aa2d57a4b9530399a2177d74de6417f Mon Sep 17 00:00:00 2001
From: Dan Salvato <dan at teamsalvato.com>
Date: Sat, 28 Mar 2026 07:21:11 -0400
Subject: [PATCH 5/6] Improve verbosity of comments to explain the nature of
the workaround
---
llvm/lib/Target/M68k/M68kInstrInfo.cpp | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index d8ee37daf6a9e..c7cdb99a58d3e 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -702,6 +702,8 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
// Asymmetric register copies
+ // NOTE: There is no implicit sext/zext occurring during these moves, so the
+ // upper bits will be undefined.
// 8 -> 16
else if (M68k::DR8RegClass.contains(SrcReg) &&
M68k::XR16RegClass.contains(DstReg)) {
@@ -718,6 +720,7 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// Copy from CCR
// NOTE: M68000 uses MOVE from SR to copy from CCR, all other variants use
+ // MOVE from CCR.
else if (SrcReg == M68k::CCR) {
if (M68k::DR8RegClass.contains(DstReg) ||
M68k::DR16RegClass.contains(DstReg) ||
@@ -752,6 +755,19 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
llvm_unreachable("Cannot emit physreg copy instruction");
}
+ // FIXME
+ // Below is a workaround to prevent a live CCR from being killed by the COPY
+ // instruction. LLVM sometimes inserts a COPY pseudo instruction between
+ // compare and branch during MIR generation (e.g. during PHI node elimination)
+ // without any idea that on M68k, this is extremely likely to implicitly kill
+ // the CCR.
+ // The workaround checks whether CCR is live during this copy, and if so,
+ // backs up CCR and restores it after the copy. It's inefficient and prevents
+ // M68000-targeted builds from running on 010+ (because 000 uses MOVE from SR
+ // and 010+ uses MOVE from CCR).
+ // The fix condition is to prevent COPY from ever being inserted while CCR is
+ // live (which would also stop this workaround from ever triggering).
+
unsigned CCRSrcReg = STI.isM68000() ? M68k::SR : M68k::CCR;
// Get the live registers right before the COPY instruction. If CCR is
@@ -780,7 +796,7 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// CCR is live, so we must restore it after the copy. Prepare push/pop ops.
// 68000 must use MOVE from SR, 68010+ must use MOVE from CCR. In either
- // case, MOVE to CCR masks out the upper byte.
+ // case, upon moving back, MOVE to CCR will mask out the upper byte anyway.
// Look for an available data register for the CCR, or push to stack if
// there are none
>From 51ed2861b29d39c8c287230f94a83ccd2504fedf Mon Sep 17 00:00:00 2001
From: Dan Salvato <dan at teamsalvato.com>
Date: Thu, 30 Jul 2026 10:59:45 -0400
Subject: [PATCH 6/6] Update tests
---
llvm/test/CodeGen/M68k/Atomics/rmw.ll | 66 ++++-----
.../M68k/CodeModel/Large/Atomics/rmw.ll | 132 +++++++++---------
2 files changed, 102 insertions(+), 96 deletions(-)
diff --git a/llvm/test/CodeGen/M68k/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/Atomics/rmw.ll
index 34dbb72f8ff0a..8de7f952977af 100644
--- a/llvm/test/CodeGen/M68k/Atomics/rmw.ll
+++ b/llvm/test/CodeGen/M68k/Atomics/rmw.ll
@@ -445,13 +445,14 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-000-NEXT: suba.l #52, %sp
; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-000-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-000-NEXT: move.l (60,%sp), %d3
-; NO-ATOMIC-000-NEXT: move.l (56,%sp), %d4
-; NO-ATOMIC-000-NEXT: move.l (64,%sp), %a2
-; NO-ATOMIC-000-NEXT: move.l (4,%a2), %d1
-; NO-ATOMIC-000-NEXT: move.l (%a2), %d0
-; NO-ATOMIC-000-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-000-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-000-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-000-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-000-NEXT: jsr __atomic_load_8
+; NO-ATOMIC-000-NEXT: lea (24,%sp), %a2
; NO-ATOMIC-000-NEXT: bra .LBB7_1
; NO-ATOMIC-000-NEXT: .LBB7_3: ; %atomicrmw.start
; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
@@ -469,12 +470,12 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; =>This Inner Loop Header: Depth=1
; NO-ATOMIC-000-NEXT: move.l %d0, (24,%sp)
; NO-ATOMIC-000-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-000-NEXT: move.l %a2, (%sp)
-; NO-ATOMIC-000-NEXT: move.l %a3, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l %d3, %d2
+; NO-ATOMIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-000-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d4, %d2
; NO-ATOMIC-000-NEXT: sub.l %d1, %d2
; NO-ATOMIC-000-NEXT: move.w %sr, -(%sp)
-; NO-ATOMIC-000-NEXT: move.l %d4, %d2
+; NO-ATOMIC-000-NEXT: move.l %d5, %d2
; NO-ATOMIC-000-NEXT: move.w (%sp)+, %ccr
; NO-ATOMIC-000-NEXT: subx.l %d0, %d2
; NO-ATOMIC-000-NEXT: slt %d2
@@ -482,11 +483,11 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: bne .LBB7_3
; NO-ATOMIC-000-NEXT: ; %bb.2: ; %atomicrmw.start
; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-000-NEXT: move.l %d3, %d1
-; NO-ATOMIC-000-NEXT: move.l %d4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d4, %d1
+; NO-ATOMIC-000-NEXT: move.l %d5, %d0
; NO-ATOMIC-000-NEXT: bra .LBB7_3
; NO-ATOMIC-000-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-000-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-000-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
; NO-ATOMIC-000-NEXT: adda.l #52, %sp
; NO-ATOMIC-000-NEXT: rts
;
@@ -495,13 +496,14 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-010-NEXT: suba.l #52, %sp
; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-010-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-010-NEXT: move.l (60,%sp), %d3
-; NO-ATOMIC-010-NEXT: move.l (56,%sp), %d4
-; NO-ATOMIC-010-NEXT: move.l (64,%sp), %a2
-; NO-ATOMIC-010-NEXT: move.l (4,%a2), %d1
-; NO-ATOMIC-010-NEXT: move.l (%a2), %d0
-; NO-ATOMIC-010-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-010-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-010-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-010-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-010-NEXT: jsr __atomic_load_8
+; NO-ATOMIC-010-NEXT: lea (24,%sp), %a2
; NO-ATOMIC-010-NEXT: bra .LBB7_1
; NO-ATOMIC-010-NEXT: .LBB7_3: ; %atomicrmw.start
; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
@@ -519,12 +521,12 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; =>This Inner Loop Header: Depth=1
; NO-ATOMIC-010-NEXT: move.l %d0, (24,%sp)
; NO-ATOMIC-010-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-010-NEXT: move.l %a2, (%sp)
-; NO-ATOMIC-010-NEXT: move.l %a3, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l %d3, %d2
+; NO-ATOMIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-010-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d4, %d2
; NO-ATOMIC-010-NEXT: sub.l %d1, %d2
; NO-ATOMIC-010-NEXT: move.w %ccr, -(%sp)
-; NO-ATOMIC-010-NEXT: move.l %d4, %d2
+; NO-ATOMIC-010-NEXT: move.l %d5, %d2
; NO-ATOMIC-010-NEXT: move.w (%sp)+, %ccr
; NO-ATOMIC-010-NEXT: subx.l %d0, %d2
; NO-ATOMIC-010-NEXT: slt %d2
@@ -532,11 +534,11 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: bne .LBB7_3
; NO-ATOMIC-010-NEXT: ; %bb.2: ; %atomicrmw.start
; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-010-NEXT: move.l %d3, %d1
-; NO-ATOMIC-010-NEXT: move.l %d4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d4, %d1
+; NO-ATOMIC-010-NEXT: move.l %d5, %d0
; NO-ATOMIC-010-NEXT: bra .LBB7_3
; NO-ATOMIC-010-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-010-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-010-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
; NO-ATOMIC-010-NEXT: adda.l #52, %sp
; NO-ATOMIC-010-NEXT: rts
;
@@ -570,12 +572,12 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d0, (24,%sp)
; ATOMIC-NEXT: move.l %d1, (28,%sp)
-; ATOMIC-NEXT: move.l %a2, (%sp)
-; ATOMIC-NEXT: move.l %a3, (4,%sp)
-; ATOMIC-NEXT: move.l %d3, %d2
+; ATOMIC-NEXT: move.l %d3, (%sp)
+; ATOMIC-NEXT: move.l %a2, (4,%sp)
+; ATOMIC-NEXT: move.l %d4, %d2
; ATOMIC-NEXT: sub.l %d1, %d2
; ATOMIC-NEXT: move.w %ccr, -(%sp)
-; ATOMIC-NEXT: move.l %d4, %d2
+; ATOMIC-NEXT: move.l %d5, %d2
; ATOMIC-NEXT: move.w (%sp)+, %ccr
; ATOMIC-NEXT: subx.l %d0, %d2
; ATOMIC-NEXT: slt %d2
diff --git a/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
index db59f986d11fd..97c30b841a51e 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/Large/Atomics/rmw.ll
@@ -856,13 +856,14 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-000-NEXT: suba.l #52, %sp
; NO-ATOMIC-000-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-000-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-000-NEXT: move.l (60,%sp), %d3
-; NO-ATOMIC-000-NEXT: move.l (56,%sp), %d4
-; NO-ATOMIC-000-NEXT: move.l (64,%sp), %a2
-; NO-ATOMIC-000-NEXT: move.l (4,%a2), %d1
-; NO-ATOMIC-000-NEXT: move.l (%a2), %d0
-; NO-ATOMIC-000-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-000-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-000-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-000-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-000-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-000-NEXT: jsr __atomic_load_8
+; NO-ATOMIC-000-NEXT: lea (24,%sp), %a2
; NO-ATOMIC-000-NEXT: bra .LBB7_1
; NO-ATOMIC-000-NEXT: .LBB7_3: ; %atomicrmw.start
; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
@@ -880,12 +881,12 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: ; =>This Inner Loop Header: Depth=1
; NO-ATOMIC-000-NEXT: move.l %d0, (24,%sp)
; NO-ATOMIC-000-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-000-NEXT: move.l %a2, (%sp)
-; NO-ATOMIC-000-NEXT: move.l %a3, (4,%sp)
-; NO-ATOMIC-000-NEXT: move.l %d3, %d2
+; NO-ATOMIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-000-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-000-NEXT: move.l %d4, %d2
; NO-ATOMIC-000-NEXT: sub.l %d1, %d2
; NO-ATOMIC-000-NEXT: move.w %sr, -(%sp)
-; NO-ATOMIC-000-NEXT: move.l %d4, %d2
+; NO-ATOMIC-000-NEXT: move.l %d5, %d2
; NO-ATOMIC-000-NEXT: move.w (%sp)+, %ccr
; NO-ATOMIC-000-NEXT: subx.l %d0, %d2
; NO-ATOMIC-000-NEXT: slt %d2
@@ -893,11 +894,11 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-000-NEXT: bne .LBB7_3
; NO-ATOMIC-000-NEXT: ; %bb.2: ; %atomicrmw.start
; NO-ATOMIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-000-NEXT: move.l %d3, %d1
-; NO-ATOMIC-000-NEXT: move.l %d4, %d0
+; NO-ATOMIC-000-NEXT: move.l %d4, %d1
+; NO-ATOMIC-000-NEXT: move.l %d5, %d0
; NO-ATOMIC-000-NEXT: bra .LBB7_3
; NO-ATOMIC-000-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-000-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-000-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
; NO-ATOMIC-000-NEXT: adda.l #52, %sp
; NO-ATOMIC-000-NEXT: rts
;
@@ -906,13 +907,14 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-010-NEXT: suba.l #52, %sp
; NO-ATOMIC-010-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-010-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-010-NEXT: move.l (60,%sp), %d3
-; NO-ATOMIC-010-NEXT: move.l (56,%sp), %d4
-; NO-ATOMIC-010-NEXT: move.l (64,%sp), %a2
-; NO-ATOMIC-010-NEXT: move.l (4,%a2), %d1
-; NO-ATOMIC-010-NEXT: move.l (%a2), %d0
-; NO-ATOMIC-010-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-010-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-010-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-010-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-010-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-010-NEXT: jsr __atomic_load_8
+; NO-ATOMIC-010-NEXT: lea (24,%sp), %a2
; NO-ATOMIC-010-NEXT: bra .LBB7_1
; NO-ATOMIC-010-NEXT: .LBB7_3: ; %atomicrmw.start
; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
@@ -930,12 +932,12 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: ; =>This Inner Loop Header: Depth=1
; NO-ATOMIC-010-NEXT: move.l %d0, (24,%sp)
; NO-ATOMIC-010-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-010-NEXT: move.l %a2, (%sp)
-; NO-ATOMIC-010-NEXT: move.l %a3, (4,%sp)
-; NO-ATOMIC-010-NEXT: move.l %d3, %d2
+; NO-ATOMIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-010-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-010-NEXT: move.l %d4, %d2
; NO-ATOMIC-010-NEXT: sub.l %d1, %d2
; NO-ATOMIC-010-NEXT: move.w %ccr, -(%sp)
-; NO-ATOMIC-010-NEXT: move.l %d4, %d2
+; NO-ATOMIC-010-NEXT: move.l %d5, %d2
; NO-ATOMIC-010-NEXT: move.w (%sp)+, %ccr
; NO-ATOMIC-010-NEXT: subx.l %d0, %d2
; NO-ATOMIC-010-NEXT: slt %d2
@@ -943,11 +945,11 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-010-NEXT: bne .LBB7_3
; NO-ATOMIC-010-NEXT: ; %bb.2: ; %atomicrmw.start
; NO-ATOMIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-010-NEXT: move.l %d3, %d1
-; NO-ATOMIC-010-NEXT: move.l %d4, %d0
+; NO-ATOMIC-010-NEXT: move.l %d4, %d1
+; NO-ATOMIC-010-NEXT: move.l %d5, %d0
; NO-ATOMIC-010-NEXT: bra .LBB7_3
; NO-ATOMIC-010-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-010-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-010-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
; NO-ATOMIC-010-NEXT: adda.l #52, %sp
; NO-ATOMIC-010-NEXT: rts
;
@@ -956,13 +958,14 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: ; %bb.0:
; NO-ATOMIC-PIC-000-NEXT: suba.l #52, %sp
; NO-ATOMIC-PIC-000-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-PIC-000-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-PIC-000-NEXT: move.l (60,%sp), %d3
-; NO-ATOMIC-PIC-000-NEXT: move.l (56,%sp), %d4
-; NO-ATOMIC-PIC-000-NEXT: move.l (64,%sp), %a2
-; NO-ATOMIC-PIC-000-NEXT: move.l (4,%a2), %d1
-; NO-ATOMIC-PIC-000-NEXT: move.l (%a2), %d0
-; NO-ATOMIC-PIC-000-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-PIC-000-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-PIC-000-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-PIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-PIC-000-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-PIC-000-NEXT: jsr (__atomic_load_8 at PLT,%pc)
+; NO-ATOMIC-PIC-000-NEXT: lea (24,%sp), %a2
; NO-ATOMIC-PIC-000-NEXT: bra .LBB7_1
; NO-ATOMIC-PIC-000-NEXT: .LBB7_3: ; %atomicrmw.start
; NO-ATOMIC-PIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
@@ -980,12 +983,12 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: ; =>This Inner Loop Header: Depth=1
; NO-ATOMIC-PIC-000-NEXT: move.l %d0, (24,%sp)
; NO-ATOMIC-PIC-000-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l %a2, (%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l %a3, (4,%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l %d3, %d2
+; NO-ATOMIC-PIC-000-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-PIC-000-NEXT: move.l %d4, %d2
; NO-ATOMIC-PIC-000-NEXT: sub.l %d1, %d2
; NO-ATOMIC-PIC-000-NEXT: move.w %sr, -(%sp)
-; NO-ATOMIC-PIC-000-NEXT: move.l %d4, %d2
+; NO-ATOMIC-PIC-000-NEXT: move.l %d5, %d2
; NO-ATOMIC-PIC-000-NEXT: move.w (%sp)+, %ccr
; NO-ATOMIC-PIC-000-NEXT: subx.l %d0, %d2
; NO-ATOMIC-PIC-000-NEXT: slt %d2
@@ -993,11 +996,11 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-PIC-000-NEXT: bne .LBB7_3
; NO-ATOMIC-PIC-000-NEXT: ; %bb.2: ; %atomicrmw.start
; NO-ATOMIC-PIC-000-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-PIC-000-NEXT: move.l %d3, %d1
-; NO-ATOMIC-PIC-000-NEXT: move.l %d4, %d0
+; NO-ATOMIC-PIC-000-NEXT: move.l %d4, %d1
+; NO-ATOMIC-PIC-000-NEXT: move.l %d5, %d0
; NO-ATOMIC-PIC-000-NEXT: bra .LBB7_3
; NO-ATOMIC-PIC-000-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-PIC-000-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-PIC-000-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
; NO-ATOMIC-PIC-000-NEXT: adda.l #52, %sp
; NO-ATOMIC-PIC-000-NEXT: rts
;
@@ -1006,13 +1009,14 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: ; %bb.0:
; NO-ATOMIC-PIC-010-NEXT: suba.l #52, %sp
; NO-ATOMIC-PIC-010-NEXT: .cfi_def_cfa_offset -56
-; NO-ATOMIC-PIC-010-NEXT: movem.l %d2-%d4/%a2-%a3, (32,%sp) ; 24-byte Folded Spill
-; NO-ATOMIC-PIC-010-NEXT: move.l (60,%sp), %d3
-; NO-ATOMIC-PIC-010-NEXT: move.l (56,%sp), %d4
-; NO-ATOMIC-PIC-010-NEXT: move.l (64,%sp), %a2
-; NO-ATOMIC-PIC-010-NEXT: move.l (4,%a2), %d1
-; NO-ATOMIC-PIC-010-NEXT: move.l (%a2), %d0
-; NO-ATOMIC-PIC-010-NEXT: lea (24,%sp), %a3
+; NO-ATOMIC-PIC-010-NEXT: movem.l %d2-%d5/%a2, (32,%sp) ; 24-byte Folded Spill
+; NO-ATOMIC-PIC-010-NEXT: move.l (64,%sp), %d3
+; NO-ATOMIC-PIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l #0, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l (60,%sp), %d4
+; NO-ATOMIC-PIC-010-NEXT: move.l (56,%sp), %d5
+; NO-ATOMIC-PIC-010-NEXT: jsr (__atomic_load_8 at PLT,%pc)
+; NO-ATOMIC-PIC-010-NEXT: lea (24,%sp), %a2
; NO-ATOMIC-PIC-010-NEXT: bra .LBB7_1
; NO-ATOMIC-PIC-010-NEXT: .LBB7_3: ; %atomicrmw.start
; NO-ATOMIC-PIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
@@ -1030,12 +1034,12 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: ; =>This Inner Loop Header: Depth=1
; NO-ATOMIC-PIC-010-NEXT: move.l %d0, (24,%sp)
; NO-ATOMIC-PIC-010-NEXT: move.l %d1, (28,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l %a2, (%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l %a3, (4,%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l %d3, %d2
+; NO-ATOMIC-PIC-010-NEXT: move.l %d3, (%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %a2, (4,%sp)
+; NO-ATOMIC-PIC-010-NEXT: move.l %d4, %d2
; NO-ATOMIC-PIC-010-NEXT: sub.l %d1, %d2
; NO-ATOMIC-PIC-010-NEXT: move.w %ccr, -(%sp)
-; NO-ATOMIC-PIC-010-NEXT: move.l %d4, %d2
+; NO-ATOMIC-PIC-010-NEXT: move.l %d5, %d2
; NO-ATOMIC-PIC-010-NEXT: move.w (%sp)+, %ccr
; NO-ATOMIC-PIC-010-NEXT: subx.l %d0, %d2
; NO-ATOMIC-PIC-010-NEXT: slt %d2
@@ -1043,11 +1047,11 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; NO-ATOMIC-PIC-010-NEXT: bne .LBB7_3
; NO-ATOMIC-PIC-010-NEXT: ; %bb.2: ; %atomicrmw.start
; NO-ATOMIC-PIC-010-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; NO-ATOMIC-PIC-010-NEXT: move.l %d3, %d1
-; NO-ATOMIC-PIC-010-NEXT: move.l %d4, %d0
+; NO-ATOMIC-PIC-010-NEXT: move.l %d4, %d1
+; NO-ATOMIC-PIC-010-NEXT: move.l %d5, %d0
; NO-ATOMIC-PIC-010-NEXT: bra .LBB7_3
; NO-ATOMIC-PIC-010-NEXT: .LBB7_4: ; %atomicrmw.end
-; NO-ATOMIC-PIC-010-NEXT: movem.l (32,%sp), %d2-%d4/%a2-%a3 ; 24-byte Folded Reload
+; NO-ATOMIC-PIC-010-NEXT: movem.l (32,%sp), %d2-%d5/%a2 ; 24-byte Folded Reload
; NO-ATOMIC-PIC-010-NEXT: adda.l #52, %sp
; NO-ATOMIC-PIC-010-NEXT: rts
;
@@ -1081,12 +1085,12 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-NEXT: move.l %d0, (24,%sp)
; ATOMIC-NEXT: move.l %d1, (28,%sp)
-; ATOMIC-NEXT: move.l %a2, (%sp)
-; ATOMIC-NEXT: move.l %a3, (4,%sp)
-; ATOMIC-NEXT: move.l %d3, %d2
+; ATOMIC-NEXT: move.l %d3, (%sp)
+; ATOMIC-NEXT: move.l %a2, (4,%sp)
+; ATOMIC-NEXT: move.l %d4, %d2
; ATOMIC-NEXT: sub.l %d1, %d2
; ATOMIC-NEXT: move.w %ccr, -(%sp)
-; ATOMIC-NEXT: move.l %d4, %d2
+; ATOMIC-NEXT: move.l %d5, %d2
; ATOMIC-NEXT: move.w (%sp)+, %ccr
; ATOMIC-NEXT: subx.l %d0, %d2
; ATOMIC-NEXT: slt %d2
@@ -1132,12 +1136,12 @@ define i64 @atomicrmw_max_i64(i64 %val, ptr %ptr) {
; ATOMIC-PIC-NEXT: ; =>This Inner Loop Header: Depth=1
; ATOMIC-PIC-NEXT: move.l %d0, (24,%sp)
; ATOMIC-PIC-NEXT: move.l %d1, (28,%sp)
-; ATOMIC-PIC-NEXT: move.l %a2, (%sp)
-; ATOMIC-PIC-NEXT: move.l %a3, (4,%sp)
-; ATOMIC-PIC-NEXT: move.l %d3, %d2
+; ATOMIC-PIC-NEXT: move.l %d3, (%sp)
+; ATOMIC-PIC-NEXT: move.l %a2, (4,%sp)
+; ATOMIC-PIC-NEXT: move.l %d4, %d2
; ATOMIC-PIC-NEXT: sub.l %d1, %d2
; ATOMIC-PIC-NEXT: move.w %ccr, -(%sp)
-; ATOMIC-PIC-NEXT: move.l %d4, %d2
+; ATOMIC-PIC-NEXT: move.l %d5, %d2
; ATOMIC-PIC-NEXT: move.w (%sp)+, %ccr
; ATOMIC-PIC-NEXT: subx.l %d0, %d2
; ATOMIC-PIC-NEXT: slt %d2
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