[llvm] [AArch64] Select sqdmulh for smul.fix.sat with scale == eltbits-1 (PR #211579)

[via llvm-commits]

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@@ -8134,6 +8137,19 @@ SDValue AArch64TargetLowering::LowerVECTOR_COMPRESS(SDValue Op,
                      Passthru);
 }
 
+SDValue AArch64TargetLowering::LowerSMULFIXSAT(SDValue Op,
+                                               SelectionDAG &DAG) const {
+  EVT VT = Op.getValueType();
+  unsigned Scale = Op.getConstantOperandVal(2);
+  if (Scale != VT.getScalarSizeInBits() - 1)
+    return SDValue();
+
+  SDLoc DL(Op);
+  SDValue ID = DAG.getConstant(Intrinsic::aarch64_neon_sqdmulh, DL, MVT::i32);
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guyfischman wrote:

I took the first option since it matches the file.

Agreed on the compare, but it should probably be its own PR.

https://github.com/llvm/llvm-project/pull/211579