[llvm] [X86] Interleave independent reductions to share cross-lane extracts (PR #209963)
Pranav Gorantla via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 30 02:28:32 PDT 2026
https://github.com/pranav-159 updated https://github.com/llvm/llvm-project/pull/209963
>From 9f1bcc6b9c10e8c4f71baa318bc3a6a26b4c97c3 Mon Sep 17 00:00:00 2001
From: Pranav Gorantla <Pranav.Gorantla at amd.com>
Date: Wed, 8 Jul 2026 18:25:23 +0530
Subject: [PATCH] [X86] Interleave independent reductions to share cross-lane
extracts
A horizontal reduction collapses all lanes of a vector to a scalar. Reaching a
128-bit lane requires cross-lane extracts - vextracti64x4 (512->256) and
vextracti128 (256->128) - which are the costly part: a cross-lane move is higher
latency than the in-lane folds and competes for the limited vector-shuffle
throughput, the bottleneck when several reductions run together. N independent
reductions pay that extract chain N times.
The transform interleaves the reductions' inputs into a single register with
unpck shuffles (whose steps also apply the reduction op), then runs one shared
reduction over that register, leaving one result per lane. The expensive
cross-lane extracts are done once for the whole group instead of once per
reduction, trading N-1 extract chains for cheaper in-lane shuffles.
Each <16 x i32> add reduction, on its own, is:
vextracti64x4 ; 512 -> 256, cross-lane
vpaddd
vextracti128 ; 256 -> 128, cross-lane
vpaddd
vpshufd ; in-lane tail
vpaddd
vpshufd
vpaddd
so two of them pay both extracts twice. Interleaved:
vpunpckldq A, B
vpunpckhdq A, B
vpaddd
vextracti64x4 ; shared by A and B
vpaddd
vextracti128 ; shared by A and B
vpaddd
vpshufd ; in-lane reduction step, shared
vpaddd
vmovd ; A = lane 0
vpextrd ; B = lane 1
Implemented as combineSiblingReductions, a pre-legalize DAG combine keyed on the
integer ISD::VECREDUCE_* nodes, matching the reduction nodes directly rather than
the expanded extract/shuffle trees. Gated on the
prefer-unpck-over-cross-lane-extract subtarget feature (znver4/znver5); inert
elsewhere.
Only fires for a group of >= 2 same-(opcode, input type) integer reductions,
>= 256 bits, whose inputs are independent - no load or same-opcode reduction in
the operand chain, which would introduce a false dependency or a cycle.
Assisted-by: Claude Opus 4.7 <noreply at anthropic.com>
---
llvm/lib/Target/X86/X86.td | 10 +-
llvm/lib/Target/X86/X86ISelLowering.cpp | 205 ++-
.../CodeGen/X86/vector-reduce-interleave.ll | 1196 +++++++++++++++++
3 files changed, 1409 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/vector-reduce-interleave.ll
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index f40b937efa74b..4bd316b8ad5c2 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -842,6 +842,13 @@ def TuningFastHorizontalOps
"normal vector instructions with shuffles",
[], InlineIgnore>;
+def TuningPreferUnpckOverCrossLaneExtract
+ : SubtargetFeature<"prefer-unpck-over-cross-lane-extract",
+ "PreferUnpckOverCrossLaneExtract", "true",
+ "Prefer unpck shuffles over cross-lane extracts, e.g. to "
+ "share extracts across independent vector reductions",
+ [], InlineIgnore>;
+
def TuningFastScalarShiftMasks
: SubtargetFeature<
"fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
@@ -1716,7 +1723,8 @@ def ProcessorFeatures {
list<SubtargetFeature> ZN4AdditionalTuning = [TuningFastDPWSSD,
TuningCOMPRESSFalseDeps,
- TuningEXPANDFalseDeps];
+ TuningEXPANDFalseDeps,
+ TuningPreferUnpckOverCrossLaneExtract];
list<SubtargetFeature> ZN4Tuning =
!listconcat(ZN3Tuning, ZN4AdditionalTuning);
list<SubtargetFeature> ZN4AdditionalFeatures = [FeatureAVX512,
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d78c478ab672f..0bd75f568afab 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2827,7 +2827,15 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
ISD::ANY_EXTEND_VECTOR_INREG,
ISD::SIGN_EXTEND_VECTOR_INREG,
ISD::ZERO_EXTEND_VECTOR_INREG,
+ ISD::VECREDUCE_ADD,
ISD::VECREDUCE_MUL,
+ ISD::VECREDUCE_AND,
+ ISD::VECREDUCE_OR,
+ ISD::VECREDUCE_XOR,
+ ISD::VECREDUCE_SMAX,
+ ISD::VECREDUCE_SMIN,
+ ISD::VECREDUCE_UMAX,
+ ISD::VECREDUCE_UMIN,
ISD::SINT_TO_FP,
ISD::UINT_TO_FP,
ISD::FP_TO_SINT,
@@ -48130,6 +48138,190 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
+//===----------------------------------------------------------------------===//
+// X86 sibling-reduction interleaving.
+//
+// Fuse independent same-(opcode, element-type) reductions to share their
+// cross-lane extracts (vextracti64x4 512->256, vextracti128 256->128) -- the
+// dominant cost of a reduction. Without this each of the N reductions extracts
+// on its own; interleaving with unpck lets a single shared descent reduce all N,
+// cutting the total instruction count (one set of extracts and folds, not N).
+// Two <8 x i32> adds:
+//
+// A ; [a0 a1 a2 a3 | a4 a5 a6 a7]
+// hi = vextracti128 A ; [a4 a5 a6 a7] cross-lane, A only
+// a = add A.lo, hi ; [a0+a4 a1+a5 a2+a6 a3+a7]
+// ... in-lane fold ; a[0] = sum(A); B repeats -> a second vextracti128
+//
+// unpck mixes sibling reductions into one register; one fold reduces A and B:
+//
+// lo = unpcklo A, B ; [a0 b0 a1 b1 | a4 b4 a5 b5]
+// hi = unpckhi A, B ; [a2 b2 a3 b3 | a6 b6 a7 b7]
+// p = add lo, hi ; [a0+a2 b0+b2 a1+a3 b1+b3 |
+// a4+a6 b4+b6 a5+a7 b5+b7] A even, B odd
+// hi = vextracti128 p ; [a4+a6 b4+b6 a5+a7 b5+b7] ONE extract, shared
+// p = add p.lo, hi ; [a0+a2+a4+a6 b0+b2+b4+b6
+// a1+a3+a5+a7 b1+b3+b5+b7] still: a even, b odd
+// ... in-lane fold ; p = [sum(A) sum(B)] in lanes 0, 1
+//
+// Appends {reduction node, lane-scalar result} pairs to Repl, one per
+// reduction in the group.
+//===----------------------------------------------------------------------===//
+static void emitInterleavedReductions(SelectionDAG &DAG, const SDLoc &DL,
+ ArrayRef<SDNode *> Group, unsigned Op,
+ SmallVectorImpl<std::pair<SDNode *, SDValue>> &Repl) {
+ unsigned N = Group.size();
+ assert(N >= 2 && isPowerOf2_32(N) &&
+ N <= 128 / Group[0]->getOperand(0).getScalarValueSizeInBits() &&
+ "group must be a pow2 that fits one 128-bit lane");
+ SmallVector<SDValue, 16> V;
+ for (SDNode *R : Group)
+ V.push_back(R->getOperand(0)); // the reduction's input vector
+
+ // Pairwise tree: each level combines adjacent pairs into one, halving the
+ // number of vectors in V until a single vector packs all inputs.
+ while (V.size() > 1) {
+ unsigned NumOps = V.size();
+ for (unsigned i = 0; i != NumOps; i += 2) {
+ SDValue L = V[i], R = V[i + 1];
+ EVT VT = L.getValueType();
+ // op(unpcklo(L,R), unpckhi(L,R)): riffle L and R together and fold, so one
+ // vector carries both (L in even lanes, R in odd).
+ V[i / 2] = DAG.getNode(Op, DL, VT, getUnpackl(DAG, DL, VT, L, R),
+ getUnpackh(DAG, DL, VT, L, R));
+ }
+ V.resize(NumOps / 2);
+ }
+
+ // Fold down to one lane per reduction: while legal, split and op the lo/hi
+ // subvectors; then shuffle-fold within the 128-bit register.
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+ SDValue Packed = V[0];
+ EVT VT = Packed.getValueType();
+ for (unsigned W = VT.getVectorNumElements(); W > N; W >>= 1) {
+ EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
+ if (TLI.isOperationLegalOrCustom(Op, HalfVT)) {
+ auto [Lo, Hi] = DAG.SplitVector(Packed, DL);
+ Packed = DAG.getNode(Op, DL, HalfVT, Lo, Hi);
+ VT = HalfVT;
+ } else {
+ SDValue Hi = DAG.getVectorShuffle(
+ VT, DL, Packed, DAG.getUNDEF(VT),
+ createSequentialMask(W / 2, W / 2, VT.getVectorNumElements() - W / 2));
+ Packed = DAG.getNode(Op, DL, VT, Packed, Hi);
+ }
+ }
+
+ // Each level ran op(unpcklo(L,R), unpckhi(L,R)), which interleaves L,R so lane
+ // k goes to 2k (from L, even) or 2k+1 (from R, odd) -- doubling the index and
+ // appending the L/R choice, which is bit l of r (the reduction's index in the
+ // group):
+ //
+ // lane_l = 2 * lane_{l-1} + r_l
+ //
+ // Expanding over all l levels gives the lane as:
+ //
+ // lane = sum_l r_l * 2^(LogN-1-l)
+ //
+ // which is exactly r with its bits reversed, i.e. reverseBits(r).
+ unsigned LogN = Log2_32(N);
+ for (unsigned r = 0; r < N; ++r) {
+ unsigned Lane = APInt(LogN, r).reverseBits().getZExtValue();
+ EVT ResVT = Group[r]->getValueType(0);
+ SDValue Out = DAG.getExtractVectorElt(DL, ResVT, Packed, Lane);
+ Repl.emplace_back(Group[r], Out);
+ }
+}
+
+// True if V (a fused reduction's input) is independent of the other reductions.
+static bool isIndependentReductionInput(SDValue V, unsigned Opc,
+ unsigned Depth = 4) {
+ if (V.getOpcode() == ISD::CopyFromReg || V.getNumOperands() == 0)
+ return true; // live-in register / constant / undef leaf
+ // Bail on another reduction (cycle), a load (false dependency), or too deep.
+ if (V.getOpcode() == Opc || isa<MemSDNode>(V.getNode()) || Depth == 0)
+ return false;
+ for (SDValue O : V->op_values())
+ if (!isIndependentReductionInput(O, Opc, Depth - 1))
+ return false;
+ return true;
+}
+
+// N is a VECREDUCE_* node. Fuse it with independent sibling VECREDUCE_* nodes of
+// the same opcode and input type so they share one cross-lane extract chain.
+static SDValue combineSiblingReductions(SDNode *N, SelectionDAG &DAG,
+ TargetLowering::DAGCombinerInfo &DCI,
+ const X86Subtarget &Subtarget) {
+ if (!Subtarget.preferUnpckOverCrossLaneExtract())
+ return SDValue();
+ if (!DCI.isBeforeLegalizeOps())
+ return SDValue();
+
+ unsigned Opc = N->getOpcode();
+ ISD::NodeType BinOp = ISD::getVecReduceBaseOpcode(Opc);
+
+ SDValue Src = N->getOperand(0);
+ EVT SrcVT = Src.getValueType();
+ // Only 256/512-bit reductions need cross-lane extracts (which fusing shares).
+ unsigned SizeInBits = SrcVT.isFixedLengthVector() ? SrcVT.getFixedSizeInBits() : 0;
+ if (SizeInBits != 256 && SizeInBits != 512)
+ return SDValue();
+
+ // Only match reductions whose input is independent.
+ // Note: after fusing, each result depends on ALL fused inputs (the shared
+ // interleave consumes them together), not just its own -- a false dependency,
+ // so a late input delays every result and can lengthen the critical path,
+ // though in practice we have not seen this regress.
+ if (!isIndependentReductionInput(Src, Opc))
+ return SDValue();
+
+ // vXi8 add reductions are better lowered to PSADBW.
+ if (BinOp == ISD::ADD && SrcVT.getScalarType() == MVT::i8)
+ return SDValue();
+
+ // Gather sibling reductions with the same opcode, vector type, and an
+ // independent input. N goes first so it always lands in the first chunk.
+ SmallVector<SDNode *, 8> Work;
+ Work.push_back(N);
+ for (SDNode &M : DAG.allnodes()) {
+ if (&M == N || M.getOpcode() != Opc)
+ continue;
+ SDValue Root = M.getOperand(0);
+ if (Root.getValueType() == SrcVT && isIndependentReductionInput(Root, Opc))
+ Work.push_back(&M);
+ }
+ if (Work.size() < 2)
+ return SDValue();
+
+ // Cap each group at one 128-bit lane of elements so the interleave stays
+ // within a lane.
+ unsigned Cap = 128 / SrcVT.getScalarSizeInBits();
+
+ // Interleave the group in balanced pow2 chunks, each up to one 128-bit lane.
+ // TODO: support non-pow2 groups; a lone remainder (e.g. 3 -> {2, 1}) is
+ // reduced on its own.
+ SmallVector<std::pair<SDNode *, SDValue>, 16> Repl;
+ while (Work.size() >= 2) {
+ unsigned Take = std::min<unsigned>(Cap, llvm::bit_floor<uint32_t>(Work.size()));
+ SDLoc DL(Work.front());
+ emitInterleavedReductions(DAG, DL, ArrayRef<SDNode *>(Work).take_front(Take),
+ BinOp, Repl);
+ Work.erase(Work.begin(), Work.begin() + Take);
+ }
+ if (Repl.empty())
+ return SDValue();
+
+ // Wire in the interleaved results; return N's replacement.
+ SDValue Res;
+ for (auto &P : Repl) {
+ if (P.first == N)
+ Res = P.second;
+ else
+ DCI.CombineTo(P.first, P.second);
+ }
+ return Res;
+}
+
static SDValue combineVECREDUCE_MUL(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
SDValue Src = N->getOperand(0);
@@ -63042,7 +63234,18 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case X86ISD::VFCMULC:
case X86ISD::VFMULC: return combineFMulcFCMulc(N, DAG, Subtarget);
case ISD::FNEG: return combineFneg(N, DAG, DCI, Subtarget);
- case ISD::VECREDUCE_MUL: return combineVECREDUCE_MUL(N, DAG, Subtarget);
+ case ISD::VECREDUCE_MUL:
+ if (SDValue V = combineVECREDUCE_MUL(N, DAG, Subtarget))
+ return V;
+ return combineSiblingReductions(N, DAG, DCI, Subtarget);
+ case ISD::VECREDUCE_ADD:
+ case ISD::VECREDUCE_AND:
+ case ISD::VECREDUCE_OR:
+ case ISD::VECREDUCE_XOR:
+ case ISD::VECREDUCE_SMAX:
+ case ISD::VECREDUCE_SMIN:
+ case ISD::VECREDUCE_UMAX:
+ case ISD::VECREDUCE_UMIN: return combineSiblingReductions(N, DAG, DCI, Subtarget);
case ISD::TRUNCATE: return combineTruncate(N, DAG, Subtarget);
case X86ISD::VTRUNC: return combineVTRUNC(N, DAG, DCI);
case X86ISD::VTRUNCS:
diff --git a/llvm/test/CodeGen/X86/vector-reduce-interleave.ll b/llvm/test/CodeGen/X86/vector-reduce-interleave.ll
new file mode 100644
index 0000000000000..f750620ae5de4
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-reduce-interleave.ll
@@ -0,0 +1,1196 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -disable-expand-reductions -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl,+prefer-unpck-over-cross-lane-extract | FileCheck %s --check-prefixes=CHECK,UNPCK
+; RUN: llc < %s -mtriple=x86_64-- -disable-expand-reductions -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,BASE
+
+; -disable-expand-reductions keeps add/and/or/xor as VECREDUCE nodes (X86 expands
+; them in IR otherwise) so the interleaving combine can match them.
+
+declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
+declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64>)
+declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
+declare i8 @llvm.vector.reduce.add.v32i8(<32 x i8>)
+declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.xor.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
+declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)
+declare i8 @llvm.vector.reduce.mul.v64i8(<64 x i8>)
+declare i32 @llvm.vector.reduce.or.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.mul.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.smax.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.smin.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)
+
+; =============================================================================
+; Interleaved: element widths and vector sizes.
+; =============================================================================
+
+define i32 @add_i32_512_n2(<16 x i32> %a, <16 x i32> %b) {
+; UNPCK-LABEL: add_i32_512_n2:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm2 = zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[14],zmm0[14],zmm1[15],zmm0[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[12],zmm0[12],zmm1[13],zmm0[13]
+; UNPCK-NEXT: vpaddd %zmm2, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %ecx
+; UNPCK-NEXT: vpextrd $1, %xmm0, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i32_512_n2:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm2
+; BASE-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm2
+; BASE-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: addl %eax, %ecx
+; BASE-NEXT: vextracti64x4 $1, %zmm1, %ymm0
+; BASE-NEXT: vpaddd %ymm0, %ymm1, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %edx
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: addl %edx, %eax
+; BASE-NEXT: imull %ecx, %eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
+ %rb = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %b)
+ %r = mul i32 %ra, %rb
+ ret i32 %r
+}
+
+; i32/512, N=4.
+define i32 @add_i32_512_n4(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i32> %d) {
+; UNPCK-LABEL: add_i32_512_n4:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm4 = zmm1[2],zmm2[2],zmm1[3],zmm2[3],zmm1[6],zmm2[6],zmm1[7],zmm2[7],zmm1[10],zmm2[10],zmm1[11],zmm2[11],zmm1[14],zmm2[14],zmm1[15],zmm2[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm1 = zmm1[0],zmm2[0],zmm1[1],zmm2[1],zmm1[4],zmm2[4],zmm1[5],zmm2[5],zmm1[8],zmm2[8],zmm1[9],zmm2[9],zmm1[12],zmm2[12],zmm1[13],zmm2[13]
+; UNPCK-NEXT: vpaddd %zmm4, %zmm1, %zmm1
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm2 = zmm3[2],zmm0[2],zmm3[3],zmm0[3],zmm3[6],zmm0[6],zmm3[7],zmm0[7],zmm3[10],zmm0[10],zmm3[11],zmm0[11],zmm3[14],zmm0[14],zmm3[15],zmm0[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm3[0],zmm0[0],zmm3[1],zmm0[1],zmm3[4],zmm0[4],zmm3[5],zmm0[5],zmm3[8],zmm0[8],zmm3[9],zmm0[9],zmm3[12],zmm0[12],zmm3[13],zmm0[13]
+; UNPCK-NEXT: vpaddd %zmm2, %zmm0, %zmm0
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm2 = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13]
+; UNPCK-NEXT: vpaddd %zmm2, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %eax
+; UNPCK-NEXT: vpextrd $3, %xmm0, %ecx
+; UNPCK-NEXT: imull %eax, %ecx
+; UNPCK-NEXT: vpextrd $1, %xmm0, %edx
+; UNPCK-NEXT: vpextrd $2, %xmm0, %eax
+; UNPCK-NEXT: imull %edx, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i32_512_n4:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm4
+; BASE-NEXT: vpaddd %ymm4, %ymm0, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm4
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %edx
+; BASE-NEXT: addl %eax, %edx
+; BASE-NEXT: vextracti64x4 $1, %zmm1, %ymm0
+; BASE-NEXT: vpaddd %ymm0, %ymm1, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: addl %eax, %ecx
+; BASE-NEXT: imull %edx, %ecx
+; BASE-NEXT: vextracti64x4 $1, %zmm2, %ymm0
+; BASE-NEXT: vpaddd %ymm0, %ymm2, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %edx
+; BASE-NEXT: addl %eax, %edx
+; BASE-NEXT: vextracti64x4 $1, %zmm3, %ymm0
+; BASE-NEXT: vpaddd %ymm0, %ymm3, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %esi
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: addl %esi, %eax
+; BASE-NEXT: imull %edx, %eax
+; BASE-NEXT: imull %ecx, %eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
+ %rb = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %b)
+ %rc = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %c)
+ %rd = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %d)
+ %m0 = mul i32 %ra, %rb
+ %m1 = mul i32 %m0, %rc
+ %r = mul i32 %m1, %rd
+ ret i32 %r
+}
+
+; i32/256, N=4.
+define i32 @add_i32_256_n4(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) {
+; UNPCK-LABEL: add_i32_256_n4:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} ymm4 = ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[6],ymm2[6],ymm1[7],ymm2[7]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[4],ymm2[4],ymm1[5],ymm2[5]
+; UNPCK-NEXT: vpaddd %ymm4, %ymm1, %ymm1
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm3[2],ymm0[2],ymm3[3],ymm0[3],ymm3[6],ymm0[6],ymm3[7],ymm0[7]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm3[0],ymm0[0],ymm3[1],ymm0[1],ymm3[4],ymm0[4],ymm3[5],ymm0[5]
+; UNPCK-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} ymm2 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
+; UNPCK-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %eax
+; UNPCK-NEXT: vpextrd $3, %xmm0, %ecx
+; UNPCK-NEXT: imull %eax, %ecx
+; UNPCK-NEXT: vpextrd $1, %xmm0, %edx
+; UNPCK-NEXT: vpextrd $2, %xmm0, %eax
+; UNPCK-NEXT: imull %edx, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i32_256_n4:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm4
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: addl %eax, %ecx
+; BASE-NEXT: vextracti128 $1, %ymm1, %xmm0
+; BASE-NEXT: vpaddd %xmm0, %xmm1, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %edx
+; BASE-NEXT: addl %eax, %edx
+; BASE-NEXT: imull %ecx, %edx
+; BASE-NEXT: vextracti128 $1, %ymm2, %xmm0
+; BASE-NEXT: vpaddd %xmm0, %xmm2, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: addl %eax, %ecx
+; BASE-NEXT: vextracti128 $1, %ymm3, %xmm0
+; BASE-NEXT: vpaddd %xmm0, %xmm3, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %esi
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: addl %esi, %eax
+; BASE-NEXT: imull %ecx, %eax
+; BASE-NEXT: imull %edx, %eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %a)
+ %rb = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %b)
+ %rc = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %c)
+ %rd = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %d)
+ %m0 = mul i32 %ra, %rb
+ %m1 = mul i32 %m0, %rc
+ %r = mul i32 %m1, %rd
+ ret i32 %r
+}
+
+; i16/256, N=2.
+define i16 @add_i16_256_n2(<16 x i16> %a, <16 x i16> %b) {
+; UNPCK-LABEL: add_i16_256_n2:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhwd {{.*#+}} ymm2 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15]
+; UNPCK-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11]
+; UNPCK-NEXT: vpaddw %ymm2, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddw %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpaddw %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; UNPCK-NEXT: vpaddw %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %ecx
+; UNPCK-NEXT: vpextrw $1, %xmm0, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: # kill: def $ax killed $ax killed $eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i16_256_n2:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm2
+; BASE-NEXT: vpaddw %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddw %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,1,1]
+; BASE-NEXT: vpaddw %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpextrw $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: addl %eax, %ecx
+; BASE-NEXT: vextracti128 $1, %ymm1, %xmm0
+; BASE-NEXT: vpaddw %xmm0, %xmm1, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddw %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; BASE-NEXT: vpaddw %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrw $1, %xmm0, %edx
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: addl %edx, %eax
+; BASE-NEXT: imull %ecx, %eax
+; BASE-NEXT: # kill: def $ax killed $ax killed $eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %a)
+ %rb = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %b)
+ %r = mul i16 %ra, %rb
+ ret i16 %r
+}
+
+; i64/512, N=2 (Cap=2).
+define i64 @add_i64_512_n2(<8 x i64> %a, <8 x i64> %b) {
+; UNPCK-LABEL: add_i64_512_n2:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhqdq {{.*#+}} zmm2 = zmm1[1],zmm0[1],zmm1[3],zmm0[3],zmm1[5],zmm0[5],zmm1[7],zmm0[7]
+; UNPCK-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm1[0],zmm0[0],zmm1[2],zmm0[2],zmm1[4],zmm0[4],zmm1[6],zmm0[6]
+; UNPCK-NEXT: vpaddq %zmm2, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovq %xmm0, %rcx
+; UNPCK-NEXT: vpextrq $1, %xmm0, %rax
+; UNPCK-NEXT: imulq %rcx, %rax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i64_512_n2:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm2
+; BASE-NEXT: vpaddq %ymm2, %ymm0, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm2
+; BASE-NEXT: vpaddq %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpextrq $1, %xmm0, %rax
+; BASE-NEXT: vmovq %xmm0, %rcx
+; BASE-NEXT: addq %rax, %rcx
+; BASE-NEXT: vextracti64x4 $1, %zmm1, %ymm0
+; BASE-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrq $1, %xmm0, %rdx
+; BASE-NEXT: vmovq %xmm0, %rax
+; BASE-NEXT: addq %rdx, %rax
+; BASE-NEXT: imulq %rcx, %rax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %a)
+ %rb = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %b)
+ %r = mul i64 %ra, %rb
+ ret i64 %r
+}
+
+; i8 element width interleaves directly (using a non-add op, since i8 add is
+; PSADBW-skipped).
+define i8 @xor_i8_256_n2(<32 x i8> %a, <32 x i8> %b) {
+; UNPCK-LABEL: xor_i8_256_n2:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
+; UNPCK-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23]
+; UNPCK-NEXT: vpxor %ymm2, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; UNPCK-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpsrld $16, %xmm0, %xmm1
+; UNPCK-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %ecx
+; UNPCK-NEXT: vpextrb $1, %xmm0, %eax
+; UNPCK-NEXT: addb %cl, %al
+; UNPCK-NEXT: # kill: def $al killed $al killed $eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: xor_i8_256_n2:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm2
+; BASE-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; BASE-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,1,1]
+; BASE-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpsrld $16, %xmm0, %xmm2
+; BASE-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpsrlw $8, %xmm0, %xmm2
+; BASE-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: vextracti128 $1, %ymm1, %xmm0
+; BASE-NEXT: vpxor %xmm0, %xmm1, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; BASE-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpsrld $16, %xmm0, %xmm1
+; BASE-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpsrlw $8, %xmm0, %xmm1
+; BASE-NEXT: vpxor %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: addb %cl, %al
+; BASE-NEXT: # kill: def $al killed $al killed $eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %a)
+ %rb = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %b)
+ %r = add i8 %ra, %rb
+ ret i8 %r
+}
+
+; i8 mul: each v64i8 mul is first promoted to a v32i16 mul reduction, then the
+; promoted i16 siblings are interleaved (relaxed independence lets the
+; promotion's undef operands through).
+define i8 @mul_i8_512_n2(<64 x i8> %a, <64 x i8> %b) {
+; UNPCK-LABEL: mul_i8_512_n2:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
+; UNPCK-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
+; UNPCK-NEXT: vpmullw %zmm2, %zmm0, %zmm0
+; UNPCK-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
+; UNPCK-NEXT: vpunpcklbw {{.*#+}} zmm1 = zmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
+; UNPCK-NEXT: vpmullw %zmm2, %zmm1, %zmm1
+; UNPCK-NEXT: vpunpckhwd {{.*#+}} zmm2 = zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31]
+; UNPCK-NEXT: vpunpcklwd {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27]
+; UNPCK-NEXT: vpmullw %zmm2, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpmullw %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpmullw %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpmullw %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; UNPCK-NEXT: vpmullw %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %ecx
+; UNPCK-NEXT: vpextrw $1, %xmm0, %eax
+; UNPCK-NEXT: addb %cl, %al
+; UNPCK-NEXT: # kill: def $al killed $al killed $eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: mul_i8_512_n2:
+; BASE: # %bb.0:
+; BASE-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
+; BASE-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
+; BASE-NEXT: vpmullw %zmm2, %zmm0, %zmm0
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm2
+; BASE-NEXT: vpmullw %ymm2, %ymm0, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm2
+; BASE-NEXT: vpmullw %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; BASE-NEXT: vpmullw %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,1,1]
+; BASE-NEXT: vpmullw %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpsrld $16, %xmm0, %xmm2
+; BASE-NEXT: vpmullw %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: vpunpckhbw {{.*#+}} zmm0 = zmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
+; BASE-NEXT: vpunpcklbw {{.*#+}} zmm1 = zmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
+; BASE-NEXT: vpmullw %zmm0, %zmm1, %zmm0
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; BASE-NEXT: vpmullw %ymm1, %ymm0, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpmullw %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpmullw %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; BASE-NEXT: vpmullw %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpsrld $16, %xmm0, %xmm1
+; BASE-NEXT: vpmullw %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: addb %cl, %al
+; BASE-NEXT: # kill: def $al killed $al killed $eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> %a)
+ %rb = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> %b)
+ %r = add i8 %ra, %rb
+ ret i8 %r
+}
+
+; =============================================================================
+; Interleaved: one pair per non-add opcode -- confirms every supported opcode
+; reaches and fires the combine. Each pair is combined with a different op so it
+; is not reassociated into a single reduction first; the unpck is shared across
+; opcodes because they read the same inputs.
+; =============================================================================
+
+define i32 @nonadd_opcodes_i32_512(<16 x i32> %a, <16 x i32> %b) {
+; UNPCK-LABEL: nonadd_opcodes_i32_512:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm2 = zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[14],zmm0[14],zmm1[15],zmm0[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[12],zmm0[12],zmm1[13],zmm0[13]
+; UNPCK-NEXT: vpandd %zmm2, %zmm0, %zmm1
+; UNPCK-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; UNPCK-NEXT: vpand %ymm3, %ymm1, %ymm1
+; UNPCK-NEXT: vextracti128 $1, %ymm1, %xmm3
+; UNPCK-NEXT: vpand %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; UNPCK-NEXT: vpand %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vmovd %xmm1, %eax
+; UNPCK-NEXT: vpextrd $1, %xmm1, %edx
+; UNPCK-NEXT: imull %eax, %edx
+; UNPCK-NEXT: vpord %zmm2, %zmm0, %zmm1
+; UNPCK-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; UNPCK-NEXT: vpor %ymm3, %ymm1, %ymm1
+; UNPCK-NEXT: vextracti128 $1, %ymm1, %xmm3
+; UNPCK-NEXT: vpor %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; UNPCK-NEXT: vpor %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vmovd %xmm1, %eax
+; UNPCK-NEXT: vpextrd $1, %xmm1, %ecx
+; UNPCK-NEXT: imull %eax, %ecx
+; UNPCK-NEXT: addl %edx, %ecx
+; UNPCK-NEXT: vpxord %zmm2, %zmm0, %zmm1
+; UNPCK-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; UNPCK-NEXT: vpxor %ymm3, %ymm1, %ymm1
+; UNPCK-NEXT: vextracti128 $1, %ymm1, %xmm3
+; UNPCK-NEXT: vpxor %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; UNPCK-NEXT: vpxor %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vmovd %xmm1, %eax
+; UNPCK-NEXT: vpextrd $1, %xmm1, %edx
+; UNPCK-NEXT: imull %eax, %edx
+; UNPCK-NEXT: vpmulld %zmm2, %zmm0, %zmm1
+; UNPCK-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; UNPCK-NEXT: vpmulld %ymm3, %ymm1, %ymm1
+; UNPCK-NEXT: vextracti128 $1, %ymm1, %xmm3
+; UNPCK-NEXT: vpmulld %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; UNPCK-NEXT: vpmulld %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vmovd %xmm1, %esi
+; UNPCK-NEXT: vpextrd $1, %xmm1, %eax
+; UNPCK-NEXT: addl %esi, %eax
+; UNPCK-NEXT: addl %edx, %eax
+; UNPCK-NEXT: addl %ecx, %eax
+; UNPCK-NEXT: vpmaxsd %zmm2, %zmm0, %zmm1
+; UNPCK-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; UNPCK-NEXT: vpmaxsd %ymm3, %ymm1, %ymm1
+; UNPCK-NEXT: vextracti128 $1, %ymm1, %xmm3
+; UNPCK-NEXT: vpmaxsd %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; UNPCK-NEXT: vpmaxsd %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vmovd %xmm1, %ecx
+; UNPCK-NEXT: vpextrd $1, %xmm1, %edx
+; UNPCK-NEXT: imull %ecx, %edx
+; UNPCK-NEXT: vpminsd %zmm2, %zmm0, %zmm1
+; UNPCK-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; UNPCK-NEXT: vpminsd %ymm3, %ymm1, %ymm1
+; UNPCK-NEXT: vextracti128 $1, %ymm1, %xmm3
+; UNPCK-NEXT: vpminsd %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; UNPCK-NEXT: vpminsd %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vmovd %xmm1, %ecx
+; UNPCK-NEXT: vpextrd $1, %xmm1, %esi
+; UNPCK-NEXT: imull %ecx, %esi
+; UNPCK-NEXT: addl %edx, %esi
+; UNPCK-NEXT: vpmaxud %zmm2, %zmm0, %zmm1
+; UNPCK-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; UNPCK-NEXT: vpmaxud %ymm3, %ymm1, %ymm1
+; UNPCK-NEXT: vextracti128 $1, %ymm1, %xmm3
+; UNPCK-NEXT: vpmaxud %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; UNPCK-NEXT: vpmaxud %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vmovd %xmm1, %ecx
+; UNPCK-NEXT: vpextrd $1, %xmm1, %edx
+; UNPCK-NEXT: imull %ecx, %edx
+; UNPCK-NEXT: addl %esi, %edx
+; UNPCK-NEXT: addl %eax, %edx
+; UNPCK-NEXT: vpminud %zmm2, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpminud %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpminud %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpminud %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %ecx
+; UNPCK-NEXT: vpextrd $1, %xmm0, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: addl %edx, %eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: nonadd_opcodes_i32_512:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm2
+; BASE-NEXT: vpand %ymm2, %ymm0, %ymm3
+; BASE-NEXT: vextracti128 $1, %ymm3, %xmm4
+; BASE-NEXT: vpand %xmm4, %xmm3, %xmm3
+; BASE-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]
+; BASE-NEXT: vpand %xmm4, %xmm3, %xmm3
+; BASE-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[1,1,1,1]
+; BASE-NEXT: vpand %xmm4, %xmm3, %xmm3
+; BASE-NEXT: vmovd %xmm3, %eax
+; BASE-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; BASE-NEXT: vpand %ymm3, %ymm1, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpand %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpand %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpand %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %edx
+; BASE-NEXT: imull %eax, %edx
+; BASE-NEXT: vpor %ymm2, %ymm0, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %eax
+; BASE-NEXT: vpor %ymm3, %ymm1, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %ecx
+; BASE-NEXT: imull %eax, %ecx
+; BASE-NEXT: addl %edx, %ecx
+; BASE-NEXT: vpxor %ymm2, %ymm0, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpxor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpxor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpxor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %eax
+; BASE-NEXT: vpxor %ymm3, %ymm1, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpxor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpxor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpxor %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %edx
+; BASE-NEXT: imull %eax, %edx
+; BASE-NEXT: vpmulld %ymm2, %ymm0, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpmulld %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpmulld %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpmulld %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %esi
+; BASE-NEXT: vpmulld %ymm3, %ymm1, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpmulld %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpmulld %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpmulld %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %eax
+; BASE-NEXT: addl %esi, %eax
+; BASE-NEXT: addl %edx, %eax
+; BASE-NEXT: addl %ecx, %eax
+; BASE-NEXT: vpmaxsd %ymm2, %ymm0, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpmaxsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpmaxsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpmaxsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %ecx
+; BASE-NEXT: vpmaxsd %ymm3, %ymm1, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpmaxsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpmaxsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpmaxsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %edx
+; BASE-NEXT: imull %ecx, %edx
+; BASE-NEXT: vpminsd %ymm2, %ymm0, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpminsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpminsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpminsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %ecx
+; BASE-NEXT: vpminsd %ymm3, %ymm1, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpminsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpminsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpminsd %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %esi
+; BASE-NEXT: imull %ecx, %esi
+; BASE-NEXT: addl %edx, %esi
+; BASE-NEXT: vpmaxud %ymm2, %ymm0, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpmaxud %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpmaxud %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpmaxud %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %ecx
+; BASE-NEXT: vpmaxud %ymm3, %ymm1, %ymm4
+; BASE-NEXT: vextracti128 $1, %ymm4, %xmm5
+; BASE-NEXT: vpmaxud %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; BASE-NEXT: vpmaxud %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[1,1,1,1]
+; BASE-NEXT: vpmaxud %xmm5, %xmm4, %xmm4
+; BASE-NEXT: vmovd %xmm4, %edx
+; BASE-NEXT: imull %ecx, %edx
+; BASE-NEXT: addl %esi, %edx
+; BASE-NEXT: addl %eax, %edx
+; BASE-NEXT: vpminud %ymm2, %ymm0, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm2
+; BASE-NEXT: vpminud %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; BASE-NEXT: vpminud %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,1,1]
+; BASE-NEXT: vpminud %xmm2, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: vpminud %ymm3, %ymm1, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpminud %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpminud %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; BASE-NEXT: vpminud %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: imull %ecx, %eax
+; BASE-NEXT: addl %edx, %eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %and_a = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a)
+ %and_b = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %b)
+ %or_a = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %a)
+ %or_b = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %b)
+ %xor_a = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %a)
+ %xor_b = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %b)
+ %mul_a = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %a)
+ %mul_b = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %b)
+ %smax_a = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %a)
+ %smax_b = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %b)
+ %smin_a = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %a)
+ %smin_b = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %b)
+ %umax_a = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %a)
+ %umax_b = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %b)
+ %umin_a = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %a)
+ %umin_b = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %b)
+ %p_and = mul i32 %and_a, %and_b
+ %p_or = mul i32 %or_a, %or_b
+ %p_xor = mul i32 %xor_a, %xor_b
+ %p_mul = add i32 %mul_a, %mul_b
+ %p_smax = mul i32 %smax_a, %smax_b
+ %p_smin = mul i32 %smin_a, %smin_b
+ %p_umax = mul i32 %umax_a, %umax_b
+ %p_umin = mul i32 %umin_a, %umin_b
+ %s1 = add i32 %p_and, %p_or
+ %s2 = add i32 %s1, %p_xor
+ %s3 = add i32 %s2, %p_mul
+ %s4 = add i32 %s3, %p_smax
+ %s5 = add i32 %s4, %p_smin
+ %s6 = add i32 %s5, %p_umax
+ %r = add i32 %s6, %p_umin
+ ret i32 %r
+}
+
+; =============================================================================
+; Interleaved: multiple groups.
+; =============================================================================
+
+; N > Cap: i64/512 has Cap=2, so N=4 is emitted as two fused chunks {2, 2}.
+define i64 @add_i64_512_n4(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i64> %d) {
+; UNPCK-LABEL: add_i64_512_n4:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhqdq {{.*#+}} zmm4 = zmm1[1],zmm2[1],zmm1[3],zmm2[3],zmm1[5],zmm2[5],zmm1[7],zmm2[7]
+; UNPCK-NEXT: vpunpcklqdq {{.*#+}} zmm1 = zmm1[0],zmm2[0],zmm1[2],zmm2[2],zmm1[4],zmm2[4],zmm1[6],zmm2[6]
+; UNPCK-NEXT: vpaddq %zmm4, %zmm1, %zmm1
+; UNPCK-NEXT: vextracti64x4 $1, %zmm1, %ymm2
+; UNPCK-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; UNPCK-NEXT: vextracti128 $1, %ymm1, %xmm2
+; UNPCK-NEXT: vpaddq %xmm2, %xmm1, %xmm1
+; UNPCK-NEXT: vpextrq $1, %xmm1, %rax
+; UNPCK-NEXT: vmovq %xmm1, %rcx
+; UNPCK-NEXT: vpunpckhqdq {{.*#+}} zmm1 = zmm3[1],zmm0[1],zmm3[3],zmm0[3],zmm3[5],zmm0[5],zmm3[7],zmm0[7]
+; UNPCK-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm3[0],zmm0[0],zmm3[2],zmm0[2],zmm3[4],zmm0[4],zmm3[6],zmm0[6]
+; UNPCK-NEXT: vpaddq %zmm1, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovq %xmm0, %rdx
+; UNPCK-NEXT: imulq %rax, %rdx
+; UNPCK-NEXT: vpextrq $1, %xmm0, %rax
+; UNPCK-NEXT: imulq %rcx, %rax
+; UNPCK-NEXT: imulq %rdx, %rax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i64_512_n4:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm4
+; BASE-NEXT: vpaddq %ymm4, %ymm0, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm4
+; BASE-NEXT: vpaddq %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpextrq $1, %xmm0, %rax
+; BASE-NEXT: vmovq %xmm0, %rcx
+; BASE-NEXT: addq %rax, %rcx
+; BASE-NEXT: vextracti64x4 $1, %zmm1, %ymm0
+; BASE-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrq $1, %xmm0, %rax
+; BASE-NEXT: vmovq %xmm0, %rdx
+; BASE-NEXT: addq %rax, %rdx
+; BASE-NEXT: imulq %rcx, %rdx
+; BASE-NEXT: vextracti64x4 $1, %zmm2, %ymm0
+; BASE-NEXT: vpaddq %ymm0, %ymm2, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrq $1, %xmm0, %rax
+; BASE-NEXT: vmovq %xmm0, %rcx
+; BASE-NEXT: addq %rax, %rcx
+; BASE-NEXT: vextracti64x4 $1, %zmm3, %ymm0
+; BASE-NEXT: vpaddq %ymm0, %ymm3, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddq %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrq $1, %xmm0, %rsi
+; BASE-NEXT: vmovq %xmm0, %rax
+; BASE-NEXT: addq %rsi, %rax
+; BASE-NEXT: imulq %rcx, %rax
+; BASE-NEXT: imulq %rdx, %rax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %a)
+ %rb = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %b)
+ %rc = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %c)
+ %rd = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %d)
+ %m0 = mul i64 %ra, %rb
+ %m1 = mul i64 %m0, %rc
+ %r = mul i64 %m1, %rd
+ ret i64 %r
+}
+
+; Non-power-of-2 group: chunked into {2, 1}.
+define i32 @add_i32_512_n3(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c) {
+; UNPCK-LABEL: add_i32_512_n3:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vextracti64x4 $1, %zmm1, %ymm3
+; UNPCK-NEXT: vpaddd %ymm3, %ymm1, %ymm1
+; UNPCK-NEXT: vextracti128 $1, %ymm1, %xmm3
+; UNPCK-NEXT: vpaddd %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[2,3,2,3]
+; UNPCK-NEXT: vpaddd %xmm3, %xmm1, %xmm1
+; UNPCK-NEXT: vpextrd $1, %xmm1, %eax
+; UNPCK-NEXT: vmovd %xmm1, %ecx
+; UNPCK-NEXT: addl %eax, %ecx
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm1 = zmm2[2],zmm0[2],zmm2[3],zmm0[3],zmm2[6],zmm0[6],zmm2[7],zmm0[7],zmm2[10],zmm0[10],zmm2[11],zmm0[11],zmm2[14],zmm0[14],zmm2[15],zmm0[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm2[0],zmm0[0],zmm2[1],zmm0[1],zmm2[4],zmm0[4],zmm2[5],zmm0[5],zmm2[8],zmm0[8],zmm2[9],zmm0[9],zmm2[12],zmm0[12],zmm2[13],zmm0[13]
+; UNPCK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %edx
+; UNPCK-NEXT: vpextrd $1, %xmm0, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: imull %edx, %eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i32_512_n3:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm3
+; BASE-NEXT: vpaddd %ymm3, %ymm0, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm3
+; BASE-NEXT: vpaddd %xmm3, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm3, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: addl %eax, %ecx
+; BASE-NEXT: vextracti64x4 $1, %zmm1, %ymm0
+; BASE-NEXT: vpaddd %ymm0, %ymm1, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %edx
+; BASE-NEXT: addl %eax, %edx
+; BASE-NEXT: imull %ecx, %edx
+; BASE-NEXT: vextracti64x4 $1, %zmm2, %ymm0
+; BASE-NEXT: vpaddd %ymm0, %ymm2, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %ecx
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: addl %ecx, %eax
+; BASE-NEXT: imull %edx, %eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
+ %rb = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %b)
+ %rc = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %c)
+ %m0 = mul i32 %ra, %rb
+ %r = mul i32 %m0, %rc
+ ret i32 %r
+}
+
+; Same opcode, different input width: the v16i32 and v8i32 adds form separate
+; groups (each fused on its own), never one mixed group.
+define i32 @add_i32_mixed_width(<16 x i32> %a, <16 x i32> %b, <8 x i32> %c, <8 x i32> %d) {
+; UNPCK-LABEL: add_i32_mixed_width:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm4 = zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[14],zmm0[14],zmm1[15],zmm0[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[12],zmm0[12],zmm1[13],zmm0[13]
+; UNPCK-NEXT: vpaddd %zmm4, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %eax
+; UNPCK-NEXT: vpextrd $1, %xmm0, %ecx
+; UNPCK-NEXT: imull %eax, %ecx
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} ymm0 = ymm3[2],ymm2[2],ymm3[3],ymm2[3],ymm3[6],ymm2[6],ymm3[7],ymm2[7]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} ymm1 = ymm3[0],ymm2[0],ymm3[1],ymm2[1],ymm3[4],ymm2[4],ymm3[5],ymm2[5]
+; UNPCK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %edx
+; UNPCK-NEXT: vpextrd $1, %xmm0, %eax
+; UNPCK-NEXT: imull %edx, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_i32_mixed_width:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm4
+; BASE-NEXT: vpaddd %ymm4, %ymm0, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm4
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: addl %eax, %ecx
+; BASE-NEXT: vextracti64x4 $1, %zmm1, %ymm0
+; BASE-NEXT: vpaddd %ymm0, %ymm1, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %edx
+; BASE-NEXT: addl %eax, %edx
+; BASE-NEXT: imull %ecx, %edx
+; BASE-NEXT: vextracti128 $1, %ymm2, %xmm0
+; BASE-NEXT: vpaddd %xmm0, %xmm2, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: addl %eax, %ecx
+; BASE-NEXT: vextracti128 $1, %ymm3, %xmm0
+; BASE-NEXT: vpaddd %xmm0, %xmm3, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %esi
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: addl %esi, %eax
+; BASE-NEXT: imull %ecx, %eax
+; BASE-NEXT: imull %edx, %eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
+ %rb = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %b)
+ %rc = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %c)
+ %rd = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %d)
+ %m0 = mul i32 %ra, %rb
+ %m1 = mul i32 %rc, %rd
+ %r = mul i32 %m0, %m1
+ ret i32 %r
+}
+
+; Different opcodes: the add pair and the and pair form separate groups, each
+; interleaved on its own. The add pair is combined with mul (not add) so it is
+; not reassociated into a single add-reduction before interleaving.
+define i32 @add_and_mixed_opcode(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i32> %d) {
+; UNPCK-LABEL: add_and_mixed_opcode:
+; UNPCK: # %bb.0:
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm4 = zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[14],zmm0[14],zmm1[15],zmm0[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm0 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[12],zmm0[12],zmm1[13],zmm0[13]
+; UNPCK-NEXT: vpaddd %zmm4, %zmm0, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %eax
+; UNPCK-NEXT: vpextrd $1, %xmm0, %ecx
+; UNPCK-NEXT: imull %eax, %ecx
+; UNPCK-NEXT: vpunpckhdq {{.*#+}} zmm0 = zmm3[2],zmm2[2],zmm3[3],zmm2[3],zmm3[6],zmm2[6],zmm3[7],zmm2[7],zmm3[10],zmm2[10],zmm3[11],zmm2[11],zmm3[14],zmm2[14],zmm3[15],zmm2[15]
+; UNPCK-NEXT: vpunpckldq {{.*#+}} zmm1 = zmm3[0],zmm2[0],zmm3[1],zmm2[1],zmm3[4],zmm2[4],zmm3[5],zmm2[5],zmm3[8],zmm2[8],zmm3[9],zmm2[9],zmm3[12],zmm2[12],zmm3[13],zmm2[13]
+; UNPCK-NEXT: vpandd %zmm0, %zmm1, %zmm0
+; UNPCK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; UNPCK-NEXT: vpand %ymm1, %ymm0, %ymm0
+; UNPCK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; UNPCK-NEXT: vpand %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; UNPCK-NEXT: vpand %xmm1, %xmm0, %xmm0
+; UNPCK-NEXT: vmovd %xmm0, %edx
+; UNPCK-NEXT: vpextrd $1, %xmm0, %eax
+; UNPCK-NEXT: addl %edx, %eax
+; UNPCK-NEXT: imull %ecx, %eax
+; UNPCK-NEXT: vzeroupper
+; UNPCK-NEXT: retq
+;
+; BASE-LABEL: add_and_mixed_opcode:
+; BASE: # %bb.0:
+; BASE-NEXT: vextracti64x4 $1, %zmm0, %ymm4
+; BASE-NEXT: vpaddd %ymm4, %ymm0, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm4
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm4, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: addl %eax, %ecx
+; BASE-NEXT: vextracti64x4 $1, %zmm1, %ymm0
+; BASE-NEXT: vpaddd %ymm0, %ymm1, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpextrd $1, %xmm0, %eax
+; BASE-NEXT: vmovd %xmm0, %edx
+; BASE-NEXT: addl %eax, %edx
+; BASE-NEXT: imull %ecx, %edx
+; BASE-NEXT: vextracti64x4 $1, %zmm2, %ymm0
+; BASE-NEXT: vpand %ymm0, %ymm2, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpand %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpand %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; BASE-NEXT: vpand %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %ecx
+; BASE-NEXT: vextracti64x4 $1, %zmm3, %ymm0
+; BASE-NEXT: vpand %ymm0, %ymm3, %ymm0
+; BASE-NEXT: vextracti128 $1, %ymm0, %xmm1
+; BASE-NEXT: vpand %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; BASE-NEXT: vpand %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; BASE-NEXT: vpand %xmm1, %xmm0, %xmm0
+; BASE-NEXT: vmovd %xmm0, %eax
+; BASE-NEXT: addl %ecx, %eax
+; BASE-NEXT: imull %edx, %eax
+; BASE-NEXT: vzeroupper
+; BASE-NEXT: retq
+ %ra = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
+ %rb = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %b)
+ %rc = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %c)
+ %rd = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %d)
+ %m0 = mul i32 %ra, %rb
+ %m1 = add i32 %rc, %rd
+ %r = mul i32 %m0, %m1
+ ret i32 %r
+}
+
+; =============================================================================
+; Not interleaved.
+; =============================================================================
+
+; i8 add: skipped by the ADD/PSADBW guard, so it lowers to PSADBW instead of
+; being interleaved.
+define i8 @add_i8_256_n2(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: add_i8_256_n2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm2
+; CHECK-NEXT: vpaddb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
+; CHECK-NEXT: vpaddb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,1,1]
+; CHECK-NEXT: vpaddb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm2
+; CHECK-NEXT: vpaddb %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vpextrb $1, %xmm0, %ecx
+; CHECK-NEXT: vmovd %xmm0, %eax
+; CHECK-NEXT: addb %cl, %al
+; CHECK-NEXT: vextracti128 $1, %ymm1, %xmm0
+; CHECK-NEXT: vpaddb %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; CHECK-NEXT: vpaddb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; CHECK-NEXT: vpaddb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpsrld $16, %xmm0, %xmm1
+; CHECK-NEXT: vpaddb %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpextrb $1, %xmm0, %ecx
+; CHECK-NEXT: vmovd %xmm0, %edx
+; CHECK-NEXT: addb %cl, %dl
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: mulb %dl
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %ra = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %a)
+ %rb = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %b)
+ %r = mul i8 %ra, %rb
+ ret i8 %r
+}
+
+; Single reduction: needs >= 2 siblings.
+define i32 @single_i32_512(<16 x i32> %a) {
+; CHECK-LABEL: single_i32_512:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpextrd $1, %xmm0, %ecx
+; CHECK-NEXT: vmovd %xmm0, %eax
+; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %r = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
+ ret i32 %r
+}
+
+; 128-bit input: no cross-lane extract to share.
+define i32 @add_i32_128_n2(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: add_i32_128_n2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vpextrd $1, %xmm0, %eax
+; CHECK-NEXT: vmovd %xmm0, %ecx
+; CHECK-NEXT: addl %eax, %ecx
+; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
+; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vpextrd $1, %xmm0, %edx
+; CHECK-NEXT: vmovd %xmm0, %eax
+; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: imull %ecx, %eax
+; CHECK-NEXT: retq
+ %ra = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)
+ %rb = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %b)
+ %r = mul i32 %ra, %rb
+ ret i32 %r
+}
+
+; Loaded inputs: the load in each reduction's chain is rejected as a false
+; dependency (unpredictable latency), so the pair is not interleaved.
+define i32 @add_i32_512_loads(ptr %pa, ptr %pb) {
+; CHECK-LABEL: add_i32_512_loads:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovdqa (%rdi), %ymm0
+; CHECK-NEXT: vpaddd 32(%rdi), %ymm0, %ymm0
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpextrd $1, %xmm0, %eax
+; CHECK-NEXT: vmovd %xmm0, %ecx
+; CHECK-NEXT: addl %eax, %ecx
+; CHECK-NEXT: vmovdqa (%rsi), %ymm0
+; CHECK-NEXT: vpaddd 32(%rsi), %ymm0, %ymm0
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpextrd $1, %xmm0, %edx
+; CHECK-NEXT: vmovd %xmm0, %eax
+; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: imull %ecx, %eax
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %a = load <16 x i32>, ptr %pa
+ %b = load <16 x i32>, ptr %pb
+ %ra = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
+ %rb = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %b)
+ %r = mul i32 %ra, %rb
+ ret i32 %r
+}
+
+; Dependent inputs: %rb's input is built from %ra (a sibling add-reduction), so
+; the same-opcode reduction in its chain marks it non-independent. Interleaving
+; would create a false cross-lane dependency, so the pair is not fused.
+define i32 @add_i32_512_dependent(<16 x i32> %a, <16 x i32> %b) {
+; CHECK-LABEL: add_i32_512_dependent:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2
+; CHECK-NEXT: vpaddd %ymm2, %ymm0, %ymm0
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm2
+; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
+; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
+; CHECK-NEXT: vpextrd $1, %xmm0, %eax
+; CHECK-NEXT: vmovd %xmm0, %ecx
+; CHECK-NEXT: addl %eax, %ecx
+; CHECK-NEXT: vpbroadcastd %ecx, %zmm0
+; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
+; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
+; CHECK-NEXT: vpaddd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
+; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpextrd $1, %xmm0, %edx
+; CHECK-NEXT: vmovd %xmm0, %eax
+; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: imull %ecx, %eax
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %ra = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
+ %ins = insertelement <16 x i32> poison, i32 %ra, i64 0
+ %splat = shufflevector <16 x i32> %ins, <16 x i32> poison, <16 x i32> zeroinitializer
+ %b2 = add <16 x i32> %b, %splat
+ %rb = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %b2)
+ %r = mul i32 %ra, %rb
+ ret i32 %r
+}
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