[llvm] [Docs][AMDGPU] availability/visibility in addrspace(3) (PR #212707)

[Sameer Sahasrabuddhe via llvm-commits]

================
@@ -126,47 +126,80 @@ these necessary conditions, and hence they can be explained using the rules from
 either memory model. But the new intrinsics and metadata *opt out* of the LLVM
 memory model, and can only be explained using the AMDGPU memory model.
 
+### Store-Available and Load-Visible
+
 (amdgpu-store-available)=
 
-### store-available
+#### store-available
 
 ```llvm
- at llvm.amdgcn.av.global.store.b128(ptr, value, scope)
-store atomic [syncscope("<target-scope>")]
-atomicrmw    [syncscope("<target-scope>")]
-cmpxchg      [syncscope("<target-scope>")]
+ at llvm.amdgcn.av.global.store.b128(
+    ptr addrspace(1) %addr,
+    <4 x i32> %value,
+    metadata !scope)
 ```
 
 The `@llvm.amdgcn.av.global.store.b128` intrinsic performs a non-atomic
-*store-available* operation on `ptr` with scope `scope`.
+*store-available* operation on `%addr` with scope `!scope`.
+
+```llvm
+store atomic ..., [syncscope("<target-scope>")]
+atomicrmw    ..., [syncscope("<target-scope>")]
+cmpxchg      ..., [syncscope("<target-scope>")]
+```
 
 An atomic operation that results in a store operation is a *store-available*
 operation with scope `syncscope`.
 
+```llvm
+store ..., ptr addrspace(N) %addr
+```
+
+A `store` operation to `addrspace(3)` is always performed as a *store-available*
+operation with "workgroup" scope.
----------------
ssahasra wrote:

> The scope instance of a store-available operation is different from the scope instance of a store atomic operation although they are performed by the same instruction.

I created a new heading for addrspace(3), and added an explanatory note about the two kinds of scopes.

https://github.com/llvm/llvm-project/pull/212707