[llvm] [RISCV] Split and rename WriteVSlideI/WriteVISlide1X/WriteVFSlide1F (PR #212184)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 29 23:01:54 PDT 2026
https://github.com/LiqinWeng updated https://github.com/llvm/llvm-project/pull/212184
>From e0e80bc6ad6bb3fafdee1bc87a57c6f1fb0f9dd2 Mon Sep 17 00:00:00 2001
From: wengliqin <liqin.weng at spacemit.com>
Date: Thu, 23 Jul 2026 10:47:39 +0800
Subject: [PATCH] [RISCV] Split and rename
WriteVSlideI/WriteVISlide1X/WriteVFSlide1F
Split each of these SchedWrites into separate slide-up and slide-down
variants:
- WriteVSlideI -> WriteVSlideUpI, WriteVSlideDownI
- WriteVISlide1X -> WriteVISlide1Up, WriteVISlide1Down
- WriteVFSlide1F -> WriteVFSlide1Up, WriteVFSlide1Down
SpacemiT X100 and A100 have different latencies and/or
throughput for slide up vs. slide down operations, so they need
separate SchedWrites to model that difference.
---
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 23 ++++++++++---------
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 21 +++++++++--------
llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td | 4 ++--
llvm/lib/Target/RISCV/RISCVSchedAndes45.td | 9 +++++---
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 9 +++++---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 9 +++++---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 12 ++++++----
llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td | 9 +++++---
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 9 +++++---
llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td | 9 +++++---
llvm/lib/Target/RISCV/RISCVScheduleV.td | 18 ++++++++++-----
11 files changed, 82 insertions(+), 50 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index a60d11c8172b8..63bc4eecfbe37 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1052,23 +1052,24 @@ multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
}
multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6, bit slidesUp> {
- // Note: In the future, if VISlideI is also split into VSlideUpI and
- // VSlideDownI, it'll probably better to use two separate multiclasses.
defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");
+ defvar WriteSlideI = !if(slidesUp, "WriteVSlideUpI", "WriteVSlideDownI");
def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
SchedBinaryMC<WriteSlideX, "ReadVISlideV", "ReadVISlideX">;
def I : VALUVI<funct6, opcodestr # ".vi", uimm5>,
- SchedUnaryMC<"WriteVSlideI", "ReadVISlideV">;
+ SchedUnaryMC<WriteSlideI, "ReadVISlideV">;
}
-multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6> {
+multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6, bit slidesUp> {
+ defvar WriteSlide1X = !if(slidesUp, "WriteVISlide1Up", "WriteVISlide1Down");
def X : VALUVX<funct6, OPMVX, opcodestr # ".vx">,
- SchedBinaryMC<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX">;
+ SchedBinaryMC<WriteSlide1X, "ReadVISlideV", "ReadVISlideX">;
}
-multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6> {
+multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6, bit slidesUp> {
+ defvar WriteSlide1F = !if(slidesUp, "WriteVFSlide1Up", "WriteVFSlide1Down");
def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
- SchedBinaryMC<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF">;
+ SchedBinaryMC<WriteSlide1F, "ReadVFSlideV", "ReadVFSlideF">;
}
multiclass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6> {
@@ -1765,21 +1766,21 @@ let Predicates = [HasVInstructions] in {
let Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp,
ElementsDependOn = EltDepsNone in {
defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, /*slidesUp=*/true>;
-defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>;
+defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110, /*slidesUp=*/true>;
} // Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp, ElementsDependOn = EltDepsNone
let ElementsDependOn = EltDepsNone, ReadsPastVL = 1 in
defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, /*slidesUp=*/false>;
let ElementsDependOn = EltDepsVL, ReadsPastVL = 1 in
-defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>;
+defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111, /*slidesUp=*/false>;
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF] in {
let Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp,
ElementsDependOn = EltDepsNone in {
-defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110>;
+defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110, /*slidesUp=*/true>;
} // Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp
let ElementsDependOn = EltDepsVL, ReadsPastVL = 1 in
-defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>;
+defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111, /*slidesUp=*/false>;
} // Predicates = [HasVInstructionsAnyF]
let Predicates = [HasVInstructions] in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index c2bd8b82b2272..86ea79581e7a6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2222,10 +2222,11 @@ multiclass VPseudoBinaryV_VX_RM<LMULInfo m, string Constraint = ""> {
defm "_VX" : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, GPR, m, Constraint>;
}
-multiclass VPseudoVSLD1_VX<string Constraint = ""> {
+multiclass VPseudoVSLD1_VX<bit slidesUp = false, string Constraint = ""> {
+ defvar WriteSlide1X = !if(slidesUp, "WriteVISlide1Up", "WriteVISlide1Down");
foreach m = MxList in {
defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>,
- SchedBinary<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX",
+ SchedBinary<WriteSlide1X, "ReadVISlideV", "ReadVISlideX",
m.MX, forcePassthruRead=true>;
}
}
@@ -2241,12 +2242,13 @@ multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, int sew> {
UsesVXRM=0>;
}
-multiclass VPseudoVSLD1_VF<string Constraint = ""> {
+multiclass VPseudoVSLD1_VF<bit slidesUp = false, string Constraint = ""> {
+ defvar WriteSlide1F = !if(slidesUp, "WriteVFSlide1Up", "WriteVFSlide1Down");
foreach f = FPList in {
foreach m = f.MxList in {
defm "_V" #f.FX
: VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>,
- SchedBinary<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF", m.MX,
+ SchedBinary<WriteSlide1F, "ReadVFSlideV", "ReadVFSlideF", m.MX,
forcePassthruRead=true>;
}
}
@@ -3317,13 +3319,14 @@ multiclass VPseudoVMAC_VV_VF_AAXA_RM {
multiclass VPseudoVSLD_VX_VI<bit slidesUp = false, string Constraint = ""> {
defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");
+ defvar WriteSlideI = !if(slidesUp, "WriteVSlideUpI", "WriteVSlideDownI");
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoVSLDV_VX<m, Constraint>,
SchedTernary<WriteSlideX, "ReadVISlideV", "ReadVISlideV",
"ReadVISlideX", mx>;
defm "" : VPseudoVSLDV_VI<m, Constraint>,
- SchedBinary<"WriteVSlideI", "ReadVISlideV", "ReadVISlideV", mx>;
+ SchedBinary<WriteSlideI, "ReadVISlideV", "ReadVISlideV", mx>;
}
}
@@ -6751,13 +6754,13 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
let Predicates = [HasVInstructions] in {
defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI</*slidesUp=*/true, "@earlyclobber $rd">;
defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI</*slidesUp=*/false>;
- defm PseudoVSLIDE1UP : VPseudoVSLD1_VX<"@earlyclobber $rd">;
- defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX;
+ defm PseudoVSLIDE1UP : VPseudoVSLD1_VX</*slidesUp=*/true, "@earlyclobber $rd">;
+ defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX</*slidesUp=*/false>;
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in {
- defm PseudoVFSLIDE1UP : VPseudoVSLD1_VF<"@earlyclobber $rd">;
- defm PseudoVFSLIDE1DOWN : VPseudoVSLD1_VF;
+ defm PseudoVFSLIDE1UP : VPseudoVSLD1_VF</*slidesUp=*/true, "@earlyclobber $rd">;
+ defm PseudoVFSLIDE1DOWN : VPseudoVSLD1_VF</*slidesUp=*/false>;
} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
index f6489c8a273fb..ccf4a85c80824 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
@@ -373,8 +373,8 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>;
}
-defm PseudoVFSLIDE1UP_ALT : VPseudoVSLD1_VF<"@earlyclobber $rd">;
-defm PseudoVFSLIDE1DOWN_ALT : VPseudoVSLD1_VF;
+defm PseudoVFSLIDE1UP_ALT : VPseudoVSLD1_VF</*slidesUp=*/true, "@earlyclobber $rd">;
+defm PseudoVFSLIDE1DOWN_ALT : VPseudoVSLD1_VF</*slidesUp=*/false>;
} // Predicates = [HasVInstructionsBF16], AltFmtType = IS_ALTFMT
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index 21663207cf792..867c1f2d24ad1 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -1133,10 +1133,13 @@ foreach mx = SchedMxList in {
defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [Andes45VPERMUT], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlide1X", [Andes45VPERMUT], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [Andes45VPERMUT], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSlideUpX", [Andes45VPERMUT], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSlideDownX", [Andes45VPERMUT], mx, IsWorstCase>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index c2dcdaa5cd828..d163a9e73fe26 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -1141,9 +1141,12 @@ multiclass SiFive7WriteResBase<int VLEN,
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm : LMULWriteResMX<"WriteVSlideUpX", [VCQ, VA1], mx, IsWorstCase>;
defm : LMULWriteResMX<"WriteVSlideDownX", [VCQ, VA1], mx, IsWorstCase>;
- defm : LMULWriteResMX<"WriteVSlideI", [VCQ, VA1], mx, IsWorstCase>;
- defm : LMULWriteResMX<"WriteVISlide1X", [VCQ, VA1], mx, IsWorstCase>;
- defm : LMULWriteResMX<"WriteVFSlide1F", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVSlideUpI", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVSlideDownI", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVISlide1Up", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVISlide1Down", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVFSlide1Up", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVFSlide1Down", [VCQ, VA1], mx, IsWorstCase>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 5b999c98fbc7c..1323e694dbe36 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -370,11 +370,14 @@ foreach mx = SchedMxList in {
defvar LMulLat = SiFive8VecGetLMulCycles<mx>.c;
defvar IsWorstCase = SiFive8VecIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
}
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP400VEXQ0], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SiFiveP400VEXQ0], mx, IsWorstCase>;
}
}
foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index db9b17f193a56..eef45b4a74fc8 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -981,12 +981,16 @@ foreach mx = SchedMxList in {
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
let ReleaseAtCycles = [LMulLat] in {
- let Latency = SiFiveP600VSlideI<mx>.c in
- defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ let Latency = SiFiveP600VSlideI<mx>.c in {
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ }
let Latency = SiFiveP600VSlide1<mx>.c in {
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP600VEXQ0], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SiFiveP600VEXQ0], mx, IsWorstCase>;
}
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
index b0e1c7056c34d..bda3bc8f1c3c9 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -698,11 +698,14 @@ foreach mx = SchedMxList in {
defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SiFiveP800VEXQ0], mx, IsWorstCase>;
}
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP800VEXQ0], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SiFiveP800VEXQ0], mx, IsWorstCase>;
}
}
foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
index 3d97bb0569291..95f8c1c487832 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -973,10 +973,13 @@ foreach mx = SchedMxList in {
// The following group slide up and down together, so we use the worst-case
// (slide down) for all.
let Latency = VSlideDownLat, ReleaseAtCycles =[VSlideDownOcc] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SMX60_VFP], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SMX60_VFP], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SMX60_VFP], mx, IsWorstCase>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td
index eecae36a2d83d..d6a1f341e3e33 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td
@@ -875,9 +875,12 @@ foreach mx = SchedMxList in {
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm "" : LMULWriteResMX<"WriteVSlideUpX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSlideDownX", [AscalonFX, AscalonV], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSlideI", [AscalonFX, AscalonV], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlide1X", [AscalonFX, AscalonV], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [AscalonFX, AscalonV], mx, IsWorstCase>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 601308b377c6f..77eec16987b87 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -558,9 +558,12 @@ def WriteVMovFS : SchedWrite;
// 16.3. Vector Slide Instructions
defm "" : LMULSchedWrites<"WriteVSlideUpX">;
defm "" : LMULSchedWrites<"WriteVSlideDownX">;
-defm "" : LMULSchedWrites<"WriteVSlideI">;
-defm "" : LMULSchedWrites<"WriteVISlide1X">;
-defm "" : LMULSchedWrites<"WriteVFSlide1F">;
+defm "" : LMULSchedWrites<"WriteVSlideUpI">;
+defm "" : LMULSchedWrites<"WriteVSlideDownI">;
+defm "" : LMULSchedWrites<"WriteVISlide1Up">;
+defm "" : LMULSchedWrites<"WriteVISlide1Down">;
+defm "" : LMULSchedWrites<"WriteVFSlide1Up">;
+defm "" : LMULSchedWrites<"WriteVFSlide1Down">;
// 16.4. Vector Register Gather Instructions
defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">;
defm "" : LMULSEWSchedWrites<"WriteVRGatherEI16VV">;
@@ -1000,9 +1003,12 @@ def : WriteRes<WriteVMovSF, []>;
def : WriteRes<WriteVMovFS, []>;
defm "" : LMULWriteRes<"WriteVSlideUpX", []>;
defm "" : LMULWriteRes<"WriteVSlideDownX", []>;
-defm "" : LMULWriteRes<"WriteVSlideI", []>;
-defm "" : LMULWriteRes<"WriteVISlide1X", []>;
-defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
+defm "" : LMULWriteRes<"WriteVSlideUpI", []>;
+defm "" : LMULWriteRes<"WriteVSlideDownI", []>;
+defm "" : LMULWriteRes<"WriteVISlide1Up", []>;
+defm "" : LMULWriteRes<"WriteVISlide1Down", []>;
+defm "" : LMULWriteRes<"WriteVFSlide1Up", []>;
+defm "" : LMULWriteRes<"WriteVFSlide1Down", []>;
defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;
defm "" : LMULSEWWriteRes<"WriteVRGatherEI16VV", []>;
defm "" : LMULWriteRes<"WriteVRGatherVX", []>;
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