[llvm] AMDGPU/GlobalISel: Switch more FP opcodes to extended LLTs (part 2) (PR #212909)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 29 18:31:05 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: vangthao95
<details>
<summary>Changes</summary>
Migrate G_FPOW, G_FPOWI, G_INTRINSIC_FPTRUNC_ROUND, and FP<->INT conversions opcodes to extended float LLTs.
Also update the relevant MIR tests.
---
Patch is 232.26 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/212909.diff
9 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+36-35)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir (+305-321)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir (+66-70)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir (+240-240)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir (+225-225)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir (+127-127)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir (+118-118)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi-sat.mir (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui-sat.mir (+7-7)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 20e0a82f5832c..920fad64b1977 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -294,7 +294,6 @@ static LegalityPredicate elementTypeIsLegal(unsigned TypeIdx) {
};
}
-const LLT I16 = LLT::integer(16);
constexpr LLT F16 = LLT::float16();
constexpr LLT BF16 = LLT::bfloat16();
constexpr LLT F32 = LLT::float32();
@@ -740,6 +739,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
V2S64};
const LLT MinScalarFPTy = ST.has16BitInsts() ? S16 : S32;
+ const LLT MinExtendedFPTy = ST.has16BitInsts() ? F16 : F32;
+ const LLT I1 = LLT::integer(1);
+ const LLT I16 = LLT::integer(16);
+ const LLT I32 = LLT::integer(32);
+ const LLT I64 = LLT::integer(64);
+ const LLT V2I16 = LLT::fixed_vector(2, I16);
getActionDefinitionsBuilder(G_BR).alwaysLegal();
@@ -1224,48 +1229,45 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
// TODO: Split s1->s64 during regbankselect for VALU.
auto &IToFP = getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
- .legalFor({{S32, S32}, {S64, S32}})
- .widenScalarFor({{S16, S32}}, changeElementSizeTo(0, S32))
- .lowerIf(typeIs(1, S1))
- .customFor({{S32, S64}, {S64, S64}});
+ .legalFor({{F32, I32}, {F64, I32}})
+ .widenScalarFor({{F16, I32}}, changeElementSizeTo(0, F32))
+ .lowerIf(typeIs(1, I1))
+ .customFor({{F32, I64}, {F64, I64}});
if (ST.has16BitInsts())
- IToFP.legalFor({{S16, S16}});
- IToFP.clampScalar(1, S32, S64)
- .minScalar(0, S32)
- .scalarize(0)
- .widenScalarToNextPow2(1);
+ IToFP.legalFor({{F16, I16}});
+ IToFP.clampScalar(1, I32, I64)
+ .minScalar(0, F32)
+ .scalarize(0)
+ .widenScalarToNextPow2(1);
auto &FPToI = getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
- .legalFor({{S32, S32}, {S32, S64}})
- .customFor({{S64, S32}, {S64, S64}})
- .widenScalarFor({{S32, S16}}, changeElementSizeTo(1, S32))
- .narrowScalarFor({{S64, S16}}, changeElementSizeTo(0, S32));
+ .legalFor({{I32, F32}, {I32, F64}})
+ .customFor({{I64, F32}, {I64, F64}})
+ .widenScalarFor({{I32, F16}}, changeElementSizeTo(1, F32))
+ .narrowScalarFor({{I64, F16}}, changeElementSizeTo(0, I32));
if (ST.has16BitInsts())
- FPToI.legalFor({{S16, S16}});
+ FPToI.legalFor({{I16, F16}});
else
- FPToI.minScalar(1, S32);
+ FPToI.minScalar(1, F32);
- FPToI.minScalar(0, S32)
- .widenScalarToNextPow2(0, 32)
- .scalarize(0)
- .lower();
+ FPToI.minScalar(0, I32).widenScalarToNextPow2(0, 32).scalarize(0).lower();
// clang-format off
auto &FPToISat = getActionDefinitionsBuilder({G_FPTOSI_SAT, G_FPTOUI_SAT})
- .legalFor({{S32, S32}, {S32, S64}, {S16, S32}})
- .legalFor(ST.has16BitInsts(), {{S16, S16}})
- .legalFor(ST.hasVCvtPkIU16F32(), {{V2S16, V2S32}})
- .narrowScalarFor({{S64, S16}}, changeElementSizeTo(0, S32));
+ .legalFor({{I32, F32}, {I32, F64}, {I16, F32}})
+ .legalFor(ST.has16BitInsts(), {{I16, F16}})
+ .legalFor(ST.hasVCvtPkIU16F32(), {{V2I16, V2F32}})
+ .narrowScalarFor({{I64, F16}}, changeElementSizeTo(0, I32));
// If available, widen width <16 to i16, intead of i32 so v_cvt_i16/u16_f16 can be used.
if (ST.has16BitInsts())
- FPToISat.minScalarIf(typeIs(1, S16), 0, S16);
+ FPToISat.minScalarIf(typeIs(1, F16), 0, I16);
if (ST.hasVCvtPkIU16F32())
- FPToISat.clampMaxNumElements(0, S16, 2);
+ FPToISat.clampMaxNumElements(0, I16, 2);
- FPToISat.minScalar(1, S32);
- FPToISat.minScalar(0, S32)
+ FPToISat.minScalar(1, F32);
+ FPToISat.minScalar(0, I32)
.widenScalarToNextPow2(0, 32)
.scalarize(0)
.lower();
@@ -1277,7 +1279,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.lower();
getActionDefinitionsBuilder(G_INTRINSIC_FPTRUNC_ROUND)
- .legalFor({S16, S32})
+ .legalFor({F16, F32})
.scalarize(0)
.lower();
@@ -1364,15 +1366,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
// FIXME: fpow has a selection pattern that should move to custom lowering.
auto &ExpOps = getActionDefinitionsBuilder(G_FPOW);
if (ST.has16BitInsts())
- ExpOps.customFor({{S32}, {S16}});
+ ExpOps.customFor({{F32}, {F16}});
else
- ExpOps.customFor({S32});
- ExpOps.clampScalar(0, MinScalarFPTy, S32)
- .scalarize(0);
+ ExpOps.customFor({F32});
+ ExpOps.clampScalar(0, MinExtendedFPTy, F32).scalarize(0);
getActionDefinitionsBuilder(G_FPOWI)
- .clampScalar(0, MinScalarFPTy, S32)
- .lower();
+ .clampScalar(0, MinExtendedFPTy, F32)
+ .lower();
getActionDefinitionsBuilder(G_FLOG2)
.legalFor(ST.has16BitInsts(), {S16})
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
index f9abf16bf55e1..e2021809ab3d8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
@@ -5,18 +5,18 @@
# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=GFX9 %s
---
-name: test_fpow_s32
+name: test_fpow_f32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; GFX6-LABEL: name: test_fpow_s32
+ ; GFX6-LABEL: name: test_fpow_f32
; GFX6: liveins: $vgpr0, $vgpr1
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
@@ -26,27 +26,25 @@ body: |
; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[COPY1]](s32)
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[COPY1]](f32)
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
- ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C7]]
+ ; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INT1]], [[SELECT2]]
- ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX6-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C8]], [[C9]]
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT3]]
- ; GFX6-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
+ ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX6-NEXT: $vgpr0 = COPY [[FMUL1]](f32)
;
- ; GFX9-LABEL: name: test_fpow_s32
+ ; GFX9-LABEL: name: test_fpow_f32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](s32), [[C]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[COPY]](f32), [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
@@ -56,40 +54,38 @@ body: |
; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[COPY1]](s32)
- ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[COPY1]](f32)
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
- ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C7]]
+ ; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INT1]], [[SELECT2]]
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX9-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX9-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C8]], [[C9]]
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT3]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FMUL1]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FPOW %0, %1
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FMUL1]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FPOW %0, %1
$vgpr0 = COPY %2
...
---
-name: test_fpow_v2s32
+name: test_fpow_v2f32
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
- ; GFX6-LABEL: name: test_fpow_v2s32
+ ; GFX6-LABEL: name: test_fpow_v2f32
; GFX6: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX6-NEXT: {{ $}}
- ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX6-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; GFX6-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX6-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX6-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX6-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; GFX6-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
+ ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
; GFX6-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX6-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
@@ -99,43 +95,41 @@ body: |
; GFX6-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
- ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[UV2]](s32)
- ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
+ ; GFX6-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[UV2]](f32)
+ ; GFX6-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX6-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
- ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C7]]
+ ; GFX6-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX6-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INT1]], [[SELECT2]]
- ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX6-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX6-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C8]], [[C9]]
- ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT3]]
- ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; GFX6-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX6-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX6-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX6-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](f32), [[C]]
; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C1]], [[C2]]
; GFX6-NEXT: [[FMUL2:%[0-9]+]]:_(f32) = G_FMUL [[UV1]], [[SELECT4]]
; GFX6-NEXT: [[INT3:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), [[FMUL2]](f32)
; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(f32) = G_SELECT [[FCMP2]](s1), [[C3]], [[C4]]
; GFX6-NEXT: [[FSUB1:%[0-9]+]]:_(f32) = G_FSUB [[INT3]], [[SELECT5]]
- ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](f32), [[UV3]](s32)
+ ; GFX6-NEXT: [[INT4:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB1]](f32), [[UV3]](f32)
; GFX6-NEXT: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT4]](f32), [[C5]]
- ; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C6]], [[C7]]
+ ; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C6]], [[C4]]
; GFX6-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[INT4]], [[SELECT6]]
- ; GFX6-NEXT: [[INT5:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
- ; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C8]], [[C9]]
- ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(s32) = G_FMUL [[INT5]], [[SELECT7]]
- ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL1]](s32), [[FMUL3]](s32)
- ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; GFX6-NEXT: [[INT5:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD1]](f32)
+ ; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(f32) = G_SELECT [[FCMP3]](s1), [[C7]], [[C2]]
+ ; GFX6-NEXT: [[FMUL3:%[0-9]+]]:_(f32) = G_FMUL [[INT5]], [[SELECT7]]
+ ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FMUL1]](f32), [[FMUL3]](f32)
+ ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; GFX9-LABEL: name: test_fpow_v2s32
+ ; GFX9-LABEL: name: test_fpow_v2f32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
; GFX9-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x00800000
- ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](s32), [[C]]
+ ; GFX9-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV]](f32), [[C]]
; GFX9-NEXT: [[C1:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x4F800000
; GFX9-NEXT: [[C2:%[0-9]+]]:_(f32) = G_FCONSTANT float 1.000000e+00
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
@@ -145,54 +139,52 @@ body: |
; GFX9-NEXT: [[C4:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(f32) = G_SELECT [[FCMP]](s1), [[C3]], [[C4]]
; GFX9-NEXT: [[FSUB:%[0-9]+]]:_(f32) = G_FSUB [[INT]], [[SELECT1]]
- ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[UV2]](s32)
- ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.260000e+02
+ ; GFX9-NEXT: [[INT1:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FSUB]](f32), [[UV2]](f32)
+ ; GFX9-NEXT: [[C5:%[0-9]+]]:_(f32) = G_FCONSTANT float -1.260000e+02
; GFX9-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[INT1]](f32), [[C5]]
- ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
- ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
- ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C7]]
+ ; GFX9-NEXT: [[C6:%[0-9]+]]:_(f32) = G_FCONSTANT float 6.400000e+01
+ ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C6]], [[C4]]
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[INT1]], [[SELECT2]]
- ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
- ; GFX9-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float f0x1F800000
- ; GFX9-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
- ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C8]], [[C9]]
- ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[INT2]], [[SELECT3]]
- ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[UV1]](s32), [[C]]
+ ; GFX9-NEXT: [[INT2:%[0-9]+]]:_(f32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), [[FADD]](f32)
+ ; GFX9-NEXT: [[C7:%[0-9]+]]:_(f32) = G_FCONSTANT float f0x1F800000
+ ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(f32) = G_SELECT [[FCMP1]](s1), [[C7]], [[C2]]
+ ; GFX9-NEXT: [[FMUL1:%[0-9]+]]:_(f32) = G_FMUL [[INT2]], [[SELECT3]]
+ ; GFX9-NEXT: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(o...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/212909
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