[llvm] 2faa90a - [AMDGPU] Retain subreg when legalising generic operand (#212636)

[via llvm-commits]

Author: Zach Goldthorpe
Date: 2026-07-29T13:50:14Z
New Revision: 2faa90a208a14b7e681dc9122a889c894823814a

URL: https://github.com/llvm/llvm-project/commit/2faa90a208a14b7e681dc9122a889c894823814a
DIFF: https://github.com/llvm/llvm-project/commit/2faa90a208a14b7e681dc9122a889c894823814a.diff

LOG: [AMDGPU] Retain subreg when legalising generic operand (#212636)

When building a `COPY` to legalise a generic operand whose register
class does not match what is expected, the subregister is not retained
in the copy, and is not dropped from the newly created virtual
destination register.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 0b07d970654bd..d3a5c1e1cf281 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7074,9 +7074,10 @@ void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,
     return;
 
   Register DstReg = MRI.createVirtualRegister(DstRC);
-  auto Copy =
-      BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).addReg(OpReg);
+  auto Copy = BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg)
+                  .addReg(OpReg, {}, OpSubReg);
   Op.setReg(DstReg);
+  Op.setSubReg(AMDGPU::NoSubRegister);
 
   MachineInstr *Def = MRI.getVRegDef(OpReg);
   if (!Def)

diff  --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
index 56b950a727e38..6c96be0860b43 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
@@ -221,6 +221,41 @@ body:             |
     %2:sreg_32 = S_XOR_B32 %1:sreg_32, %1:sreg_32, implicit-def $scc
 ...
 
+---
+name:            copy_lo16_sreg32_usedby_phi
+tracksRegLiveness: true
+body:             |
+  ; GCN-LABEL: name: copy_lo16_sreg32_usedby_phi
+  ; GCN: bb.0:
+  ; GCN-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; GCN-NEXT:   liveins: $scc
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+  ; GCN-NEXT:   S_CBRANCH_SCC1 %bb.2, implicit $scc
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.1:
+  ; GCN-NEXT:   successors: %bb.2(0x80000000)
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_16 = COPY [[DEF]].lo16
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.2:
+  ; GCN-NEXT:   [[PHI:%[0-9]+]]:vgpr_16 = PHI [[DEF1]], %bb.0, [[COPY]], %bb.1
+  ; GCN-NEXT:   S_ENDPGM 0, implicit [[PHI]]
+  bb.0:
+    liveins: $scc
+    %0:vgpr_32 = IMPLICIT_DEF
+    %1:vgpr_16 = IMPLICIT_DEF
+    S_CBRANCH_SCC1 %bb.2, implicit $scc
+
+  bb.1:
+    %2:sreg_32 = COPY %0.lo16
+
+  bb.2:
+    %3:vgpr_16 = PHI %1, %bb.0, %2, %bb.1
+    S_ENDPGM 0, implicit %3
+...
+
 ---
 name:            S_FMAC_F16
 body:             |