[llvm] [LLVM][CodeGen][SVE] Add isel patterns for add/sub where the second operand is promoted. (PR #212771)
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 29 06:36:57 PDT 2026
https://github.com/paulwalker-arm created https://github.com/llvm/llvm-project/pull/212771
None
>From fecf88ef8100f643c049d7dfd27dc85a5554fd91 Mon Sep 17 00:00:00 2001
From: Paul Walker <paul.walker at arm.com>
Date: Wed, 29 Jul 2026 11:33:12 +0100
Subject: [PATCH 1/2] add tests
---
.../AArch64/sve-partial-reduce-wide-add.ll | 38 +++++++++
llvm/test/CodeGen/AArch64/sve2-wide-ops.ll | 84 +++++++++++++++++++
2 files changed, 122 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/sve2-wide-ops.ll
diff --git a/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll b/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
index cf738b61a01ee..80e9e608d3695 100644
--- a/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
+++ b/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
@@ -42,6 +42,44 @@ entry:
ret <vscale x 2 x i64> %partial.reduce
}
+define <vscale x 4 x i32> @signed_wide_add_nxv4i32_nxv4i16(<vscale x 4 x i32> %acc, <vscale x 4 x i16> %input){
+; CHECK-SVE-LABEL: signed_wide_add_nxv4i32_nxv4i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: sxth z1.s, p0/m, z1.s
+; CHECK-SVE-NEXT: add z0.s, z0.s, z1.s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-SVE2-LABEL: signed_wide_add_nxv4i32_nxv4i16:
+; CHECK-SVE2: // %bb.0: // %entry
+; CHECK-SVE2-NEXT: ptrue p0.s
+; CHECK-SVE2-NEXT: sxth z1.s, p0/m, z1.s
+; CHECK-SVE2-NEXT: add z0.s, z0.s, z1.s
+; CHECK-SVE2-NEXT: ret
+entry:
+ %input.wide = sext <vscale x 4 x i16> %input to <vscale x 4 x i32>
+ %partial.reduce = tail call <vscale x 4 x i32> @llvm.vector.partial.reduce.add.nxv4i32.nxv8i32(<vscale x 4 x i32> %acc, <vscale x 4 x i32> %input.wide)
+ ret <vscale x 4 x i32> %partial.reduce
+}
+
+define <vscale x 4 x i32> @unsigned_wide_add_nxv4i32_nxv4i16(<vscale x 4 x i32> %acc, <vscale x 4 x i16> %input){
+; CHECK-SVE-LABEL: unsigned_wide_add_nxv4i32_nxv4i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: and z1.s, z1.s, #0xffff
+; CHECK-SVE-NEXT: add z0.s, z0.s, z1.s
+; CHECK-SVE-NEXT: ret
+;
+; CHECK-SVE2-LABEL: unsigned_wide_add_nxv4i32_nxv4i16:
+; CHECK-SVE2: // %bb.0: // %entry
+; CHECK-SVE2-NEXT: and z1.s, z1.s, #0xffff
+; CHECK-SVE2-NEXT: add z0.s, z0.s, z1.s
+; CHECK-SVE2-NEXT: ret
+entry:
+ %input.wide = zext <vscale x 4 x i16> %input to <vscale x 4 x i32>
+ %partial.reduce = tail call <vscale x 4 x i32> @llvm.vector.partial.reduce.add.nxv4i32.nxv8i32(<vscale x 4 x i32> %acc, <vscale x 4 x i32> %input.wide)
+ ret <vscale x 4 x i32> %partial.reduce
+}
+
define <vscale x 4 x i32> @signed_wide_add_nxv8i16(<vscale x 4 x i32> %acc, <vscale x 8 x i16> %input){
; CHECK-SVE-LABEL: signed_wide_add_nxv8i16:
; CHECK-SVE: // %bb.0: // %entry
diff --git a/llvm/test/CodeGen/AArch64/sve2-wide-ops.ll b/llvm/test/CodeGen/AArch64/sve2-wide-ops.ll
new file mode 100644
index 0000000000000..6e7cba3556a3d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve2-wide-ops.ll
@@ -0,0 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mattr=+sve2 < %s | FileCheck %s --check-prefixes=CHECK,SVE
+; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,SME
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define <vscale x 8 x i16> @add_nxv8i16_sext_nxv8i8(<vscale x 8 x i16> %a, <vscale x 8 x i8> %b) {
+; CHECK-LABEL: add_nxv8i16_sext_nxv8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: sxtb z1.h, p0/m, z1.h
+; CHECK-NEXT: add z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+ %b.ext = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>
+ %r = add <vscale x 8 x i16> %a, %b.ext
+ ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 4 x i32> @add_nxv4i32_sext_nxv4i16(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b) {
+; CHECK-LABEL: add_nxv4i32_sext_nxv4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sxth z1.s, p0/m, z1.s
+; CHECK-NEXT: add z0.s, z0.s, z1.s
+; CHECK-NEXT: ret
+ %b.ext = sext <vscale x 4 x i16> %b to <vscale x 4 x i32>
+ %r = add <vscale x 4 x i32> %a, %b.ext
+ ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 2 x i64> @add_nxv2i64_sext_nxv2i32(<vscale x 2 x i64> %a, <vscale x 2 x i32> %b) {
+; SVE-LABEL: add_nxv2i64_sext_nxv2i32:
+; SVE: // %bb.0:
+; SVE-NEXT: adr z0.d, [z0.d, z1.d, sxtw]
+; SVE-NEXT: ret
+;
+; SME-LABEL: add_nxv2i64_sext_nxv2i32:
+; SME: // %bb.0:
+; SME-NEXT: ptrue p0.d
+; SME-NEXT: sxtw z1.d, p0/m, z1.d
+; SME-NEXT: add z0.d, z0.d, z1.d
+; SME-NEXT: ret
+ %b.ext = sext <vscale x 2 x i32> %b to <vscale x 2 x i64>
+ %r = add <vscale x 2 x i64> %a, %b.ext
+ ret <vscale x 2 x i64> %r
+}
+
+define <vscale x 8 x i16> @add_nxv8i16_zext_nxv8i8(<vscale x 8 x i16> %a, <vscale x 8 x i8> %b) {
+; CHECK-LABEL: add_nxv8i16_zext_nxv8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and z1.h, z1.h, #0xff
+; CHECK-NEXT: add z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+ %b.ext = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>
+ %r = add <vscale x 8 x i16> %a, %b.ext
+ ret <vscale x 8 x i16> %r
+}
+
+define <vscale x 4 x i32> @add_nxv4i32_zext_nxv4i16(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b) {
+; CHECK-LABEL: add_nxv4i32_zext_nxv4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and z1.s, z1.s, #0xffff
+; CHECK-NEXT: add z0.s, z0.s, z1.s
+; CHECK-NEXT: ret
+ %b.ext = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>
+ %r = add <vscale x 4 x i32> %a, %b.ext
+ ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 2 x i64> @add_nxv2i64_zext_nxv2i32(<vscale x 2 x i64> %a, <vscale x 2 x i32> %b) {
+; SVE-LABEL: add_nxv2i64_zext_nxv2i32:
+; SVE: // %bb.0:
+; SVE-NEXT: adr z0.d, [z0.d, z1.d, uxtw]
+; SVE-NEXT: ret
+;
+; SME-LABEL: add_nxv2i64_zext_nxv2i32:
+; SME: // %bb.0:
+; SME-NEXT: and z1.d, z1.d, #0xffffffff
+; SME-NEXT: add z0.d, z0.d, z1.d
+; SME-NEXT: ret
+ %b.ext = zext <vscale x 2 x i32> %b to <vscale x 2 x i64>
+ %r = add <vscale x 2 x i64> %a, %b.ext
+ ret <vscale x 2 x i64> %r
+}
>From fb89386913d104deb76de998bfe354cba49e3d5b Mon Sep 17 00:00:00 2001
From: Paul Walker <paul.walker at arm.com>
Date: Wed, 29 Jul 2026 11:34:52 +0100
Subject: [PATCH 2/2] [LLVM][CodeGen][SVE] Add isel patterns for add/sub where
the second operand is promoted.
---
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 28 +++++++++++
llvm/test/CodeGen/AArch64/sve-hadd.ll | 48 ++++++++++++-------
.../AArch64/sve-partial-reduce-wide-add.ll | 7 +--
llvm/test/CodeGen/AArch64/sve2-wide-ops.ll | 21 +++-----
4 files changed, 68 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index d926c4023acb3..28ed7f35743a7 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -4136,6 +4136,34 @@ let Predicates = [HasSVE2_or_SME] in {
defm USUBWB_ZZZ : sve2_wide_int_arith_wide<0b110, "usubwb", int_aarch64_sve_usubwb>;
defm USUBWT_ZZZ : sve2_wide_int_arith_wide<0b111, "usubwt", int_aarch64_sve_usubwt>;
+ def : Pat<(add nxv8i16:$Acc, (sext_inreg nxv8i16:$Input, nxv8i8)),
+ (SADDWB_ZZZ_H $Acc, $Input)>;
+ def : Pat<(add nxv4i32:$Acc, (sext_inreg nxv4i32:$Input, nxv4i16)),
+ (SADDWB_ZZZ_S $Acc, $Input)>;
+ def : Pat<(add nxv2i64:$Acc, (sext_inreg nxv2i64:$Input, nxv2i32)),
+ (SADDWB_ZZZ_D $Acc, $Input)>;
+
+ def : Pat<(sub nxv8i16:$Acc, (sext_inreg nxv8i16:$Input, nxv8i8)),
+ (SSUBWB_ZZZ_H $Acc, $Input)>;
+ def : Pat<(sub nxv4i32:$Acc, (sext_inreg nxv4i32:$Input, nxv4i16)),
+ (SSUBWB_ZZZ_S $Acc, $Input)>;
+ def : Pat<(sub nxv2i64:$Acc, (sext_inreg nxv2i64:$Input, nxv2i32)),
+ (SSUBWB_ZZZ_D $Acc, $Input)>;
+
+ def : Pat<(add nxv8i16:$Acc, (and nxv8i16:$Input, (splat_vector (i32 0xFF)))),
+ (UADDWB_ZZZ_H $Acc, $Input)>;
+ def : Pat<(add nxv4i32:$Acc, (and nxv4i32:$Input, (splat_vector (i32 0xFFFF)))),
+ (UADDWB_ZZZ_S $Acc, $Input)>;
+ def : Pat<(add nxv2i64:$Acc, (and nxv2i64:$Input, (splat_vector (i64 0xFFFFFFFF)))),
+ (UADDWB_ZZZ_D $Acc, $Input)>;
+
+ def : Pat<(sub nxv8i16:$Acc, (and nxv8i16:$Input, (splat_vector (i32 0xFF)))),
+ (USUBWB_ZZZ_H $Acc, $Input)>;
+ def : Pat<(sub nxv4i32:$Acc, (and nxv4i32:$Input, (splat_vector (i32 0xFFFF)))),
+ (USUBWB_ZZZ_S $Acc, $Input)>;
+ def : Pat<(sub nxv2i64:$Acc, (and nxv2i64:$Input, (splat_vector (i64 0xFFFFFFFF)))),
+ (USUBWB_ZZZ_D $Acc, $Input)>;
+
def : Pat<(nxv2i64 (partial_reduce_umla nxv2i64:$Acc, nxv4i32:$Input, (nxv4i32 (splat_vector (i32 1))))),
(UADDWT_ZZZ_D (UADDWB_ZZZ_D $Acc, $Input), $Input)>;
def : Pat<(nxv2i64 (partial_reduce_smla nxv2i64:$Acc, nxv4i32:$Input, (nxv4i32 (splat_vector (i32 1))))),
diff --git a/llvm/test/CodeGen/AArch64/sve-hadd.ll b/llvm/test/CodeGen/AArch64/sve-hadd.ll
index 0bc810fa4f7e7..31681d57dd9da 100644
--- a/llvm/test/CodeGen/AArch64/sve-hadd.ll
+++ b/llvm/test/CodeGen/AArch64/sve-hadd.ll
@@ -303,14 +303,22 @@ entry:
}
define <vscale x 4 x i16> @hadds_v4i16_lsh(<vscale x 4 x i16> %s0, <vscale x 4 x i16> %s1) {
-; CHECK-LABEL: hadds_v4i16_lsh:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: sxth z0.s, p0/m, z0.s
-; CHECK-NEXT: sxth z1.s, p0/m, z1.s
-; CHECK-NEXT: add z0.s, z0.s, z1.s
-; CHECK-NEXT: lsr z0.s, z0.s, #1
-; CHECK-NEXT: ret
+; SVE-LABEL: hadds_v4i16_lsh:
+; SVE: // %bb.0: // %entry
+; SVE-NEXT: ptrue p0.s
+; SVE-NEXT: sxth z0.s, p0/m, z0.s
+; SVE-NEXT: sxth z1.s, p0/m, z1.s
+; SVE-NEXT: add z0.s, z0.s, z1.s
+; SVE-NEXT: lsr z0.s, z0.s, #1
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: hadds_v4i16_lsh:
+; SVE2: // %bb.0: // %entry
+; SVE2-NEXT: ptrue p0.s
+; SVE2-NEXT: sxth z0.s, p0/m, z0.s
+; SVE2-NEXT: saddwb z0.s, z0.s, z1.h
+; SVE2-NEXT: lsr z0.s, z0.s, #1
+; SVE2-NEXT: ret
entry:
%s0s = sext <vscale x 4 x i16> %s0 to <vscale x 4 x i32>
%s1s = sext <vscale x 4 x i16> %s1 to <vscale x 4 x i32>
@@ -511,14 +519,22 @@ entry:
}
define <vscale x 8 x i8> @hadds_v8i8_lsh(<vscale x 8 x i8> %s0, <vscale x 8 x i8> %s1) {
-; CHECK-LABEL: hadds_v8i8_lsh:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: sxtb z0.h, p0/m, z0.h
-; CHECK-NEXT: sxtb z1.h, p0/m, z1.h
-; CHECK-NEXT: add z0.h, z0.h, z1.h
-; CHECK-NEXT: lsr z0.h, z0.h, #1
-; CHECK-NEXT: ret
+; SVE-LABEL: hadds_v8i8_lsh:
+; SVE: // %bb.0: // %entry
+; SVE-NEXT: ptrue p0.h
+; SVE-NEXT: sxtb z0.h, p0/m, z0.h
+; SVE-NEXT: sxtb z1.h, p0/m, z1.h
+; SVE-NEXT: add z0.h, z0.h, z1.h
+; SVE-NEXT: lsr z0.h, z0.h, #1
+; SVE-NEXT: ret
+;
+; SVE2-LABEL: hadds_v8i8_lsh:
+; SVE2: // %bb.0: // %entry
+; SVE2-NEXT: ptrue p0.h
+; SVE2-NEXT: sxtb z0.h, p0/m, z0.h
+; SVE2-NEXT: saddwb z0.h, z0.h, z1.b
+; SVE2-NEXT: lsr z0.h, z0.h, #1
+; SVE2-NEXT: ret
entry:
%s0s = sext <vscale x 8 x i8> %s0 to <vscale x 8 x i16>
%s1s = sext <vscale x 8 x i8> %s1 to <vscale x 8 x i16>
diff --git a/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll b/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
index 80e9e608d3695..e329979b58f98 100644
--- a/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
+++ b/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
@@ -52,9 +52,7 @@ define <vscale x 4 x i32> @signed_wide_add_nxv4i32_nxv4i16(<vscale x 4 x i32> %a
;
; CHECK-SVE2-LABEL: signed_wide_add_nxv4i32_nxv4i16:
; CHECK-SVE2: // %bb.0: // %entry
-; CHECK-SVE2-NEXT: ptrue p0.s
-; CHECK-SVE2-NEXT: sxth z1.s, p0/m, z1.s
-; CHECK-SVE2-NEXT: add z0.s, z0.s, z1.s
+; CHECK-SVE2-NEXT: saddwb z0.s, z0.s, z1.h
; CHECK-SVE2-NEXT: ret
entry:
%input.wide = sext <vscale x 4 x i16> %input to <vscale x 4 x i32>
@@ -71,8 +69,7 @@ define <vscale x 4 x i32> @unsigned_wide_add_nxv4i32_nxv4i16(<vscale x 4 x i32>
;
; CHECK-SVE2-LABEL: unsigned_wide_add_nxv4i32_nxv4i16:
; CHECK-SVE2: // %bb.0: // %entry
-; CHECK-SVE2-NEXT: and z1.s, z1.s, #0xffff
-; CHECK-SVE2-NEXT: add z0.s, z0.s, z1.s
+; CHECK-SVE2-NEXT: uaddwb z0.s, z0.s, z1.h
; CHECK-SVE2-NEXT: ret
entry:
%input.wide = zext <vscale x 4 x i16> %input to <vscale x 4 x i32>
diff --git a/llvm/test/CodeGen/AArch64/sve2-wide-ops.ll b/llvm/test/CodeGen/AArch64/sve2-wide-ops.ll
index 6e7cba3556a3d..ee81c58779fcc 100644
--- a/llvm/test/CodeGen/AArch64/sve2-wide-ops.ll
+++ b/llvm/test/CodeGen/AArch64/sve2-wide-ops.ll
@@ -7,9 +7,7 @@ target triple = "aarch64-unknown-linux-gnu"
define <vscale x 8 x i16> @add_nxv8i16_sext_nxv8i8(<vscale x 8 x i16> %a, <vscale x 8 x i8> %b) {
; CHECK-LABEL: add_nxv8i16_sext_nxv8i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: sxtb z1.h, p0/m, z1.h
-; CHECK-NEXT: add z0.h, z0.h, z1.h
+; CHECK-NEXT: saddwb z0.h, z0.h, z1.b
; CHECK-NEXT: ret
%b.ext = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>
%r = add <vscale x 8 x i16> %a, %b.ext
@@ -19,9 +17,7 @@ define <vscale x 8 x i16> @add_nxv8i16_sext_nxv8i8(<vscale x 8 x i16> %a, <vscal
define <vscale x 4 x i32> @add_nxv4i32_sext_nxv4i16(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b) {
; CHECK-LABEL: add_nxv4i32_sext_nxv4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: sxth z1.s, p0/m, z1.s
-; CHECK-NEXT: add z0.s, z0.s, z1.s
+; CHECK-NEXT: saddwb z0.s, z0.s, z1.h
; CHECK-NEXT: ret
%b.ext = sext <vscale x 4 x i16> %b to <vscale x 4 x i32>
%r = add <vscale x 4 x i32> %a, %b.ext
@@ -36,9 +32,7 @@ define <vscale x 2 x i64> @add_nxv2i64_sext_nxv2i32(<vscale x 2 x i64> %a, <vsca
;
; SME-LABEL: add_nxv2i64_sext_nxv2i32:
; SME: // %bb.0:
-; SME-NEXT: ptrue p0.d
-; SME-NEXT: sxtw z1.d, p0/m, z1.d
-; SME-NEXT: add z0.d, z0.d, z1.d
+; SME-NEXT: saddwb z0.d, z0.d, z1.s
; SME-NEXT: ret
%b.ext = sext <vscale x 2 x i32> %b to <vscale x 2 x i64>
%r = add <vscale x 2 x i64> %a, %b.ext
@@ -48,8 +42,7 @@ define <vscale x 2 x i64> @add_nxv2i64_sext_nxv2i32(<vscale x 2 x i64> %a, <vsca
define <vscale x 8 x i16> @add_nxv8i16_zext_nxv8i8(<vscale x 8 x i16> %a, <vscale x 8 x i8> %b) {
; CHECK-LABEL: add_nxv8i16_zext_nxv8i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: and z1.h, z1.h, #0xff
-; CHECK-NEXT: add z0.h, z0.h, z1.h
+; CHECK-NEXT: uaddwb z0.h, z0.h, z1.b
; CHECK-NEXT: ret
%b.ext = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>
%r = add <vscale x 8 x i16> %a, %b.ext
@@ -59,8 +52,7 @@ define <vscale x 8 x i16> @add_nxv8i16_zext_nxv8i8(<vscale x 8 x i16> %a, <vscal
define <vscale x 4 x i32> @add_nxv4i32_zext_nxv4i16(<vscale x 4 x i32> %a, <vscale x 4 x i16> %b) {
; CHECK-LABEL: add_nxv4i32_zext_nxv4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: and z1.s, z1.s, #0xffff
-; CHECK-NEXT: add z0.s, z0.s, z1.s
+; CHECK-NEXT: uaddwb z0.s, z0.s, z1.h
; CHECK-NEXT: ret
%b.ext = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>
%r = add <vscale x 4 x i32> %a, %b.ext
@@ -75,8 +67,7 @@ define <vscale x 2 x i64> @add_nxv2i64_zext_nxv2i32(<vscale x 2 x i64> %a, <vsca
;
; SME-LABEL: add_nxv2i64_zext_nxv2i32:
; SME: // %bb.0:
-; SME-NEXT: and z1.d, z1.d, #0xffffffff
-; SME-NEXT: add z0.d, z0.d, z1.d
+; SME-NEXT: uaddwb z0.d, z0.d, z1.s
; SME-NEXT: ret
%b.ext = zext <vscale x 2 x i32> %b to <vscale x 2 x i64>
%r = add <vscale x 2 x i64> %a, %b.ext
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