[llvm] [AMDGPU][CodeGen] Incrementally update reserved regs for SIPreAllocateWWMRegs pass in RegisterClassInfo (PR #212201)

[Matt Arsenault via llvm-commits]

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@@ -123,6 +123,81 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf,
   }
 }
 
+void RegisterClassInfo::updateReservedRegs(const BitVector &ReservedInput) {
+  assert(MF && TRI && RegClass &&
+         "RegisterClassInfo must be initialized before updating reserved regs");
+  assert(ReservedInput.size() == Reserved.size() &&
+         "Reserved register bit vectors must have the same size");
+  if (ReservedInput == Reserved)
+    return;
+
+  // Cached orders cannot regain unreserved registers; recompute them lazily.
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arsenm wrote:

For AMDGPU we do have uses for re-introducing reserved registers, but it would require writing a new optimization pass. We have to reserve registers to manage spilling, but if we know after RA there are no spills, we can free those up and make use of them

https://github.com/llvm/llvm-project/pull/212201