[llvm] [X86] Fold MOVAPS+SHUFPS into PSHUFD to eliminate redundant copies when … (PR #212626)

[via llvm-commits]

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@@ -688,6 +688,13 @@ def TuningNoDomainDelayShuffle : SubtargetFeature<"no-bypass-delay-shuffle",
                                    "Has no bypass delay when using the 'wrong' shuffle type",
                                    [], InlineIgnore>;
 
+// AMD processors (bdver and znver) consider any fp data movement within
+// a register (except blends) to be integer domain.
+def TuningIntDomainFloatShuffle : SubtargetFeature<"int-domain-float-shuffle",
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zero318 wrote:

That flag doesn't do anything in this scenario. The codegen currently considers `SHUFPS` to be FP domain unconditionally, so even setting TuningNoDomainDelayShuffle doesn't make it always generate `PSHUFD`. 

Compiling this with `-march=znver2 -mno-avx -O3 -Xclang -target-feature -Xclang +no-bypass-delay-shuffle` shows the behavior with a shuffle where both the input/output are float domain:
```C++
typedef float vecf32_4 __attribute__((vector_size(16)));

vecf32_4 shuffle_test(
    vecf32_4 A,
    vecf32_4 B,
    vecf32_4* C
) {
    A += A;
    *C = B + __builtin_shufflevector(A, A, 2, 2, 2, 2);
    return A;
}
```
currently compiles to
```asm
shuffle_test:
  ADDPS XMM0, XMM0
  MOVAPS XMM2, XMM0
  SHUFPS XMM2, XMM0, 0xAA
  ADDPS XMM2, XMM1
  MOVAPS [RDI], XMM2
  RET
```
Because float-type shuffles are integer domain on these processors it should be much more aggressively checking all available opcodes because the delays are unavoidable for floats and zero for ints.

These are all of the opcodes classified this way for each applicable generation:
- bdver1-bdver4 and znver1-znver4:
  - `MOVLHPS`/`MOVHLPS`
  - `SHUFPS`/`SHUFPD`
  - `VPERMILPS`/`VPERMILPD`
  - `UNPCKLPS`/`UNPCKLPD`/`UNPCKHPS`/`UNPCKHPD`
  - `VPERM2F128`
  - `INSERTPS reg, reg, imm` (not reg, mem, imm)
  - `VINSERTF128 reg, reg, imm` (not reg, mem, imm)
  - `VEXTRACTF128 reg, reg, imm` (not reg, mem, imm)
  - `MOVDDUP reg, reg` (not reg, mem)
  - `MOVSLDUP reg, reg`/`MOVSHDUP reg, reg` (not reg, mem)
- bdver1-bdver2 only:
  - `BLENDPS`/`BLENDPD`
  - `BLENDVPS`/`BLENDVPD`
- bdver1-bdver4 only:
  - `ANDPS`/`ANDPD`
  - `ANDNPS`/`ANDNPD`
  - `ORPS`/`ORPD`
  - `XORPS`/`XORPD`
- Unclear from documentation I've read:
  - `VPERMPS`/`VPERMPD`
  - AVX512 opcodes on znver4
  - `VPERMIL2PS`/`VPERMIL2PD` (probably int domain though)
  - `VPPERM` (probably int domain though)

https://github.com/llvm/llvm-project/pull/212626