[llvm] [AArch64] Remove GPR64arg register class (PR #212457)
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 29 05:19:13 PDT 2026
https://github.com/c-rhodes updated https://github.com/llvm/llvm-project/pull/212457
>From 829e6f93abbaf67de8084316b0092f841ebf2f9c Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Wed, 22 Jul 2026 15:40:11 +0000
Subject: [PATCH 1/5] [AArch64] Mark GPR64arg register class as non-allocatable
GPR64arg was added in fcbec02ea6fb to describe X0-X7 for the reserved
argument-register check. It is an ABI register set rather than an
allocation constraint and should not be used for register allocation.
This exposes that GlobalISel recomputes the minimal register class when
a matching inline asm input is tied to a fixed physical-register output.
For X2 that class is GPR64arg, triggering an assertion when it is used
to create a virtual register after becoming non-allocatable.
getRegistersForValue already asks the target which class implements the
output constraint. Retain that class and reuse it for the matching
input.
Assisted-by: codex
---
llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp | 14 +++++++++-----
llvm/lib/Target/AArch64/AArch64RegisterInfo.td | 4 +++-
.../AArch64/GlobalISel/irtranslator-inline-asm.ll | 2 +-
3 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index b5bbcc193b6b7..8830494fc9681 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -46,6 +46,9 @@ class GISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
/// contains the set of assigned registers corresponding to the operand.
SmallVector<Register, 1> Regs;
+ /// The register class selected for this operand's constraint.
+ const TargetRegisterClass *RegClass = nullptr;
+
explicit GISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &Info)
: TargetLowering::AsmOperandInfo(Info) {}
};
@@ -112,6 +115,7 @@ static void getRegistersForValue(MachineFunction &MF,
// RC is unset only on failure. Return immediately.
if (!RC)
return;
+ OpInfo.RegClass = RC;
// No need to allocate a matching input constraint since the constraint it's
// matching to has already been allocated.
@@ -425,14 +429,14 @@ bool InlineAsmLowering::lowerInlineAsm(
// We need the tied input to live in the same register class as the def.
//
// - if Def is a vreg, we can just use its regclass.
- // - if Def is a physreg, create a vreg in the minimal regclass for that
- // physreg.
+ // - if Def is a physreg, create a vreg in the regclass selected for its
+ // constraint.
//
// Otherwise RegBankSelect may leave it in the wrong bank (e.g. GPR even
// though it's tied to an FP physreg).
- const TargetRegisterClass *RC = Def.isVirtual()
- ? MRI->getRegClass(Def)
- : TRI->getMinimalPhysRegClass(Def);
+ const TargetRegisterClass *RC =
+ Def.isVirtual() ? MRI->getRegClass(Def) : OpInfo.RegClass;
+ assert(RC && "Expected a register class for matching constraint");
// Materialize `In` in a new vreg that has a register class that matches
// the register class of `Def`.
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 5dd8171853fd3..2964357343d02 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -248,7 +248,9 @@ def GPR64z : RegisterOperand<GPR64> {
let GIZeroRegister = XZR;
}
-// GPR argument registers.
+// GPR argument registers. This is an ABI register set, not an allocation
+// constraint.
+let isAllocatable = 0 in
def GPR64arg : RegisterClass<"AArch64", [i64], 64, (sequence "X%u", 0, 7)>;
// GPR register classes which include WZR/XZR AND SP/WSP. This is not a
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
index d627e11f4aa0c..5b783e44a66ec 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
@@ -270,7 +270,7 @@ define i64 @test_input_with_matching_constraint_to_physical_register() {
; CHECK-LABEL: name: test_input_with_matching_constraint_to_physical_register
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64arg = COPY [[C]](i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY [[C]](i64)
; CHECK-NEXT: INLINEASM &"", attdialect, regdef, implicit-def $x2, reguse tiedto:$0, [[COPY]](tied-def 3)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x2
; CHECK-NEXT: $x0 = COPY [[COPY1]](i64)
>From 360668449b6e79bb3d225b09e159fc461d758ba1 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Tue, 28 Jul 2026 11:25:58 +0000
Subject: [PATCH 2/5] address comments
---
llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 8830494fc9681..10d2d99138e8f 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -429,13 +429,14 @@ bool InlineAsmLowering::lowerInlineAsm(
// We need the tied input to live in the same register class as the def.
//
// - if Def is a vreg, we can just use its regclass.
- // - if Def is a physreg, create a vreg in the regclass selected for its
- // constraint.
+ // - if Def is a physreg, create a vreg in an allocatable subclass of
+ // the regclass selected for its constraint.
//
// Otherwise RegBankSelect may leave it in the wrong bank (e.g. GPR even
// though it's tied to an FP physreg).
const TargetRegisterClass *RC =
- Def.isVirtual() ? MRI->getRegClass(Def) : OpInfo.RegClass;
+ Def.isVirtual() ? MRI->getRegClass(Def)
+ : TRI->getAllocatableClass(OpInfo.RegClass);
assert(RC && "Expected a register class for matching constraint");
// Materialize `In` in a new vreg that has a register class that matches
>From cff942b44cbf303d4ca06ad7d8f0d681b70c0b32 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Wed, 22 Jul 2026 14:59:22 +0000
Subject: [PATCH 3/5] [AArch64] Remove the GPR64arg register class
---
llvm/lib/Target/AArch64/AArch64CallingConvention.cpp | 3 +++
llvm/lib/Target/AArch64/AArch64CallingConvention.h | 8 ++++++++
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 11 -----------
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 4 ----
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 3 ++-
llvm/lib/Target/AArch64/AArch64RegisterInfo.td | 5 -----
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp | 1 +
llvm/test/TableGen/aarch64-register-info-stats.td | 6 +++---
8 files changed, 17 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp b/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
index b094a058e50a7..ecf59bdadd83a 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
@@ -40,6 +40,9 @@ static const MCPhysReg ZRegList[] = {AArch64::Z0, AArch64::Z1, AArch64::Z2,
static const MCPhysReg PRegList[] = {AArch64::P0, AArch64::P1, AArch64::P2,
AArch64::P3};
+ArrayRef<MCPhysReg> llvm::AArch64::getGPRArgRegs() { return XRegList; }
+ArrayRef<MCPhysReg> llvm::AArch64::getFPRArgRegs() { return QRegList; }
+
static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
CCState &State, Align SlotAlign) {
diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.h b/llvm/lib/Target/AArch64/AArch64CallingConvention.h
index 7105fa695334b..09717cc11cde5 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.h
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.h
@@ -13,9 +13,17 @@
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
#define LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
+#include "llvm/ADT/ArrayRef.h"
#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/MC/MCRegister.h"
namespace llvm {
+namespace AArch64 {
+// Registers used to pass function arguments.
+ArrayRef<MCPhysReg> getGPRArgRegs();
+ArrayRef<MCPhysReg> getFPRArgRegs();
+} // namespace AArch64
+
bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
Type *OrigTy, CCState &State);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8e3cf9d31a923..190bb086b174b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -223,17 +223,6 @@ constexpr MVT CondCodeVT = MVT::i32;
/// Value type used for NZCV flags.
constexpr MVT FlagsVT = MVT::i32;
-static const MCPhysReg GPRArgRegs[] = {AArch64::X0, AArch64::X1, AArch64::X2,
- AArch64::X3, AArch64::X4, AArch64::X5,
- AArch64::X6, AArch64::X7};
-static const MCPhysReg FPRArgRegs[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
- AArch64::Q3, AArch64::Q4, AArch64::Q5,
- AArch64::Q6, AArch64::Q7};
-
-ArrayRef<MCPhysReg> llvm::AArch64::getGPRArgRegs() { return GPRArgRegs; }
-
-ArrayRef<MCPhysReg> llvm::AArch64::getFPRArgRegs() { return FPRArgRegs; }
-
static inline EVT getPackedSVEVectorVT(EVT VT) {
switch (VT.getSimpleVT().SimpleTy) {
default:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 9c2ea0faee5ec..8f6edf8cc5d93 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -42,10 +42,6 @@ const unsigned RoundingBitsPos = 22;
// Reserved bits should be preserved when modifying FPCR.
const uint64_t ReservedFPControlBits = 0xfffffffff80040f8;
-// Registers used to pass function arguments.
-ArrayRef<MCPhysReg> getGPRArgRegs();
-ArrayRef<MCPhysReg> getFPRArgRegs();
-
/// Maximum allowed number of unprobed bytes above SP at an ABI
/// boundary.
const unsigned StackProbeMaxUnprobedStack = 1024;
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index edca3e94a0afe..3bc09feb12c6e 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "AArch64RegisterInfo.h"
+#include "AArch64CallingConvention.h"
#include "AArch64FrameLowering.h"
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
@@ -576,7 +577,7 @@ bool AArch64RegisterInfo::isStrictlyReservedReg(const MachineFunction &MF,
}
bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {
- for (size_t i = 0; i < AArch64::GPR64argRegClass.getNumRegs(); ++i) {
+ for (size_t i = 0; i < AArch64::getGPRArgRegs().size(); ++i) {
if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i))
return true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 2964357343d02..7e5baaf5882fb 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -248,11 +248,6 @@ def GPR64z : RegisterOperand<GPR64> {
let GIZeroRegister = XZR;
}
-// GPR argument registers. This is an ABI register set, not an allocation
-// constraint.
-let isAllocatable = 0 in
-def GPR64arg : RegisterClass<"AArch64", [i64], 64, (sequence "X%u", 0, 7)>;
-
// GPR register classes which include WZR/XZR AND SP/WSP. This is not a
// constraint used by any instructions, it is used as a common super-class.
def GPR32all : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR, WSP)>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index b0a409d153fd2..28b73d58c77e0 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -13,6 +13,7 @@
//===----------------------------------------------------------------------===//
#include "AArch64CallLowering.h"
+#include "AArch64CallingConvention.h"
#include "AArch64GlobalISelUtils.h"
#include "AArch64ISelLowering.h"
#include "AArch64MachineFunctionInfo.h"
diff --git a/llvm/test/TableGen/aarch64-register-info-stats.td b/llvm/test/TableGen/aarch64-register-info-stats.td
index b1a33cc2dfe42..6e004d018c00c 100644
--- a/llvm/test/TableGen/aarch64-register-info-stats.td
+++ b/llvm/test/TableGen/aarch64-register-info-stats.td
@@ -13,6 +13,6 @@ def TestTarget : Target {
let InstructionSet = TestInstrInfo;
}
-// CHECK-DAG: 82 register-info-emitter - Number of explicit register classes
-// CHECK-DAG: 446 register-info-emitter - Number of synthesized register classes
-// CHECK-DAG: 189 register-info-emitter - Number of register pressure sets
+// CHECK-DAG: 81 register-info-emitter - Number of explicit register classes
+// CHECK-DAG: 440 register-info-emitter - Number of synthesized register classes
+// CHECK-DAG: 190 register-info-emitter - Number of register pressure sets
>From f946d4ce2be027e02f2a01bf4d693d788e1f2e07 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Wed, 29 Jul 2026 11:21:44 +0000
Subject: [PATCH 4/5] Remove getAllocatableClass call
---
llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
index 10d2d99138e8f..8830494fc9681 100644
--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -429,14 +429,13 @@ bool InlineAsmLowering::lowerInlineAsm(
// We need the tied input to live in the same register class as the def.
//
// - if Def is a vreg, we can just use its regclass.
- // - if Def is a physreg, create a vreg in an allocatable subclass of
- // the regclass selected for its constraint.
+ // - if Def is a physreg, create a vreg in the regclass selected for its
+ // constraint.
//
// Otherwise RegBankSelect may leave it in the wrong bank (e.g. GPR even
// though it's tied to an FP physreg).
const TargetRegisterClass *RC =
- Def.isVirtual() ? MRI->getRegClass(Def)
- : TRI->getAllocatableClass(OpInfo.RegClass);
+ Def.isVirtual() ? MRI->getRegClass(Def) : OpInfo.RegClass;
assert(RC && "Expected a register class for matching constraint");
// Materialize `In` in a new vreg that has a register class that matches
>From 66d0e297873ddbd158da2e0f43966e8f401a9c12 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Wed, 29 Jul 2026 12:14:05 +0000
Subject: [PATCH 5/5] address comments
---
llvm/lib/Target/AArch64/AArch64CallingConvention.cpp | 3 ---
llvm/lib/Target/AArch64/AArch64CallingConvention.h | 8 --------
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 11 +++++++++++
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 4 ++++
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 3 +--
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp | 1 -
6 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp b/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
index ecf59bdadd83a..b094a058e50a7 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
@@ -40,9 +40,6 @@ static const MCPhysReg ZRegList[] = {AArch64::Z0, AArch64::Z1, AArch64::Z2,
static const MCPhysReg PRegList[] = {AArch64::P0, AArch64::P1, AArch64::P2,
AArch64::P3};
-ArrayRef<MCPhysReg> llvm::AArch64::getGPRArgRegs() { return XRegList; }
-ArrayRef<MCPhysReg> llvm::AArch64::getFPRArgRegs() { return QRegList; }
-
static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
CCState &State, Align SlotAlign) {
diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.h b/llvm/lib/Target/AArch64/AArch64CallingConvention.h
index 09717cc11cde5..7105fa695334b 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.h
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.h
@@ -13,17 +13,9 @@
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
#define LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
-#include "llvm/ADT/ArrayRef.h"
#include "llvm/CodeGen/CallingConvLower.h"
-#include "llvm/MC/MCRegister.h"
namespace llvm {
-namespace AArch64 {
-// Registers used to pass function arguments.
-ArrayRef<MCPhysReg> getGPRArgRegs();
-ArrayRef<MCPhysReg> getFPRArgRegs();
-} // namespace AArch64
-
bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
Type *OrigTy, CCState &State);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 405638141ce7d..a5a2c9e430ac2 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -230,6 +230,17 @@ constexpr MVT CondCodeVT = MVT::i32;
/// Value type used for NZCV flags.
constexpr MVT FlagsVT = MVT::i32;
+static const MCPhysReg GPRArgRegs[] = {AArch64::X0, AArch64::X1, AArch64::X2,
+ AArch64::X3, AArch64::X4, AArch64::X5,
+ AArch64::X6, AArch64::X7};
+static const MCPhysReg FPRArgRegs[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
+ AArch64::Q3, AArch64::Q4, AArch64::Q5,
+ AArch64::Q6, AArch64::Q7};
+
+ArrayRef<MCPhysReg> llvm::AArch64::getGPRArgRegs() { return GPRArgRegs; }
+
+ArrayRef<MCPhysReg> llvm::AArch64::getFPRArgRegs() { return FPRArgRegs; }
+
static inline EVT getPackedSVEVectorVT(EVT VT) {
switch (VT.getSimpleVT().SimpleTy) {
default:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index f6b5b9e305206..35f7ef0e2151e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -42,6 +42,10 @@ const unsigned RoundingBitsPos = 22;
// Reserved bits should be preserved when modifying FPCR.
const uint64_t ReservedFPControlBits = 0xfffffffff80040f8;
+// Registers used to pass function arguments.
+ArrayRef<MCPhysReg> getGPRArgRegs();
+ArrayRef<MCPhysReg> getFPRArgRegs();
+
/// Maximum allowed number of unprobed bytes above SP at an ABI
/// boundary.
const unsigned StackProbeMaxUnprobedStack = 1024;
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 3bc09feb12c6e..502c91fe3e531 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//
#include "AArch64RegisterInfo.h"
-#include "AArch64CallingConvention.h"
#include "AArch64FrameLowering.h"
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
@@ -577,7 +576,7 @@ bool AArch64RegisterInfo::isStrictlyReservedReg(const MachineFunction &MF,
}
bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {
- for (size_t i = 0; i < AArch64::getGPRArgRegs().size(); ++i) {
+ for (size_t i = 0; i < 8; ++i) {
if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i))
return true;
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 28b73d58c77e0..b0a409d153fd2 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -13,7 +13,6 @@
//===----------------------------------------------------------------------===//
#include "AArch64CallLowering.h"
-#include "AArch64CallingConvention.h"
#include "AArch64GlobalISelUtils.h"
#include "AArch64ISelLowering.h"
#include "AArch64MachineFunctionInfo.h"
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