[llvm] [AMDGPU] Fix typos SGRP and VGRP. NFC. (PR #212732)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 29 03:35:13 PDT 2026
https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/212732
None
>From 53b6deb0024ccb5d6c9ec70b2995a844ae089379 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 29 Jul 2026 11:34:28 +0100
Subject: [PATCH] [AMDGPU] Fix typos SGRP and VGRP. NFC.
---
llvm/docs/AMDGPUUsage.rst | 2 +-
llvm/lib/Target/AMDGPU/SIProgramInfo.cpp | 6 +++---
.../AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir | 8 ++++----
llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt | 4 ++--
llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt | 8 ++++----
5 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 2a4f290effc6d..e65baa0f48b78 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -20421,7 +20421,7 @@ after the source language arguments in the following order:
1. Work-Item ID (1 VGPR)
- The X, Y and Z work-item ID are packed into a single VGRP with the following
+ The X, Y and Z work-item ID are packed into a single VGPR with the following
layout. Only fields actually used by the function are set. The other bits
are undefined.
diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
index 27cef7a1b9158..713f214bf315a 100644
--- a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
@@ -138,11 +138,11 @@ static uint64_t getPGMRSrc1Reg(const SIProgramInfo &ProgInfo,
static uint64_t getComputePGMRSrc2Reg(const GCNSubtarget &ST,
const SIProgramInfo &ProgInfo) {
- uint64_t MaxNumUserSGRPs = AMDGPU::getMaxNumUserSGPRs(ST);
+ uint64_t MaxNumUserSGPRs = AMDGPU::getMaxNumUserSGPRs(ST);
uint64_t Reg = 0;
- if (MaxNumUserSGRPs == 32) {
+ if (MaxNumUserSGPRs == 32) {
Reg = S_00B84C_USER_SGPR_GFX1250(ProgInfo.UserSGPR);
- } else if (MaxNumUserSGRPs == 16) {
+ } else if (MaxNumUserSGPRs == 16) {
Reg = (S_00B84C_USER_SGPR(ProgInfo.UserSGPR) |
S_00B84C_TRAP_HANDLER(ProgInfo.TrapHandlerEnable));
} else {
diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
index 6120da6b5d5fe..8b928bc9defa5 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
+++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir
@@ -15,7 +15,7 @@
define void @dont_remat_at_max_occ() "amdgpu-waves-per-eu"="8,8" {
ret void
}
- define void @reduce_arch_and_acc_vgrp_spill() "amdgpu-waves-per-eu"="8,8" {
+ define void @reduce_arch_and_acc_vgpr_spill() "amdgpu-waves-per-eu"="8,8" {
ret void
}
define void @reduce_spill_archvgpr_above_addressable_limit() "amdgpu-flat-work-group-size"="1,64" "amdgpu-waves-per-eu"="1,2" {
@@ -757,12 +757,12 @@ body: |
# unified RF case (gfx90a) the ArchVGPR allocation granule may force us to remat
# more ArchVGPRs to eliminate spilling.
---
-name: reduce_arch_and_acc_vgrp_spill
+name: reduce_arch_and_acc_vgpr_spill
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
body: |
- ; GFX908-LABEL: name: reduce_arch_and_acc_vgrp_spill
+ ; GFX908-LABEL: name: reduce_arch_and_acc_vgpr_spill
; GFX908: bb.0:
; GFX908-NEXT: successors: %bb.1(0x80000000)
; GFX908-NEXT: {{ $}}
@@ -850,7 +850,7 @@ body: |
; GFX908-NEXT: S_NOP 0, implicit [[DEF28]]
; GFX908-NEXT: S_ENDPGM 0
;
- ; GFX90A-LABEL: name: reduce_arch_and_acc_vgrp_spill
+ ; GFX90A-LABEL: name: reduce_arch_and_acc_vgpr_spill
; GFX90A: bb.0:
; GFX90A-NEXT: successors: %bb.1(0x80000000)
; GFX90A-NEXT: {{ $}}
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt
index 57931a325a5f0..950abbc5123b9 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem.txt
@@ -414,7 +414,7 @@
0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00
# CHECK: s_load_dword s5, s[2:3], s101 ; encoding: [0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00]
-# The SGRP variants can alternatively be encoded with imm=0, soffset_en=1
+# The SGPR variants can alternatively be encoded with imm=0, soffset_en=1
# and the offset register encoded in the soffset field with the offset
# field being disregarded.
0x41,0x41,0x00,0xc0,0x65,0x00,0x00,0x80
@@ -722,7 +722,7 @@
0x41,0x41,0x42,0xc0,0x00,0x00,0x00,0x00
# CHECK: s_store_dword s5, s[2:3], s0 offset:0x0 ; encoding: [0x41,0x41,0x42,0xc0,0x00,0x00,0x00,0x00]
-# The SGRP variants can alternatively be encoded with imm=0, soffset_en=1
+# The SGPR variants can alternatively be encoded with imm=0, soffset_en=1
# and the offset register encoded in the soffset field with the offset
# field being disregarded.
0x41,0x41,0x40,0xc0,0x65,0x00,0x00,0x80
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt
index 9456b6188944c..1111104bacdb8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_smem_features.txt
@@ -49,7 +49,7 @@
0xc2,0x01,0x98,0xc0,0x09,0x00,0x00,0x00
# GFX9: s_atc_probe 7, s[4:5], s9 ; encoding: [0xc2,0x01,0x98,0xc0,0x09,0x00,0x00,0x00]
-# The SGRP variants can alternatively be encoded with imm=0, soffset_en=1
+# The SGPR variants can alternatively be encoded with imm=0, soffset_en=1
# and the offset register encoded in the soffset field with the offset
# field being disregarded.
0xc2,0x41,0x98,0xc0,0x2e,0x00,0x00,0x12
@@ -70,13 +70,13 @@
0x41,0x01,0x08,0xc2,0x65,0x00,0x00,0x00
# GFX9: s_atomic_add s5, s[2:3], s101 ; encoding: [0x41,0x01,0x08,0xc2,0x65,0x00,0x00,0x00]
-# The SGRP variants can alternatively be encoded with imm=0, soffset_en=1
+# The SGPR variants can alternatively be encoded with imm=0, soffset_en=1
# and the offset register encoded in the soffset field with the offset
# field being disregarded.
0x41,0x41,0x08,0xc2,0x2e,0x00,0x00,0xca
# GFX9: s_atomic_add s5, s[2:3], s101 ; encoding: [0x41,0x41,0x08,0xc2,0x00,0x00,0x00,0xca]
-# The SGRP variants can alternatively be encoded with imm=0, soffset_en=1
+# The SGPR variants can alternatively be encoded with imm=0, soffset_en=1
# and the offset register encoded in the soffset field with the offset
# field being disregarded.
0x41,0x41,0x09,0xc2,0x2e,0x00,0x00,0xca
@@ -292,7 +292,7 @@
0x32,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00
# GFX9: s_dcache_discard s[100:101], s0 ; encoding: [0x32,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00]
-# The SGRP variants can alternatively be encoded with imm=0, soffset_en=1
+# The SGPR variants can alternatively be encoded with imm=0, soffset_en=1
# and the offset register encoded in the soffset field with the offset
# field being disregarded.
0x32,0x40,0xa0,0xc0,0x25,0x00,0x00,0x80
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