[llvm] [AArch64] C1-Premium SME defintions (PR #212482)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 29 02:46:25 PDT 2026
================
@@ -0,0 +1,356 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-premium -instruction-tables -mattr=+sme2p2,+mca-streaming-sched,+fp8,+sve-b16b16,+sme-b16b16,+sme-f64f64,+faminmax,+sme-f8f32,+sme-lutv2,+f64mm < %p/../Inputs/streaming-sme-only-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 2 1.00 U add za.s[w8, 0, vgx2], { z0.s, z1.s }
+# CHECK-NEXT: 1 2 1.00 U sub za.s[w8, 0, vgx2], { z0.s, z1.s }
+# CHECK-NEXT: 1 5 1.00 U add { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 2.00 U addha za0.s, p0/m, p0/m, z0.s
+# CHECK-NEXT: 1 4 2.00 U addva za0.s, p0/m, p0/m, z0.s
+# CHECK-NEXT: 1 11 1.00 U bf1cvt { z0.h, z1.h }, z0.b
+# CHECK-NEXT: 1 11 1.00 * bf1cvtlt z0.h, z0.b
+# CHECK-NEXT: 1 11 1.00 U bf2cvt { z0.h, z1.h }, z0.b
+# CHECK-NEXT: 1 11 1.00 * bf2cvtlt z0.h, z0.b
+# CHECK-NEXT: 1 4 1.00 U bfadd za.h[w8, 0, vgx2], { z0.h, z1.h }
+# CHECK-NEXT: 1 11 1.00 U bfcvt z0.h, { z0.s, z1.s }
+# CHECK-NEXT: 1 7 1.00 U bfcvtn z0.h, { z0.s, z1.s }
+# CHECK-NEXT: 1 5 1.00 U bfclamp { z0.h, z1.h }, z0.h, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfmax { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfmaxnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfmin { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfminnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfmlal za.s[w8, 0:1], z1.h, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfmlal za.s[w8, 0:1], z1.h, z0.h[0]
+# CHECK-NEXT: 1 4 1.00 U fmlal za.s[w8, 0:1], z1.h, z0.h
+# CHECK-NEXT: 1 4 1.00 U fmlal za.s[w8, 0:1], z1.h, z0.h[0]
+# CHECK-NEXT: 1 4 1.00 U bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfmlsl za.s[w8, 0:1], z1.h, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfmlsl za.s[w8, 0:1], z1.h, z0.h[0]
+# CHECK-NEXT: 1 4 1.00 U fmlsl za.s[w8, 0:1], z1.h, z0.h
+# CHECK-NEXT: 1 4 1.00 U fmlsl za.s[w8, 0:1], z1.h, z0.h[0]
+# CHECK-NEXT: 1 4 2.00 U bfmopa za0.s, p0/m, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 4 2.00 U bfmops za0.s, p0/m, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 4 1.00 U bfvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+# CHECK-NEXT: 1 2 2.00 U bmopa za0.s, p0/m, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 2.00 U bmops za0.s, p0/m, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 4 1.00 * f1cvt z0.h, z0.b
+# CHECK-NEXT: 1 4 1.00 * f1cvtlt z0.h, z0.b
+# CHECK-NEXT: 1 4 1.00 * f2cvt z0.h, z0.b
+# CHECK-NEXT: 1 4 1.00 * f2cvtlt z0.h, z0.b
+# CHECK-NEXT: 1 4 1.00 U fadd za.s[w8, 0, vgx2], { z0.s, z1.s }
+# CHECK-NEXT: 1 5 1.00 U famax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+# CHECK-NEXT: 1 5 1.00 U famin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }
+# CHECK-NEXT: 1 5 1.00 U fclamp { z0.h, z1.h }, z0.h, z0.h
+# CHECK-NEXT: 1 4 1.00 U fcvt z0.h, { z0.s, z1.s }
+# CHECK-NEXT: 1 4 1.00 U fcvtn z0.h, { z0.s, z1.s }
+# CHECK-NEXT: 1 4 1.00 U fcvtzs { z0.s, z1.s }, { z0.s, z1.s }
+# CHECK-NEXT: 1 4 1.00 U fcvtzu { z0.s, z1.s }, { z0.s, z1.s }
+# CHECK-NEXT: 1 4 2.00 U fmopa za0.s, p0/m, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 4 2.00 U fmops za0.s, p0/m, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 5 1.00 U fmax { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 4 1.00 U fmaxnm { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 5 1.00 U fmin { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 4 1.00 U fminnm { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 4 1.00 U fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 4 1.00 U fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U fmlall za.s[w8, 0:3], z0.b, z0.b
+# CHECK-NEXT: 1 4 1.00 U fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 4 1.00 U fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h
+# CHECK-NEXT: 1 4 1.00 U frinta { z0.s, z1.s }, { z0.s, z1.s }
+# CHECK-NEXT: 1 4 1.00 U frintm { z0.s, z1.s }, { z0.s, z1.s }
+# CHECK-NEXT: 1 4 1.00 U frintn { z0.s, z1.s }, { z0.s, z1.s }
+# CHECK-NEXT: 1 4 1.00 U frintp { z0.s, z1.s }, { z0.s, z1.s }
+# CHECK-NEXT: 1 4 1.00 U fvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]
+# CHECK-NEXT: 1 4 2.00 U fvdotb za.s[w8, 0, vgx4], { z0.b, z1.b }, z0.b[0]
+# CHECK-NEXT: 1 4 2.00 U fvdott za.s[w8, 0, vgx4], { z0.b, z1.b }, z0.b[0]
+# CHECK-NEXT: 1 4 1.00 U fscale { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 5 2.00 U luti2 { z0.h, z1.h }, zt0, z0[0]
+# CHECK-NEXT: 1 5 2.00 U luti4 { z0.h, z1.h }, zt0, z0[0]
+# CHECK-NEXT: 1 2 1.00 * ld1b { z0.b, z1.b }, pn8/z, [x0]
+# CHECK-NEXT: 1 2 1.00 * ld1b { z0.b - z3.b }, pn8/z, [x0]
+# CHECK-NEXT: 1 2 1.00 * ldnt1b { z0.b, z1.b }, pn8/z, [x0]
+# CHECK-NEXT: 1 2 1.00 * ldnt1b { z0.b - z3.b }, pn8/z, [x0]
+# CHECK-NEXT: 1 9 1.00 * U mov { z0.s, z1.s }, za0h.s[w12, 0:1]
+# CHECK-NEXT: 1 9 1.00 * mov z0.s, p0/m, za0h.s[w12, 0]
+# CHECK-NEXT: 1 5 1.00 U mov za0h.b[w12, 0], p0/m, z0.b
+# CHECK-NEXT: 1 4 1.00 U movt zt0[0], x0
+# CHECK-NEXT: 1 8 1.00 U movt x0, zt0[0]
+# CHECK-NEXT: 1 5 1.00 U sclamp { z0.h, z1.h }, z0.h, z0.h
+# CHECK-NEXT: 1 4 1.00 U smax { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 4 1.00 U smin { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 5 1.00 U uclamp { z0.h, z1.h }, z0.h, z0.h
+# CHECK-NEXT: 1 4 1.00 U umax { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 4 1.00 U umin { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+# CHECK-NEXT: 1 5 2.00 U smax { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+# CHECK-NEXT: 1 5 2.00 U umin { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+# CHECK-NEXT: 1 4 1.00 U scvtf { z0.s, z1.s }, { z0.s, z1.s }
+# CHECK-NEXT: 1 4 1.00 U ucvtf { z0.s, z1.s }, { z0.s, z1.s }
+# CHECK-NEXT: 1 4 0.50 U sel { z0.h, z1.h }, pn8, { z0.h, z1.h }, { z0.h, z1.h }
----------------
walkerkd wrote:
rthroughput should be 1
3.12 SME Misc instructions / 3-11 SME Misc instructions.,"Multi-vector conditionally select elements from two vectors, 2-reg."
https://github.com/llvm/llvm-project/pull/212482
More information about the llvm-commits
mailing list