[llvm] [AMDGPU] Fix verifier false positive for AV-class atomic registers (PR #212721)

[Matt Arsenault via llvm-commits]

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@@ -5854,14 +5854,20 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
       Data = nullptr;
 
     if (ST.hasGFX90AInsts()) {
+      auto IsAGPRFileMismatch = [&](Register X, Register Y) {
+        if (RI.isVectorSuperClass(RI.getRegClassForReg(MRI, X)) ||
+            RI.isVectorSuperClass(RI.getRegClassForReg(MRI, Y)))
+          return false;
+        return RI.isAGPR(MRI, X) != RI.isAGPR(MRI, Y);
+      };
       if (Dst && Data && !Dst->isTied() && !Data->isTied() &&
-          (RI.isAGPR(MRI, Dst->getReg()) != RI.isAGPR(MRI, Data->getReg()))) {
+          IsAGPRFileMismatch(Dst->getReg(), Data->getReg())) {
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arsenm wrote:

This shouldn't require manual verification. All of this code is a leftover from before we had correct instruction definitions and can probably be deleted 

https://github.com/llvm/llvm-project/pull/212721