[llvm] [X86] Lower scalar bf16 arithmetic on AVX10.2 via packed ops (PR #212245)

[Phoebe Wang via llvm-commits]

================
@@ -34513,6 +34522,32 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   }
 }
 
+/// Lower a scalar bf16 arithmetic node whose type is being soft-promoted.
+///
+/// AVX10.2 has no scalar bf16 arithmetic instructions, and bf16 is a
+/// soft-promoted-half type, so scalar ops would otherwise be promoted to f32.
+/// Instead widen each operand to a v8bf16 vector, perform the legal packed
+/// operation, and extract the low element afterwards.
+///
+/// Each operand is reinterpreted as f16 before building the vector. bf16 has no
+/// scalar register class of its own, but f16 does (FR16X), and bf16/f16 share
+/// the same bits and vector register class (VR128X).
+///
+/// Returns a bf16-typed value.
+static SDValue LowerScalarBF16ArithViaVector(SDNode *N, SelectionDAG &DAG) {
----------------
phoebewang wrote:

I think we can move the code into ReplaceNodeResults like others. The code is simple and the function cannot be reused by other types, nor other nodes of BF16.

https://github.com/llvm/llvm-project/pull/212245