[llvm] [AArch64] Mark GPR64arg register class as non-allocatable (PR #212457)

[Matt Arsenault via llvm-commits]

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@@ -425,14 +429,14 @@ bool InlineAsmLowering::lowerInlineAsm(
         // We need the tied input to live in the same register class as the def.
         //
         // - if Def is a vreg, we can just use its regclass.
-        // - if Def is a physreg, create a vreg in the minimal regclass for that
-        //   physreg.
+        // - if Def is a physreg, create a vreg in the regclass selected for its
+        //   constraint.
         //
         // Otherwise RegBankSelect may leave it in the wrong bank (e.g. GPR even
         // though it's tied to an FP physreg).
-        const TargetRegisterClass *RC = Def.isVirtual()
-                                            ? MRI->getRegClass(Def)
-                                            : TRI->getMinimalPhysRegClass(Def);
+        const TargetRegisterClass *RC =
+            Def.isVirtual() ? MRI->getRegClass(Def) : OpInfo.RegClass;
+        assert(RC && "Expected a register class for matching constraint");
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arsenm wrote:

OK, in that case it's not necessary. getRegistersForValue should trivially return an allocatable class 

https://github.com/llvm/llvm-project/pull/212457