[llvm] 9cd13c1 - [X86] Remove TuningFastSHLDRotate from BMI2 targets (#211217)
via llvm-commits
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Wed Jul 29 01:22:06 PDT 2026
Author: 222rohan
Date: 2026-07-29T13:52:01+05:30
New Revision: 9cd13c11bacc9a5b83640a7168ab0f51160e4ee0
URL: https://github.com/llvm/llvm-project/commit/9cd13c11bacc9a5b83640a7168ab0f51160e4ee0
DIFF: https://github.com/llvm/llvm-project/commit/9cd13c11bacc9a5b83640a7168ab0f51160e4ee0.diff
LOG: [X86] Remove TuningFastSHLDRotate from BMI2 targets (#211217)
This flag has no effect at `x86-64-v3` or `v4`. It only enables a pseudo
that lowers `rotl`/`rotr` by immediate to `shld $imm, %reg, %reg`, but a
higher-priority `RORX` pattern matches the same case and always wins the
iSel tie.
Both patterns match `rotl(GR64, imm)`; only their `AddedComplexity`
differs:
```
// X86InstrShiftRotate.td:507 -- SHLD-rotate pseudo, complexity 5
let Predicates = [HasFastSHLDRotate], AddedComplexity = 5, ... in {
def SHLDROT64ri : ... [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$shamt)))]>;
}
// X86InstrShiftRotate.td:602 -- RORX pattern, complexity 10, only needs BMI2
let AddedComplexity = 10 in {
def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
(RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
}
```
LLVM's iSel always picks `RORX`, and it only requires BMI2, which is
part of `x86-64-v3` and up, so it is picked unconditionally on every
v3/v4 build regardless of `TuningFastSHLDRotate`.
No codegen change; existing lit tests unaffected.
Added:
Modified:
llvm/lib/Target/X86/X86.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index ab27fb0b6aa10..f40b937efa74b 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -983,7 +983,6 @@ def ProcessorFeatures {
TuningSlow3OpsLEA,
TuningSlowDivide64,
TuningFastScalarFSQRT,
- TuningFastSHLDRotate,
TuningFast15ByteNOP,
TuningFastVariableCrossLaneShuffle,
TuningFastVariablePerLaneShuffle,
@@ -1006,7 +1005,6 @@ def ProcessorFeatures {
TuningSlowDivide64,
TuningFastScalarFSQRT,
TuningFastVectorFSQRT,
- TuningFastSHLDRotate,
TuningFast15ByteNOP,
TuningFastVariableCrossLaneShuffle,
TuningFastVariablePerLaneShuffle,
@@ -1068,7 +1066,6 @@ def ProcessorFeatures {
TuningSlow3OpsLEA,
TuningSlowDivide64,
TuningFastScalarFSQRT,
- TuningFastSHLDRotate,
TuningFast15ByteNOP,
TuningFastVariableCrossLaneShuffle,
TuningFastVariablePerLaneShuffle,
@@ -1101,7 +1098,6 @@ def ProcessorFeatures {
TuningSlowDivide64,
TuningFastScalarFSQRT,
TuningFastVectorFSQRT,
- TuningFastSHLDRotate,
TuningFast15ByteNOP,
TuningFastVariableCrossLaneShuffle,
TuningFastVariablePerLaneShuffle,
@@ -1132,7 +1128,6 @@ def ProcessorFeatures {
TuningSlowDivide64,
TuningFastScalarFSQRT,
TuningFastVectorFSQRT,
- TuningFastSHLDRotate,
TuningFast15ByteNOP,
TuningFastVariableCrossLaneShuffle,
TuningFastVariablePerLaneShuffle,
@@ -1176,7 +1171,6 @@ def ProcessorFeatures {
TuningSlowDivide64,
TuningFastScalarFSQRT,
TuningFastVectorFSQRT,
- TuningFastSHLDRotate,
TuningFast15ByteNOP,
TuningFastVariableCrossLaneShuffle,
TuningFastVariablePerLaneShuffle,
@@ -1206,7 +1200,6 @@ def ProcessorFeatures {
TuningSlowDivide64,
TuningFastScalarFSQRT,
TuningFastVectorFSQRT,
- TuningFastSHLDRotate,
TuningFast15ByteNOP,
TuningFastVariableCrossLaneShuffle,
TuningFastVariablePerLaneShuffle,
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