[llvm] [AMDGPU] Gate TBUFFER merging on relaxed OOB mode (PR #212695)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 28 23:59:22 PDT 2026
https://github.com/harrisonGPU created https://github.com/llvm/llvm-project/pull/212695
SILoadStoreOptimizer can combine adjacent TBUFFER accesses into a wider
typed buffer instruction. This changes the granularity of hardware OOB
handling and may affect neighboring components when an access is partially
out of bounds.
Only allow TBUFFER load/store merging when
`amdgpu.tbuffer.oob.mode` is set to relaxed. Keep the accesses separate when
the flag is absent, any, or strict to preserve strict OOB semantics.
Reference: https://github.com/llvm/llvm-project/pull/160922
>From 7c08016eda084dfa687bfb74d6022ea03f1a2c9c Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Wed, 29 Jul 2026 14:41:14 +0800
Subject: [PATCH] [AMDGPU] Gate TBUFFER merging on relaxed OOB mode
---
.../Target/AMDGPU/SILoadStoreOptimizer.cpp | 6 ++
.../CodeGen/AMDGPU/merge-tbuffer-gfx10.mir | 56 ++++++++++++++
.../CodeGen/AMDGPU/merge-tbuffer-gfx11.mir | 75 +++++++++++++++++++
.../CodeGen/AMDGPU/merge-tbuffer-gfx12.mir | 56 ++++++++++++++
.../CodeGen/AMDGPU/merge-tbuffer-gfx9.mir | 57 ++++++++++++++
5 files changed, 250 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 897be1d6739e1..3f6371029c444 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -2670,6 +2670,12 @@ SILoadStoreOptimizer::collectMergeableInsts(
continue;
if (InstClass == TBUFFER_LOAD || InstClass == TBUFFER_STORE) {
+ if (!STM->hasRelaxedTBufferOOBMode()) {
+ LLVM_DEBUG(
+ dbgs() << "Skip tbuffer combine: relaxed OOB mode not enabled\n");
+ continue;
+ }
+
const MachineOperand *Fmt =
TII->getNamedOperand(MI, AMDGPU::OpName::format);
if (!AMDGPU::getGcnBufferFormatInfo(Fmt->getImm(), *STM)) {
diff --git a/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir b/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
index e983b74b1ae65..ef568d1bf5e15 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
+++ b/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx10.mir
@@ -1,6 +1,62 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgpu10.10 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX10 %s
+--- |
+ define void @gfx10_tbuffer_load_x_xyz() { entry: ret void }
+ define void @gfx10_tbuffer_load_xyz_x() { entry: ret void }
+ define void @gfx10_tbuffer_load_xy_xy() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_xy() { entry: ret void }
+ define void @gfx10_tbuffer_load_xy_x() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_x() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_x_format_32_32_32_32() { entry: ret void }
+ define void @gfx10_tbuffer_load_float_32() { entry: ret void }
+ define void @gfx10_tbuffer_load_sint_32() { entry: ret void }
+ define void @gfx10_tbuffer_load_uint_32() { entry: ret void }
+ define void @gfx10_tbuffer_load_not_merged_data_format_mismatch() { entry: ret void }
+ define void @gfx10_tbuffer_load_not_merged_num_format_mismatch() { entry: ret void }
+ define void @gfx10_tbuffer_store_x_xyz() { entry: ret void }
+ define void @gfx10_tbuffer_store_xyz_x() { entry: ret void }
+ define void @gfx10_tbuffer_store_xy_xy() { entry: ret void }
+ define void @gfx10_tbuffer_store_x_xy() { entry: ret void }
+ define void @gfx10_tbuffer_store_xy_x() { entry: ret void }
+ define void @gfx10_tbuffer_store_x_x() { entry: ret void }
+ define void @gfx10_tbuffer_store_x_x_format_32_32_32_32() { entry: ret void }
+ define void @gfx10_tbuffer_store_float32() { entry: ret void }
+ define void @gfx10_tbuffer_store_sint32() { entry: ret void }
+ define void @gfx10_tbuffer_store_uint32() { entry: ret void }
+ define void @gfx10_tbuffer_store_not_merged_data_format_mismatch() { entry: ret void }
+ define void @gfx10_tbuffer_store_not_merged_num_format_mismatch() { entry: ret void }
+ define void @gfx10_tbuffer_load_not_merged_swizzled_0() { entry: ret void }
+ define void @gfx10_tbuffer_load_not_merged_swizzled_1() { entry: ret void }
+ define void @gfx10_tbuffer_load_merge_across_swizzle() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_x_idxen() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_xy_idxen() { entry: ret void }
+ define void @gfx10_tbuffer_load_xy_xy_idxen() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_xyz_idxen() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_x_x_idxen_exact() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_x_x_idxen_exact_swizzled_0() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_x_bothen() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_xy_bothen() { entry: ret void }
+ define void @gfx10_tbuffer_load_xy_xy_bothen() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_xyz_bothen() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_x_idxen_exact() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_xy_idxen_exact() { entry: ret void }
+ define void @gfx10_tbuffer_load_xy_xy_idxen_exact() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_xyz_idxen_exact() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_x_bothen_exact() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_xy_bothen_exact() { entry: ret void }
+ define void @gfx10_tbuffer_load_xy_xy_bothen_exact() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_xyz_bothen_exact() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_x_x_bothen_exact() { entry: ret void }
+ define void @gfx10_tbuffer_load_x_x_x_bothen_exact_swizzled_0() { entry: ret void }
+ define void @gfx10_tbuffer_load_xy_xy_bothen_exact_diff_vaddr() { entry: ret void }
+ define void @gfx10_tbuffer_load_xy_xy_bothen_exact_diff_srsrc() { entry: ret void }
+ define void @gfx10_tbuffer_load_xy_xy_idxen_exact_diff_vaddr() { entry: ret void }
+ define void @gfx10_tbuffer_load_xy_xy_idxen_exact_diff_srsrc() { entry: ret void }
+
+ !llvm.module.flags = !{!0}
+ !0 = !{i32 7, !"amdgpu.tbuffer.oob.mode", i32 1}
+...
---
name: gfx10_tbuffer_load_x_xyz
body: |
diff --git a/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir b/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
index f07931f088b02..0d75c368b1ecc 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
+++ b/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx11.mir
@@ -1,6 +1,81 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=amdgpu11.00 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX11 %s
+--- |
+ define void @gfx11_tbuffer_load_x_xyz() { entry: ret void }
+ define void @gfx11_tbuffer_load_xyz_x() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_xy() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_x() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_format_32_32_32_32() { entry: ret void }
+ define void @gfx11_tbuffer_load_float_32() { entry: ret void }
+ define void @gfx11_tbuffer_load_sint_32() { entry: ret void }
+ define void @gfx11_tbuffer_load_uint_32() { entry: ret void }
+ define void @gfx11_tbuffer_load_not_merged_data_format_mismatch() { entry: ret void }
+ define void @gfx11_tbuffer_load_not_merged_num_format_mismatch() { entry: ret void }
+ define void @gfx11_tbuffer_store_x_xyz() { entry: ret void }
+ define void @gfx11_tbuffer_store_xyz_x() { entry: ret void }
+ define void @gfx11_tbuffer_store_xy_xy() { entry: ret void }
+ define void @gfx11_tbuffer_store_x_xy() { entry: ret void }
+ define void @gfx11_tbuffer_store_xy_x() { entry: ret void }
+ define void @gfx11_tbuffer_store_x_x() { entry: ret void }
+ define void @gfx11_tbuffer_store_x_x_format_32_32_32_32() { entry: ret void }
+ define void @gfx11_tbuffer_store_float32() { entry: ret void }
+ define void @gfx11_tbuffer_store_sint32() { entry: ret void }
+ define void @gfx11_tbuffer_store_uint32() { entry: ret void }
+ define void @gfx11_tbuffer_store_not_merged_data_format_mismatch() { entry: ret void }
+ define void @gfx11_tbuffer_store_not_merged_num_format_mismatch() { entry: ret void }
+ define void @gfx11_tbuffer_load_not_merged_swizzled_0() { entry: ret void }
+ define void @gfx11_tbuffer_load_not_merged_swizzled_1() { entry: ret void }
+ define void @gfx11_tbuffer_load_merge_across_swizzle() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_idxen() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_xy_idxen() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_idxen() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_xyz_idxen() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_bothen() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_xy_bothen() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_bothen() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_xyz_bothen() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_idxen_exact() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_xy_idxen_exact() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_idxen_exact() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_xyz_idxen_exact() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_x_idxen_exact() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_x_idxen_exact_swizzled_0() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_bothen_exact() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_xy_bothen_exact() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_bothen_exact() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_xyz_bothen_exact() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_bothen_exact_diff_vaddr() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_bothen_exact_diff_srsrc() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_idxen_exact_diff_vaddr() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_idxen_exact_diff_srsrc() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_x_bothen_exact() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_x_bothen_exact_swizzled_0() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_x_idxen_16bit() { entry: ret void }
+ define void @gfx11_tbuffer_load_idxen_16_bit() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_idxen_uint_16_bit() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_idxen_sint_16_bit() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_off2_off4_16bit_no_merge() { entry: ret void }
+ define void @gfx11_tbuffer_store_x_x_x_idxen_16_bit() { entry: ret void }
+ define void @gfx11_tbuffer_store_idxen_16_bit() { entry: ret void }
+ define void @gfx11_tbuffer_store_xy_xy_uint_16_bit() { entry: ret void }
+ define void @gfx11_tbuffer_store_xy_xy_sint_16_bit() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_x_x_idxen_8bit() { entry: ret void }
+ define void @gfx11_tbuffer_load_idxen_8bit() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_idxen_uint_8bit() { entry: ret void }
+ define void @gfx11_tbuffer_load_xy_xy_idxen_sint_8bit() { entry: ret void }
+ define void @gfx11_tbuffer_load_x_off3_off4_8bit_no_merge() { entry: ret void }
+ define void @gfx11_tbuffer_store_x_x_x_idxen_8bit() { entry: ret void }
+ define void @gfx11_tbuffer_store_idxen_8bit() { entry: ret void }
+ define void @gfx11_tbuffer_store_xy_xy_idxen_uint_8bit() { entry: ret void }
+ define void @gfx11_tbuffer_store_xy_xy_idxen_sint_8bit() { entry: ret void }
+ define void @gfx11_tbuffer_store_x_off3_off4_8bit_no_merge() { entry: ret void }
+
+ !llvm.module.flags = !{!0}
+ !0 = !{i32 7, !"amdgpu.tbuffer.oob.mode", i32 1}
+...
---
name: gfx11_tbuffer_load_x_xyz
body: |
diff --git a/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir b/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
index aeed14126f50c..de814ed2bdc2f 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
+++ b/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx12.mir
@@ -1,6 +1,62 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=amdgpu12.00 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX12 %s
+--- |
+ define void @gfx12_tbuffer_load_x_xyz() { entry: ret void }
+ define void @gfx12_tbuffer_load_xyz_x() { entry: ret void }
+ define void @gfx12_tbuffer_load_xy_xy() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_xy() { entry: ret void }
+ define void @gfx12_tbuffer_load_xy_x() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_x() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_x_format_32_32_32_32() { entry: ret void }
+ define void @gfx12_tbuffer_load_float_32() { entry: ret void }
+ define void @gfx12_tbuffer_load_sint_32() { entry: ret void }
+ define void @gfx12_tbuffer_load_uint_32() { entry: ret void }
+ define void @gfx12_tbuffer_load_not_merged_data_format_mismatch() { entry: ret void }
+ define void @gfx12_tbuffer_load_not_merged_num_format_mismatch() { entry: ret void }
+ define void @gfx12_tbuffer_store_x_xyz() { entry: ret void }
+ define void @gfx12_tbuffer_store_xyz_x() { entry: ret void }
+ define void @gfx12_tbuffer_store_xy_xy() { entry: ret void }
+ define void @gfx12_tbuffer_store_x_xy() { entry: ret void }
+ define void @gfx12_tbuffer_store_xy_x() { entry: ret void }
+ define void @gfx12_tbuffer_store_x_x() { entry: ret void }
+ define void @gfx12_tbuffer_store_x_x_format_32_32_32_32() { entry: ret void }
+ define void @gfx12_tbuffer_store_float32() { entry: ret void }
+ define void @gfx12_tbuffer_store_sint32() { entry: ret void }
+ define void @gfx12_tbuffer_store_uint32() { entry: ret void }
+ define void @gfx12_tbuffer_store_not_merged_data_format_mismatch() { entry: ret void }
+ define void @gfx12_tbuffer_store_not_merged_num_format_mismatch() { entry: ret void }
+ define void @gfx12_tbuffer_load_not_merged_swizzled_0() { entry: ret void }
+ define void @gfx12_tbuffer_load_not_merged_swizzled_1() { entry: ret void }
+ define void @gfx12_tbuffer_load_merge_across_swizzle() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_x_idxen() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_xy_idxen() { entry: ret void }
+ define void @gfx12_tbuffer_load_xy_xy_idxen() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_xyz_idxen() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_x_bothen() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_xy_bothen() { entry: ret void }
+ define void @gfx12_tbuffer_load_xy_xy_bothen() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_xyz_bothen() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_x_idxen_exact() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_xy_idxen_exact() { entry: ret void }
+ define void @gfx12_tbuffer_load_xy_xy_idxen_exact() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_xyz_idxen_exact() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_x_x_idxen_exact() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_x_x_idxen_exact_swizzled_0() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_x_bothen_exact() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_xy_bothen_exact() { entry: ret void }
+ define void @gfx12_tbuffer_load_xy_xy_bothen_exact() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_xyz_bothen_exact() { entry: ret void }
+ define void @gfx12_tbuffer_load_xy_xy_bothen_exact_diff_vaddr() { entry: ret void }
+ define void @gfx12_tbuffer_load_xy_xy_bothen_exact_diff_srsrc() { entry: ret void }
+ define void @gfx12_tbuffer_load_xy_xy_idxen_exact_diff_vaddr() { entry: ret void }
+ define void @gfx12_tbuffer_load_xy_xy_idxen_exact_diff_srsrc() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_x_x_bothen_exact() { entry: ret void }
+ define void @gfx12_tbuffer_load_x_x_x_bothen_exact_swizzled_0() { entry: ret void }
+
+ !llvm.module.flags = !{!0}
+ !0 = !{i32 7, !"amdgpu.tbuffer.oob.mode", i32 1}
+...
---
name: gfx12_tbuffer_load_x_xyz
body: |
diff --git a/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir b/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
index 076b735ad6719..c11d4861c5b0d 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
+++ b/llvm/test/CodeGen/AMDGPU/merge-tbuffer-gfx9.mir
@@ -1,6 +1,63 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX9 %s
+--- |
+ define void @gfx9_tbuffer_load_x_xyz() { entry: ret void }
+ define void @gfx9_tbuffer_load_xyz_x() { entry: ret void }
+ define void @gfx9_tbuffer_load_xy_xy() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_xy() { entry: ret void }
+ define void @gfx9_tbuffer_load_xy_x() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_x() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_x_format_32_32_32_32() { entry: ret void }
+ define void @gfx9_tbuffer_load_float_32() { entry: ret void }
+ define void @gfx9_tbuffer_load_sint_32() { entry: ret void }
+ define void @gfx9_tbuffer_load_uint_32() { entry: ret void }
+ define void @gfx9_tbuffer_load_not_merged_data_format_mismatch() { entry: ret void }
+ define void @gfx9_tbuffer_load_not_merged_num_format_mismatch() { entry: ret void }
+ define void @gfx9_tbuffer_store_x_xyz() { entry: ret void }
+ define void @gfx9_tbuffer_store_xyz_x() { entry: ret void }
+ define void @gfx9_tbuffer_store_xy_xy() { entry: ret void }
+ define void @gfx9_tbuffer_store_x_xy() { entry: ret void }
+ define void @gfx9_tbuffer_store_xy_x() { entry: ret void }
+ define void @gfx9_tbuffer_store_x_x() { entry: ret void }
+ define void @gfx9_tbuffer_store_x_x_format_32_32_32_32() { entry: ret void }
+ define void @gfx9_tbuffer_store_float32() { entry: ret void }
+ define void @gfx9_tbuffer_store_sint32() { entry: ret void }
+ define void @gfx9_tbuffer_store_uint32() { entry: ret void }
+ define void @gfx9_tbuffer_store_not_merged_data_format_mismatch() { entry: ret void }
+ define void @gfx9_tbuffer_store_not_merged_num_format_mismatch() { entry: ret void }
+ define void @gfx9_tbuffer_load_not_merged_swizzled_0() { entry: ret void }
+ define void @gfx9_tbuffer_load_not_merged_swizzled_1() { entry: ret void }
+ define void @gfx9_tbuffer_load_merge_across_swizzle() { entry: ret void }
+ define void @gfx9_tbuffer_load_merge_across_swizzled_store() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_x_idxen() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_xy_idxen() { entry: ret void }
+ define void @gfx9_tbuffer_load_xy_xy_idxen() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_xyz_idxen() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_x_bothen() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_xy_bothen() { entry: ret void }
+ define void @gfx9_tbuffer_load_xy_xy_bothen() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_xyz_bothen() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_x_idxen_exact() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_xy_idxen_exact() { entry: ret void }
+ define void @gfx9_tbuffer_load_xy_xy_idxen_exact() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_xyz_idxen_exact() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_x_x_idxen_exact() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_x_x_idxen_exact_swizzled_0() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_x_bothen_exact() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_xy_bothen_exact() { entry: ret void }
+ define void @gfx9_tbuffer_load_xy_xy_bothen_exact() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_xyz_bothen_exact() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_x_x_bothen_exact() { entry: ret void }
+ define void @gfx9_tbuffer_load_x_x_x_bothen_exact_swizzled_0() { entry: ret void }
+ define void @gfx9_tbuffer_load_xy_xy_bothen_exact_diff_vaddr() { entry: ret void }
+ define void @gfx9_tbuffer_load_xy_xy_bothen_exact_diff_srsrc() { entry: ret void }
+ define void @gfx9_tbuffer_load_xy_xy_idxen_exact_diff_vaddr() { entry: ret void }
+ define void @gfx9_tbuffer_load_xy_xy_idxen_exact_diff_srsrc() { entry: ret void }
+
+ !llvm.module.flags = !{!0}
+ !0 = !{i32 7, !"amdgpu.tbuffer.oob.mode", i32 1}
+...
---
name: gfx9_tbuffer_load_x_xyz
body: |
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