[llvm] [RISCV] Deduplicate frame base address materializations for large stack frames (PR #211748)
Yingying Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 28 23:24:25 PDT 2026
https://github.com/buggfg updated https://github.com/llvm/llvm-project/pull/211748
>From a266120b6de7464da9c4d5c6c5fd46cf5ee7b573 Mon Sep 17 00:00:00 2001
From: buggfg <3171290993 at qq.com>
Date: Tue, 28 Jul 2026 10:20:25 +0800
Subject: [PATCH 1/2] [RISCV][test] Add test for large stack-frame base address
materialization (NFC)
---
.../CodeGen/RISCV/frame-base-addr-reuse.mir | 178 ++++++++++++++++++
1 file changed, 178 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
diff --git a/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir b/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
new file mode 100644
index 0000000000000..7363ec8b73f92
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
@@ -0,0 +1,178 @@
+# REQUIRES: asserts
+#
+# RUN: llc -mtriple=riscv64 \
+# RUN: -run-pass=prolog-epilog -run-pass=machine-latecleanup -o - %s \
+# RUN: | FileCheck -check-prefix=RV64 %s
+# RUN: llc -mtriple=riscv64 \
+# RUN: -run-pass=prolog-epilog -run-pass=machine-latecleanup \
+# RUN: -run-pass=riscv-post-ra-expand-pseudo -o - %s \
+# RUN: | FileCheck -check-prefix=RV64-EXPAND %s
+# RUN: llc -mtriple=riscv32 \
+# RUN: -run-pass=prolog-epilog -run-pass=machine-latecleanup -o - %s \
+# RUN: | FileCheck -check-prefix=RV32 %s
+#
+# Test codegen for large stack-frame base address materializations.
+
+--- |
+ define void @test_same_region() nounwind { ret void }
+ define void @test_different_regions() nounwind { ret void }
+ define void @test_small_offset_no_pseudo() nounwind { ret void }
+ define void @test_rv32() nounwind { ret void }
+...
+---
+# Multiple accesses to stack slots in the same 4096-aligned region.
+# Each access independently materializes LUI+ADD to the same base.
+name: test_same_region
+alignment: 4
+tracksRegLiveness: true
+frameInfo:
+ maxAlignment: 8
+ hasCalls: false
+ maxCallFrameSize: 0
+stack:
+ - { id: 0, size: 8, alignment: 8 }
+ - { id: 1, size: 8, alignment: 8 }
+ - { id: 2, size: 16384, alignment: 8 }
+body: |
+ bb.0:
+ liveins: $x10, $x11
+
+ ; RV64-LABEL: name: test_same_region
+ ; RV64: $x12 = LUI 4
+ ; RV64-NEXT: $x12 = ADD $x2, killed $x12
+ ; RV64-NEXT: SD $x10, killed $x12, 24 :: (store (s64))
+ ; RV64-NEXT: $x10 = LUI 4
+ ; RV64-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-NEXT: SD $x11, killed $x10, 16 :: (store (s64))
+ ; RV64-NEXT: $x10 = LUI 4
+ ; RV64-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-NEXT: $x12 = LD killed $x10, 24 :: (load (s64))
+ ; RV64-NEXT: $x10 = LUI 4
+ ; RV64-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-NEXT: $x13 = LD killed $x10, 16 :: (load (s64))
+
+ ; RV64-EXPAND-LABEL: name: test_same_region
+ ; RV64-EXPAND: $x12 = LUI 4
+ ; RV64-EXPAND-NEXT: $x12 = ADD $x2, killed $x12
+ ; RV64-EXPAND-NEXT: SD $x10, killed $x12, 24 :: (store (s64))
+ ; RV64-EXPAND-NEXT: $x10 = LUI 4
+ ; RV64-EXPAND-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-EXPAND-NEXT: SD $x11, killed $x10, 16 :: (store (s64))
+ ; RV64-EXPAND-NEXT: $x10 = LUI 4
+ ; RV64-EXPAND-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-EXPAND-NEXT: $x12 = LD killed $x10, 24 :: (load (s64))
+ ; RV64-EXPAND-NEXT: $x10 = LUI 4
+ ; RV64-EXPAND-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-EXPAND-NEXT: $x13 = LD killed $x10, 16 :: (load (s64))
+
+ SD $x10, %stack.0, 0 :: (store (s64))
+ SD $x11, %stack.1, 0 :: (store (s64))
+ $x12 = LD %stack.0, 0 :: (load (s64))
+ $x13 = LD %stack.1, 0 :: (load (s64))
+ PseudoRET
+...
+---
+# Accesses to stack slots in different 4096-aligned regions.
+name: test_different_regions
+alignment: 4
+tracksRegLiveness: true
+frameInfo:
+ maxAlignment: 8
+ hasCalls: false
+ maxCallFrameSize: 0
+stack:
+ - { id: 0, size: 8, alignment: 8 }
+ - { id: 1, size: 4096, alignment: 8 }
+ - { id: 2, size: 8, alignment: 8 }
+ - { id: 3, size: 16384, alignment: 8 }
+body: |
+ bb.0:
+ liveins: $x10, $x11
+
+ ; RV64-LABEL: name: test_different_regions
+ ; RV64: $x12 = LUI 5
+ ; RV64-NEXT: $x12 = ADD $x2, killed $x12
+ ; RV64-NEXT: SD $x10, killed $x12, 24 :: (store (s64))
+ ; RV64-NEXT: $x10 = LUI 4
+ ; RV64-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-NEXT: SD $x11, killed $x10, 16 :: (store (s64))
+
+ ; RV64-EXPAND-LABEL: name: test_different_regions
+ ; RV64-EXPAND: $x12 = LUI 5
+ ; RV64-EXPAND-NEXT: $x12 = ADD $x2, killed $x12
+ ; RV64-EXPAND-NEXT: SD $x10, killed $x12, 24 :: (store (s64))
+ ; RV64-EXPAND-NEXT: $x10 = LUI 4
+ ; RV64-EXPAND-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-EXPAND-NEXT: SD $x11, killed $x10, 16 :: (store (s64))
+
+ SD $x10, %stack.0, 0 :: (store (s64))
+ SD $x11, %stack.2, 0 :: (store (s64))
+ PseudoRET
+...
+---
+# Small stack frame -- offsets fit in 12-bit signed immediate.
+name: test_small_offset_no_pseudo
+alignment: 4
+tracksRegLiveness: true
+frameInfo:
+ maxAlignment: 8
+ hasCalls: false
+ maxCallFrameSize: 0
+stack:
+ - { id: 0, size: 8, alignment: 8 }
+ - { id: 1, size: 8, alignment: 8 }
+body: |
+ bb.0:
+ liveins: $x10, $x11
+
+ ; RV64-LABEL: name: test_small_offset_no_pseudo
+ ; RV64-NOT: LUI
+ ; RV64: SD $x10, $x2, 8 :: (store (s64))
+ ; RV64-NEXT: SD $x11, $x2, 0 :: (store (s64))
+
+ ; RV64-EXPAND-LABEL: name: test_small_offset_no_pseudo
+ ; RV64-EXPAND-NOT: LUI
+ ; RV64-EXPAND: SD $x10, $x2, 8 :: (store (s64))
+ ; RV64-EXPAND-NEXT: SD $x11, $x2, 0 :: (store (s64))
+
+ SD $x10, %stack.0, 0 :: (store (s64))
+ SD $x11, %stack.1, 0 :: (store (s64))
+ PseudoRET
+...
+---
+# RV32 -- verify with 32-bit stores/loads.
+name: test_rv32
+alignment: 4
+tracksRegLiveness: true
+frameInfo:
+ maxAlignment: 4
+ hasCalls: false
+ maxCallFrameSize: 0
+stack:
+ - { id: 0, size: 4, alignment: 4 }
+ - { id: 1, size: 4, alignment: 4 }
+ - { id: 2, size: 16384, alignment: 4 }
+body: |
+ bb.0:
+ liveins: $x10, $x11
+
+ ; RV32-LABEL: name: test_rv32
+ ; RV32: $x12 = LUI 4
+ ; RV32-NEXT: $x12 = ADD $x2, killed $x12
+ ; RV32-NEXT: SW $x10, killed $x12, 12 :: (store (s32))
+ ; RV32-NEXT: $x10 = LUI 4
+ ; RV32-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV32-NEXT: SW $x11, killed $x10, 8 :: (store (s32))
+ ; RV32-NEXT: $x10 = LUI 4
+ ; RV32-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV32-NEXT: $x12 = LW killed $x10, 12 :: (load (s32))
+ ; RV32-NEXT: $x10 = LUI 4
+ ; RV32-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV32-NEXT: $x13 = LW killed $x10, 8 :: (load (s32))
+
+ SW $x10, %stack.0, 0 :: (store (s32))
+ SW $x11, %stack.1, 0 :: (store (s32))
+ $x12 = LW %stack.0, 0 :: (load (s32))
+ $x13 = LW %stack.1, 0 :: (load (s32))
+ PseudoRET
+...
>From 852966db3a89658fb41531726d3b71bd6df3fc40 Mon Sep 17 00:00:00 2001
From: buggfg <3171290993 at qq.com>
Date: Tue, 28 Jul 2026 10:30:32 +0800
Subject: [PATCH 2/2] [RISCV] Deduplicate large stack-frame base address
materializations
Wrap the LUI+ADD sequence for large frame base addresses into a single
PseudoFrameBaseAddr so that MachineLateInstrsCleanup can CSE identical
anchors within a basic block. The pseudo is expanded back to LUI+ADD by
RISCVPostRAExpandPseudo.
---
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 8 +++
.../RISCV/RISCVPostRAExpandPseudoInsts.cpp | 28 ++++++++++
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 12 +++++
llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll | 16 ------
.../CodeGen/RISCV/frame-base-addr-reuse.mir | 52 +++++++------------
.../riscv-scavenge-crash-2nd-pass-rv32.mir | 6 +--
llvm/test/CodeGen/RISCV/vararg.ll | 30 -----------
llvm/test/CodeGen/RISCV/zdinx-large-spill.mir | 4 --
8 files changed, 69 insertions(+), 87 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index e10ee7389db0e..aeed53c06bb29 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1918,6 +1918,14 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8,
def PseudoMovImm : Pseudo<(outs GPR:$dst), (ins i32imm:$imm), []>,
Sched<[WriteIALU]>;
+// Materializes "$base + (imm << 12)" as a single pseudo so that
+// MachineLateInstrsCleanup can CSE identical upper-immediate additions.
+// Expanded to LUI+ADD by RISCVPostRAExpandPseudo.
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8 in
+def PseudoAddUI
+ : Pseudo<(outs GPR:$dst), (ins GPR:$base, uimm20_lui:$hi), []>,
+ Sched<[WriteIALU, ReadIALU]>;
+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8,
isCodeGenOnly = 0 in
def PseudoLLA : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
diff --git a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
index 7fe67e3fb8ea0..51e3792b14fd1 100644
--- a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
@@ -44,6 +44,8 @@ class RISCVPostRAExpandPseudo : public MachineFunctionPass {
bool expandMovImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
bool expandMovAddr(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
bool expandMERGE(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
+ bool expandAddUI(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI);
};
char RISCVPostRAExpandPseudo::ID = 0;
@@ -77,6 +79,8 @@ bool RISCVPostRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
return expandMovImm(MBB, MBBI);
case RISCV::PseudoMovAddr:
return expandMovAddr(MBB, MBBI);
+ case RISCV::PseudoAddUI:
+ return expandAddUI(MBB, MBBI);
case RISCV::PseudoMERGE:
return expandMERGE(MBB, MBBI);
default:
@@ -121,6 +125,30 @@ bool RISCVPostRAExpandPseudo::expandMovAddr(MachineBasicBlock &MBB,
return true;
}
+bool RISCVPostRAExpandPseudo::expandAddUI(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
+ DebugLoc DL = MBBI->getDebugLoc();
+
+ Register DstReg = MBBI->getOperand(0).getReg();
+ bool DstIsDead = MBBI->getOperand(0).isDead();
+ bool Renamable = MBBI->getOperand(0).isRenamable();
+ Register BaseReg = MBBI->getOperand(1).getReg();
+ int64_t Hi = MBBI->getOperand(2).getImm();
+
+ // Expand to LUI+ADD: the immediate is already the upper 20-bit value.
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::LUI))
+ .addReg(DstReg, RegState::Define | getRenamableRegState(Renamable))
+ .addImm(Hi);
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD))
+ .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead) |
+ getRenamableRegState(Renamable))
+ .addReg(BaseReg)
+ .addReg(DstReg, RegState::Kill | getRenamableRegState(Renamable));
+
+ MBBI->eraseFromParent();
+ return true;
+}
+
/// Transfer implicit operands on the pseudo instruction to the
/// instructions created from the expansion.
static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &MI) {
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 7dbdc881ea6c0..e0962f1f6457f 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -437,6 +437,18 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
}
}
+ // Emit a PseudoAddUI instead of LUI+ADD when the offset is a multiple of
+ // 4096 and the source is the frame register. The frame register is invariant
+ // after PEI, so MachineLateInstrsCleanup can CSE identical pseudos. The
+ // pseudo is later expanded back to LUI+ADD.
+ if (Flag == MachineInstr::NoFlags && !KillSrcReg && DestReg != SrcReg &&
+ SrcReg == getFrameRegister(MF) && isInt<32>(Val) && (Val & 0xFFF) == 0) {
+ BuildMI(MBB, II, DL, TII->get(RISCV::PseudoAddUI), DestReg)
+ .addReg(SrcReg)
+ .addImm(static_cast<uint32_t>(Val) >> 12);
+ return;
+ }
+
unsigned Opc = RISCV::ADD;
if (Val < 0) {
Val = -Val;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
index 8f5c126d9e549..2bb48fea434dc 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
@@ -1586,21 +1586,13 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV32-NEXT: lui a1, 24414
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: sw a2, 280(a1)
-; RV32-NEXT: lui a1, 24414
-; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: sw a3, 284(a1)
-; RV32-NEXT: lui a1, 24414
-; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: sw a4, 288(a1)
; RV32-NEXT: addi a1, a0, 4
; RV32-NEXT: lui a2, 24414
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: sw a5, 292(a2)
-; RV32-NEXT: lui a2, 24414
-; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: sw a6, 296(a2)
-; RV32-NEXT: lui a2, 24414
-; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: sw a7, 300(a2)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: lw a0, 0(a0)
@@ -1631,21 +1623,13 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV64-NEXT: lui a1, 24414
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: sd a2, 288(a1)
-; RV64-NEXT: lui a1, 24414
-; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: sd a3, 296(a1)
-; RV64-NEXT: lui a1, 24414
-; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: sd a4, 304(a1)
; RV64-NEXT: addi a1, a0, 4
; RV64-NEXT: lui a2, 24414
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: sd a5, 312(a2)
-; RV64-NEXT: lui a2, 24414
-; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: sd a6, 320(a2)
-; RV64-NEXT: lui a2, 24414
-; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: sd a7, 328(a2)
; RV64-NEXT: srli a2, a1, 32
; RV64-NEXT: sw a1, 8(sp)
diff --git a/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir b/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
index 7363ec8b73f92..ded44e1e071c4 100644
--- a/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
+++ b/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
@@ -11,7 +11,8 @@
# RUN: -run-pass=prolog-epilog -run-pass=machine-latecleanup -o - %s \
# RUN: | FileCheck -check-prefix=RV32 %s
#
-# Test codegen for large stack-frame base address materializations.
+# Test that identical large stack-frame base address materializations are
+# deduplicated by MachineLateInstrsCleanup via PseudoAddUI.
--- |
define void @test_same_region() nounwind { ret void }
@@ -21,7 +22,8 @@
...
---
# Multiple accesses to stack slots in the same 4096-aligned region.
-# Each access independently materializes LUI+ADD to the same base.
+# PEI emits 4 PseudoAddUI, MachineLateInstrsCleanup CSEs to 2.
+# After expansion, only 2 LUI+ADD pairs remain instead of 4.
name: test_same_region
alignment: 4
tracksRegLiveness: true
@@ -38,17 +40,11 @@ body: |
liveins: $x10, $x11
; RV64-LABEL: name: test_same_region
- ; RV64: $x12 = LUI 4
- ; RV64-NEXT: $x12 = ADD $x2, killed $x12
+ ; RV64: $x12 = PseudoAddUI $x2, 4
; RV64-NEXT: SD $x10, killed $x12, 24 :: (store (s64))
- ; RV64-NEXT: $x10 = LUI 4
- ; RV64-NEXT: $x10 = ADD $x2, killed $x10
- ; RV64-NEXT: SD $x11, killed $x10, 16 :: (store (s64))
- ; RV64-NEXT: $x10 = LUI 4
- ; RV64-NEXT: $x10 = ADD $x2, killed $x10
- ; RV64-NEXT: $x12 = LD killed $x10, 24 :: (load (s64))
- ; RV64-NEXT: $x10 = LUI 4
- ; RV64-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-NEXT: $x10 = PseudoAddUI $x2, 4
+ ; RV64-NEXT: SD $x11, $x10, 16 :: (store (s64))
+ ; RV64-NEXT: $x12 = LD $x10, 24 :: (load (s64))
; RV64-NEXT: $x13 = LD killed $x10, 16 :: (load (s64))
; RV64-EXPAND-LABEL: name: test_same_region
@@ -57,12 +53,8 @@ body: |
; RV64-EXPAND-NEXT: SD $x10, killed $x12, 24 :: (store (s64))
; RV64-EXPAND-NEXT: $x10 = LUI 4
; RV64-EXPAND-NEXT: $x10 = ADD $x2, killed $x10
- ; RV64-EXPAND-NEXT: SD $x11, killed $x10, 16 :: (store (s64))
- ; RV64-EXPAND-NEXT: $x10 = LUI 4
- ; RV64-EXPAND-NEXT: $x10 = ADD $x2, killed $x10
- ; RV64-EXPAND-NEXT: $x12 = LD killed $x10, 24 :: (load (s64))
- ; RV64-EXPAND-NEXT: $x10 = LUI 4
- ; RV64-EXPAND-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-EXPAND-NEXT: SD $x11, $x10, 16 :: (store (s64))
+ ; RV64-EXPAND-NEXT: $x12 = LD $x10, 24 :: (load (s64))
; RV64-EXPAND-NEXT: $x13 = LD killed $x10, 16 :: (load (s64))
SD $x10, %stack.0, 0 :: (store (s64))
@@ -73,6 +65,7 @@ body: |
...
---
# Accesses to stack slots in different 4096-aligned regions.
+# Different base anchors cannot be CSE'd with each other.
name: test_different_regions
alignment: 4
tracksRegLiveness: true
@@ -90,11 +83,9 @@ body: |
liveins: $x10, $x11
; RV64-LABEL: name: test_different_regions
- ; RV64: $x12 = LUI 5
- ; RV64-NEXT: $x12 = ADD $x2, killed $x12
+ ; RV64: $x12 = PseudoAddUI $x2, 5
; RV64-NEXT: SD $x10, killed $x12, 24 :: (store (s64))
- ; RV64-NEXT: $x10 = LUI 4
- ; RV64-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV64-NEXT: $x10 = PseudoAddUI $x2, 4
; RV64-NEXT: SD $x11, killed $x10, 16 :: (store (s64))
; RV64-EXPAND-LABEL: name: test_different_regions
@@ -111,6 +102,7 @@ body: |
...
---
# Small stack frame -- offsets fit in 12-bit signed immediate.
+# No PseudoAddUI generated.
name: test_small_offset_no_pseudo
alignment: 4
tracksRegLiveness: true
@@ -126,7 +118,7 @@ body: |
liveins: $x10, $x11
; RV64-LABEL: name: test_small_offset_no_pseudo
- ; RV64-NOT: LUI
+ ; RV64-NOT: PseudoAddUI
; RV64: SD $x10, $x2, 8 :: (store (s64))
; RV64-NEXT: SD $x11, $x2, 0 :: (store (s64))
@@ -157,17 +149,11 @@ body: |
liveins: $x10, $x11
; RV32-LABEL: name: test_rv32
- ; RV32: $x12 = LUI 4
- ; RV32-NEXT: $x12 = ADD $x2, killed $x12
+ ; RV32: $x12 = PseudoAddUI $x2, 4
; RV32-NEXT: SW $x10, killed $x12, 12 :: (store (s32))
- ; RV32-NEXT: $x10 = LUI 4
- ; RV32-NEXT: $x10 = ADD $x2, killed $x10
- ; RV32-NEXT: SW $x11, killed $x10, 8 :: (store (s32))
- ; RV32-NEXT: $x10 = LUI 4
- ; RV32-NEXT: $x10 = ADD $x2, killed $x10
- ; RV32-NEXT: $x12 = LW killed $x10, 12 :: (load (s32))
- ; RV32-NEXT: $x10 = LUI 4
- ; RV32-NEXT: $x10 = ADD $x2, killed $x10
+ ; RV32-NEXT: $x10 = PseudoAddUI $x2, 4
+ ; RV32-NEXT: SW $x11, $x10, 8 :: (store (s32))
+ ; RV32-NEXT: $x12 = LW $x10, 12 :: (load (s32))
; RV32-NEXT: $x13 = LW killed $x10, 8 :: (load (s32))
SW $x10, %stack.0, 0 :: (store (s32))
diff --git a/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir b/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
index dabf65824cc0a..44cb6465dc076 100644
--- a/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
@@ -63,8 +63,7 @@ body: |
; CHECK-NEXT: $x10 = frame-setup ADDI killed $x10, -1168
; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10
; CHECK-NEXT: renamable $x10 = ADDI $x8, -440
- ; CHECK-NEXT: $x11 = LUI 2
- ; CHECK-NEXT: $x11 = SUB $x8, killed $x11
+ ; CHECK-NEXT: $x11 = PseudoAddUI $x8, 1048574
; CHECK-NEXT: $x11 = LW killed $x11, 1420
; CHECK-NEXT: renamable $x12 = LW undef renamable $x10, 1
; CHECK-NEXT: renamable $x13 = LW undef renamable $x10, 9
@@ -92,8 +91,7 @@ body: |
; CHECK-NEXT: renamable $x27 = LW undef renamable $x10, 101
; CHECK-NEXT: renamable $x1 = LW undef renamable $x10, 105
; CHECK-NEXT: SW killed $x11, $x8, -56 :: (store (s32) into %stack.17)
- ; CHECK-NEXT: $x11 = LUI 1
- ; CHECK-NEXT: $x11 = SUB $x8, killed $x11
+ ; CHECK-NEXT: $x11 = PseudoAddUI $x8, 1048575
; CHECK-NEXT: SW $x10, killed $x11, -472
; CHECK-NEXT: $x11 = LW $x8, -56 :: (load (s32) from %stack.17)
; CHECK-NEXT: SW killed renamable $x1, undef renamable $x11, 105
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
index 1e1ff7bb52cda..6e8311b0d81ea 100644
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -2814,17 +2814,11 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; ILP32-ILP32F-FPELIM-NEXT: lui a5, 24414
; ILP32-ILP32F-FPELIM-NEXT: add a5, sp, a5
; ILP32-ILP32F-FPELIM-NEXT: sw a6, 296(a5)
-; ILP32-ILP32F-FPELIM-NEXT: lui a5, 24414
-; ILP32-ILP32F-FPELIM-NEXT: add a5, sp, a5
; ILP32-ILP32F-FPELIM-NEXT: sw a7, 300(a5)
-; ILP32-ILP32F-FPELIM-NEXT: lui a5, 24414
-; ILP32-ILP32F-FPELIM-NEXT: add a5, sp, a5
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 276(a5)
; ILP32-ILP32F-FPELIM-NEXT: lui a1, 24414
; ILP32-ILP32F-FPELIM-NEXT: add a1, sp, a1
; ILP32-ILP32F-FPELIM-NEXT: sw a2, 280(a1)
-; ILP32-ILP32F-FPELIM-NEXT: lui a1, 24414
-; ILP32-ILP32F-FPELIM-NEXT: add a1, sp, a1
; ILP32-ILP32F-FPELIM-NEXT: sw a3, 284(a1)
; ILP32-ILP32F-FPELIM-NEXT: lui a1, 24414
; ILP32-ILP32F-FPELIM-NEXT: addi a1, a1, 280
@@ -2887,17 +2881,11 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a5, 24414
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a5, sp, a5
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a6, 296(a5)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a5, 24414
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a5, sp, a5
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a7, 300(a5)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a5, 24414
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a5, sp, a5
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 276(a5)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a1, 24414
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, sp, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a2, 280(a1)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a1, 24414
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add a1, sp, a1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a3, 284(a1)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a1, 24414
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a1, 280
@@ -2928,8 +2916,6 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; ILP32E-FPELIM-NEXT: lui a1, 24414
; ILP32E-FPELIM-NEXT: add a1, sp, a1
; ILP32E-FPELIM-NEXT: sw a2, 272(a1)
-; ILP32E-FPELIM-NEXT: lui a1, 24414
-; ILP32E-FPELIM-NEXT: add a1, sp, a1
; ILP32E-FPELIM-NEXT: sw a3, 276(a1)
; ILP32E-FPELIM-NEXT: lui a1, 24414
; ILP32E-FPELIM-NEXT: addi a1, a1, 272
@@ -2996,20 +2982,10 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a5, 312(a1)
-; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
-; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a6, 320(a1)
-; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
-; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a7, 328(a1)
-; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
-; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 288(a1)
-; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
-; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 296(a1)
-; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
-; LP64-LP64F-LP64D-FPELIM-NEXT: add a1, sp, a1
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 304(a1)
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 336
@@ -3071,14 +3047,8 @@ define i32 @va_large_stack(ptr %fmt, ...) {
; LP64E-FPELIM-NEXT: lui a1, 24414
; LP64E-FPELIM-NEXT: add a1, sp, a1
; LP64E-FPELIM-NEXT: sd a5, 312(a1)
-; LP64E-FPELIM-NEXT: lui a1, 24414
-; LP64E-FPELIM-NEXT: add a1, sp, a1
; LP64E-FPELIM-NEXT: sd a2, 288(a1)
-; LP64E-FPELIM-NEXT: lui a1, 24414
-; LP64E-FPELIM-NEXT: add a1, sp, a1
; LP64E-FPELIM-NEXT: sd a3, 296(a1)
-; LP64E-FPELIM-NEXT: lui a1, 24414
-; LP64E-FPELIM-NEXT: add a1, sp, a1
; LP64E-FPELIM-NEXT: sd a4, 304(a1)
; LP64E-FPELIM-NEXT: lui a1, 24414
; LP64E-FPELIM-NEXT: addi a1, a1, 320
diff --git a/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir b/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
index 1889ad8924a61..99c0bc4ef0f1f 100644
--- a/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
+++ b/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
@@ -20,8 +20,6 @@
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: sw a2, -2032(a0) # 4-byte Folded Spill
; CHECK-NEXT: sw a3, -2028(a0) # 4-byte Folded Spill
- ; CHECK-NEXT: lui a0, 1
- ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: sw a4, -2040(a0) # 4-byte Folded Spill
; CHECK-NEXT: sw a5, -2036(a0) # 4-byte Folded Spill
; CHECK-NEXT: addi a0, sp, 2044
@@ -35,8 +33,6 @@
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: lw a2, -2032(a0) # 4-byte Folded Reload
; CHECK-NEXT: lw a3, -2028(a0) # 4-byte Folded Reload
- ; CHECK-NEXT: lui a0, 1
- ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: lw a4, -2040(a0) # 4-byte Folded Reload
; CHECK-NEXT: lw a5, -2036(a0) # 4-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 2044
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