[llvm] ab99380 - [X86] Fix redundant zeroing operations when casting ints to FP vectors (#212065)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 28 22:17:16 PDT 2026
Author: AZero13
Date: 2026-07-29T13:17:12+08:00
New Revision: ab993800519301853d4dfebcf4aa454d95938ee4
URL: https://github.com/llvm/llvm-project/commit/ab993800519301853d4dfebcf4aa454d95938ee4
DIFF: https://github.com/llvm/llvm-project/commit/ab993800519301853d4dfebcf4aa454d95938ee4.diff
LOG: [X86] Fix redundant zeroing operations when casting ints to FP vectors (#212065)
Added:
llvm/test/CodeGen/X86/vector-sint-to-fp-zero.ll
llvm/test/CodeGen/X86/vector-uint-to-fp-zero.ll
Modified:
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrSSE.td
llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index f3596b0eb4b68..d2916346e7d33 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -7382,6 +7382,15 @@ def : Pat<(f64 (any_sint_to_fp GR32:$src)),
def : Pat<(f64 (any_sint_to_fp GR64:$src)),
(VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
+def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (f32 (any_sint_to_fp GR32:$src)))))),
+ (VCVTSI2SSZrr_Int (v4f32 (AVX512_128_SET0)), GR32:$src)>;
+def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (f32 (any_sint_to_fp GR64:$src)))))),
+ (VCVTSI642SSZrr_Int (v4f32 (AVX512_128_SET0)), GR64:$src)>;
+def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (f64 (any_sint_to_fp GR32:$src)))))),
+ (VCVTSI2SDZrr_Int (v2f64 (AVX512_128_SET0)), GR32:$src)>;
+def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (f64 (any_sint_to_fp GR64:$src)))))),
+ (VCVTSI642SDZrr_Int (v2f64 (AVX512_128_SET0)), GR64:$src)>;
+
defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd,
WriteCvtI2SS, GR32,
v4f32x_info, i32mem, loadi32,
@@ -7420,6 +7429,15 @@ def : Pat<(f64 (any_uint_to_fp GR32:$src)),
(VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
def : Pat<(f64 (any_uint_to_fp GR64:$src)),
(VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
+
+def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (f32 (any_uint_to_fp GR32:$src)))))),
+ (VCVTUSI2SSZrr_Int (v4f32 (AVX512_128_SET0)), GR32:$src)>;
+def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (f32 (any_uint_to_fp GR64:$src)))))),
+ (VCVTUSI642SSZrr_Int (v4f32 (AVX512_128_SET0)), GR64:$src)>;
+def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (f64 (any_uint_to_fp GR32:$src)))))),
+ (VCVTUSI2SDZrr_Int (v2f64 (AVX512_128_SET0)), GR32:$src)>;
+def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (f64 (any_uint_to_fp GR64:$src)))))),
+ (VCVTUSI642SDZrr_Int (v2f64 (AVX512_128_SET0)), GR64:$src)>;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index fbabffc9a6f98..bf262315d7ea5 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -1156,6 +1156,53 @@ def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
(CVTSI2SDrm_Int VR128:$dst, i32mem:$src), 0, "att">;
+let Predicates = [UseSSE1] in {
+def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (f32 (any_sint_to_fp GR32:$src)))))),
+ (CVTSI2SSrr_Int (v4f32 (V_SET0)), GR32:$src)>;
+def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (f32 (any_sint_to_fp GR64:$src)))))),
+ (CVTSI642SSrr_Int (v4f32 (V_SET0)), GR64:$src)>;
+}
+
+let Predicates = [UseSSE2] in {
+def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (f64 (any_sint_to_fp GR32:$src)))))),
+ (CVTSI2SDrr_Int (v2f64 (V_SET0)), GR32:$src)>;
+def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (f64 (any_sint_to_fp GR64:$src)))))),
+ (CVTSI642SDrr_Int (v2f64 (V_SET0)), GR64:$src)>;
+}
+
+let Predicates = [UseAVX] in {
+def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (f32 (any_sint_to_fp GR32:$src)))))),
+ (VCVTSI2SSrr_Int (v4f32 (V_SET0)), GR32:$src)>;
+def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (f32 (any_sint_to_fp GR64:$src)))))),
+ (VCVTSI642SSrr_Int (v4f32 (V_SET0)), GR64:$src)>;
+def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (f64 (any_sint_to_fp GR32:$src)))))),
+ (VCVTSI2SDrr_Int (v2f64 (V_SET0)), GR32:$src)>;
+def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (f64 (any_sint_to_fp GR64:$src)))))),
+ (VCVTSI642SDrr_Int (v2f64 (V_SET0)), GR64:$src)>;
+}
+
+let Predicates = [UseSSE41] in {
+def : Pat<(v4f32 (X86Blendi (v4f32 immAllZerosV),
+ (v4f32 (scalar_to_vector (f32 (any_sint_to_fp GR32:$src)))),
+ (i8 1))),
+ (CVTSI2SSrr_Int (v4f32 (V_SET0)), GR32:$src)>;
+def : Pat<(v4f32 (X86Blendi (v4f32 immAllZerosV),
+ (v4f32 (scalar_to_vector (f32 (any_sint_to_fp GR64:$src)))),
+ (i8 1))),
+ (CVTSI642SSrr_Int (v4f32 (V_SET0)), GR64:$src)>;
+}
+
+let Predicates = [UseAVX] in {
+def : Pat<(v4f32 (X86Blendi (v4f32 immAllZerosV),
+ (v4f32 (scalar_to_vector (f32 (any_sint_to_fp GR32:$src)))),
+ (i8 1))),
+ (VCVTSI2SSrr_Int (v4f32 (V_SET0)), GR32:$src)>;
+def : Pat<(v4f32 (X86Blendi (v4f32 immAllZerosV),
+ (v4f32 (scalar_to_vector (f32 (any_sint_to_fp GR64:$src)))),
+ (i8 1))),
+ (VCVTSI642SSrr_Int (v4f32 (V_SET0)), GR64:$src)>;
+}
+
/// SSE 1 Only
// Aliases for intrinsics
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
index 6312a26db9bf4..b5d6e21238cde 100644
--- a/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
@@ -33,9 +33,8 @@ define half @sitofp_i1tof16(i1 %x) #0 {
; AVX-NEXT: andb $1, %dil
; AVX-NEXT: negb %dil
; AVX-NEXT: movsbl %dil, %eax
-; AVX-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
-; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %eax, %xmm0, %xmm0
; AVX-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX-NEXT: retq
;
@@ -74,9 +73,8 @@ define half @sitofp_i8tof16(i8 %x) #0 {
; AVX-LABEL: sitofp_i8tof16:
; AVX: # %bb.0:
; AVX-NEXT: movsbl %dil, %eax
-; AVX-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
-; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %eax, %xmm0, %xmm0
; AVX-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX-NEXT: retq
;
@@ -110,9 +108,8 @@ define half @sitofp_i16tof16(i16 %x) #0 {
; AVX-LABEL: sitofp_i16tof16:
; AVX: # %bb.0:
; AVX-NEXT: movswl %di, %eax
-; AVX-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
-; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %eax, %xmm0, %xmm0
; AVX-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX-NEXT: retq
;
@@ -144,9 +141,8 @@ define half @sitofp_i32tof16(i32 %x) #0 {
;
; AVX-LABEL: sitofp_i32tof16:
; AVX: # %bb.0:
-; AVX-NEXT: vcvtsi2ss %edi, %xmm15, %xmm0
-; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %edi, %xmm0, %xmm0
; AVX-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX-NEXT: retq
;
@@ -176,9 +172,8 @@ define half @sitofp_i64tof16(i64 %x) #0 {
;
; AVX-LABEL: sitofp_i64tof16:
; AVX: # %bb.0:
-; AVX-NEXT: vcvtsi2ss %rdi, %xmm15, %xmm0
-; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %rdi, %xmm0, %xmm0
; AVX-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX-NEXT: retq
;
@@ -211,9 +206,8 @@ define half @uitofp_i1tof16(i1 %x) #0 {
; AVX-LABEL: uitofp_i1tof16:
; AVX: # %bb.0:
; AVX-NEXT: andl $1, %edi
-; AVX-NEXT: vcvtsi2ss %edi, %xmm15, %xmm0
-; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %edi, %xmm0, %xmm0
; AVX-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX-NEXT: retq
;
@@ -249,9 +243,8 @@ define half @uitofp_i8tof16(i8 %x) #0 {
; AVX-LABEL: uitofp_i8tof16:
; AVX: # %bb.0:
; AVX-NEXT: movzbl %dil, %eax
-; AVX-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
-; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %eax, %xmm0, %xmm0
; AVX-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX-NEXT: retq
;
@@ -285,9 +278,8 @@ define half @uitofp_i16tof16(i16 %x) #0 {
; AVX-LABEL: uitofp_i16tof16:
; AVX: # %bb.0:
; AVX-NEXT: movzwl %di, %eax
-; AVX-NEXT: vcvtsi2ss %eax, %xmm15, %xmm0
-; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %eax, %xmm0, %xmm0
; AVX-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX-NEXT: retq
;
@@ -321,17 +313,15 @@ define half @uitofp_i32tof16(i32 %x) #0 {
; F16C-LABEL: uitofp_i32tof16:
; F16C: # %bb.0:
; F16C-NEXT: movl %edi, %eax
-; F16C-NEXT: vcvtsi2ss %rax, %xmm15, %xmm0
-; F16C-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; F16C-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; F16C-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; F16C-NEXT: vcvtsi2ss %rax, %xmm0, %xmm0
; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; F16C-NEXT: retq
;
; AVX512-LABEL: uitofp_i32tof16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vcvtusi2ss %edi, %xmm15, %xmm0
-; AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2ss %edi, %xmm0, %xmm0
; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX512-NEXT: retq
;
@@ -393,9 +383,8 @@ define half @uitofp_i64tof16(i64 %x) #0 {
;
; AVX512-LABEL: uitofp_i64tof16:
; AVX512: # %bb.0:
-; AVX512-NEXT: vcvtusi2ss %rdi, %xmm15, %xmm0
-; AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2ss %rdi, %xmm0, %xmm0
; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0
; AVX512-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll
index d7c9438c92ac4..7250c8f7b74d8 100644
--- a/llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll
+++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx1.ll
@@ -1034,8 +1034,8 @@ define <2 x double> @stack_fold_cvtsi2sd_int(i32 %a0) {
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: vcvtsi2sdl {{[-0-9]+}}(%r{{[sb]}}p), %xmm15, %xmm0 # 4-byte Folded Reload
-; CHECK-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vcvtsi2sdl {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 4-byte Folded Reload
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: popq %r12
@@ -1124,8 +1124,8 @@ define <2 x double> @stack_fold_cvtsi642sd_int(i64 %a0) {
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: vcvtsi2sdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm15, %xmm0 # 8-byte Folded Reload
-; CHECK-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
+; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vcvtsi2sdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 8-byte Folded Reload
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: popq %r12
@@ -1214,9 +1214,8 @@ define <4 x float> @stack_fold_cvtsi2ss_int(i32 %a0) {
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: vcvtsi2ssl {{[-0-9]+}}(%r{{[sb]}}p), %xmm15, %xmm0 # 4-byte Folded Reload
-; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vcvtsi2ssl {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 4-byte Folded Reload
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: popq %r12
@@ -1305,9 +1304,8 @@ define <4 x float> @stack_fold_cvtsi642ss_int(i64 %a0) {
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: vcvtsi2ssq {{[-0-9]+}}(%r{{[sb]}}p), %xmm15, %xmm0 # 8-byte Folded Reload
-; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: vcvtsi2ssq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 # 8-byte Folded Reload
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: popq %r12
diff --git a/llvm/test/CodeGen/X86/vector-sint-to-fp-zero.ll b/llvm/test/CodeGen/X86/vector-sint-to-fp-zero.ll
new file mode 100644
index 0000000000000..86c9b76c5230e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-sint-to-fp-zero.ll
@@ -0,0 +1,121 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefixes=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512
+
+define <4 x float> @test_v4f32_i32(i32 %x) {
+; AVX-LABEL: test_v4f32_i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %edi, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; SSE-LABEL: test_v4f32_i32:
+; SSE: # %bb.0:
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2ss %edi, %xmm0
+; SSE-NEXT: retq
+;
+; SSE41-LABEL: test_v4f32_i32:
+; SSE41: # %bb.0:
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %edi, %xmm0
+; SSE41-NEXT: retq
+;
+; AVX512-LABEL: test_v4f32_i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vcvtsi2ss %edi, %xmm0, %xmm0
+; AVX512-NEXT: retq
+ %f = sitofp i32 %x to float
+ %v0 = insertelement <4 x float> zeroinitializer, float %f, i32 0
+ ret <4 x float> %v0
+}
+
+define <4 x float> @test_v4f32_i64(i64 %x) {
+; AVX-LABEL: test_v4f32_i64:
+; AVX: # %bb.0:
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %rdi, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; SSE-LABEL: test_v4f32_i64:
+; SSE: # %bb.0:
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2ss %rdi, %xmm0
+; SSE-NEXT: retq
+;
+; SSE41-LABEL: test_v4f32_i64:
+; SSE41: # %bb.0:
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rdi, %xmm0
+; SSE41-NEXT: retq
+;
+; AVX512-LABEL: test_v4f32_i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vcvtsi2ss %rdi, %xmm0, %xmm0
+; AVX512-NEXT: retq
+ %f = sitofp i64 %x to float
+ %v0 = insertelement <4 x float> zeroinitializer, float %f, i32 0
+ ret <4 x float> %v0
+}
+
+define <2 x double> @test_v2f64_i32(i32 %x) {
+; AVX-LABEL: test_v2f64_i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2sd %edi, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; SSE-LABEL: test_v2f64_i32:
+; SSE: # %bb.0:
+; SSE-NEXT: xorpd %xmm0, %xmm0
+; SSE-NEXT: cvtsi2sd %edi, %xmm0
+; SSE-NEXT: retq
+;
+; SSE41-LABEL: test_v2f64_i32:
+; SSE41: # %bb.0:
+; SSE41-NEXT: xorpd %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2sd %edi, %xmm0
+; SSE41-NEXT: retq
+;
+; AVX512-LABEL: test_v2f64_i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vcvtsi2sd %edi, %xmm0, %xmm0
+; AVX512-NEXT: retq
+ %d = sitofp i32 %x to double
+ %v0 = insertelement <2 x double> zeroinitializer, double %d, i32 0
+ ret <2 x double> %v0
+}
+
+define <2 x double> @test_v2f64_i64(i64 %x) {
+; AVX-LABEL: test_v2f64_i64:
+; AVX: # %bb.0:
+; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2sd %rdi, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; SSE-LABEL: test_v2f64_i64:
+; SSE: # %bb.0:
+; SSE-NEXT: xorpd %xmm0, %xmm0
+; SSE-NEXT: cvtsi2sd %rdi, %xmm0
+; SSE-NEXT: retq
+;
+; SSE41-LABEL: test_v2f64_i64:
+; SSE41: # %bb.0:
+; SSE41-NEXT: xorpd %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2sd %rdi, %xmm0
+; SSE41-NEXT: retq
+;
+; AVX512-LABEL: test_v2f64_i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vcvtsi2sd %rdi, %xmm0, %xmm0
+; AVX512-NEXT: retq
+ %d = sitofp i64 %x to double
+ %v0 = insertelement <2 x double> zeroinitializer, double %d, i32 0
+ ret <2 x double> %v0
+}
diff --git a/llvm/test/CodeGen/X86/vector-uint-to-fp-zero.ll b/llvm/test/CodeGen/X86/vector-uint-to-fp-zero.ll
new file mode 100644
index 0000000000000..64ce6d2af719a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-uint-to-fp-zero.ll
@@ -0,0 +1,180 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefixes=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512
+
+define <4 x float> @test_v4f32_u32(i32 %x) {
+; AVX-LABEL: test_v4f32_u32:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2ss %rax, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; SSE-LABEL: test_v4f32_u32:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2ss %rax, %xmm0
+; SSE-NEXT: retq
+;
+; SSE41-LABEL: test_v4f32_u32:
+; SSE41: # %bb.0:
+; SSE41-NEXT: movl %edi, %eax
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2ss %rax, %xmm0
+; SSE41-NEXT: retq
+;
+; AVX512-LABEL: test_v4f32_u32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2ss %edi, %xmm0, %xmm0
+; AVX512-NEXT: retq
+ %f = uitofp i32 %x to float
+ %v0 = insertelement <4 x float> zeroinitializer, float %f, i32 0
+ ret <4 x float> %v0
+}
+
+define <4 x float> @test_v4f32_u64(i64 %x) {
+; AVX-LABEL: test_v4f32_u64:
+; AVX: # %bb.0:
+; AVX-NEXT: testq %rdi, %rdi
+; AVX-NEXT: js .LBB1_1
+; AVX-NEXT: # %bb.2:
+; AVX-NEXT: vcvtsi2ss %rdi, %xmm15, %xmm0
+; AVX-NEXT: jmp .LBB1_3
+; AVX-NEXT: .LBB1_1:
+; AVX-NEXT: movq %rdi, %rax
+; AVX-NEXT: shrq %rax
+; AVX-NEXT: andl $1, %edi
+; AVX-NEXT: orq %rax, %rdi
+; AVX-NEXT: vcvtsi2ss %rdi, %xmm15, %xmm0
+; AVX-NEXT: vaddss %xmm0, %xmm0, %xmm0
+; AVX-NEXT: .LBB1_3:
+; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
+; AVX-NEXT: retq
+;
+; SSE-LABEL: test_v4f32_u64:
+; SSE: # %bb.0:
+; SSE-NEXT: testq %rdi, %rdi
+; SSE-NEXT: js .LBB1_1
+; SSE-NEXT: # %bb.2:
+; SSE-NEXT: cvtsi2ss %rdi, %xmm1
+; SSE-NEXT: jmp .LBB1_3
+; SSE-NEXT: .LBB1_1:
+; SSE-NEXT: movq %rdi, %rax
+; SSE-NEXT: shrq %rax
+; SSE-NEXT: andl $1, %edi
+; SSE-NEXT: orq %rax, %rdi
+; SSE-NEXT: cvtsi2ss %rdi, %xmm1
+; SSE-NEXT: addss %xmm1, %xmm1
+; SSE-NEXT: .LBB1_3:
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE-NEXT: retq
+;
+; SSE41-LABEL: test_v4f32_u64:
+; SSE41: # %bb.0:
+; SSE41-NEXT: testq %rdi, %rdi
+; SSE41-NEXT: js .LBB1_1
+; SSE41-NEXT: # %bb.2:
+; SSE41-NEXT: cvtsi2ss %rdi, %xmm1
+; SSE41-NEXT: jmp .LBB1_3
+; SSE41-NEXT: .LBB1_1:
+; SSE41-NEXT: movq %rdi, %rax
+; SSE41-NEXT: shrq %rax
+; SSE41-NEXT: andl $1, %edi
+; SSE41-NEXT: orq %rax, %rdi
+; SSE41-NEXT: cvtsi2ss %rdi, %xmm1
+; SSE41-NEXT: addss %xmm1, %xmm1
+; SSE41-NEXT: .LBB1_3:
+; SSE41-NEXT: xorps %xmm0, %xmm0
+; SSE41-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
+; SSE41-NEXT: retq
+;
+; AVX512-LABEL: test_v4f32_u64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2ss %rdi, %xmm0, %xmm0
+; AVX512-NEXT: retq
+ %f = uitofp i64 %x to float
+ %v0 = insertelement <4 x float> zeroinitializer, float %f, i32 0
+ ret <4 x float> %v0
+}
+
+define <2 x double> @test_v2f64_u32(i32 %x) {
+; AVX-LABEL: test_v2f64_u32:
+; AVX: # %bb.0:
+; AVX-NEXT: movl %edi, %eax
+; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vcvtsi2sd %rax, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; SSE-LABEL: test_v2f64_u32:
+; SSE: # %bb.0:
+; SSE-NEXT: movl %edi, %eax
+; SSE-NEXT: xorpd %xmm0, %xmm0
+; SSE-NEXT: cvtsi2sd %rax, %xmm0
+; SSE-NEXT: retq
+;
+; SSE41-LABEL: test_v2f64_u32:
+; SSE41: # %bb.0:
+; SSE41-NEXT: movl %edi, %eax
+; SSE41-NEXT: xorpd %xmm0, %xmm0
+; SSE41-NEXT: cvtsi2sd %rax, %xmm0
+; SSE41-NEXT: retq
+;
+; AVX512-LABEL: test_v2f64_u32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2sd %edi, %xmm0, %xmm0
+; AVX512-NEXT: retq
+ %d = uitofp i32 %x to double
+ %v0 = insertelement <2 x double> zeroinitializer, double %d, i32 0
+ ret <2 x double> %v0
+}
+
+define <2 x double> @test_v2f64_u64(i64 %x) {
+; AVX-LABEL: test_v2f64_u64:
+; AVX: # %bb.0:
+; AVX-NEXT: vmovq %rdi, %xmm0
+; AVX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
+; AVX-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX-NEXT: vaddpd %xmm0, %xmm1, %xmm0
+; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
+; AVX-NEXT: retq
+;
+; SSE-LABEL: test_v2f64_u64:
+; SSE: # %bb.0:
+; SSE-NEXT: movq %rdi, %xmm0
+; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
+; SSE-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: movapd %xmm0, %xmm1
+; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
+; SSE-NEXT: addpd %xmm0, %xmm1
+; SSE-NEXT: movq {{.*#+}} xmm0 = xmm1[0],zero
+; SSE-NEXT: retq
+;
+; SSE41-LABEL: test_v2f64_u64:
+; SSE41: # %bb.0:
+; SSE41-NEXT: movq %rdi, %xmm0
+; SSE41-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
+; SSE41-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: movapd %xmm0, %xmm1
+; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
+; SSE41-NEXT: addpd %xmm0, %xmm1
+; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm1[0],zero
+; SSE41-NEXT: retq
+;
+; AVX512-LABEL: test_v2f64_u64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vxorpd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT: vcvtusi2sd %rdi, %xmm0, %xmm0
+; AVX512-NEXT: retq
+ %d = uitofp i64 %x to double
+ %v0 = insertelement <2 x double> zeroinitializer, double %d, i32 0
+ ret <2 x double> %v0
+}
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