[llvm] AMDGPU/GlobalISel: Switch some FP opcodes to extended LLTs (PR #212664)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 28 18:10:25 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: vangthao95
<details>
<summary>Changes</summary>
Migrate G_FADD, G_FMUL, G_FMA, and G_FSUB and their strict variants, along with G_FCANONICALIZE to use extended LLTs.
Also update the relevant MIR tests.
---
Patch is 322.69 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/212664.diff
7 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+26-29)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir (+414-414)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir (+260-260)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir (+521-521)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir (+414-414)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir (+461-461)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-strict_fsub.mir (+41-21)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 20e0a82f5832c..74273a6dc4987 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -302,6 +302,7 @@ constexpr LLT F64 = LLT::float64();
constexpr LLT V2F16 = LLT::fixed_vector(2, F16);
constexpr LLT V2BF16 = LLT::fixed_vector(2, BF16);
constexpr LLT V2F32 = LLT::fixed_vector(2, F32);
+constexpr LLT V2F64 = LLT::fixed_vector(2, F64);
constexpr LLT S1 = LLT::scalar(1);
constexpr LLT S8 = LLT::scalar(8);
@@ -979,10 +980,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
getActionDefinitionsBuilder(G_BLOCK_ADDR).legalFor({CodePtr});
- auto &FPOpActions = getActionDefinitionsBuilder(
- { G_FADD, G_FMUL, G_FMA, G_FCANONICALIZE,
- G_STRICT_FADD, G_STRICT_FMUL, G_STRICT_FMA})
- .legalFor({S32, S64});
+ auto &FPOpActions =
+ getActionDefinitionsBuilder({G_FADD, G_FMUL, G_FMA, G_FCANONICALIZE,
+ G_STRICT_FADD, G_STRICT_FMUL, G_STRICT_FMA})
+ .legalFor({F32, F64});
auto &TrigActions = getActionDefinitionsBuilder({G_FSIN, G_FCOS})
.customFor({S32, S64});
auto &FDIVActions = getActionDefinitionsBuilder(G_FDIV)
@@ -990,27 +991,27 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
if (ST.has16BitInsts()) {
if (ST.hasVOP3PInsts())
- FPOpActions.legalFor({S16, V2S16});
+ FPOpActions.legalFor({F16, V2F16});
else
- FPOpActions.legalFor({S16});
+ FPOpActions.legalFor({F16});
TrigActions.customFor({S16});
FDIVActions.customFor({S16});
}
if (ST.hasPackedFP32Ops()) {
- FPOpActions.legalFor({V2S32});
- FPOpActions.clampMaxNumElementsStrict(0, S32, 2);
+ FPOpActions.legalFor({V2F32});
+ FPOpActions.clampMaxNumElementsStrict(0, F32, 2);
}
if (ST.hasPackedFP64Ops()) {
- FPOpActions.legalFor({V2S64});
- FPOpActions.clampMaxNumElementsStrict(0, S64, 2);
+ FPOpActions.legalFor({V2F64});
+ FPOpActions.clampMaxNumElementsStrict(0, F64, 2);
}
if (ST.hasPackedFP64Ops()) {
- FPOpActions.legalFor({V2S64});
- FPOpActions.clampMaxNumElementsStrict(0, S64, 2);
+ FPOpActions.legalFor({V2F64});
+ FPOpActions.clampMaxNumElementsStrict(0, F64, 2);
}
auto &MinNumMaxNumIeee =
@@ -1057,11 +1058,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
}
if (ST.hasVOP3PInsts())
- FPOpActions.clampMaxNumElementsStrict(0, S16, 2);
+ FPOpActions.clampMaxNumElementsStrict(0, F16, 2);
- FPOpActions
- .scalarize(0)
- .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64);
+ FPOpActions.scalarize(0).clampScalar(0, ST.has16BitInsts() ? F16 : F32, F64);
TrigActions
.scalarize(0)
@@ -1164,25 +1163,23 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
auto &FSubActions = getActionDefinitionsBuilder({G_FSUB, G_STRICT_FSUB});
if (ST.has16BitInsts()) {
FSubActions
- // Use actual fsub instruction
- .legalFor({S32, S16})
- // Must use fadd + fneg
- .lowerFor({S64, V2S16});
+ // Use actual fsub instruction
+ .legalFor({F32, F16})
+ // Must use fadd + fneg
+ .lowerFor({F64, V2F16});
} else {
FSubActions
- // Use actual fsub instruction
- .legalFor({S32})
- // Must use fadd + fneg
- .lowerFor({S64, S16, V2S16});
+ // Use actual fsub instruction
+ .legalFor({F32})
+ // Must use fadd + fneg
+ .lowerFor({F64, F16, V2F16});
}
if (ST.hasPackedFP32Ops())
- FSubActions.lowerFor({V2S32}).clampMaxNumElements(0, S32, 2);
+ FSubActions.lowerFor({V2F32}).clampMaxNumElements(0, F32, 2);
- FSubActions
- .clampMaxNumElements(0, S16, 2)
- .scalarize(0)
- .clampScalar(0, S32, S64);
+ FSubActions.clampMaxNumElements(0, F16, 2).scalarize(0).clampScalar(0, F32,
+ F64);
// Whether this is legal depends on the floating point mode for the function.
auto &FMad = getActionDefinitionsBuilder(G_FMAD);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
index d75a820c67fa7..82313437412a9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
@@ -6,624 +6,624 @@
# RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -run-pass=legalizer %s -o - | FileCheck -check-prefixes=GFX9 %s
---
-name: test_fadd_s32
+name: test_fadd_f32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; SI-LABEL: name: test_fadd_s32
+ ; SI-LABEL: name: test_fadd_f32
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
- ; SI-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; SI-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[COPY1]]
+ ; SI-NEXT: $vgpr0 = COPY [[FADD]](f32)
;
- ; VI-LABEL: name: test_fadd_s32
+ ; VI-LABEL: name: test_fadd_f32
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
- ; VI-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; VI-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[COPY1]]
+ ; VI-NEXT: $vgpr0 = COPY [[FADD]](f32)
;
- ; GFX9-LABEL: name: test_fadd_s32
+ ; GFX9-LABEL: name: test_fadd_f32
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
- ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s32) = G_FADD %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f32) = COPY $vgpr1
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](f32)
+ %0:_(f32) = COPY $vgpr0
+ %1:_(f32) = COPY $vgpr1
+ %2:_(f32) = G_FADD %0, %1
$vgpr0 = COPY %2
...
---
-name: test_fadd_s64
+name: test_fadd_f64
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
- ; SI-LABEL: name: test_fadd_s64
+ ; SI-LABEL: name: test_fadd_f64
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[COPY]], [[COPY1]]
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](f64)
;
- ; VI-LABEL: name: test_fadd_s64
+ ; VI-LABEL: name: test_fadd_f64
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[COPY]], [[COPY1]]
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](f64)
;
- ; GFX9-LABEL: name: test_fadd_s64
+ ; GFX9-LABEL: name: test_fadd_f64
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = COPY $vgpr2_vgpr3
- %2:_(s64) = G_FADD %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(f64) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f64) = G_FADD [[COPY]], [[COPY1]]
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](f64)
+ %0:_(f64) = COPY $vgpr0_vgpr1
+ %1:_(f64) = COPY $vgpr2_vgpr3
+ %2:_(f64) = G_FADD %0, %1
$vgpr0_vgpr1 = COPY %2
...
---
-name: test_fadd_s16
+name: test_fadd_f16
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; SI-LABEL: name: test_fadd_s16
+ ; SI-LABEL: name: test_fadd_f16
; SI: liveins: $vgpr0, $vgpr1
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
- ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
- ; SI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT]], [[FPEXT1]]
- ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
- ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
- ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; SI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; SI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; SI-NEXT: [[FPEXT:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC]](f16)
+ ; SI-NEXT: [[FPEXT1:%[0-9]+]]:_(f32) = G_FPEXT [[TRUNC1]](f16)
+ ; SI-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[FPEXT]], [[FPEXT1]]
+ ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(f16) = G_FPTRUNC [[FADD]](f32)
+ ; SI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FPTRUNC]](f16)
+ ; SI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; VI-LABEL: name: test_fadd_s16
+ ; VI-LABEL: name: test_fadd_f16
; VI: liveins: $vgpr0, $vgpr1
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[TRUNC1]]
- ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
- ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; VI-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; VI-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; VI-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[TRUNC]], [[TRUNC1]]
+ ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FADD]](f16)
+ ; VI-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
;
- ; GFX9-LABEL: name: test_fadd_s16
+ ; GFX9-LABEL: name: test_fadd_f16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[TRUNC]], [[TRUNC1]]
- ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
- ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s16) = G_TRUNC %0
- %3:_(s16) = G_TRUNC %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $vgpr0
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $vgpr1
+ ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY]](i32)
+ ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(f16) = G_TRUNC [[COPY1]](i32)
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f16) = G_FADD [[TRUNC]], [[TRUNC1]]
+ ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(i32) = G_ANYEXT [[FADD]](f16)
+ ; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](i32)
+ %0:_(i32) = COPY $vgpr0
+ %1:_(i32) = COPY $vgpr1
+ %2:_(f16) = G_TRUNC %0
+ %3:_(f16) = G_TRUNC %1
- %4:_(s16) = G_FADD %2, %3
- %5:_(s32) = G_ANYEXT %4
+ %4:_(f16) = G_FADD %2, %3
+ %5:_(i32) = G_ANYEXT %4
$vgpr0 = COPY %5
...
---
-name: test_fadd_v2s32
+name: test_fadd_v2f32
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
- ; SI-LABEL: name: test_fadd_v2s32
+ ; SI-LABEL: name: test_fadd_v2f32
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; SI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[UV2]]
- ; SI-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[UV1]], [[UV3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; SI-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[UV]], [[UV2]]
+ ; SI-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[UV1]], [[UV3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; VI-LABEL: name: test_fadd_v2s32
+ ; VI-LABEL: name: test_fadd_v2f32
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; VI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[UV2]]
- ; VI-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[UV1]], [[UV3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; VI-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[UV]], [[UV2]]
+ ; VI-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[UV1]], [[UV3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; GFX9-LABEL: name: test_fadd_v2s32
+ ; GFX9-LABEL: name: test_fadd_v2f32
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX9-NEXT: {{ $}}
- ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[UV2]]
- ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD [[UV1]], [[UV3]]
- ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
- %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
- %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
- %2:_(<2 x s32>) = G_FADD %0, %1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; GFX9-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; GFX9-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(f32) = G_FADD [[UV]], [[UV2]]
+ ; GFX9-NEXT: [[FADD1:%[0-9]+]]:_(f32) = G_FADD [[UV1]], [[UV3]]
+ ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
+ %0:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ %1:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ %2:_(<2 x f32>) = G_FADD %0, %1
$vgpr0_vgpr1 = COPY %2
...
---
-name: test_fadd_v2s32_flags
+name: test_fadd_v2f32_flags
body: |
bb.0.entry:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
- ; SI-LABEL: name: test_fadd_v2s32_flags
+ ; SI-LABEL: name: test_fadd_v2f32_flags
; SI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-NEXT: {{ $}}
- ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; SI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; SI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; SI-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[UV]], [[UV2]]
- ; SI-NEXT: [[FADD1:%[0-9]+]]:_(s32) = nnan G_FADD [[UV1]], [[UV3]]
- ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; SI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; SI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; SI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; SI-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[UV]], [[UV2]]
+ ; SI-NEXT: [[FADD1:%[0-9]+]]:_(f32) = nnan G_FADD [[UV1]], [[UV3]]
+ ; SI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [[FADD1]](f32)
+ ; SI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x f32>)
;
- ; VI-LABEL: name: test_fadd_v2s32_flags
+ ; VI-LABEL: name: test_fadd_v2f32_flags
; VI: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; VI-NEXT: {{ $}}
- ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
- ; VI-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; VI-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; VI-NEXT: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[UV]], [[UV2]]
- ; VI-NEXT: [[FADD1:%[0-9]+]]:_(s32) = nnan G_FADD [[UV1]], [[UV3]]
- ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
- ; VI-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; VI-NEXT: [[COPY:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr0_vgpr1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:_(<2 x f32>) = COPY $vgpr2_vgpr3
+ ; VI-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY]](<2 x f32>)
+ ; VI-NEXT: [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[COPY1]](<2 x f32>)
+ ; VI-NEXT: [[FADD:%[0-9]+]]:_(f32) = nnan G_FADD [[UV]], [[UV2]]
+ ; VI-NEXT: [[FADD1:%[0-9]+]]:_(f32) = nnan G_FADD [[UV1]], [[UV3]]
+ ; VI-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[FADD]](f32), [...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/212664
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