[llvm] [RISCV] Fix incorrect lowering of VECTOR_INTERLEAVE on fixed vectors (PR #212642)
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llvm-commits at lists.llvm.org
Tue Jul 28 15:48:22 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Min-Yih Hsu (mshockwave)
<details>
<summary>Changes</summary>
This is the sibling patch of #<!-- -->207254, as it turns out VECTOR_INTERLEAVE has the same problem on fixed vectors as well.
Instead of converting individual operands into scalable vectors, this patch puts each of the operands directly onto stack using the fixed vector version of segmented store intrinsics, before loading them back.
---
Patch is 101.66 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/212642.diff
2 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+49-39)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll (+690-1062)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 384777b52e9a9..644f2d3531334 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13835,29 +13835,12 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
if (VecVT.getVectorElementType() == MVT::i1)
return widenVectorOpsToi8(Op, DL, DAG);
- // Convert to scalable vectors first.
- if (VecVT.isFixedLengthVector()) {
- MVT ContainerVT = getContainerForFixedLengthVector(VecVT);
- SmallVector<SDValue, 8> Ops(Factor);
- for (unsigned i = 0U; i < Factor; ++i)
- Ops[i] = convertToScalableVector(ContainerVT, Op.getOperand(i), DAG,
- Subtarget);
-
- SmallVector<EVT, 8> VTs(Factor, ContainerVT);
- SDValue NewInterleave = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, VTs, Ops);
-
- SmallVector<SDValue, 8> Res(Factor);
- for (unsigned i = 0U; i < Factor; ++i)
- Res[i] = convertFromScalableVector(VecVT, NewInterleave.getValue(i), DAG,
- Subtarget);
- return DAG.getMergeValues(Res, DL);
- }
-
- MVT XLenVT = Subtarget.getXLenVT();
- auto [Mask, VL] = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget);
+ MVT ContainerVecVT = VecVT;
+ if (VecVT.isFixedLengthVector())
+ ContainerVecVT = getContainerForFixedLengthVector(VecVT);
// If the VT is larger than LMUL=8, we need to split and reassemble.
- if ((VecVT.getSizeInBits().getKnownMinValue() * Factor) >
+ if ((ContainerVecVT.getSizeInBits().getKnownMinValue() * Factor) >
(8 * RISCV::RVVBitsPerBlock)) {
SmallVector<SDValue, 8> Ops(Factor * 2);
for (unsigned i = 0; i != Factor; ++i) {
@@ -13885,6 +13868,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
return DAG.getMergeValues(Concats, DL);
}
+ MVT XLenVT = Subtarget.getXLenVT();
+ auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVecVT, DL, DAG, Subtarget);
+
SDValue Interleaved;
// Spill to the stack using a segment store for simplicity.
@@ -13908,25 +13894,45 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
Intrinsic::riscv_vsseg6_mask, Intrinsic::riscv_vsseg7_mask,
Intrinsic::riscv_vsseg8_mask,
};
+ static const Intrinsic::ID FixedIntrIds[] = {
+ Intrinsic::riscv_seg2_store_mask, Intrinsic::riscv_seg3_store_mask,
+ Intrinsic::riscv_seg4_store_mask, Intrinsic::riscv_seg5_store_mask,
+ Intrinsic::riscv_seg6_store_mask, Intrinsic::riscv_seg7_store_mask,
+ Intrinsic::riscv_seg8_store_mask,
+ };
- unsigned Sz =
- Factor * VecVT.getVectorMinNumElements() * VecVT.getScalarSizeInBits();
- EVT VecTupTy = MVT::getRISCVVectorTupleVT(Sz, Factor);
-
- SDValue StoredVal = DAG.getUNDEF(VecTupTy);
- for (unsigned i = 0; i < Factor; i++)
- StoredVal =
- DAG.getNode(RISCVISD::TUPLE_INSERT, DL, VecTupTy, StoredVal,
- Op.getOperand(i), DAG.getTargetConstant(i, DL, MVT::i32));
-
- SDValue Ops[] = {DAG.getEntryNode(),
- DAG.getTargetConstant(IntrIds[Factor - 2], DL, XLenVT),
- StoredVal,
- StackPtr,
- Mask,
- VL,
- DAG.getTargetConstant(Log2_64(VecVT.getScalarSizeInBits()),
- DL, XLenVT)};
+ SmallVector<SDValue> Ops;
+ if (VecVT.isFixedLengthVector()) {
+ Ops = {DAG.getEntryNode(),
+ DAG.getTargetConstant(FixedIntrIds[Factor - 2], DL, XLenVT)};
+ for (unsigned i = 0U; i < Factor; ++i)
+ Ops.push_back(Op.getOperand(i));
+
+ // We cannot use Mask (or getAllOnesMask) here as it is a scalable vector
+ // mask.
+ SDValue FixedAllOnesMask = DAG.getSplat(getMaskTypeFor(VecVT), DL,
+ DAG.getConstant(1, DL, XLenVT));
+ Ops.append({StackPtr, FixedAllOnesMask, VL});
+ } else {
+ unsigned Sz = Factor * VecVT.getVectorMinNumElements() *
+ VecVT.getScalarSizeInBits();
+ EVT VecTupTy = MVT::getRISCVVectorTupleVT(Sz, Factor);
+
+ SDValue StoredVal = DAG.getUNDEF(VecTupTy);
+ for (unsigned i = 0; i < Factor; i++)
+ StoredVal = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, VecTupTy, StoredVal,
+ Op.getOperand(i),
+ DAG.getTargetConstant(i, DL, MVT::i32));
+
+ Ops = {DAG.getEntryNode(),
+ DAG.getTargetConstant(IntrIds[Factor - 2], DL, XLenVT),
+ StoredVal,
+ StackPtr,
+ Mask,
+ VL,
+ DAG.getTargetConstant(Log2_64(VecVT.getScalarSizeInBits()), DL,
+ XLenVT)};
+ }
SDValue Chain = DAG.getMemIntrinsicNode(
ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), Ops,
@@ -13946,6 +13952,10 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
return DAG.getMergeValues(Loads, DL);
}
+ assert(!VecVT.isFixedLengthVector() &&
+ "Fixed factor=2 vector interleave should already lower to "
+ "SHUFFLE_VECTOR");
+
if (Subtarget.hasStdExtZvzip() && !Op.getOperand(0).isUndef() &&
!Op.getOperand(1).isUndef()) {
MVT VT = Op->getSimpleValueType(0);
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index a56bb463dd2c4..56a68500747dd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -171,83 +171,59 @@ define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
define <6 x i32> @vector_interleave3_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind {
; CHECK-LABEL: vector_interleave3_v6i32_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: addi a0, sp, 8
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsseg3e32.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: vle32.v v9, (a2)
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 2
-; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: addi a0, sp, 24
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 4
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave3_v6i32_v2i32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: addi sp, sp, -16
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: sub sp, sp, a0
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: addi sp, sp, -32
+; ZVBB-NEXT: addi a0, sp, 8
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: srli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: vle32.v v9, (a2)
+; ZVBB-NEXT: addi a1, sp, 16
+; ZVBB-NEXT: vle32.v v9, (a1)
; ZVBB-NEXT: vle32.v v8, (a0)
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v9, 2
-; ZVBB-NEXT: add a1, a2, a1
-; ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a1)
+; ZVBB-NEXT: addi a0, sp, 24
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v10, (a0)
; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 4
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: add sp, sp, a0
-; ZVBB-NEXT: addi sp, sp, 16
+; ZVBB-NEXT: addi sp, sp, 32
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave3_v6i32_v2i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -16
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: sub sp, sp, a0
-; ZVZIP-NEXT: addi a0, sp, 16
-; ZVZIP-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVZIP-NEXT: addi sp, sp, -32
+; ZVZIP-NEXT: addi a0, sp, 8
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVZIP-NEXT: vsseg3e32.v v8, (a0)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: srli a1, a1, 1
-; ZVZIP-NEXT: add a2, a0, a1
-; ZVZIP-NEXT: vle32.v v9, (a2)
+; ZVZIP-NEXT: addi a1, sp, 16
+; ZVZIP-NEXT: vle32.v v9, (a1)
; ZVZIP-NEXT: vle32.v v8, (a0)
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v9, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZVZIP-NEXT: vle32.v v10, (a1)
+; ZVZIP-NEXT: addi a0, sp, 24
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v10, (a0)
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: add sp, sp, a0
-; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
%res = call <6 x i32> @llvm.vector.interleave3.v6i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c)
ret <6 x i32> %res
@@ -256,95 +232,71 @@ define <6 x i32> @vector_interleave3_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) nounwind {
; CHECK-LABEL: vector_interleave4_v8i32_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: mv a0, sp
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsseg4e32.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a1, a3, a1
+; CHECK-NEXT: addi a1, sp, 24
; CHECK-NEXT: vle32.v v9, (a1)
-; CHECK-NEXT: vle32.v v10, (a2)
+; CHECK-NEXT: addi a1, sp, 8
+; CHECK-NEXT: vle32.v v10, (a1)
; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a3)
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v10, v9, 2
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 4
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave4_v8i32_v2i32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: addi sp, sp, -16
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: sub sp, sp, a0
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: addi sp, sp, -32
+; ZVBB-NEXT: mv a0, sp
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: srli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a1, a3, a1
+; ZVBB-NEXT: addi a1, sp, 24
; ZVBB-NEXT: vle32.v v9, (a1)
-; ZVBB-NEXT: vle32.v v10, (a2)
+; ZVBB-NEXT: addi a1, sp, 8
+; ZVBB-NEXT: vle32.v v10, (a1)
; ZVBB-NEXT: vle32.v v8, (a0)
+; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 2
-; ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a3)
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v10, (a0)
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v10, v9, 2
; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 4
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: add sp, sp, a0
-; ZVBB-NEXT: addi sp, sp, 16
+; ZVBB-NEXT: addi sp, sp, 32
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave4_v8i32_v2i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -16
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: sub sp, sp, a0
-; ZVZIP-NEXT: addi a0, sp, 16
-; ZVZIP-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVZIP-NEXT: addi sp, sp, -32
+; ZVZIP-NEXT: mv a0, sp
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVZIP-NEXT: vsseg4e32.v v8, (a0)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: srli a1, a1, 1
-; ZVZIP-NEXT: add a2, a0, a1
-; ZVZIP-NEXT: add a3, a2, a1
-; ZVZIP-NEXT: add a1, a3, a1
+; ZVZIP-NEXT: addi a1, sp, 24
; ZVZIP-NEXT: vle32.v v9, (a1)
-; ZVZIP-NEXT: vle32.v v10, (a2)
+; ZVZIP-NEXT: addi a1, sp, 8
+; ZVZIP-NEXT: vle32.v v10, (a1)
; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: addi a0, sp, 16
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 2
-; ZVZIP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZVZIP-NEXT: vle32.v v10, (a3)
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v10, (a0)
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v10, v9, 2
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: add sp, sp, a0
-; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)
ret <8 x i32> %res
@@ -353,104 +305,80 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e) nounwind {
; CHECK-LABEL: vector_interleave5_v10i16_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: addi a0, sp, 12
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsseg5e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: vle16.v v9, (a2)
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vle16.v v10, (a3)
-; CHECK-NEXT: vle16.v v11, (a2)
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: addi a1, sp, 24
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: addi a1, sp, 20
+; CHECK-NEXT: vle16.v v11, (a1)
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v11, v10, 2
; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v11, 4
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: addi a0, sp, 28
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave5_v10i16_v2i16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: addi sp, sp, -16
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: sub sp, sp, a0
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: addi sp, sp, -32
+; ZVBB-NEXT: addi a0, sp, 12
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: vle16.v v9, (a2)
-; ZVBB-NEXT: add a2, a2, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: vle16.v v10, (a3)
-; ZVBB-NEXT: vle16.v v11, (a2)
+; ZVBB-NEXT: addi a1, sp, 16
+; ZVBB-NEXT: vle16.v v9, (a1)
+; ZVBB-NEXT: addi a1, sp, 24
+; ZVBB-NEXT: vle16.v v10, (a1)
+; ZVBB-NEXT: addi a1, sp, 20
+; ZVBB-NEXT: vle16.v v11, (a1)
; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVBB-NEXT: vslideup.vi v11, v10, 2
; ZVBB-NEXT: vslideup.vi v8, v9, 2
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v11, 4
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v10, (a1)
+; ZVBB-NEXT: addi a0, sp, 28
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vle16.v v10, (a0)
; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 8
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: add sp, sp, a0
-; ZVBB-NEXT: addi sp, sp, 16
+; ZVBB-NEXT: addi sp, sp, 32
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave5_v10i16_v2i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -16
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: sub sp, sp, a0
-; ZVZIP-NEXT: addi a0, sp, 16
-; ZVZIP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: addi sp, sp, -32
+; ZVZIP-NEXT: addi a0, sp, 12
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVZIP-NEXT: vsseg5e16.v v8, (a0)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: srli a1, a1, 2
-; ZVZIP-NEXT: add a2, a0, a1
-; ZVZIP-NEXT: vle16.v v9, (a2)
-; ZVZIP-NEXT: add a2, a2, a1
-; ZVZIP-NEXT: add a3, a2, a1
-; ZVZIP-NEXT: vle16.v v10, (a3)
-; ZVZIP-NEXT: vle16.v v11, (a2)
+; ZVZIP-NEXT: addi a1, sp, 16
+; ZVZIP-NEXT: vle16.v v9, (a1)
+; ZVZIP-NEXT: addi a1, sp, 24
+; ZVZIP-NEXT: vle16.v v10, (a1)
+; ZVZIP-NEXT: addi a1, sp, 20
+; ZVZIP-NEXT: vle16.v v11, (a1)
; ZVZIP-NEXT: vle16.v v8, (a0)
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVZIP-NEXT: vslideup.vi v11, v10, 2
; ZVZIP-NEXT: vslideup.vi v8, v9, 2
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v11, 4
-; ZVZIP-NEXT: add a1, a3, a1
-; ZVZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v10, (a1)
+; ZVZIP-NEXT: addi a0, sp, 28
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v10, (a0)
; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 8
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: add sp, sp, a0
-; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
%res = call <10 x i16> @llvm.vector.interleave5.v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e)
ret <10 x i16> %res
@@ -459,119 +387,95 @@ define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <
define <12 x i16> @vector_interleave6_v12i16_v2i16(<2 x i16> %a, <2 x i16> %b, <2 ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/212642
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