[llvm] [AMDGPU] Fix S_ADD_I32 frame index folding emitting COPY with immediate (PR #212440)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 28 09:52:58 PDT 2026
https://github.com/adeshcom14 updated https://github.com/llvm/llvm-project/pull/212440
>From 8920c810719e95893ab77d688685428c423bb2a5 Mon Sep 17 00:00:00 2001
From: Adesh Adikane <aadikane at amd.com>
Date: Tue, 28 Jul 2026 09:04:44 +0000
Subject: [PATCH 1/2] Fix S_ADD_I32 frame index folding emitting COPY with
immediate
---
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 7 ++-
.../AMDGPU/eliminate-frame-index-s-add-i32.ll | 61 +++++++++++++++++++
2 files changed, 65 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.ll
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 14f5c397e7585..01220a701a453 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3138,13 +3138,14 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
assert(Offset == 0);
MI->removeOperand(3);
MI->removeOperand(OtherOpIdx);
- MI->setDesc(TII->get(FIOp->isReg() ? AMDGPU::COPY : AMDGPU::S_MOV_B32));
+ MachineOperand &Src = MI->getOperand(1);
+ MI->setDesc(TII->get(Src.isReg() ? AMDGPU::COPY : AMDGPU::S_MOV_B32));
} else if (DeadSCC && FIOp->isImm() && FIOp->getImm() == 0) {
assert(Offset == 0);
MI->removeOperand(3);
MI->removeOperand(FIOperandNum);
- MI->setDesc(
- TII->get(OtherOp.isReg() ? AMDGPU::COPY : AMDGPU::S_MOV_B32));
+ MachineOperand &Src = MI->getOperand(1);
+ MI->setDesc(TII->get(Src.isReg() ? AMDGPU::COPY : AMDGPU::S_MOV_B32));
}
assert(!FIOp->isFI());
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.ll b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.ll
new file mode 100644
index 0000000000000..663831365f2cf
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.ll
@@ -0,0 +1,61 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O3 < %s | FileCheck %s
+;
+; eliminateFrameIndex must emit s_mov_b32 for S_ADD_I32 %fi, imm.
+
+define amdgpu_kernel void @kernel() {
+; CHECK-LABEL: kernel:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
+; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
+; CHECK-NEXT: v_pk_mov_b32 v[0:1], 0, 0
+; CHECK-NEXT: flat_load_ubyte v0, v[0:1]
+; CHECK-NEXT: s_add_u32 s0, s0, s17
+; CHECK-NEXT: s_addc_u32 s1, s1, 0
+; CHECK-NEXT: s_mov_b32 s4, 4
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
+; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
+; CHECK-NEXT: s_cbranch_execnz .LBB0_3
+; CHECK-NEXT: ; %bb.1: ; %Flow
+; CHECK-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
+; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[4:5], s[4:5] op_sel:[0,1]
+; CHECK-NEXT: s_xor_b64 exec, exec, s[6:7]
+; CHECK-NEXT: s_cbranch_execnz .LBB0_4
+; CHECK-NEXT: .LBB0_2: ; %end
+; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], 0 offset:4
+; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CHECK-NEXT: s_endpgm
+; CHECK-NEXT: .LBB0_3: ; %then
+; CHECK-NEXT: s_mov_b64 s[8:9], src_private_base
+; CHECK-NEXT: s_mov_b32 s5, s9
+; CHECK-NEXT: s_or_saveexec_b64 s[6:7], s[6:7]
+; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[4:5], s[4:5] op_sel:[0,1]
+; CHECK-NEXT: s_xor_b64 exec, exec, s[6:7]
+; CHECK-NEXT: s_cbranch_execz .LBB0_2
+; CHECK-NEXT: .LBB0_4: ; %entry.end_crit_edge
+; CHECK-NEXT: s_mov_b64 s[8:9], src_private_base
+; CHECK-NEXT: s_mov_b32 s5, s9
+; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[4:5], s[4:5] op_sel:[0,1]
+; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
+; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], 0 offset:4
+; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CHECK-NEXT: s_endpgm
+entry:
+ %a = alloca [2 x i32], align 4, addrspace(5)
+ %p = getelementptr i8, ptr addrspace(5) %a, i32 4
+ %c = load i8, ptr null, align 1
+ %cond = icmp eq i8 %c, 0
+ br i1 %cond, label %end, label %then
+
+then:
+ %unused = addrspacecast ptr addrspace(5) %p to ptr
+ br label %end
+
+end:
+ %q = addrspacecast ptr addrspace(5) %p to ptr
+ store ptr %q, ptr addrspace(5) null, align 8
+ ret void
+}
>From 8e583530323262dd0577f9f73ff4fda889dded54 Mon Sep 17 00:00:00 2001
From: Adesh Adikane <aadikane at amd.com>
Date: Tue, 28 Jul 2026 16:34:19 +0000
Subject: [PATCH 2/2] Adding mir test
---
.../AMDGPU/eliminate-frame-index-s-add-i32.ll | 2 +-
.../eliminate-frame-index-s-add-i32.mir | 48 ++++++++++++++++++-
2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.ll b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.ll
index 663831365f2cf..674ca0f8bcd07 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O3 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -O3 < %s | FileCheck %s
;
; eliminateFrameIndex must emit s_mov_b32 for S_ADD_I32 %fi, imm.
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
index 265d0dfc03605..b9a6132176385 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
@@ -1,4 +1,4 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --global-value-regex "s_add_i32__kernel__fi_offset0__inline_imm_dead_scc_subreg"
# RUN: llc -mtriple=amdgpu7.00-amd-amdhsa -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
# RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
# RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
@@ -1990,3 +1990,49 @@ body: |
SI_RETURN implicit $vcc_lo, implicit $vcc_hi, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $sgpr16, implicit $sgpr17, implicit $sgpr18, implicit $sgpr19, implicit $sgpr20, implicit $sgpr21, implicit $sgpr22, implicit $sgpr23, implicit $sgpr24, implicit $sgpr25, implicit $sgpr26, implicit $sgpr27, implicit $sgpr28, implicit $sgpr29, implicit $sgpr30, implicit $sgpr31, implicit $sgpr32, implicit $sgpr33, implicit $sgpr34, implicit $sgpr35, implicit $sgpr36, implicit $sgpr37, implicit $sgpr38, implicit $sgpr39, implicit $sgpr40, implicit $sgpr41, implicit $sgpr42, implicit $sgpr43, implicit $sgpr44, implicit $sgpr45, implicit $sgpr46, implicit $sgpr47, implicit $sgpr48, implicit $sgpr49, implicit $sgpr50, implicit $sgpr51, implicit $sgpr52, implicit $sgpr53, implicit $sgpr54, implicit $sgpr55, implicit $sgpr56, implicit $sgpr57, implicit $sgpr58, implicit $sgpr59, implicit $sgpr60, implicit $sgpr61, implicit $sgpr62, implicit $sgpr63, implicit $sgpr64, implicit $sgpr65, implicit $sgpr66, implicit $sgpr67, implicit $sgpr68, implicit $sgpr69, implicit $sgpr70, implicit $sgpr71, implicit $sgpr72, implicit $sgpr73, implicit $sgpr74, implicit $sgpr75, implicit $sgpr76, implicit $sgpr77, implicit $sgpr78, implicit $sgpr79, implicit $sgpr80, implicit $sgpr81, implicit $sgpr82, implicit $sgpr83, implicit $sgpr84, implicit $sgpr85, implicit $sgpr86, implicit $sgpr87, implicit $sgpr88, implicit $sgpr89, implicit $sgpr90, implicit $sgpr91, implicit $sgpr92, implicit $sgpr93, implicit $sgpr94, implicit $sgpr95
...
+---
+name: s_add_i32__kernel__fi_offset0__inline_imm_dead_scc_subreg
+tracksRegLiveness: true
+stack:
+ - { id: 0, type: default, offset: 0, size: 8, alignment: 4 }
+machineFunctionInfo:
+ isEntryFunction: true
+body: |
+ bb.0:
+ ; MUBUFW64-LABEL: name: s_add_i32__kernel__fi_offset0__inline_imm_dead_scc_subreg
+ ; MUBUFW64: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+ ; MUBUFW64-NEXT: {{ $}}
+ ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02
+ ; MUBUFW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg
+ ; MUBUFW64-NEXT: $private_rsrc_reg = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+ ; MUBUFW64-NEXT: $noreg = S_ADD_U32 $noreg, $noreg, implicit-def $scc, implicit-def $private_rsrc_reg
+ ; MUBUFW64-NEXT: $noreg = S_ADDC_U32 $noreg, 0, implicit-def dead $scc, implicit $scc, implicit-def $private_rsrc_reg
+ ; MUBUFW64-NEXT: renamable $sgpr4 = S_MOV_B32 4, implicit-def $sgpr5
+ ; MUBUFW64-NEXT: S_ENDPGM 0
+ ;
+ ; MUBUFW32-LABEL: name: s_add_i32__kernel__fi_offset0__inline_imm_dead_scc_subreg
+ ; MUBUFW32: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+ ; MUBUFW32-NEXT: {{ $}}
+ ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02
+ ; MUBUFW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg
+ ; MUBUFW32-NEXT: $private_rsrc_reg = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+ ; MUBUFW32-NEXT: $noreg = S_ADD_U32 $noreg, $noreg, implicit-def $scc, implicit-def $private_rsrc_reg
+ ; MUBUFW32-NEXT: $noreg = S_ADDC_U32 $noreg, 0, implicit-def dead $scc, implicit $scc, implicit-def $private_rsrc_reg
+ ; MUBUFW32-NEXT: renamable $sgpr4 = S_MOV_B32 4, implicit-def $sgpr5
+ ; MUBUFW32-NEXT: S_ENDPGM 0
+ ;
+ ; FLATSCRW64-LABEL: name: s_add_i32__kernel__fi_offset0__inline_imm_dead_scc_subreg
+ ; FLATSCRW64: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02
+ ; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg
+ ; FLATSCRW64-NEXT: renamable $sgpr4 = S_MOV_B32 4, implicit-def $sgpr5
+ ; FLATSCRW64-NEXT: S_ENDPGM 0
+ ;
+ ; FLATSCRW32-LABEL: name: s_add_i32__kernel__fi_offset0__inline_imm_dead_scc_subreg
+ ; FLATSCRW32: frame-setup CFI_INSTRUCTION escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02
+ ; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $pc_reg
+ ; FLATSCRW32-NEXT: renamable $sgpr4 = S_MOV_B32 4, implicit-def $sgpr5
+ ; FLATSCRW32-NEXT: S_ENDPGM 0
+ renamable $sgpr4 = S_ADD_I32 %stack.0, 4, implicit-def dead $scc, implicit-def $sgpr5
+ S_ENDPGM 0
+...
+
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