[llvm] [X86] Lower scalar bf16 arithmetic on AVX10.2 via packed ops (PR #212245)

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``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index ca80ade65..315f76e9e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -34531,8 +34531,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
 ///
 /// Each operand is reinterpreted as f16 before building the vector. bf16 has no
 /// scalar register class of its own, but f16 does (FR16X), and bf16/f16 share
-/// the same bits and vector register class (VR128X). Going through f16 keeps the
-/// value in an XMM register: bf16->f16 bitcast, f16->v8f16 SCALAR_TO_VECTOR
+/// the same bits and vector register class (VR128X). Going through f16 keeps
+/// the value in an XMM register: bf16->f16 bitcast, f16->v8f16 SCALAR_TO_VECTOR
 /// (a free COPY_TO_REGCLASS), and v8f16->v8bf16 bitcast are all free. Feeding a
 /// scalar bf16 to SCALAR_TO_VECTOR directly would instead route through bf16's
 /// i16 soft-promote carrier, forcing xmm<->GPR vmovw roundtrips.

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https://github.com/llvm/llvm-project/pull/212245