[llvm] [X86] Add pass to coalesce redundant vector constant materializations (PR #211619)

[via llvm-commits]

AZero13 wrote:

> This is a great patch to use to review all the codegen changes to workout WHY they didn't fold to a single zero register and see which can/should be addressed in isel first.
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> I've always thought it weird that we have 512/256-bit SET0 pseudos instead of just SUBREG_TO_REG(V_SET0) like we do for AVX implicit zeroupper patterns - I think that is the cause of a lot of these..... Makes the (very rare) load folding case harder, which is the only problem afaict - but even that can be addressed I think.
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> Open to suggestions on the ALLONES cases :/ 

Was originally going to support all cases and all numbers but 0 and -1 were easiest for now.

https://github.com/llvm/llvm-project/pull/211619