[llvm] [AMDGPU] Support FLAT_SCRATCH in SILoadStoreOptimizer const offset promotion (PR #212507)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 28 07:25:46 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Arseniy Obolenskiy (aobolensk)
<details>
<summary>Changes</summary>
Add a 32-bit base/offset extraction path for the V_ADD_U32_e64 pattern used by FLAT_SCRATCH vaddr and enable promoteConstantOffsetToImm for FLAT_SCRATCH instructions that have a vaddr operand.
---
Patch is 128.49 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/212507.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (+74-7)
- (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll (+172-246)
- (modified) llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll (+1197-10)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 897be1d6739e1..fc124c240a56f 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -196,6 +196,8 @@ class SILoadStoreOptimizer {
unsigned HiSubReg = 0;
// True when using V_ADD_U64_e64 pattern
bool UseV64Pattern = false;
+ // True when using V_ADD_U32_e64 pattern (32-bit FLAT_SCRATCH vaddr)
+ bool UseScratchVGPRPattern = false;
};
struct MemAddress {
@@ -288,6 +290,9 @@ class SILoadStoreOptimizer {
bool processBaseWithConstOffset64(MachineInstr *AddDef,
const MachineOperand &Base,
MemAddress &Addr) const;
+ bool processBaseWithConstOffset32(MachineInstr *AddDef,
+ const MachineOperand &Base,
+ MemAddress &Addr) const;
void processBaseWithConstOffset(const MachineOperand &Base, MemAddress &Addr) const;
/// Promotes constant offset to the immediate by adjusting the base. It
/// tries to use a base from the nearby instructions that allows it to have
@@ -2198,6 +2203,23 @@ Register SILoadStoreOptimizer::computeBase(MachineInstr &MI,
return FullDestReg;
}
+ // Use V_ADD_U32_e64 for the 32-bit FLAT_SCRATCH vaddr base.
+ if (Addr.Base.UseScratchVGPRPattern) {
+ MachineOperand OffsetOp =
+ createRegOrImm(static_cast<int32_t>(Addr.Offset), MI);
+
+ Register FullDestReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ MachineInstr *Add32 =
+ BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_U32_e64), FullDestReg)
+ .addReg(Addr.Base.LoReg)
+ .add(OffsetOp)
+ .addImm(0); // clamp bit
+ (void)Add32;
+ LLVM_DEBUG(dbgs() << " " << *Add32 << "\n\n";);
+
+ return FullDestReg;
+ }
+
// Original carry-chain pattern (V_ADD_CO_U32 + V_ADDC_U32)
assert((TRI->getRegSizeInBits(Addr.Base.LoReg, *MRI) == 32 ||
Addr.Base.LoSubReg) &&
@@ -2289,6 +2311,39 @@ bool SILoadStoreOptimizer::processBaseWithConstOffset64(
return true;
}
+// Helper to extract a 32-bit constant offset from a V_ADD_U32_e64 instruction.
+// This is the pattern used for the 32-bit vaddr of FLAT_SCRATCH instructions.
+// Returns true if successful, populating Addr with base register info and
+// offset.
+bool SILoadStoreOptimizer::processBaseWithConstOffset32(
+ MachineInstr *AddDef, const MachineOperand &Base, MemAddress &Addr) const {
+ if (!Base.isReg())
+ return false;
+
+ MachineOperand *Src0 = TII->getNamedOperand(*AddDef, AMDGPU::OpName::src0);
+ MachineOperand *Src1 = TII->getNamedOperand(*AddDef, AMDGPU::OpName::src1);
+
+ const MachineOperand *BaseOp = nullptr;
+
+ if (auto Offset = TII->getImmOrMaterializedImm(*Src1)) {
+ BaseOp = Src0;
+ Addr.Offset = *Offset;
+ } else if (auto Offset0 = TII->getImmOrMaterializedImm(*Src0)) {
+ BaseOp = Src1;
+ Addr.Offset = *Offset0;
+ } else {
+ // Both or neither are constants - can't handle this pattern
+ return false;
+ }
+
+ if (!BaseOp->isReg())
+ return false;
+
+ Addr.Base.LoReg = BaseOp->getReg();
+ Addr.Base.UseScratchVGPRPattern = true;
+ return true;
+}
+
// Analyze Base and extracts:
// - 32bit base registers, subregisters
// - 64bit constant offset
@@ -2303,6 +2358,10 @@ bool SILoadStoreOptimizer::processBaseWithConstOffset64(
// Also handles V_ADD_U64_e64 pattern (gfx1250+):
// %OFFSET:sreg_64 = S_MOV_B64_IMM_PSEUDO 256
// %Base:vreg_64 = V_ADD_U64_e64 %BASE:vreg_64, %OFFSET:sreg_64, 0
+//
+// Also handles the 32-bit VGPR pattern used for FLAT_SCRATCH vaddr:
+// %OFFSET:sreg_32 = S_MOV_B32 4096
+// %Base:vgpr_32 = V_ADD_U32_e64 %BASE:vgpr_32, %OFFSET:sreg_32, 0
void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base,
MemAddress &Addr) const {
if (!Base.isReg())
@@ -2318,6 +2377,12 @@ void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base
return;
}
+ // Try V_ADD_U32_e64 pattern (32-bit base, used for FLAT_SCRATCH vaddr)
+ if (Def->getOpcode() == AMDGPU::V_ADD_U32_e64) {
+ if (processBaseWithConstOffset32(Def, Base, Addr))
+ return;
+ }
+
// Fall through to REG_SEQUENCE + V_ADD_CO_U32 + V_ADDC_U32 pattern
if (Def->getOpcode() != AMDGPU::REG_SEQUENCE || Def->getNumOperands() != 5)
return;
@@ -2405,16 +2470,18 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
if (!STM->hasFlatInstOffsets() || !SIInstrInfo::isFLAT(MI))
return false;
- // TODO: Support FLAT_SCRATCH. Currently code expects 64-bit pointers.
- if (SIInstrInfo::isFLATScratch(MI))
+ if (SIInstrInfo::isFLATScratch(MI) &&
+ !TII->getNamedOperand(MI, AMDGPU::OpName::vaddr))
return false;
- unsigned AS = SIInstrInfo::isFLATGlobal(MI) ? AMDGPUAS::GLOBAL_ADDRESS
- : AMDGPUAS::FLAT_ADDRESS;
+ unsigned AS = SIInstrInfo::isFLATGlobal(MI) ? AMDGPUAS::GLOBAL_ADDRESS
+ : SIInstrInfo::isFLATScratch(MI) ? AMDGPUAS::PRIVATE_ADDRESS
+ : AMDGPUAS::FLAT_ADDRESS;
- AMDGPU::FlatAddrSpace FlatVariant = AS == AMDGPUAS::GLOBAL_ADDRESS
- ? AMDGPU::FlatAddrSpace::FlatGlobal
- : AMDGPU::FlatAddrSpace::FLAT;
+ AMDGPU::FlatAddrSpace FlatVariant =
+ AS == AMDGPUAS::GLOBAL_ADDRESS ? AMDGPU::FlatAddrSpace::FlatGlobal
+ : AS == AMDGPUAS::PRIVATE_ADDRESS ? AMDGPU::FlatAddrSpace::FlatScratch
+ : AMDGPU::FlatAddrSpace::FLAT;
bool AllowNegativeOffset =
TII->allowNegativeFlatOffset(FlatVariant) && !TII->usesASYNC_CNT(MI);
// The async global instructions use i24 offset for global address but u16
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
index d5a03b11d4cb4..469cb8da7a138 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
@@ -21,18 +21,16 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX942-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX942-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: v_add_u32_e32 v0, s0, v0
-; GFX942-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
-; GFX942-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
-; GFX942-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
+; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 1, v0
+; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 2
-; GFX942-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
+; GFX942-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 4
-; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off sc0 sc1
+; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off offset:3 sc0 sc1
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX942-SDAG-NEXT: s_endpgm
;
@@ -41,18 +39,16 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX942-GISEL-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 1
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, 2
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_add_u32_e32 v0, s0, v0
-; GFX942-GISEL-NEXT: v_add_u32_e32 v2, 1, v0
-; GFX942-GISEL-NEXT: v_add_u32_e32 v3, 2, v0
-; GFX942-GISEL-NEXT: scratch_store_byte v2, v1, off sc0 sc1
+; GFX942-GISEL-NEXT: v_add_u32_e32 v0, 1, v0
+; GFX942-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 2
-; GFX942-GISEL-NEXT: scratch_store_byte v3, v1, off sc0 sc1
+; GFX942-GISEL-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX942-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX942-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
+; GFX942-GISEL-NEXT: scratch_store_byte v0, v1, off offset:3 sc0 sc1
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX942-GISEL-NEXT: s_endpgm
;
@@ -60,18 +56,16 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %bb
; GFX11-SDAG-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 4
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v2, 0, s0, v0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v1, 0, s0, v0
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 1
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, 2
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u32_e32 v3, 1, v2
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u32_e32 v4, 2, v2
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u32_e32 v2, 4, v2
-; GFX11-SDAG-TRUE16-NEXT: scratch_store_b8 v3, v0, off dlc
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u32_e32 v2, 4, v1
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 4
+; GFX11-SDAG-TRUE16-NEXT: scratch_store_b8 v2, v0, off offset:-3 dlc
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-TRUE16-NEXT: scratch_store_d16_hi_b8 v4, v0, off dlc
+; GFX11-SDAG-TRUE16-NEXT: scratch_store_d16_hi_b8 v2, v0, off offset:-2 dlc
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-TRUE16-NEXT: scratch_store_b8 v2, v1, off dlc
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -85,12 +79,10 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_add3_u32 v0, 0, s0, v0
-; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u32_e32 v4, 1, v0
-; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u32_e32 v5, 2, v0
; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u32_e32 v0, 4, v0
-; GFX11-SDAG-FAKE16-NEXT: scratch_store_b8 v4, v1, off dlc
+; GFX11-SDAG-FAKE16-NEXT: scratch_store_b8 v0, v1, off offset:-3 dlc
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-FAKE16-NEXT: scratch_store_b8 v5, v2, off dlc
+; GFX11-SDAG-FAKE16-NEXT: scratch_store_b8 v0, v2, off offset:-2 dlc
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-FAKE16-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -100,15 +92,14 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, 2 :: v_dual_mov_b32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 4 :: v_dual_add_nc_u32 v0, s0, v0
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, 2 :: v_dual_add_nc_u32 v5, 2, v0
-; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v4, 1, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, s0, v0
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:-3 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:-2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
@@ -179,18 +170,16 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX942-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX942-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: v_mad_u32_u24 v0, v0, 2, s0
-; GFX942-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
-; GFX942-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
-; GFX942-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
+; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 1, v0
+; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 2
-; GFX942-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
+; GFX942-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 4
-; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off sc0 sc1
+; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off offset:3 sc0 sc1
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX942-SDAG-NEXT: s_endpgm
;
@@ -202,16 +191,14 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 1
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_add_u32_e32 v0, s0, v0
-; GFX942-GISEL-NEXT: v_add_u32_e32 v2, 1, v0
-; GFX942-GISEL-NEXT: scratch_store_byte v2, v1, off sc0 sc1
+; GFX942-GISEL-NEXT: v_add_u32_e32 v0, 1, v0
+; GFX942-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX942-GISEL-NEXT: v_add_u32_e32 v1, 2, v0
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, 2
-; GFX942-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 2
+; GFX942-GISEL-NEXT: scratch_store_byte v0, v1, off offset:1 sc0 sc1
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX942-GISEL-NEXT: v_add_u32_e32 v0, 4, v0
; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 4
-; GFX942-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
+; GFX942-GISEL-NEXT: scratch_store_byte v0, v1, off offset:3 sc0 sc1
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX942-GISEL-NEXT: s_endpgm
;
@@ -219,18 +206,16 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %bb
; GFX11-SDAG-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 4
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_mad_u32_u24 v2, v0, 2, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: v_mad_u32_u24 v1, v0, 2, s0
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 1
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, 2
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u32_e32 v3, 1, v2
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u32_e32 v4, 2, v2
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u32_e32 v2, 4, v2
-; GFX11-SDAG-TRUE16-NEXT: scratch_store_b8 v3, v0, off dlc
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u32_e32 v2, 4, v1
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 4
+; GFX11-SDAG-TRUE16-NEXT: scratch_store_b8 v2, v0, off offset:-3 dlc
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-TRUE16-NEXT: scratch_store_d16_hi_b8 v4, v0, off dlc
+; GFX11-SDAG-TRUE16-NEXT: scratch_store_d16_hi_b8 v2, v0, off offset:-2 dlc
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-TRUE16-NEXT: scratch_store_b8 v2, v1, off dlc
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -244,12 +229,10 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-FAKE16-NEXT: v_mad_u32_u24 v0, v0, 2, s0
-; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u32_e32 v4, 1, v0
-; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u32_e32 v5, 2, v0
; GFX11-SDAG-FAKE16-NEXT: v_add_nc_u32_e32 v0, 4, v0
-; GFX11-SDAG-FAKE16-NEXT: scratch_store_b8 v4, v1, off dlc
+; GFX11-SDAG-FAKE16-NEXT: scratch_store_b8 v0, v1, off offset:-3 dlc
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-SDAG-FAKE16-NEXT: scratch_store_b8 v5, v2, off dlc
+; GFX11-SDAG-FAKE16-NEXT: scratch_store_b8 v0, v2, off offset:-2 dlc
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-FAKE16-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-SDAG-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -259,18 +242,16 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, 2 :: v_dual_mov_b32 v3, 4
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_mul_u32_u24_e32 v0, 2, v0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, s0, v0
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, 2 :: v_dual_add_nc_u32 v5, 2, v0
-; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v4, 1, v0
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 4, v0
-; GFX11-GISEL-NEXT: scratch_store_b8 v4, v1, off dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:-3 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-GISEL-NEXT: scratch_store_b8 v5, v2, off dlc
+; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:-2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
@@ -347,18 +328,16 @@ define amdgpu_kernel void @soff1_voff4(i32 %soff) {
; GFX942-SDAG-NEXT: s_load_dword s0, s[4:5], 0x24
; GFX942-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 1
+; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT: v_mad_u32_u24 v0, v0, 4, s0
-; GFX942-SDAG-NEXT: v_add_u32_e32 v2, 1, v0
-; GFX942-SDAG-NEXT: v_add_u32_e32 v3, 2, v0
-; GFX942-SDAG-NEXT: scratch_store_byte v2, v1, off sc0 sc1
+; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 1, v0
+; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 2
-; GFX942-SDAG-NEXT: scratch_store_byte v3, v1, off sc0 sc1
+; GFX942-SDAG-NEXT: scratch_store_byte v0, v2, off offset:1 sc0 sc1
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 4, v0
; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 4
-; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off sc0 sc1
+; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off offset:3 sc0 sc1
; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX942-SDAG-NEXT: s_endpgm
;
@@ -370,16 +349,14 @@ define amdgpu_kernel void @soff1_voff4(i32 %soff) {
; GFX942-GISEL-NEXT: v_mov_b32_e32 v1, 1
; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT: v_add_u32_e32 v0, s0, v0
-; GFX942-GISEL-NEXT: v_add_u32_e32 v2, 1, v0
-; GFX942-GISEL-NEXT: scratch_store_byte v2, v1, off sc0 sc1
+; GFX942-GISEL-NEXT: v_add_u32_e32 v0, 1, v0
+; GFX942-GISEL-NEXT: scratch_store_byte v0, v1, off sc0 sc1
; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX942-GISEL-NEXT: v_add_u32_e32 v1, 2, v0
-; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, 2
-; GFX942-GISEL-NEXT: scratch_store_byte v1, v2, off sc0 sc1
+; GFX942-GISEL-NEXT: v_mov_b32_...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/212507
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