[llvm] [AArch64][SME2] Add stridedorcontiguous pseudos for multi-vector-stores (PR #211551)

[Sander de Smalen via llvm-commits]

================
@@ -4697,6 +4697,88 @@ defm WHILELO_CXX : sve2p1_int_while_rr_pn<"whilelo", 0b110, AArch64whilelo_pn_fl
 defm WHILELS_CXX : sve2p1_int_while_rr_pn<"whilels", 0b111, AArch64whilels_pn_flag>;
 } // End HasSVE2p1_or_StreamingSME2
 
+multiclass store_pn_x2_sme2<ValueType Ty, SDPatternOperator Store,
+                             Instruction RegImmPseudo> {
+  let AddedComplexity = 2 in {
+    // scalar + immediate (mul vl)
+    def : Pat<(Store Ty:$vec0, Ty:$vec1, aarch64svcount:$PNg,
+                (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset)),
+              (RegImmPseudo
+                  (REG_SEQUENCE ZPR2StridedOrContiguous,
+                                Ty:$vec0, zsub0, Ty:$vec1, zsub1),
+                  PNR:$PNg, GPR64:$base, simm4s1:$offset)>;
+  }
+
+  let AddedComplexity = 1 in
+  def : Pat<(Store Ty:$vec0, Ty:$vec1, aarch64svcount:$PNg, GPR64:$base),
+            (RegImmPseudo
+                (REG_SEQUENCE ZPR2StridedOrContiguous,
+                              Ty:$vec0, zsub0, Ty:$vec1, zsub1),
+                PNR:$PNg, GPR64:$base, (i64 0))>;
+}
+
+multiclass store_pn_x4_sme2<ValueType Ty, SDPatternOperator Store,
+                             Instruction RegImmPseudo> {
+  let AddedComplexity = 2 in {
+    // scalar + immediate (mul vl)
+    def : Pat<(Store Ty:$vec0, Ty:$vec1, Ty:$vec2, Ty:$vec3,
+                aarch64svcount:$PNg,
+                (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset)),
+              (RegImmPseudo
+                  (REG_SEQUENCE ZPR4StridedOrContiguous,
+                                Ty:$vec0, zsub0, Ty:$vec1, zsub1,
+                                Ty:$vec2, zsub2, Ty:$vec3, zsub3),
+                  PNR:$PNg, GPR64:$base, simm4s1:$offset)>;
+  }
+
+  let AddedComplexity = 1 in
+  def : Pat<(Store Ty:$vec0, Ty:$vec1, Ty:$vec2, Ty:$vec3,
+                  aarch64svcount:$PNg, GPR64:$base),
+            (RegImmPseudo
+                (REG_SEQUENCE ZPR4StridedOrContiguous,
+                              Ty:$vec0, zsub0, Ty:$vec1, zsub1,
+                              Ty:$vec2, zsub2, Ty:$vec3, zsub3),
+                PNR:$PNg, GPR64:$base, (i64 0))>;
+}
+
+let Predicates = [HasSME2] in {
----------------
sdesmalen-arm wrote:

HasSME2 is defined as:
```
def HasSME2          : Predicate<"Subtarget->isStreaming() && Subtarget->hasSME2()">,
                                 AssemblerPredicateWithAll<(all_of FeatureSME2), "sme2">;
```
so it checks for streaming property for the patterns.

https://github.com/llvm/llvm-project/pull/211551