[llvm] 7d4160e - [AMDGPU] Stop rounding up LDS block size for gfx950 (#208046)

[via llvm-commits]

Author: Frederik Harwath
Date: 2026-07-28T16:16:06+02:00
New Revision: 7d4160e52ba0e06d1450fa8e9c31518c0e58895c

URL: https://github.com/llvm/llvm-project/commit/7d4160e52ba0e06d1450fa8e9c31518c0e58895c
DIFF: https://github.com/llvm/llvm-project/commit/7d4160e52ba0e06d1450fa8e9c31518c0e58895c.diff

LOG: [AMDGPU] Stop rounding up LDS block size for gfx950 (#208046)

The AMDGPUAsmPrinter::getSIProgramInfo function calculates the number of
LDS blocks in a somewhat indirect way: It obtains the LDS granularity
from another function, determines an "LDSAlignShift" based on this and
then uses shifts to determine the alignment and for division. The use of
shifts forces the alignment to be a power of two which works for all LDS
granularity values except for the value of 1280 bytes used for gfx950.
For this, the function uses LDSAlignShift = 11 which means that the
block size gets rounded up to 2048. This implies that the computed
number of LDS blocks is too small.

Remove the use of LDSAlignShift from getSIProgramInfo and use the LDS
granularity directly for alignment and division.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
    llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
    llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
    llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 01eebf593769e..e1800c4ebded2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -1417,29 +1417,14 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 
   // Make clamp modifier on NaN input returns 0.
   ProgInfo.DX10Clamp = Mode.DX10Clamp;
-
-  unsigned LDSAlignShift = 8;
-  switch (getLdsDwGranularity(STM)) {
-  case 512:
-  case 320:
-    LDSAlignShift = 11;
-    break;
-  case 128:
-    LDSAlignShift = 9;
-    break;
-  case 64:
-    LDSAlignShift = 8;
-    break;
-  default:
-    llvm_unreachable("invald LDS block size");
-  }
-
   ProgInfo.SGPRSpill = MFI->getNumSpilledSGPRs();
   ProgInfo.VGPRSpill = MFI->getNumSpilledVGPRs();
 
   ProgInfo.LDSSize = MFI->getLDSSize();
+
+  unsigned LDSGranularityBytes = getLdsDwGranularity(STM) * 4;
   ProgInfo.LDSBlocks =
-      alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
+      alignTo(ProgInfo.LDSSize, LDSGranularityBytes) / LDSGranularityBytes;
 
   // The MCExpr equivalent of divideCeil.
   auto DivideCeil = [&Ctx](const MCExpr *Numerator, const MCExpr *Denominator) {

diff  --git a/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll b/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
index 399fd47345fbb..30100302f102f 100644
--- a/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
@@ -21,10 +21,10 @@
 ; GFX11-MESA: .long 45100
 ; GFX11-MESA-NEXT: .long 1024
 
-; GFX950-PAL: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x200
+; GFX950-PAL: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x400
 
 ; GFX950-MESA: .long 45100
-; GFX950-MESA-NEXT: .long 512
+; GFX950-MESA-NEXT: .long 1024
 
 ; GFX1200-PAL: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x400
 

diff  --git a/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll b/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
index 38dfdf9757d7d..690143f007937 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-size-hsa-gfx950.ll
@@ -11,7 +11,7 @@
 ; GCN-LABEL: test_lds_array_size_131076:
 ; GCN: .amdhsa_group_segment_fixed_size 131076
 ; GCN: ; LDSByteSize: 131076 bytes/workgroup
-; MESA: granulated_lds_size = 65
+; MESA: granulated_lds_size = 103
 define amdgpu_kernel void @test_lds_array_size_131076() {
   %gep = getelementptr inbounds [32768 x i32], ptr addrspace(3) @lds.array.size.131076, i32 0, i32 20
   %val = load i32, ptr addrspace(3) %gep
@@ -22,7 +22,7 @@ define amdgpu_kernel void @test_lds_array_size_131076() {
 ; GCN-LABEL: test_lds_array_size_163840:
 ; GCN: .amdhsa_group_segment_fixed_size 163840
 ; GCN: ; LDSByteSize: 163840 bytes/workgroup
-; MESA: granulated_lds_size = 80
+; MESA: granulated_lds_size = 128
 define amdgpu_kernel void @test_lds_array_size_163840() {
   %gep = getelementptr inbounds [40959 x i32], ptr addrspace(3) @lds.array.size.163840 , i32 0, i32 20
   %val = load i32, ptr addrspace(3) %gep

diff  --git a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
index e60cd9c1be284..d4b40b3edf6cf 100644
--- a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
@@ -131,7 +131,7 @@
 ; CHECK-NEXT:        .entry_point_symbol:    hs_shader
 ; CHECK-NEXT:        .forward_progress: false
 ; CHECK-NEXT:        .ieee_mode:      false
-; CHECK-NEXT:        .lds_size:       0xa00
+; CHECK-NEXT:        .lds_size:       0x1400
 ; CHECK-NEXT:        .mem_ordered:    false
 ; CHECK-NEXT:        .scratch_en:     false
 ; CHECK-NEXT:        .scratch_memory_size: 0