[llvm] [TableGen][AMDGPU][AsmParser] Catch and fix ambiguous instructions (PR #211093)

[Matt Arsenault via llvm-commits]

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@@ -2911,6 +2913,102 @@ def isWave32Strict : Predicate<"Subtarget->isWave32()">,
 def isWave64Strict : Predicate<"Subtarget->isWave64()">,
   AssemblerPredicate <(all_of FeatureWavefrontSize64)>;
 
+def : MutuallyExclusiveAssemblerPredicates<isGFX8GFX9NotGFX90A,
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arsenm wrote:

> with predicates like isGFX90APlus in the picture

My point is these predicates should not exist. Ideally there would be no isGFXN predicates of any kind

https://github.com/llvm/llvm-project/pull/211093