[llvm] [RISCV][MC] Improve FPR Error Messages (PR #212492)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 28 06:36:03 PDT 2026
https://github.com/saloni-shinde-Q created https://github.com/llvm/llvm-project/pull/212492
For the usual FPR RegClasses (FPR16, FPR32, FPR64, FPR128, FPR256)
For the compressed FPR RegClasses (FPR16C, FPR32C, FPR64C) which are
limited to f8 to f15.
For GPR-as-FPR classes used by Zfinx/Zdinx extensions
(GPRAsFPR16, GPRAsFPR32, GPRF64AsFPR, GPRPairAsFPR).
>From dca33dc288867f04ea0ea98db0a4e35ed0714702 Mon Sep 17 00:00:00 2001
From: Saloni Shinde <saloshin at hu-saloshin-lv.qualcomm.com>
Date: Tue, 28 Jul 2026 01:11:07 -0700
Subject: [PATCH] [RISCV][MC] Improve FPR Error Messages
---
llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td | 1 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 41 +++++++++++++++----
llvm/test/MC/RISCV/rv32d-invalid.s | 9 ++--
llvm/test/MC/RISCV/rv32dc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32f-invalid.s | 8 ++--
llvm/test/MC/RISCV/rv32fc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32q-invalid.s | 6 +--
llvm/test/MC/RISCV/rv32zdinx-invalid.s | 8 ++--
llvm/test/MC/RISCV/rv32zfh-invalid.s | 12 +++---
llvm/test/MC/RISCV/rv32zfinx-invalid.s | 8 ++--
llvm/test/MC/RISCV/rv32zhinx-invalid.s | 8 ++--
llvm/test/MC/RISCV/rv32zhinxmin-invalid.s | 4 +-
llvm/test/MC/RISCV/rv64d-invalid.s | 12 ++++--
llvm/test/MC/RISCV/rv64f-invalid.s | 9 +++-
llvm/test/MC/RISCV/rv64q-invalid.s | 4 +-
.../test/MC/RISCV/rv64xtheadfmemidx-invalid.s | 4 +-
llvm/test/MC/RISCV/rv64zdinx-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zfh-invalid.s | 8 +++-
llvm/test/MC/RISCV/rv64zfinx-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zhinx-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zhinxmin-invalid.s | 4 +-
llvm/test/MC/RISCV/rvzfbfmin-invalid.s | 4 +-
llvm/test/MC/RISCV/rvzfhmin-invalid.s | 4 +-
25 files changed, 108 insertions(+), 59 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index d8f9c551d9e5d..3d5d4a2b883fe 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -38,6 +38,7 @@ def GPRPairAsFPR : AsmOperandClass {
let ParserMethod = "parseGPRPairAsFPR64";
let PredicateMethod = "isGPRPairAsFPR64";
let RenderMethod = "addRegOperands";
+ let DiagnosticString = "register must be an even-numbered GPR when used as FPR";
}
def GPRF64AsFPR : AsmOperandClass {
@@ -45,6 +46,7 @@ def GPRF64AsFPR : AsmOperandClass {
let PredicateMethod = "isGPRAsFPR";
let ParserMethod = "parseGPRAsFPR64";
let RenderMethod = "addRegOperands";
+ let DiagnosticString = "register must be a GPR when used as FPR";
}
def FPR64INX : RegisterOperand<GPR> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 1ccbc7e76de30..9f01c5ab78dda 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -115,6 +115,7 @@ def GPRAsFPR32 : AsmOperandClass {
let Name = "GPRAsFPR32";
let ParserMethod = "parseGPRAsFPR";
let RenderMethod = "addRegOperands";
+ let DiagnosticString = "register must be a GPR when used as FPR";
}
def FPR32INX : RegisterOperand<GPRF32> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index 79a4a95ab3448..f43185105ceb5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -46,6 +46,7 @@ def GPRAsFPR16 : AsmOperandClass {
let Name = "GPRAsFPR16";
let ParserMethod = "parseGPRAsFPR";
let RenderMethod = "addRegOperands";
+ let DiagnosticString = "register must be a GPR when used as FPR";
}
def FPR16INX : RegisterOperand<GPRF16> {
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index fc9fb66d59f4b..9d43277bcdafe 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -546,21 +546,43 @@ class FPRCRegisterClass<list<ValueType> regTypes, int align, string regSuffix>
// meaning caller-save regs are listed before callee-save.
// We start by allocating argument registers in reverse order since they are
// compressible.
-def FPR16 : FPRRegisterClass<[f16, bf16], 16, "H">;
+def FPR16 : FPRRegisterClass<[f16, bf16], 16, "H"> {
+ let DiagnosticType = "InvalidRegClassFPR16";
+ let DiagnosticString = "register must be a FPR";
+}
-def FPR16C : FPRCRegisterClass<[f16, bf16], 16, "H">;
+def FPR16C : FPRCRegisterClass<[f16, bf16], 16, "H"> {
+ let DiagnosticType = "InvalidRegClassFPR16C";
+ let DiagnosticString = "register must be a FPR from f8 to f15 (fs0-fs1, fa0-fa5)";
+}
-def FPR32 : FPRRegisterClass<[f32], 32, "F">;
+def FPR32 : FPRRegisterClass<[f32], 32, "F"> {
+ let DiagnosticType = "InvalidRegClassFPR32";
+ let DiagnosticString = "register must be a FPR";
+}
+
+def FPR32C : FPRCRegisterClass<[f32], 32, "F"> {
+ let DiagnosticType = "InvalidRegClassFPR32C";
+ let DiagnosticString = "register must be a FPR from f8 to f15 (fs0-fs1, fa0-fa5)";
+}
-def FPR32C : FPRCRegisterClass<[f32], 32, "F">;
// The order of registers represents the preferred allocation sequence,
// meaning caller-save regs are listed before callee-save.
-def FPR64 : FPRRegisterClass<[f64], 64, "D">;
+def FPR64 : FPRRegisterClass<[f64], 64, "D"> {
+ let DiagnosticType = "InvalidRegClassFPR64";
+ let DiagnosticString = "register must be a FPR";
+}
-def FPR64C : FPRCRegisterClass<[f64], 64, "D">;
+def FPR64C : FPRCRegisterClass<[f64], 64, "D"> {
+ let DiagnosticType = "InvalidRegClassFPR64C";
+ let DiagnosticString = "register must be a FPR from f8 to f15 (fs0-fs1, fa0-fa5)";
+}
-def FPR128 : FPRRegisterClass<[f128], 128, "Q">;
+def FPR128 : FPRRegisterClass<[f128], 128, "Q"> {
+ let DiagnosticType = "InvalidRegClassFPR128";
+ let DiagnosticString = "register must be a FPR";
+}
//===----------------------------------------------------------------------===//
// GPR Classes for "H/F/D in X"
@@ -1016,7 +1038,10 @@ let RegAltNameIndices = [ABIRegAltName] in
// The order of registers represents the preferred allocation sequence,
// meaning caller-save regs are listed before callee-save.
-def FPR256 : FPRRegisterClass<[v8i32, v8f32], 256, "Q2">;
+def FPR256 : FPRRegisterClass<[v8i32, v8f32], 256, "Q2"> {
+ let DiagnosticType = "InvalidRegClassFPR256";
+ let DiagnosticString = "register must be a FPR";
+}
// Mask registers m0 to m7
foreach Index = 0-7 in
diff --git a/llvm/test/MC/RISCV/rv32d-invalid.s b/llvm/test/MC/RISCV/rv32d-invalid.s
index 582ff22814c9d..3cc0c146bbf11 100644
--- a/llvm/test/MC/RISCV/rv32d-invalid.s
+++ b/llvm/test/MC/RISCV/rv32d-invalid.s
@@ -10,12 +10,15 @@ fld ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: register must be a GPR
fsd ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: register must be a GPR
# Invalid register names
-fld ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fld ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: register must be a FPR
fld ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
-fsgnjn.d fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+fsgnjn.d fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: register must be a FPR
# Integer registers where FP regs are expected
-fadd.d a2, a1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+fadd.d a2, a1, a0 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:8: note: register must be a FPR
+# CHECK: :[[@LINE-2]]:8: note: register must be a GPR when used as FPR
+# CHECK: :[[@LINE-3]]:8: note: register must be an even-numbered GPR when used as FPR
# FP registers where integer regs are expected
fcvt.wu.d ft2, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
diff --git a/llvm/test/MC/RISCV/rv32dc-invalid.s b/llvm/test/MC/RISCV/rv32dc-invalid.s
index 6c91a7c7a5594..9521320879db6 100644
--- a/llvm/test/MC/RISCV/rv32dc-invalid.s
+++ b/llvm/test/MC/RISCV/rv32dc-invalid.s
@@ -1,7 +1,7 @@
# RUN: not llvm-mc -triple=riscv32 -mattr=+c,+d < %s 2>&1 | FileCheck %s
## FPRC
-c.fld ft3, 8(a5) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+c.fld ft3, 8(a5) # CHECK: :[[@LINE]]:8: error: register must be a FPR
## uimm9_lsb000
c.fldsp fs1, 512(sp) # CHECK: :[[@LINE]]:15: error: immediate must be a multiple of 8 bytes in the range [0, 504]
diff --git a/llvm/test/MC/RISCV/rv32f-invalid.s b/llvm/test/MC/RISCV/rv32f-invalid.s
index 0d8d5f001228c..56dee318a9933 100644
--- a/llvm/test/MC/RISCV/rv32f-invalid.s
+++ b/llvm/test/MC/RISCV/rv32f-invalid.s
@@ -10,18 +10,18 @@ flw ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: register must be a GPR
fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: register must be a GPR
# Invalid register names
-flw ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flw ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: register must be a FPR
flw ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
-fsgnjn.s fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+fsgnjn.s fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: register must be a FPR
# Integer registers where FP regs are expected
fmv.x.w fs7, a2 # CHECK: :[[@LINE]]:9: error: register must be a GPR
# FP registers where integer regs are expected
-fmv.w.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+fmv.w.x a8, ft2 # CHECK: :[[@LINE]]:9: error: register must be a FPR
# Rounding mode when a register is expected
-fmadd.s f10, f11, f12, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
+fmadd.s f10, f11, f12, ree # CHECK: :[[@LINE]]:24: error: register must be a FPR
# Invalid rounding modes
fmadd.s f10, f11, f12, f13, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
diff --git a/llvm/test/MC/RISCV/rv32fc-invalid.s b/llvm/test/MC/RISCV/rv32fc-invalid.s
index f379402786ec5..22178deb32df6 100644
--- a/llvm/test/MC/RISCV/rv32fc-invalid.s
+++ b/llvm/test/MC/RISCV/rv32fc-invalid.s
@@ -1,7 +1,7 @@
# RUN: not llvm-mc -triple=riscv32 -mattr=+c,+f < %s 2>&1 | FileCheck %s
## FPRC
-c.flw ft3, 8(a5) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+c.flw ft3, 8(a5) # CHECK: :[[@LINE]]:8: error: register must be a FPR
## uimm8_lsb00
c.flwsp fs1, 256(sp) # CHECK: :[[@LINE]]:15: error: immediate must be a multiple of 4 bytes in the range [0, 252]
diff --git a/llvm/test/MC/RISCV/rv32q-invalid.s b/llvm/test/MC/RISCV/rv32q-invalid.s
index 1f9258758120f..4e5ba9f145923 100644
--- a/llvm/test/MC/RISCV/rv32q-invalid.s
+++ b/llvm/test/MC/RISCV/rv32q-invalid.s
@@ -10,12 +10,12 @@ flq ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: register must be a GPR
fsq ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: register must be a GPR
# Invalid register names
-flq ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flq ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: register must be a FPR
flq ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
-fsgnjn.q fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+fsgnjn.q fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: register must be a FPR
# Integer registers where FP regs are expected
-fadd.q a2, a1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+fadd.q a2, a1, a0 # CHECK: :[[@LINE]]:8: error: register must be a FPR
# FP registers where integer regs are expected
fcvt.wu.q ft2, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
diff --git a/llvm/test/MC/RISCV/rv32zdinx-invalid.s b/llvm/test/MC/RISCV/rv32zdinx-invalid.s
index 23a35ceced398..553131974462d 100644
--- a/llvm/test/MC/RISCV/rv32zdinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zdinx-invalid.s
@@ -8,15 +8,15 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fadd.d fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
fmv.x.w s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
# Invalid register names
-fadd.d a100, a2, a4 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-fsgnjn.d a100, a2, a4 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+fadd.d a100, a2, a4 # CHECK: :[[@LINE]]:8: error: register must be an even-numbered GPR when used as FPR
+fsgnjn.d a100, a2, a4 # CHECK: :[[@LINE]]:10: error: register must be an even-numbered GPR when used as FPR
# Rounding mode when a register is expected
-fmadd.d x10, x12, x14, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
+fmadd.d x10, x12, x14, ree # CHECK: :[[@LINE]]:24: error: register must be an even-numbered GPR when used as FPR
# Invalid rounding modes
fmadd.d x10, x12, x14, x16, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
diff --git a/llvm/test/MC/RISCV/rv32zfh-invalid.s b/llvm/test/MC/RISCV/rv32zfh-invalid.s
index bb9722cca75a4..cd9995b43b0a9 100644
--- a/llvm/test/MC/RISCV/rv32zfh-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zfh-invalid.s
@@ -11,18 +11,18 @@ flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: register must be a GPR
fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: register must be a GPR
# Invalid register names
-flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: register must be a FPR
flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
-fsgnjn.h fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+fsgnjn.h fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: register must be a FPR
# Integer registers where FP regs are expected
fmv.x.h fs7, a2 # CHECK: :[[@LINE]]:9: error: register must be a GPR
# FP registers where integer regs are expected
-fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: register must be a FPR
# Rounding mode when a register is expected
-fmadd.h f10, f11, f12, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
+fmadd.h f10, f11, f12, ree # CHECK: :[[@LINE]]:24: error: register must be a FPR
# Invalid rounding modes
fmadd.h f10, f11, f12, f13, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
@@ -30,7 +30,9 @@ fmsub.h f14, f15, f16, f17, 0 # CHECK: :[[@LINE]]:29: error: operand must be a v
fnmsub.h f18, f19, f20, f21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic
# Integer registers where FP regs are expected
-fadd.h a2, a1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+fadd.h a2, a1, a0 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:8: note: register must be a FPR
+# CHECK: :[[@LINE-2]]:8: note: register must be a GPR when used as FPR
# FP registers where integer regs are expected
fcvt.wu.h ft2, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
diff --git a/llvm/test/MC/RISCV/rv32zfinx-invalid.s b/llvm/test/MC/RISCV/rv32zfinx-invalid.s
index a134313fae70e..b5bfd1237ced0 100644
--- a/llvm/test/MC/RISCV/rv32zfinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zfinx-invalid.s
@@ -5,16 +5,16 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fadd.s fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
fmv.x.w s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
fadd.d t1, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer){{$}}
# Invalid register names
-fadd.s a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-fsgnjn.s a100, a2, a3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+fadd.s a100, a2, a3 # CHECK: :[[@LINE]]:8: error: register must be a GPR when used as FPR
+fsgnjn.s a100, a2, a3 # CHECK: :[[@LINE]]:10: error: register must be a GPR when used as FPR
# Rounding mode when a register is expected
-fmadd.s x10, x11, x12, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
+fmadd.s x10, x11, x12, ree # CHECK: :[[@LINE]]:24: error: register must be a GPR when used as FPR
# Invalid rounding modes
fmadd.s x10, x11, x12, x13, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
diff --git a/llvm/test/MC/RISCV/rv32zhinx-invalid.s b/llvm/test/MC/RISCV/rv32zhinx-invalid.s
index 8b87b3279bc39..c4ef52d87ee89 100644
--- a/llvm/test/MC/RISCV/rv32zhinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zhinx-invalid.s
@@ -5,15 +5,15 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fadd.h fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
fmv.x.h s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
# Invalid register names
-fadd.h a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-fsgnjn.h a100, a2, a3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+fadd.h a100, a2, a3 # CHECK: :[[@LINE]]:8: error: register must be a GPR when used as FPR
+fsgnjn.h a100, a2, a3 # CHECK: :[[@LINE]]:10: error: register must be a GPR when used as FPR
# Rounding mode when a register is expected
-fmadd.h x10, x11, x12, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
+fmadd.h x10, x11, x12, ree # CHECK: :[[@LINE]]:24: error: register must be a GPR when used as FPR
# Invalid rounding modes
fmadd.h x10, x11, x12, x13, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
diff --git a/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
index 7d6f1686513a1..8ca26fa59066f 100644
--- a/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
@@ -5,11 +5,11 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fcvt.h.s fa0, fa1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
fmv.x.h s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
# Invalid register names
-fcvt.h.s a100, a1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+fcvt.h.s a100, a1 # CHECK: :[[@LINE]]:10: error: register must be a GPR when used as FPR
# Valid in Zhinx
fmadd.h x10, x11, x12, x13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer){{$}}
diff --git a/llvm/test/MC/RISCV/rv64d-invalid.s b/llvm/test/MC/RISCV/rv64d-invalid.s
index ce41e7f50f5fc..db5b96b9cda52 100644
--- a/llvm/test/MC/RISCV/rv64d-invalid.s
+++ b/llvm/test/MC/RISCV/rv64d-invalid.s
@@ -6,6 +6,12 @@ fcvt.lu.d ft1, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
fmv.x.d ft2, a2 # CHECK: :[[@LINE]]:9: error: register must be a GPR
# FP registers where integer regs are expected
-fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
-fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-fmv.d.x a5, ft5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:10: note: register must be a FPR
+# CHECK: :[[@LINE-2]]:10: note: register must be a GPR when used as FPR
+
+fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:11: note: register must be a FPR
+# CHECK: :[[@LINE-2]]:11: note: register must be a GPR when used as FPR
+
+fmv.d.x a5, ft5 # CHECK: :[[@LINE]]:9: error: register must be a FPR
diff --git a/llvm/test/MC/RISCV/rv64f-invalid.s b/llvm/test/MC/RISCV/rv64f-invalid.s
index 32c1e0e9d9697..4490d708d9bbd 100644
--- a/llvm/test/MC/RISCV/rv64f-invalid.s
+++ b/llvm/test/MC/RISCV/rv64f-invalid.s
@@ -5,5 +5,10 @@ fcvt.l.s ft0, a0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
fcvt.lu.s ft1, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
# FP registers where integer regs are expected
-fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
-fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:10: note: register must be a FPR
+# CHECK: :[[@LINE-2]]:10: note: register must be a GPR when used as FPR
+
+fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:11: note: register must be a FPR
+# CHECK: :[[@LINE-2]]:11: note: register must be a GPR when used as FPR
diff --git a/llvm/test/MC/RISCV/rv64q-invalid.s b/llvm/test/MC/RISCV/rv64q-invalid.s
index 90bb719197b40..cc2b657e3e492 100644
--- a/llvm/test/MC/RISCV/rv64q-invalid.s
+++ b/llvm/test/MC/RISCV/rv64q-invalid.s
@@ -5,5 +5,5 @@ fcvt.l.q ft0, a0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
fcvt.lu.q ft1, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
# FP registers where integer regs are expected
-fcvt.q.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
-fcvt.q.lu a4, ft4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+fcvt.q.l a3, ft3 # CHECK: :[[@LINE]]:10: error: register must be a FPR
+fcvt.q.lu a4, ft4 # CHECK: :[[@LINE]]:11: error: register must be a FPR
diff --git a/llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s b/llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
index 409e729fe222d..47d2e6881bda1 100644
--- a/llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
@@ -2,8 +2,8 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+d -mattr=+xtheadfmemidx < %s 2>&1 | FileCheck %s
th.flrd fa0, a1, a2, 5 # CHECK: :[[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
-th.flrd a0, a1, a2, 3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-th.flrw 0(fa0), a1, a2, 0 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+th.flrd a0, a1, a2, 3 # CHECK: :[[@LINE]]:9: error: register must be a FPR
+th.flrw 0(fa0), a1, a2, 0 # CHECK: :[[@LINE]]:9: error: register must be a FPR
th.flrw fa0, 4(a1), a2, 3 # CHECK: :[[@LINE]]:14: error: register must be a GPR
th.fsrd fa0, a1, -1(a2), 0 # CHECK: :[[@LINE]]:18: error: register must be a GPR
th.fsrd fa0, a1, a2, -3 # CHECK: :[[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
diff --git a/llvm/test/MC/RISCV/rv64zdinx-invalid.s b/llvm/test/MC/RISCV/rv64zdinx-invalid.s
index bf00d215806bd..9c2c38e8d10fa 100644
--- a/llvm/test/MC/RISCV/rv64zdinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zdinx-invalid.s
@@ -5,7 +5,7 @@ fld fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
ld a0, -2049(a1) # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
# Invalid instructions
-fsd a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fsd a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
sd fa4, 64(sp) # CHECK: :[[@LINE]]:4: error: register must be a GPR
fmv.x.d t2, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
fmv.d.x a5, t5 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/rv64zfh-invalid.s b/llvm/test/MC/RISCV/rv64zfh-invalid.s
index f52ff2f806839..1d6166e9dcb1a 100644
--- a/llvm/test/MC/RISCV/rv64zfh-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zfh-invalid.s
@@ -11,5 +11,9 @@ fcvt.l.h ft0, a0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
fcvt.lu.h ft1, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
# FP registers where integer regs are expected
-fcvt.h.l a2, ft2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
-fcvt.h.lu a3, ft3 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+fcvt.h.l a2, ft2 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:10: note: register must be a FPR
+# CHECK: :[[@LINE-2]]:10: note: register must be a GPR when used as FPR
+fcvt.h.lu a3, ft3 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:11: note: register must be a FPR
+# CHECK: :[[@LINE-2]]:11: note: register must be a GPR when used as FPR
diff --git a/llvm/test/MC/RISCV/rv64zfinx-invalid.s b/llvm/test/MC/RISCV/rv64zfinx-invalid.s
index e23726ad9ccf5..b5b4a27df1ab1 100644
--- a/llvm/test/MC/RISCV/rv64zfinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zfinx-invalid.s
@@ -4,7 +4,7 @@
flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
fmv.x.w t2, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
fmv.w.x a5, t5 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/rv64zhinx-invalid.s b/llvm/test/MC/RISCV/rv64zhinx-invalid.s
index a14cba07cfc75..e2fc5151434bc 100644
--- a/llvm/test/MC/RISCV/rv64zhinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zhinx-invalid.s
@@ -4,7 +4,7 @@
flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
# Invalid instructions
-fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
fmv.x.h t2, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
fmv.h.x a5, t5 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
index f7866d906b604..3ec55d2ac3b1b 100644
--- a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
@@ -4,10 +4,10 @@
flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
# Invalid instructions
-fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
fmv.x.h t2, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
fmv.h.x a5, t5 # CHECK: :[[@LINE]]:1: error: invalid instruction
# FP registers where integer regs are expected
-fcvt.d.h a0, fa2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+fcvt.d.h a0, fa2 # CHECK: :[[@LINE]]:10: error: register must be an even-numbered GPR when used as FPR
fcvt.h.d a0, fa2 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/rvzfbfmin-invalid.s b/llvm/test/MC/RISCV/rvzfbfmin-invalid.s
index fc4d36902eee5..cb4b532b557ce 100644
--- a/llvm/test/MC/RISCV/rvzfbfmin-invalid.s
+++ b/llvm/test/MC/RISCV/rvzfbfmin-invalid.s
@@ -12,14 +12,14 @@ fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %
flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: register must be a GPR
# Invalid register names
-flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: register must be a FPR
flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
# Integer registers where FP regs are expected
fmv.x.h fs7, a2 # CHECK: :[[@LINE]]:9: error: register must be a GPR
# FP registers where integer regs are expected
-fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: register must be a FPR
# Attempting to use fcvt instructions from zfhmin
fcvt.s.h fa0, ft0 # CHECK: [[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal)
diff --git a/llvm/test/MC/RISCV/rvzfhmin-invalid.s b/llvm/test/MC/RISCV/rvzfhmin-invalid.s
index 120b854ab9531..5e21f804b4cee 100644
--- a/llvm/test/MC/RISCV/rvzfhmin-invalid.s
+++ b/llvm/test/MC/RISCV/rvzfhmin-invalid.s
@@ -12,14 +12,14 @@ fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %
flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: register must be a GPR
# Invalid register names
-flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: register must be a FPR
flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
# Integer registers where FP regs are expected
fmv.x.h fs7, a2 # CHECK: :[[@LINE]]:9: error: register must be a GPR
# FP registers where integer regs are expected
-fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: register must be a FPR
# Zfh instructions
fmadd.h f10, f11, f12, f13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
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