[llvm] [AMDGPU][GlobalISel] Eliminate READANYLANE round trips in mixed build_vector/merge (PR #210449)

[Petar Avramovic via llvm-commits]

https://github.com/petar-avramovic commented:

mostly looks fine.

Now this comment is not really related to this patch but
copies of large sgpr to vgpr are in general terrible. first (sgpr) reg alloc will try to have contiguous sgprs for copy src even that was not really necessary. Final ISA will end up with bunch of moves for pretty much no reason.
So I was thinking to try and move all large register sgpr to vgpr copies to vgpr by element copy. But then the problem is that there are many regressions in cases where user instr could have used sgpr. So don't know, maybe this kind of combine should happen much later, was thinking near SIFoldOperands

https://github.com/llvm/llvm-project/pull/210449