[llvm] [RISCV] Add macro fusion support for the Xqci extension instructions (PR #209542)

[Sam Elliott via llvm-commits]

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@@ -0,0 +1,120 @@
+//==---- RISCVMacroFusionXQCI.td - Macro Fusions for XQCI -----*- tablegen-*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// ===---------------------------------------------------------------------===//
+// The following definitions describe macro fusion predicators applicable to
+// Xqci instructions.
+
+// Fuse two instructions where the destination register of the first
+// instruction is the same as the destination register of the second
+// instruction.
+class FirstRdEqSecondRdFusion<string name, string fieldName, string desc,
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lenary wrote:

Sorry, I didn't respond on Friday. The situation here is we will have, post-ra:

```
inst0 rd0, rs0
inst1 rd0 // essentially: inst rd0, rd0
```

But of course, this is post-ra, not pre-ra. Pre-ra the dest of inst1 is a different vreg to the dest of inst0.

So yes I think i can see that we end up with both `TieReg` and `SecondInstHasSameReg`. I'll check Pankaj's implementation.

https://github.com/llvm/llvm-project/pull/209542