[llvm] [VPlan] Expand sequential/regular UMin SCEVs in VPSCEVExpander. (PR #209786)

Ramkumar Ramachandra via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 27 10:04:03 PDT 2026


================
@@ -959,19 +975,26 @@ VPValue *VPSCEVExpander::tryToExpand(const SCEV *S) {
       llvm_unreachable("Unexpected min/max SCEV type");
     }
     // Chain operands in reverse order matching SCEVExpander's expansion of
-    // min/max expressions.
-    SmallVector<VPValue *, 2> Ops;
-    for (const SCEVUse &Op : reverse(MinMax->operands())) {
-      VPValue *OpV = tryToExpand(Op);
-      if (!OpV)
+    // min/max expressions. In SafeUDivMode freeze expansion results of operands
+    // other than the first for sequential UMins, to avoid short-circuiting
+    // divide-by-0/poison.
+    bool IsSequential = S->getSCEVType() == scSequentialUMinExpr;
+    Type *ResultTy = MinMax->getType();
+    bool PrevSafeMode = SafeUDivMode;
+    VPValue *Result = nullptr;
+    for (const auto &[I, SCEVOp] : enumerate(reverse(MinMax->operands()))) {
+      bool MayShortCircuit = IsSequential && I != MinMax->getNumOperands() - 1;
+      SafeUDivMode = MayShortCircuit || PrevSafeMode;
+      VPValue *Op = tryToExpand(SCEVOp);
+      SafeUDivMode = PrevSafeMode;
+      if (!Op)
         return nullptr;
-      Ops.push_back(OpV);
----------------
artagnon wrote:

Hm, we're not collecting ops as before, potentially creating dead instructions, but it shouldn't be a problem with our AddRec patch nearly ready?

https://github.com/llvm/llvm-project/pull/209786


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