[llvm] [RISCV] Declare TLSDESC clobbers for vector registers and CSRs per psABI (PR #205027)

[via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv64 -mattr=+v -relocation-model=pic -enable-tlsdesc < %s \
+; RUN:     | FileCheck %s --check-prefix=RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v -relocation-model=pic -enable-tlsdesc < %s \
+; RUN:     | FileCheck %s --check-prefix=RV32
+
+;; Verify that when the V extension is enabled, vector registers whose live
+;; ranges span a TLSDESC call are spilled and reloaded, because the TLSDESC
+;; resolver clobbers all vector registers per the psABI.
+
+ at tls_var = external thread_local global i32
+
+define void @test_vector_reg_clobber() nounwind {
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LukeZhuang wrote:

Thanks for the suggestion! I will follow that

https://github.com/llvm/llvm-project/pull/205027