[llvm] [SLP] Use constant 64-bit indices for Extract/InsertElement (PR #208957)
Andreas Jonson via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 11 15:00:40 PDT 2026
https://github.com/andjo403 created https://github.com/llvm/llvm-project/pull/208957
The canonical form preferred by instCombine is to use 64-bit values for constant index in ExtractElement and InsertElement see
https://github.com/llvm/llvm-project/blob/9d5d8834793da9efe297620db3ef39633688f830/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp#L401-L411
>From efdcc042aca5025b730377ffb6fece794b3880c1 Mon Sep 17 00:00:00 2001
From: Andreas Jonson <andjo403 at hotmail.com>
Date: Sat, 11 Jul 2026 23:59:12 +0200
Subject: [PATCH] [SLP] Use constant 64-bit indices for Extract/InsertElement
---
.../Transforms/Vectorize/SLPVectorizer.cpp | 7 +-
.../AArch64/InstructionsState-is-invalid-0.ll | 8 +-
.../SLPVectorizer/AArch64/commute.ll | 8 +-
.../AArch64/div-like-mixed-with-undefs.ll | 18 +-
.../Transforms/SLPVectorizer/AArch64/div.ll | 8 +-
.../AArch64/externally-used-copyables.ll | 62 +++----
.../AArch64/extract-subvector-long-input.ll | 2 +-
.../AArch64/extractelements-to-shuffle.ll | 4 +-
.../AArch64/fma-conversion-multi-use-guard.ll | 2 +-
.../AArch64/fma-reduce-regression.ll | 2 +-
.../SLPVectorizer/AArch64/fmulladd.ll | 2 +-
...ather-buildvector-with-minbitwidth-user.ll | 32 ++--
.../SLPVectorizer/AArch64/gather-cost.ll | 8 +-
.../SLPVectorizer/AArch64/gather-reduce.ll | 64 +++----
.../SLPVectorizer/AArch64/getelementptr.ll | 36 ++--
.../SLPVectorizer/AArch64/getelementptr2.ll | 16 +-
.../SLPVectorizer/AArch64/landing_pad.ll | 12 +-
.../SLPVectorizer/AArch64/loadi8.ll | 4 +-
.../AArch64/long-non-power-of-2.ll | 22 +--
.../SLPVectorizer/AArch64/matmul.ll | 8 +-
.../AArch64/memory-runtime-checks.ll | 8 +-
.../non-inst-abs-sub-copyable-value.ll | 6 +-
.../non-power-of-2-with-adjusted-gathers.ll | 8 +-
.../AArch64/phi-node-bitwidt-op-not.ll | 14 +-
.../AArch64/recalc-copyable-node.ll | 14 +-
.../SLPVectorizer/AArch64/reduce-fadd.ll | 8 +-
.../AArch64/reorder-fmuladd-crash.ll | 4 +-
.../AArch64/reused-scalar-repeated-in-node.ll | 42 ++---
.../AArch64/scalarization-overhead.ll | 10 +-
.../AArch64/shuffle-vectors-mask-size.ll | 2 +-
...p-extval-struct-operand-no-scalar-reuse.ll | 4 +-
.../SLPVectorizer/AArch64/slp-fma-loss.ll | 6 +-
.../AArch64/spillcost-loop-backedge.ll | 4 +-
.../AArch64/spillcost-noreturn-block.ll | 8 +-
.../SLPVectorizer/AArch64/splat-loads.ll | 16 +-
.../AArch64/transpose-with-constants.ll | 4 +-
.../SLPVectorizer/AArch64/trunc-insertion.ll | 4 +-
.../SLPVectorizer/AArch64/tsc-s116.ll | 2 +-
.../SLPVectorizer/AArch64/tsc-s352.ll | 8 +-
.../SLPVectorizer/AArch64/unique_values.ll | 2 +-
.../SLPVectorizer/AArch64/uselistorder.ll | 4 +-
.../SLPVectorizer/AArch64/vec3-base.ll | 2 +-
.../SLPVectorizer/AArch64/vec3-calls.ll | 4 +-
.../AArch64/vec3-reorder-reshuffle.ll | 44 ++---
.../vectorizable-selects-uniform-cmps.ll | 16 +-
.../SLPVectorizer/AMDGPU/horizontal-store.ll | 16 +-
.../AMDGPU/inst-count-heuristic.ll | 32 ++--
...otriviallyvectorizableintrinsicoperands.ll | 48 ++---
.../SLPVectorizer/AMDGPU/packed-math.ll | 6 +-
.../SLPVectorizer/AMDGPU/slp-v2f16.ll | 8 +-
.../RISCV/basic-strided-loads.ll | 4 +-
.../RISCV/buildvector-all-external-scalars.ll | 28 +--
.../SLPVectorizer/RISCV/complex-loads.ll | 120 ++++++-------
.../SLPVectorizer/RISCV/fmuladd_width_prop.ll | 14 +-
.../RISCV/gather-insert-point-restore.ll | 2 +-
.../RISCV/gather-node-with-no-users.ll | 2 +-
.../SLPVectorizer/RISCV/loads-ordering.ll | 2 +-
.../RISCV/mixed-extracts-types.ll | 4 +-
...on-commutative-second-arg-only-copyable.ll | 4 +-
.../RISCV/partial-vec-invalid-cost.ll | 8 +-
.../SLPVectorizer/RISCV/reductions.ll | 10 +-
.../remark-zext-incoming-for-neg-icmp.ll | 4 +-
.../RISCV/remarks-insert-into-small-vector.ll | 2 +-
.../RISCV/reordered-buildvector-scalars.ll | 40 ++---
.../RISCV/reordered-interleaved-loads.ll | 38 ++--
.../SLPVectorizer/RISCV/revec-strided-load.ll | 8 +-
.../Transforms/SLPVectorizer/RISCV/revec.ll | 12 +-
...reversed-strided-node-with-external-ptr.ll | 6 +-
.../RISCV/rotated-strided-loads.ll | 4 +-
.../RISCV/runtime-strided-stores.ll | 164 +++++++++---------
.../RISCV/scatter-vectorize-reversed.ll | 2 +-
.../RISCV/select-profitability.ll | 8 +-
.../RISCV/shuffled-gather-casted.ll | 2 +-
.../smax-reduction-unsigned-missing-sign.ll | 2 +-
.../smin-reduction-unsigned-missing-sign.ll | 2 +-
.../RISCV/smin-signed-zextended.ll | 4 +-
.../split-vectorize-parent-for-copyables.ll | 4 +-
.../strided-loads-with-external-indices.ll | 4 +-
.../strided-loads-with-external-use-ptr.ll | 4 +-
.../RISCV/strided-unsupported-type.ll | 4 +-
.../RISCV/trunc-bv-multi-uses.ll | 8 +-
.../RISCV/unsigned-icmp-signed-op.ll | 4 +-
.../unsigned-node-trunc-with-signed-users.ll | 2 +-
.../SLPVectorizer/RISCV/vec3-base.ll | 4 +-
.../SLPVectorizer/SystemZ/cmp-ptr-minmax.ll | 14 +-
.../SystemZ/ext-alt-node-must-ext.ll | 8 +-
.../SystemZ/ext-not-resized-op-resized.ll | 6 +-
.../SystemZ/minbitwidth-root-trunc.ll | 4 +-
.../SystemZ/minbitwidth-trunc.ll | 2 +-
.../SystemZ/non-power-2-subvector-extract.ll | 12 +-
.../SLPVectorizer/SystemZ/pr34619.ll | 4 +-
.../SLPVectorizer/SystemZ/reductions-fadd.ll | 48 ++---
.../SystemZ/reductions-fmin-fmax.ll | 112 ++++++------
.../SLPVectorizer/SystemZ/reductions-fmul.ll | 48 ++---
.../SystemZ/reuse-non-power-of-2-reorder.ll | 12 +-
.../SystemZ/vec-elt-insertion.ll | 16 +-
.../WebAssembly/or-reduction-zero-test.ll | 12 +-
.../WebAssembly/simd-splat-shuffle-cost.ll | 8 +-
.../Transforms/SLPVectorizer/X86/PR35628_1.ll | 4 +-
.../Transforms/SLPVectorizer/X86/PR35628_2.ll | 6 +-
.../Transforms/SLPVectorizer/X86/PR35777.ll | 2 +-
.../Transforms/SLPVectorizer/X86/PR39774.ll | 8 +-
.../Transforms/SLPVectorizer/X86/PR40310.ll | 8 +-
.../SLPVectorizer/X86/add-sub-nsw-intmin.ll | 16 +-
.../X86/alternate-cmp-swapped-pred.ll | 4 +-
.../X86/alternate-int-inseltpoison.ll | 10 +-
.../SLPVectorizer/X86/alternate-int.ll | 10 +-
...ernate-opcode-strict-bitwidth-than-main.ll | 6 +-
.../X86/ashr-main-opcode-copyables.ll | 8 +-
.../SLPVectorizer/X86/bad-reduction.ll | 2 +-
.../SLPVectorizer/X86/barriercall.ll | 2 +-
.../X86/blending-shuffle-inseltpoison.ll | 12 +-
.../SLPVectorizer/X86/blending-shuffle.ll | 14 +-
.../SLPVectorizer/X86/broadcast-load-cost.ll | 6 +-
.../Transforms/SLPVectorizer/X86/broadcast.ll | 14 +-
.../SLPVectorizer/X86/broadcast_long.ll | 2 +-
.../buildvector-reused-with-bv-subvector.ll | 6 +-
.../X86/buildvector-same-lane-insert.ll | 8 +-
.../X86/buildvector-schedule-for-subvector.ll | 2 +-
.../X86/buildvector-shuffle-with-root.ll | 2 +-
.../SLPVectorizer/X86/buildvector-shuffle.ll | 12 +-
.../X86/buildvector-store-chains.ll | 56 +++---
.../X86/buildvector-with-reuses.ll | 10 +-
.../X86/buildvectors-parent-phi-nodes.ll | 6 +-
.../X86/buildvectors-with-same-parents.ll | 2 +-
.../X86/bv-root-part-of-graph.ll | 2 +-
.../SLPVectorizer/X86/bv-shuffle-mask.ll | 14 +-
.../Transforms/SLPVectorizer/X86/c-ray.ll | 44 ++---
.../test/Transforms/SLPVectorizer/X86/call.ll | 8 +-
.../X86/cast-operand-extracted.ll | 10 +-
.../cmp-after-intrinsic-call-minbitwidth.ll | 4 +-
.../SLPVectorizer/X86/cmp-as-alternate-ops.ll | 8 +-
.../Transforms/SLPVectorizer/X86/cmp_sel.ll | 2 +-
...ommutable-member-in-non-commutable-node.ll | 2 +-
.../commutable-node-with-non-sched-parent.ll | 6 +-
.../commutative-copyable-external-phi-use.ll | 2 +-
.../SLPVectorizer/X86/commutativity.ll | 18 +-
.../X86/compare-node-with-reuses.ll | 16 +-
.../SLPVectorizer/X86/compare-reduce.ll | 6 +-
.../SLPVectorizer/X86/complex-fma-combine.ll | 2 +-
.../SLPVectorizer/X86/control-dependence.ll | 40 ++---
.../SLPVectorizer/X86/conversion-fp16.ll | 8 +-
.../X86/copyable-child-node-used-outside.ll | 2 +-
.../X86/copyable-non-inst-in-stores.ll | 2 +-
...yable-operand-non-scheduled-parent-node.ll | 2 +-
.../X86/copyable-operands-reordering.ll | 6 +-
.../copyable-phi-scheduled-non-copyable.ll | 4 +-
.../X86/copyable-phi-used-non-copyable.ll | 4 +-
.../X86/copyable-reduced-erased.ll | 4 +-
...copyable-used-outside-with-immediate-op.ll | 4 +-
...copyable-with-non-scheduled-parent-node.ll | 2 +-
.../X86/copyable-with-used-outside-bb.ll | 4 +-
.../SLPVectorizer/X86/copyable_reorder.ll | 68 ++++----
.../copyables-with-parent-scalars-in-phis.ll | 4 +-
.../SLPVectorizer/X86/crash_bullet.ll | 38 ++--
.../SLPVectorizer/X86/crash_clear_undefs.ll | 2 +-
.../SLPVectorizer/X86/crash_cmpop.ll | 8 +-
.../SLPVectorizer/X86/crash_dequeue.ll | 10 +-
.../SLPVectorizer/X86/crash_mandeltext.ll | 20 +--
.../X86/crash_scheduling-inseltpoison.ll | 6 +-
.../SLPVectorizer/X86/crash_scheduling.ll | 6 +-
.../SLPVectorizer/X86/crash_sim4b1.ll | 34 ++--
.../SLPVectorizer/X86/crash_vectorizeTree.ll | 10 +-
llvm/test/Transforms/SLPVectorizer/X86/cse.ll | 18 +-
.../SLPVectorizer/X86/debug-counter.ll | 26 +--
.../SLPVectorizer/X86/debug-info-salvage.ll | 20 +--
.../X86/delayed-gather-emission.ll | 12 +-
.../X86/deleted-inst-reduction-attempt.ll | 12 +-
.../X86/deleted-instructions-clear.ll | 20 +--
.../deleted-node-with-copyable-operands.ll | 8 +-
.../Transforms/SLPVectorizer/X86/diamond.ll | 6 +-
.../X86/diamond_broadcast_extra_shuffle.ll | 6 +-
.../X86/div-possibly-extended-with-poisons.ll | 6 +-
.../SLPVectorizer/X86/dot-product.ll | 56 +++---
.../SLPVectorizer/X86/entries-different-vf.ll | 6 +-
.../X86/entries-shuffled-diff-sizes.ll | 4 +-
.../entry-no-bundle-but-extra-use-on-vec.ll | 12 +-
...expanded-binop-doesnotneedschedule-user.ll | 2 +-
.../X86/expanded-operand-already-scheduled.ll | 4 +-
.../X86/expected-prof-consecutive-access.ll | 4 +-
.../X86/ext-used-scalar-different-bitwidth.ll | 2 +-
.../SLPVectorizer/X86/external-bin-op-user.ll | 10 +-
.../X86/external-reduced-value-vectorized.ll | 6 +-
.../SLPVectorizer/X86/external_user.ll | 2 +-
.../X86/extract-scalar-from-undef.ll | 2 +-
.../X86/extract-subvector-long-input.ll | 2 +-
.../X86/extract-used-in-many-nodes.ll | 4 +-
.../SLPVectorizer/X86/extract_in_tree_user.ll | 6 +-
.../SLPVectorizer/X86/extractcost.ll | 4 +-
.../X86/extractelement-multi-register-use.ll | 8 +-
.../X86/extractelement-multiple-uses.ll | 4 +-
.../extractelement-single-use-many-nodes.ll | 4 +-
.../SLPVectorizer/X86/extractelement.ll | 32 ++--
.../extractelements-subnodes-same-index.ll | 20 +--
.../X86/extractelements-with-undef-vector.ll | 6 +-
.../X86/extractelemets-extended-by-poison.ll | 4 +-
.../X86/extracts-non-extendable.ll | 4 +-
.../SLPVectorizer/X86/fabs-cost-softfp.ll | 8 +-
.../SLPVectorizer/X86/fptosi-inseltpoison.ll | 16 +-
.../Transforms/SLPVectorizer/X86/fptosi.ll | 16 +-
.../X86/full-match-with-poison-scalar.ll | 2 +-
.../X86/full-matched-bv-with-subvectors.ll | 6 +-
.../X86/full-non-schedulable-overlap.ll | 6 +-
.../X86/gather-move-out-of-loop.ll | 2 +-
.../X86/gather-node-same-as-vect-but-order.ll | 8 +-
.../SLPVectorizer/X86/gather-with-cmp-user.ll | 2 +-
...gathered-delayed-nodes-with-reused-user.ll | 4 +-
.../X86/gathered-loads-non-full-reg.ll | 16 +-
.../X86/gathered-node-with-in-order-parent.ll | 2 +-
.../Transforms/SLPVectorizer/X86/hoist.ll | 4 +-
.../SLPVectorizer/X86/horizontal-list.ll | 24 +--
.../SLPVectorizer/X86/horizontal-minmax.ll | 20 +--
.../SLPVectorizer/X86/horizontal.ll | 4 +-
.../X86/icmp-altopcode-after-reordering.ll | 2 +-
.../X86/identity-match-splat-less-defined.ll | 2 +-
.../SLPVectorizer/X86/in-tree-user.ll | 6 +-
.../SLPVectorizer/X86/insert-after-bundle.ll | 2 +-
.../SLPVectorizer/X86/insert-subvector.ll | 4 +-
.../X86/insertelement-with-copyable-args.ll | 6 +-
.../SLPVectorizer/X86/insertvalue.ll | 28 +--
.../SLPVectorizer/X86/inst_size_bug.ll | 2 +-
.../X86/inversed-icmp-to-gather.ll | 2 +-
.../X86/landing-pad-for-split-node.ll | 16 +-
.../SLPVectorizer/X86/landing_pad.ll | 12 +-
.../X86/load-merge-inseltpoison.ll | 8 +-
.../SLPVectorizer/X86/load-merge.ll | 8 +-
.../Transforms/SLPVectorizer/X86/lookahead.ll | 24 +--
.../SLPVectorizer/X86/loopinvariant.ll | 2 +-
.../SLPVectorizer/X86/malformed_phis.ll | 6 +-
.../X86/many-uses-parent-node.ll | 4 +-
.../X86/matched-bv-schedulable.ll | 6 +-
.../X86/matched-gather-part-of-combined.ll | 2 +-
.../X86/matched-nodes-updated.ll | 12 +-
.../X86/matched-shuffled-entries.ll | 12 +-
.../X86/matching-gather-nodes-phi-users.ll | 8 +-
.../X86/matching-insert-point-for-nodes.ll | 16 +-
.../X86/memory-runtime-checks.ll | 2 +-
.../SLPVectorizer/X86/minbitwidth-cast.ll | 6 +-
.../X86/minbitwidth-drop-wrapping-flags.ll | 2 +-
.../X86/minbitwidth-icmp-to-trunc.ll | 8 +-
.../X86/minbitwidth-transformed-operand.ll | 2 +-
.../SLPVectorizer/X86/minbw-bitcast-to-fp.ll | 2 +-
.../SLPVectorizer/X86/minimum-sizes.ll | 16 +-
.../SLPVectorizer/X86/mul-shl-nsw-intmin.ll | 12 +-
.../X86/multi-extracts-bv-combined.ll | 2 +-
.../X86/multi-node-for-copyable-parent.ll | 4 +-
.../X86/multi-node-reuse-in-bv.ll | 2 +-
.../X86/multi-node-user-with-copyable-ops.ll | 6 +-
.../X86/multi-nodes-to-shuffle.ll | 16 +-
.../multi-parent-instr-copyable-regular.ll | 12 +-
.../X86/multi-use-bitcasted-reduction.ll | 24 +--
.../SLPVectorizer/X86/multi_user.ll | 2 +-
.../SLPVectorizer/X86/no_alternate_divrem.ll | 16 +-
.../non-commutative-op-in-commutative-inst.ll | 4 +-
.../X86/non-power-2-num-elems-reused.ll | 2 +-
.../SLPVectorizer/X86/non-power-of-2-bswap.ll | 2 +-
.../X86/non-power-of-2-order-detection.ll | 8 +-
.../X86/non-reduced-select-of-bits.ll | 4 +-
.../X86/non-schedulable-before-main.ll | 2 +-
...dulable-instructions-become-schedulable.ll | 2 +-
.../non-schedulable-parent-multi-copyables.ll | 6 +-
.../X86/non-schedulable-split-node.ll | 8 +-
.../X86/non-schedulable-user-different-bb.ll | 6 +-
.../X86/non-scheduled-inst-extern-use.ll | 2 +-
.../non-scheduled-inst-reused-as-last-inst.ll | 2 +-
.../X86/non-vectorizable-inst-operand.ll | 36 ++--
.../Transforms/SLPVectorizer/X86/odd_store.ll | 6 +-
.../SLPVectorizer/X86/opaque-ptr.ll | 12 +-
.../X86/operand-reorder-with-copyables.ll | 24 +--
.../SLPVectorizer/X86/operandorder.ll | 44 ++---
.../X86/ordered-reduction-root-deleted.ll | 12 +-
.../SLPVectorizer/X86/ordered-reductions.ll | 4 +-
.../SLPVectorizer/X86/ordering-bug.ll | 6 +-
.../original-inst-scheduled-after-copyable.ll | 8 +-
...t-node-schedulable-with-multi-copyables.ll | 26 +--
.../X86/parent-node-split-non-schedulable.ll | 36 ++--
.../X86/parent-phi-node-reordered.ll | 8 +-
.../X86/phi-node-bitwidt-op-not.ll | 14 +-
.../SLPVectorizer/X86/phi-node-with-cycle.ll | 6 +-
llvm/test/Transforms/SLPVectorizer/X86/phi.ll | 2 +-
.../test/Transforms/SLPVectorizer/X86/phi3.ll | 12 +-
.../SLPVectorizer/X86/phi_landingpad.ll | 4 +-
.../SLPVectorizer/X86/phi_overalignedtype.ll | 14 +-
.../SLPVectorizer/X86/phis-different-order.ll | 2 +-
.../X86/poor-throughput-seeds.ll | 72 ++++----
.../Transforms/SLPVectorizer/X86/pr27163.ll | 6 +-
.../Transforms/SLPVectorizer/X86/pr35497.ll | 4 +-
.../Transforms/SLPVectorizer/X86/pr40522.ll | 32 ++--
.../SLPVectorizer/X86/pr42022-inseltpoison.ll | 38 ++--
.../Transforms/SLPVectorizer/X86/pr42022.ll | 38 ++--
.../SLPVectorizer/X86/pr44067-inseltpoison.ll | 16 +-
.../Transforms/SLPVectorizer/X86/pr44067.ll | 16 +-
.../Transforms/SLPVectorizer/X86/pr46983.ll | 24 +--
.../SLPVectorizer/X86/pr47629-inseltpoison.ll | 108 ++++++------
.../Transforms/SLPVectorizer/X86/pr47629.ll | 108 ++++++------
.../Transforms/SLPVectorizer/X86/pr47642.ll | 4 +-
.../SLPVectorizer/X86/propagate-mmra.ll | 2 +-
...opyable-operand-deps-non-scheduled-node.ll | 4 +-
...ecalc-copyable-operand-deps-shared-inst.ll | 10 +-
.../reduced-bswap-with-larger-reduced-type.ll | 2 +-
...duced-val-extracted-and-externally-used.ll | 6 +-
...duced-value-replace-extractelement-cost.ll | 2 +-
.../reduced-value-replace-extractelement.ll | 6 +-
.../SLPVectorizer/X86/reduced-value-stored.ll | 6 +-
.../X86/reduction-across-different-bb.ll | 12 +-
.../X86/reduction-bool-logic-op-inside.ll | 8 +-
.../X86/reduction-copyable-reused-scalars.ll | 6 +-
.../SLPVectorizer/X86/reduction-logical.ll | 28 +--
.../SLPVectorizer/X86/reduction-same-vals.ll | 2 +-
.../X86/reduction-shl1-add-merge.ll | 8 +-
.../X86/reduction-with-removed-extracts.ll | 4 +-
.../Transforms/SLPVectorizer/X86/reduction.ll | 4 +-
.../SLPVectorizer/X86/reduction2.ll | 28 +--
.../X86/redux-feed-buildvector.ll | 2 +-
.../X86/remark-partial-loads-vectorize.ll | 4 +-
.../X86/remark_gather-load-redux-cost.ll | 2 +-
.../SLPVectorizer/X86/remark_not_all_parts.ll | 4 +-
.../X86/reorder-possible-strided-node.ll | 16 +-
.../X86/reorder-reused-subvector.ll | 28 +--
.../X86/reorder_diamond_match.ll | 8 +-
.../SLPVectorizer/X86/reorder_phi.ll | 4 +-
.../X86/reorder_with_external_users.ll | 24 +--
.../X86/replaced-external-in-reduction.ll | 6 +-
.../Transforms/SLPVectorizer/X86/resched.ll | 4 +-
.../X86/reschedule-only-scheduled.ll | 4 +-
.../resized-bv-values-non-power-of2-node.ll | 20 +--
.../X86/reused-extract-scalar-lanes.ll | 4 +-
.../SLPVectorizer/X86/reused-extracts.ll | 4 +-
.../reused-last-instruction-in-split-node.ll | 8 +-
.../X86/reused-mask-with-poison-index.ll | 8 +-
.../X86/reused-reductions-with-minbitwidth.ll | 2 +-
.../X86/reused-scalars-in-buildvector.ll | 12 +-
.../SLPVectorizer/X86/reused-undefs.ll | 4 +-
.../SLPVectorizer/X86/revec-fma-vectorize.ll | 2 +-
...revec-non-power-2-to-power-2-large-vect.ll | 16 +-
...ec-reduced-value-replace-extractelement.ll | 6 +-
.../X86/revec-scalar-insertelement.ll | 2 +-
...same-last-instruction-different-parents.ll | 6 +-
.../X86/same-operands-but-copyable.ll | 2 +-
.../X86/same-values-sub-node-with-poisons.ll | 6 +-
.../Transforms/SLPVectorizer/X86/saxpy.ll | 2 +-
.../scatter-vectorize-reorder-non-empty.ll | 2 +-
.../X86/scatter-vectorize-reorder.ll | 4 +-
.../SLPVectorizer/X86/schedule_budget.ll | 8 +-
.../X86/select-copyable-cmp-poison.ll | 8 +-
.../X86/select-logical-or-and-i1-vector.ll | 60 +++----
.../SLPVectorizer/X86/select-reduction-op.ll | 2 +-
.../X86/shl-compatible-with-add.ll | 6 +-
.../X86/shl-to-add-transformation.ll | 6 +-
.../X86/shl-to-add-transformation5.ll | 26 +--
.../X86/shuffle-mask-emission.ll | 4 +-
.../X86/sibling-loops-mismatched-tripcount.ll | 22 +--
.../Transforms/SLPVectorizer/X86/simplebb.ll | 4 +-
.../SLPVectorizer/X86/sitofp-inseltpoison.ll | 24 +--
.../X86/sitofp-minbitwidth-node.ll | 4 +-
.../Transforms/SLPVectorizer/X86/sitofp.ll | 32 ++--
.../SLPVectorizer/X86/slp-fma-loss.ll | 8 +-
.../SLPVectorizer/X86/slp-throttle.ll | 2 +-
.../small-graph-diff-block-instructions.ll | 6 +-
.../X86/split-load8_2_unord_geps.ll | 2 +-
.../X86/split-node-full-match.ll | 12 +-
.../X86/split-node-last-inst-vectorized.ll | 4 +-
.../X86/split-node-no-reorder-copy.ll | 10 +-
.../X86/split-node-num-operands.ll | 22 +--
.../split-node-parent-operands-in-spill.ll | 8 +-
.../X86/split-node-reduce-root.ll | 2 +-
.../X86/split-node-reorder-node-with-ops.ll | 48 ++---
.../X86/split-node-reused-in-later-vector.ll | 6 +-
.../SLPVectorizer/X86/split-node-throttled.ll | 4 +-
.../X86/split-vector-operand-with-reuses.ll | 2 +-
.../split-vectorize-gathered-def-after-use.ll | 18 +-
.../SLPVectorizer/X86/stacksave-dependence.ll | 24 +--
.../X86/store-load-forward-conflict.ll | 24 +--
.../SLPVectorizer/X86/stores_vectorize.ll | 2 +-
.../X86/struct-return-extract-dominance.ll | 16 +-
.../X86/struct-return-ordering-stress.ll | 8 +-
.../subvector-minbitwidth-unsigned-value.ll | 24 +--
.../Transforms/SLPVectorizer/X86/supernode.ll | 4 +-
.../Transforms/SLPVectorizer/X86/tiny-tree.ll | 14 +-
.../trunc-store-value-ty-not-power-of-2.ll | 4 +-
.../trunced-buildvector-scalar-extended.ll | 6 +-
.../X86/uitofp-with-signed-value-bitwidth.ll | 6 +-
.../SLPVectorizer/X86/used-reduced-op.ll | 114 ++++++------
.../X86/user-node-with-same-last-instr.ll | 4 +-
.../X86/user-with-multi-copyable-ops.ll | 8 +-
.../Transforms/SLPVectorizer/X86/vec3-base.ll | 6 +-
.../SLPVectorizer/X86/vec3-calls.ll | 4 +-
.../X86/vec3-gather-some-loads.ll | 18 +-
.../X86/vec3-reorder-reshuffle.ll | 48 ++---
.../X86/vec_list_bias-inseltpoison.ll | 8 +-
.../SLPVectorizer/X86/vec_list_bias.ll | 8 +-
.../vec_list_bias_external_insert_shuffled.ll | 8 +-
.../X86/vect-gather-same-nodes.ll | 4 +-
.../SLPVectorizer/X86/vectorize-pair-path.ll | 12 +-
.../X86/vectorize-widest-phis.ll | 8 +-
.../X86/whole-registers-compare.ll | 4 +-
.../SLPVectorizer/X86/xor-combined-opcode.ll | 6 +-
.../X86/xor-with-zero-and-incompat.ll | 4 +-
.../abs-overflow-incorrect-minbws.ll | 6 +-
.../SLPVectorizer/alt-cmp-vectorize.ll | 4 +-
.../alternate-cmp-swapped-pred-parent.ll | 16 +-
.../SLPVectorizer/alternate-non-profitable.ll | 12 +-
.../bool-logical-op-reduction-with-poison.ll | 6 +-
.../buildvector-nodes-dependency.ll | 12 +-
.../call-arg-reduced-by-minbitwidth.ll | 4 +-
.../SLPVectorizer/consecutive-access.ll | 12 +-
.../SLPVectorizer/crash_exceed_scheduling.ll | 16 +-
.../crash_extractelement_poison.ll | 6 +-
.../SLPVectorizer/diamond_broadcast.ll | 2 +-
.../SLPVectorizer/ext-after-phi-node.ll | 4 +-
.../ext-int-reduced-not-operand.ll | 6 +-
.../extended-vectorized-gathered-inst.ll | 4 +-
.../external-user-instruction-minbitwidth.ll | 4 +-
.../extract-many-users-buildvector.ll | 16 +-
.../extractelement-insertpoint.ll | 4 +-
.../SLPVectorizer/extracts-with-undefs.ll | 4 +-
.../SLPVectorizer/freeze-signedness-missed.ll | 4 +-
.../gather_extract_from_vectorbuild.ll | 4 +-
...hered-consecutive-loads-different-types.ll | 12 +-
...nsert-element-build-vector-inseltpoison.ll | 8 +-
.../insert-element-build-vector.ll | 8 +-
.../SLPVectorizer/insert-shuffle.ll | 4 +-
.../insertelement-across-zero.ll | 4 +-
.../SLPVectorizer/insertelement-postpone.ll | 12 +-
.../insertelement-uses-vectorized-index.ll | 2 +-
.../SLPVectorizer/int-bitcast-minbitwidth.ll | 2 +-
.../SLPVectorizer/jumbled_store_crash.ll | 12 +-
.../SLPVectorizer/last-buildvector-node.ll | 6 +-
.../materialize-vector-of-consts.ll | 28 +--
...minbitwidth-multiuse-with-insertelement.ll | 6 +-
.../SLPVectorizer/minbitwidth-user-not-min.ll | 2 +-
.../multi-node-vectorized-insts.ll | 6 +-
.../multi-uses-with-deps-in-first.ll | 2 +-
.../SLPVectorizer/operand-is-reduced-val.ll | 4 +-
.../SLPVectorizer/partial-register-extract.ll | 4 +-
.../SLPVectorizer/phi-undef-input.ll | 48 ++---
.../SLPVectorizer/postponed_gathers.ll | 2 +-
.../reduced-gathered-vectorized.ll | 8 +-
.../SLPVectorizer/reorder-clustered-node.ll | 20 +--
.../SLPVectorizer/reordered-top-scalars.ll | 4 +-
.../SLPVectorizer/reordering-single-phi.ll | 2 +-
.../Transforms/SLPVectorizer/reschedule.ll | 8 +-
.../resized-alt-shuffle-after-minbw.ll | 86 ++++-----
llvm/test/Transforms/SLPVectorizer/return.ll | 8 +-
.../reudction-or-non-poisoned.ll | 8 +-
...ed-buildvector-matching-vectorized-node.ll | 4 +-
llvm/test/Transforms/SLPVectorizer/revec.ll | 4 +-
.../SLPVectorizer/root-trunc-extract-reuse.ll | 6 +-
.../same-scalar-in-same-phi-extract.ll | 8 +-
.../SLPVectorizer/semanticly-same.ll | 8 +-
.../SLPVectorizer/shrink_after_reorder2.ll | 2 +-
.../SLPVectorizer/shuffle-multivector.ll | 8 +-
.../SLPVectorizer/shufflebuilder-bug.ll | 2 +-
.../SLPVectorizer/slp-deleted-inst.ll | 6 +-
.../SLPVectorizer/slp-max-phi-size.ll | 42 ++---
.../SLPVectorizer/splat-buildvector.ll | 4 +-
.../SLPVectorizer/stores-non-ordered.ll | 16 +-
.../SLPVectorizer/unknown-entries.ll | 2 +-
.../vectorize-reorder-alt-shuffle.ll | 4 +-
.../zext-incoming-for-neg-icmp.ll | 4 +-
460 files changed, 2737 insertions(+), 2736 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 48fb4beba6935..142fd2ad29907 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -22145,7 +22145,7 @@ Value *BoUpSLP::gather(
return Vec;
InsElt = II;
} else {
- Vec = Builder.CreateInsertElement(Vec, Scalar, Builder.getInt32(Pos));
+ Vec = Builder.CreateInsertElement(Vec, Scalar, Pos);
InsElt = dyn_cast<InsertElementInst>(Vec);
if (!InsElt)
return Vec;
@@ -25002,7 +25002,6 @@ Value *BoUpSLP::vectorizeTree(
Value *Vec = E->VectorizedValue;
assert(Vec && "Can't find vectorizable value");
- Value *Lane = Builder.getInt32(ExternalUse.Lane);
auto ExtractAndExtendIfNeeded = [&](Value *Vec) {
if (isa<InsertValueInst>(Scalar))
return Vec;
@@ -25087,7 +25086,7 @@ Value *BoUpSLP::vectorizeTree(
IV->comesBefore(IVec))
Ex = Builder.CreateExtractElement(V, ES->getIndexOperand());
else
- Ex = Builder.CreateExtractElement(Vec, Lane);
+ Ex = Builder.CreateExtractElement(Vec, ExternalUse.Lane);
} else if (auto *VecTy =
dyn_cast<FixedVectorType>(Scalar->getType())) {
assert(SLPReVec && "FixedVectorType is not expected.");
@@ -25131,7 +25130,7 @@ Value *BoUpSLP::vectorizeTree(
Ex = createExtractVector(Builder, Vec, VecTyNumElements,
ExternalUse.Lane * VecTyNumElements);
} else {
- Ex = Builder.CreateExtractElement(Vec, Lane);
+ Ex = Builder.CreateExtractElement(Vec, ExternalUse.Lane);
}
}
// If necessary, sign-extend or zero-extend ScalarRoot
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/InstructionsState-is-invalid-0.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/InstructionsState-is-invalid-0.ll
index 0f4e0ed31a554..2fc7f92a52b49 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/InstructionsState-is-invalid-0.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/InstructionsState-is-invalid-0.ll
@@ -9,13 +9,13 @@ define void @foo(ptr %0) {
; CHECK-NEXT: vector.scevcheck:
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 4
; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr null, i64 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP0]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x ptr> [[TMP1]], ptr [[SCEVGEP]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x ptr> [[TMP1]], ptr [[SCEVGEP]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x ptr> [[TMP2]], <4 x ptr> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT: [[TMP4:%.*]] = icmp ult <4 x ptr> [[TMP3]], splat (ptr null)
; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i1> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x ptr> [[TMP6]], ptr [[SCEVGEP3]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x ptr> [[TMP6]], ptr [[SCEVGEP3]], i64 1
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x ptr> [[TMP7]], <4 x ptr> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT: [[TMP9:%.*]] = icmp ult <4 x ptr> [[TMP8]], splat (ptr null)
; CHECK-NEXT: [[TMP10:%.*]] = and <4 x i1> [[TMP9]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/commute.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/commute.ll
index d6756cc9c88dd..19591818c40d7 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/commute.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/commute.ll
@@ -8,8 +8,8 @@ target triple = "aarch64--linux-gnu"
define void @test1(ptr nocapture readonly %J, i32 %xmin, i32 %ymin) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[XMIN:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[YMIN:%.*]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[XMIN:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[YMIN:%.*]], i64 1
; CHECK-NEXT: br label [[FOR_BODY3_LR_PH:%.*]]
; CHECK: for.body3.lr.ph:
; CHECK-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x float>
@@ -47,8 +47,8 @@ for.end27:
define void @test2(ptr nocapture readonly %J, i32 %xmin, i32 %ymin) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[XMIN:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[YMIN:%.*]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[XMIN:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[YMIN:%.*]], i64 1
; CHECK-NEXT: br label [[FOR_BODY3_LR_PH:%.*]]
; CHECK: for.body3.lr.ph:
; CHECK-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x float>
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/div-like-mixed-with-undefs.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/div-like-mixed-with-undefs.ll
index bb42d9ab22936..9c4b34fd50b82 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/div-like-mixed-with-undefs.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/div-like-mixed-with-undefs.ll
@@ -9,23 +9,23 @@ define ptr @test(ptr %d, i64 %v) {
; CHECK-NEXT: [[CMP4_2:%.*]] = icmp eq i8 [[TMP0]], 0
; CHECK-NEXT: [[TMP2:%.*]] = xor i64 0, [[V]]
; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[CMP4_2]], i64 0, i64 4
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i64> <i64 poison, i64 poison, i64 1>, i64 [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <3 x i64> [[TMP3]], i64 [[TMP2]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <3 x i64> <i64 1, i64 3, i64 poison>, i64 [[V]], i32 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i64> <i64 poison, i64 poison, i64 1>, i64 [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <3 x i64> [[TMP3]], i64 [[TMP2]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <3 x i64> <i64 1, i64 3, i64 poison>, i64 [[V]], i64 2
; CHECK-NEXT: [[TMP6:%.*]] = udiv <3 x i64> [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <3 x i64> [[TMP6]], <3 x i64> poison, <6 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 2>
; CHECK-NEXT: [[TMP9:%.*]] = mul <6 x i64> [[TMP8]], <i64 2, i64 6, i64 4, i64 3, i64 5, i64 4>
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <6 x i64> [[TMP9]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <6 x i64> [[TMP9]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[D]], i64 [[TMP10]]
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <6 x i64> [[TMP9]], i32 1
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <6 x i64> [[TMP9]], i64 1
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[D]], i64 [[TMP12]]
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <6 x i64> [[TMP9]], i32 2
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <6 x i64> [[TMP9]], i64 2
; CHECK-NEXT: [[SCEVGEP42:%.*]] = getelementptr i8, ptr [[D]], i64 [[TMP14]]
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <6 x i64> [[TMP9]], i32 3
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <6 x i64> [[TMP9]], i64 3
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[D]], i64 [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <6 x i64> [[TMP9]], i32 4
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <6 x i64> [[TMP9]], i64 4
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[D]], i64 [[TMP17]]
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <6 x i64> [[TMP9]], i32 5
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <6 x i64> [[TMP9]], i64 5
; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[D]], i64 [[TMP19]]
; CHECK-NEXT: ret ptr [[TMP20]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
index a71afc36a205e..1dde51c8393a1 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
@@ -529,8 +529,8 @@ define <2 x i32> @sdiv_v2i32_unknown_divisor(<2 x i32> %a, <2 x i32> %x, <2 x i3
; NO-SVE-NEXT: [[X1:%.*]] = extractelement <2 x i32> [[X]], i64 1
; NO-SVE-NEXT: [[TMP8:%.*]] = sdiv i32 [[A1]], [[X1]]
; NO-SVE-NEXT: [[TMP7:%.*]] = sdiv i32 [[A0]], [[X0]]
-; NO-SVE-NEXT: [[RES0:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i32 0
-; NO-SVE-NEXT: [[RES1:%.*]] = insertelement <2 x i32> [[RES0]], i32 [[TMP8]], i32 1
+; NO-SVE-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i64 0
+; NO-SVE-NEXT: [[RES1:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP8]], i64 1
; NO-SVE-NEXT: [[TMP5:%.*]] = add <2 x i32> [[RES1]], [[X]]
; NO-SVE-NEXT: [[TMP6:%.*]] = sub <2 x i32> [[TMP5]], [[Y]]
; NO-SVE-NEXT: [[TMP9:%.*]] = mul <2 x i32> [[TMP6]], [[Z]]
@@ -605,8 +605,8 @@ define <2 x i32> @sdiv_v2i32_Op1_unknown_Op2_const(<2 x i32> %a, <2 x i32> %x, <
; NO-SVE-NEXT: [[A1:%.*]] = extractelement <2 x i32> [[A]], i64 1
; NO-SVE-NEXT: [[TMP2:%.*]] = sdiv i32 [[A1]], 4
; NO-SVE-NEXT: [[TMP7:%.*]] = sdiv i32 [[A0]], [[A0]]
-; NO-SVE-NEXT: [[RES0:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i32 0
-; NO-SVE-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[RES0]], i32 [[TMP2]], i32 1
+; NO-SVE-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i64 0
+; NO-SVE-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP2]], i64 1
; NO-SVE-NEXT: [[TMP5:%.*]] = add <2 x i32> [[TMP4]], [[X]]
; NO-SVE-NEXT: [[TMP6:%.*]] = sub <2 x i32> [[TMP5]], [[Y]]
; NO-SVE-NEXT: [[RES1:%.*]] = mul <2 x i32> [[TMP6]], [[Z]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
index 2c9eea2571f07..f602ff125bd8c 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
@@ -5,16 +5,16 @@ define void @test(i64 %0, i64 %1, i64 %2, i64 %3, i64 %.sroa.3341.0.copyload, i6
; CHECK-LABEL: define void @test(
; CHECK-SAME: i64 [[TMP0:%.*]], i64 [[TMP1:%.*]], i64 [[TMP2:%.*]], i64 [[TMP3:%.*]], i64 [[DOTSROA_3341_0_COPYLOAD:%.*]], i64 [[DOTSROA_3308_0_COPYLOAD:%.*]], i64 [[DOTNEG1:%.*]], i64 [[INDVAR3788:%.*]], i64 [[TMP4:%.*]], i64 [[TMP5:%.*]], i64 [[TMP6:%.*]], i64 [[TMP7:%.*]], i64 [[TMP8:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[_LR_PH_PREHEADER:.*:]]
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i64> poison, i64 [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i64> [[TMP9]], i64 [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i64> poison, i64 [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i64> [[TMP9]], i64 [[TMP0]], i64 1
; CHECK-NEXT: [[TMP13:%.*]] = mul <2 x i64> [[TMP10]], <i64 1, i64 24>
; CHECK-NEXT: [[TMP17:%.*]] = mul <2 x i64> [[TMP10]], <i64 1, i64 40>
; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP0]], 48
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x i64> <i64 poison, i64 1>, i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x i64> <i64 poison, i64 1>, i64 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <2 x i64> [[TMP14]], <2 x i64> <i64 -1, i64 poison>, <2 x i32> <i32 2, i32 0>
; CHECK-NEXT: [[TMP16:%.*]] = sub <2 x i64> [[TMP14]], [[TMP15]]
; CHECK-NEXT: [[TMP20:%.*]] = shl i64 [[TMP0]], 11
-; CHECK-NEXT: [[TMP35:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP35:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x i64> [[TMP35]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP25:%.*]] = shl <2 x i64> [[TMP12]], <i64 11, i64 0>
; CHECK-NEXT: [[TMP21:%.*]] = sub i64 1, [[TMP20]]
@@ -25,20 +25,20 @@ define void @test(i64 %0, i64 %1, i64 %2, i64 %3, i64 %.sroa.3341.0.copyload, i6
; CHECK-NEXT: [[TMP19:%.*]] = or i64 [[TMP18]], [[TMP0]]
; CHECK-NEXT: [[TMP34:%.*]] = or i64 [[TMP19]], 1
; CHECK-NEXT: [[TMP55:%.*]] = mul i64 [[TMP0]], [[TMP0]]
-; CHECK-NEXT: [[TMP58:%.*]] = insertelement <8 x i64> poison, i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP58:%.*]] = insertelement <8 x i64> poison, i64 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP30:%.*]] = shufflevector <8 x i64> [[TMP58]], <8 x i64> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP31:%.*]] = shufflevector <8 x i64> [[TMP30]], <8 x i64> <i64 poison, i64 1, i64 1, i64 1, i64 poison, i64 poison, i64 poison, i64 poison>, <6 x i32> <i32 0, i32 9, i32 10, i32 11, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP32:%.*]] = shufflevector <8 x i64> [[TMP30]], <8 x i64> <i64 0, i64 0, i64 0, i64 0, i64 poison, i64 1, i64 1, i64 1>, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 0, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <8 x i64> [[TMP30]], <8 x i64> poison, <3 x i32> <i32 0, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <3 x i64> [[TMP27]], i64 [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <3 x i64> [[TMP28]], i64 [[DOTNEG1]], i32 2
+; CHECK-NEXT: [[TMP62:%.*]] = insertelement <3 x i64> [[TMP27]], i64 [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP29:%.*]] = insertelement <3 x i64> [[TMP62]], i64 [[DOTNEG1]], i64 2
; CHECK-NEXT: [[TMP36:%.*]] = shufflevector <3 x i64> [[TMP29]], <3 x i64> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 2, i32 0, i32 0, i32 0>
-; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i64> poison, i64 [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i64> [[TMP37]], i64 [[TMP8]], i32 1
-; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i64> [[TMP38]], i64 [[DOTSROA_3308_0_COPYLOAD]], i32 2
-; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i64> [[TMP39]], i64 [[TMP0]], i32 3
+; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i64> poison, i64 [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i64> [[TMP37]], i64 [[TMP8]], i64 1
+; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i64> [[TMP38]], i64 [[DOTSROA_3308_0_COPYLOAD]], i64 2
+; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i64> [[TMP39]], i64 [[TMP0]], i64 3
; CHECK-NEXT: [[TMP41:%.*]] = shufflevector <2 x i64> [[TMP17]], <2 x i64> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP74:%.*]] = insertelement <4 x i64> poison, i64 [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP63:%.*]] = insertelement <4 x i64> poison, i64 [[TMP0]], i64 1
; CHECK-NEXT: [[TMP43:%.*]] = mul i64 [[TMP0]], [[TMP0]]
; CHECK-NEXT: [[TMP44:%.*]] = shufflevector <2 x i64> [[TMP13]], <2 x i64> poison, <32 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP45:%.*]] = shufflevector <32 x i64> [[TMP44]], <32 x i64> poison, <32 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 5, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -60,40 +60,40 @@ define void @test(i64 %0, i64 %1, i64 %2, i64 %3, i64 %.sroa.3341.0.copyload, i6
; CHECK-NEXT: [[DIFF_CHECK3805:%.*]] = icmp ugt i64 [[TMP26]], 1
; CHECK-NEXT: [[TMP56:%.*]] = add <8 x i64> [[TMP52]], [[TMP32]]
; CHECK-NEXT: [[TMP57:%.*]] = icmp ult <8 x i64> [[TMP56]], [[TMP36]]
-; CHECK-NEXT: [[TMP24:%.*]] = extractelement <8 x i64> [[TMP52]], i32 5
+; CHECK-NEXT: [[TMP24:%.*]] = extractelement <8 x i64> [[TMP52]], i64 5
; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP24]], 1
; CHECK-NEXT: [[DIFF_CHECK3842:%.*]] = icmp ult i64 [[TMP42]], [[TMP0]]
; CHECK-NEXT: [[DIFF_CHECK3817:%.*]] = icmp ult i64 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[TMP76:%.*]] = add i64 [[TMP53]], 1
; CHECK-NEXT: [[DIFF_CHECK3820:%.*]] = icmp ult i64 [[TMP76]], [[TMP0]]
; CHECK-NEXT: [[TMP98:%.*]] = shl <2 x i64> [[TMP12]], splat (i64 1)
-; CHECK-NEXT: [[TMP77:%.*]] = insertelement <4 x i64> [[TMP74]], i64 [[INDVAR37888]], i32 0
+; CHECK-NEXT: [[TMP77:%.*]] = insertelement <4 x i64> [[TMP63]], i64 [[INDVAR37888]], i64 0
; CHECK-NEXT: [[TMP78:%.*]] = shufflevector <4 x i64> [[TMP77]], <4 x i64> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP80:%.*]] = shufflevector <4 x i64> [[TMP77]], <4 x i64> <i64 1, i64 poison, i64 poison, i64 poison>, <4 x i32> <i32 4, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP81:%.*]] = shufflevector <4 x i64> [[TMP80]], <4 x i64> [[TMP48]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: [[TMP82:%.*]] = mul <4 x i64> [[TMP78]], [[TMP81]]
; CHECK-NEXT: [[TMP84:%.*]] = add i64 [[TMP54]], 1
-; CHECK-NEXT: [[TMP85:%.*]] = insertelement <32 x i64> [[TMP45]], i64 [[TMP55]], i32 11
+; CHECK-NEXT: [[TMP85:%.*]] = insertelement <32 x i64> [[TMP45]], i64 [[TMP55]], i64 11
; CHECK-NEXT: [[TMP86:%.*]] = shufflevector <4 x i64> [[TMP82]], <4 x i64> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP89:%.*]] = shufflevector <32 x i64> [[TMP85]], <32 x i64> [[TMP86]], <32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 poison, i32 5, i32 poison, i32 poison, i32 poison, i32 poison, i32 10, i32 11, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP90:%.*]] = insertelement <32 x i64> [[TMP89]], i64 [[TMP84]], i32 4
+; CHECK-NEXT: [[TMP90:%.*]] = insertelement <32 x i64> [[TMP89]], i64 [[TMP84]], i64 4
; CHECK-NEXT: [[TMP100:%.*]] = shufflevector <8 x i64> [[TMP52]], <8 x i64> poison, <32 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 4, i32 5, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP73:%.*]] = shufflevector <8 x i64> [[TMP52]], <8 x i64> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP87:%.*]] = shufflevector <32 x i64> [[TMP90]], <32 x i64> [[TMP73]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 36, i32 37, i32 poison, i32 poison, i32 10, i32 11, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP125:%.*]] = shufflevector <2 x i64> [[TMP98]], <2 x i64> poison, <32 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP88:%.*]] = shufflevector <32 x i64> [[TMP87]], <32 x i64> [[TMP125]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 32, i32 33, i32 10, i32 11, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP59:%.*]] = insertelement <32 x i64> [[TMP88]], i64 [[TMP54]], i32 12
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <32 x i64> [[TMP88]], i64 [[TMP54]], i64 12
; CHECK-NEXT: [[TMP60:%.*]] = shufflevector <32 x i64> [[TMP59]], <32 x i64> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 5, i32 5, i32 7, i32 5, i32 8, i32 9, i32 10, i32 5, i32 0, i32 1, i32 11, i32 12, i32 5, i32 5, i32 6, i32 7, i32 5, i32 5, i32 7, i32 5, i32 9, i32 10, i32 0, i32 1>
; CHECK-NEXT: [[TMP61:%.*]] = shufflevector <32 x i64> [[TMP59]], <32 x i64> poison, <10 x i32> <i32 poison, i32 poison, i32 5, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP62:%.*]] = insertelement <10 x i64> [[TMP61]], i64 [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP63:%.*]] = insertelement <10 x i64> [[TMP62]], i64 [[TMP3]], i32 1
-; CHECK-NEXT: [[TMP64:%.*]] = insertelement <10 x i64> [[TMP63]], i64 [[TMP4]], i32 3
-; CHECK-NEXT: [[TMP65:%.*]] = insertelement <10 x i64> [[TMP64]], i64 [[INDVAR3788]], i32 4
-; CHECK-NEXT: [[TMP66:%.*]] = insertelement <10 x i64> [[TMP65]], i64 [[TMP2]], i32 5
-; CHECK-NEXT: [[TMP67:%.*]] = insertelement <10 x i64> [[TMP66]], i64 [[TMP5]], i32 6
-; CHECK-NEXT: [[TMP68:%.*]] = insertelement <10 x i64> [[TMP67]], i64 [[TMP6]], i32 7
-; CHECK-NEXT: [[TMP69:%.*]] = insertelement <10 x i64> [[TMP68]], i64 [[TMP7]], i32 8
-; CHECK-NEXT: [[TMP70:%.*]] = insertelement <10 x i64> [[TMP69]], i64 [[DOTSROA_3341_0_COPYLOAD]], i32 9
+; CHECK-NEXT: [[TMP109:%.*]] = insertelement <10 x i64> [[TMP61]], i64 [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP110:%.*]] = insertelement <10 x i64> [[TMP109]], i64 [[TMP3]], i64 1
+; CHECK-NEXT: [[TMP111:%.*]] = insertelement <10 x i64> [[TMP110]], i64 [[TMP4]], i64 3
+; CHECK-NEXT: [[TMP112:%.*]] = insertelement <10 x i64> [[TMP111]], i64 [[INDVAR3788]], i64 4
+; CHECK-NEXT: [[TMP113:%.*]] = insertelement <10 x i64> [[TMP112]], i64 [[TMP2]], i64 5
+; CHECK-NEXT: [[TMP114:%.*]] = insertelement <10 x i64> [[TMP113]], i64 [[TMP5]], i64 6
+; CHECK-NEXT: [[TMP115:%.*]] = insertelement <10 x i64> [[TMP114]], i64 [[TMP6]], i64 7
+; CHECK-NEXT: [[TMP116:%.*]] = insertelement <10 x i64> [[TMP115]], i64 [[TMP7]], i64 8
+; CHECK-NEXT: [[TMP70:%.*]] = insertelement <10 x i64> [[TMP116]], i64 [[DOTSROA_3341_0_COPYLOAD]], i64 9
; CHECK-NEXT: [[TMP71:%.*]] = shufflevector <10 x i64> [[TMP70]], <10 x i64> poison, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0, i32 2, i32 3, i32 4, i32 0, i32 0, i32 2, i32 2, i32 0, i32 5, i32 0, i32 0, i32 0, i32 0, i32 6, i32 7, i32 0, i32 2, i32 8, i32 9, i32 0, i32 0, i32 2, i32 0, i32 0, i32 0>
; CHECK-NEXT: [[TMP72:%.*]] = icmp ult <32 x i64> [[TMP60]], [[TMP71]]
; CHECK-NEXT: [[TMP91:%.*]] = add i64 [[TMP54]], 1
@@ -101,18 +101,18 @@ define void @test(i64 %0, i64 %1, i64 %2, i64 %3, i64 %.sroa.3341.0.copyload, i6
; CHECK-NEXT: [[TMP93:%.*]] = shufflevector <8 x i64> [[TMP92]], <8 x i64> [[TMP41]], <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 9, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP94:%.*]] = shufflevector <2 x i64> [[TMP98]], <2 x i64> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP95:%.*]] = shufflevector <8 x i64> [[TMP93]], <8 x i64> [[TMP94]], <8 x i32> <i32 0, i32 8, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: [[TMP96:%.*]] = insertelement <8 x i64> [[TMP95]], i64 [[TMP91]], i32 5
+; CHECK-NEXT: [[TMP96:%.*]] = insertelement <8 x i64> [[TMP95]], i64 [[TMP91]], i64 5
; CHECK-NEXT: [[TMP105:%.*]] = shufflevector <8 x i64> [[TMP96]], <8 x i64> poison, <2 x i32> <i32 poison, i32 3>
-; CHECK-NEXT: [[TMP107:%.*]] = insertelement <2 x i64> [[TMP105]], i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP107:%.*]] = insertelement <2 x i64> [[TMP105]], i64 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP99:%.*]] = shufflevector <2 x i64> [[TMP107]], <2 x i64> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT: [[TMP83:%.*]] = icmp ult <8 x i64> [[TMP96]], [[TMP99]]
; CHECK-NEXT: [[TMP101:%.*]] = shufflevector <8 x i64> [[TMP52]], <8 x i64> poison, <4 x i32> <i32 4, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i64> [[TMP101]], i64 [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP103:%.*]] = insertelement <4 x i64> [[TMP102]], i64 [[TMP53]], i32 3
+; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i64> [[TMP101]], i64 [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP103:%.*]] = insertelement <4 x i64> [[TMP102]], i64 [[TMP53]], i64 3
; CHECK-NEXT: [[TMP104:%.*]] = shufflevector <4 x i64> [[TMP103]], <4 x i64> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 3>
; CHECK-NEXT: [[TMP97:%.*]] = icmp ult <4 x i64> [[TMP104]], [[TMP40]]
; CHECK-NEXT: [[DIFF_CHECK3930:%.*]] = icmp ult i64 [[TMP24]], [[TMP0]]
-; CHECK-NEXT: [[TMP106:%.*]] = extractelement <2 x i64> [[TMP98]], i32 0
+; CHECK-NEXT: [[TMP106:%.*]] = extractelement <2 x i64> [[TMP98]], i64 0
; CHECK-NEXT: [[DIFF_CHECK3932:%.*]] = icmp ult i64 [[TMP106]], [[TMP1]]
; CHECK-NEXT: [[OP_RDX50:%.*]] = icmp ult i64 [[TMP1]], [[TMP0]]
; CHECK-NEXT: [[TMP126:%.*]] = icmp ult i64 [[INDVAR37888]], [[TMP0]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/extract-subvector-long-input.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/extract-subvector-long-input.ll
index 04c69106d97ff..dd4af1a170276 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/extract-subvector-long-input.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/extract-subvector-long-input.ll
@@ -8,7 +8,7 @@ define void @test() {
; CHECK: bb1:
; CHECK-NEXT: [[PHI7:%.*]] = phi i32 [ 0, [[BB10:%.*]] ], [ 0, [[BB:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = phi <8 x i32> [ poison, [[BB10]] ], [ zeroinitializer, [[BB]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[PHI7]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[PHI7]], i64 0
; CHECK-NEXT: switch i32 0, label [[BB16:%.*]] [
; CHECK-NEXT: i32 0, label [[BB14:%.*]]
; CHECK-NEXT: i32 1, label [[BB11:%.*]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll
index 7f737cd169147..b1817688f89a2 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll
@@ -655,8 +655,8 @@ define i1 @tryMapToRange(ptr %values, ptr %result, <2 x i64> %hi, <2 x i64> %lo)
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> [[A1]], <16 x i8> [[A2]], <2 x i32> <i32 8, i32 24>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i8> [[A1]], <16 x i8> [[A2]], <2 x i32> <i32 0, i32 16>
; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i8> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[O3:%.*]] = extractelement <2 x i8> [[TMP3]], i32 0
-; CHECK-NEXT: [[O2:%.*]] = extractelement <2 x i8> [[TMP3]], i32 1
+; CHECK-NEXT: [[O3:%.*]] = extractelement <2 x i8> [[TMP3]], i64 0
+; CHECK-NEXT: [[O2:%.*]] = extractelement <2 x i8> [[TMP3]], i64 1
; CHECK-NEXT: [[O4:%.*]] = or i8 [[O3]], [[O2]]
; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[O4]], 0
; CHECK-NEXT: ret i1 [[C]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
index 2acbebf259ee9..755b2c425f041 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
@@ -52,7 +52,7 @@ define void @mixed_use_v4(ptr %src0, ptr %src1, ptr %dst, ptr %extra) {
; CHECK-NEXT: [[TMP2:%.*]] = fmul fast <4 x float> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = fadd fast <4 x float> [[TMP2]], splat (float 1.000000e+00)
; CHECK-NEXT: store <4 x float> [[TMP3]], ptr [[DST:%.*]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP2]], i64 0
; CHECK-NEXT: store float [[TMP4]], ptr [[EXTRA:%.*]], align 4
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
index 74341f12670a6..f6c81beee9ff1 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
@@ -5,7 +5,7 @@ define float @test(float %arg, <2 x float> %arg1, i64 %arg2) {
; CHECK-LABEL: @test(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[ARG2:%.*]] to i16
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[ARG2]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[ARG2]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i64> [[TMP1]], <i64 32, i64 16>
; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP2]] to <2 x i16>
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/fmulladd.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/fmulladd.ll
index 24d2ed97d0fa1..e32a0b13ad0a2 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/fmulladd.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/fmulladd.ll
@@ -26,7 +26,7 @@ define void @foo(ptr %d, ptr %e) {
; CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr @a, align 8
; CHECK-NEXT: [[TMP9:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8
; CHECK-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr [[ARRAYIDX4]], align 8
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i64 0
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x double> [[TMP11]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP13:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP12]], <2 x double> [[TMP10]], <2 x double> [[TMP9]])
; CHECK-NEXT: store <2 x double> [[TMP13]], ptr [[TMP8]], align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
index 0ac3323e0a7b3..ac5b0eb330f47 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
@@ -8,35 +8,35 @@ define void @h(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i
; CHECK-NEXT: [[CONV9:%.*]] = zext i16 [[A]] to i32
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16
; CHECK-NEXT: [[CONV310:%.*]] = zext i16 [[B]] to i32
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> poison, i16 [[D]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[G]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[K]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[O]], i32 3
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[C]], i32 4
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[F]], i32 5
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[J]], i32 6
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[N]], i32 7
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> poison, i16 [[D]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[G]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[K]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[O]], i64 3
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[C]], i64 4
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[F]], i64 5
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[J]], i64 6
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[N]], i64 7
; CHECK-NEXT: [[CONV3_112:%.*]] = zext i16 [[E]] to i32
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i16> poison, i16 [[H]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i16> [[TMP8]], i16 [[L]], i32 1
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i16> poison, i16 [[I]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i16> [[TMP10]], i16 [[M]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i16> poison, i16 [[H]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i16> [[TMP8]], i16 [[L]], i64 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i16> poison, i16 [[I]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i16> [[TMP10]], i16 [[M]], i64 1
; CHECK-NEXT: [[ADD4_1:%.*]] = or i32 [[CONV3_112]], 0
; CHECK-NEXT: [[SUB39_3:%.*]] = or i32 [[CONV310]], [[CONV9]]
; CHECK-NEXT: [[SUB44_2:%.*]] = or i32 0, [[CONV3_112]]
; CHECK-NEXT: [[SUB39_2:%.*]] = or i32 [[CONV9]], [[CONV310]]
; CHECK-NEXT: [[TMP12:%.*]] = or <8 x i16> zeroinitializer, [[TMP7]]
; CHECK-NEXT: [[CONV40_2:%.*]] = trunc i32 [[SUB39_2]] to i16
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i16> poison, i16 [[CONV40_2]], i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i16> poison, i16 [[CONV40_2]], i64 0
; CHECK-NEXT: [[CONV45_2:%.*]] = trunc i32 [[SUB44_2]] to i16
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x i16> [[TMP14]], i16 [[CONV45_2]], i32 1
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x i16> [[TMP14]], i16 [[CONV45_2]], i64 1
; CHECK-NEXT: [[TMP17:%.*]] = or <2 x i16> zeroinitializer, [[TMP11]]
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <2 x i16> [[TMP17]], <2 x i16> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <8 x i16> [[TMP16]], <8 x i16> [[TMP18]], <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[CONV40_3:%.*]] = trunc i32 [[SUB39_3]] to i16
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <8 x i16> [[TMP19]], i16 [[CONV40_3]], i32 4
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <8 x i16> [[TMP19]], i16 [[CONV40_3]], i64 4
; CHECK-NEXT: [[TMP22:%.*]] = trunc i32 [[ADD4_1]] to i16
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <8 x i16> [[TMP21]], i16 [[TMP22]], i32 5
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <8 x i16> [[TMP21]], i16 [[TMP22]], i64 5
; CHECK-NEXT: [[TMP24:%.*]] = or <2 x i16> zeroinitializer, [[TMP9]]
; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <2 x i16> [[TMP24]], <2 x i16> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP26:%.*]] = shufflevector <8 x i16> [[TMP23]], <8 x i16> [[TMP25]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
index 931667ed61dc3..b9c4084bb23bf 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
@@ -14,10 +14,10 @@ target triple = "aarch64--linux-gnu"
;
define internal i32 @gather_multiple_use(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: @gather_multiple_use(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[C:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[B:%.*]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[D:%.*]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[C:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[B:%.*]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[D:%.*]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = lshr <4 x i32> [[TMP4]], splat (i32 15)
; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i32> [[TMP5]], splat (i32 65537)
; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <4 x i32> [[TMP6]], splat (i32 65535)
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-reduce.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-reduce.ll
index f83628ed17b65..5f8d23b39c06c 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-reduce.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-reduce.ll
@@ -42,42 +42,42 @@ define i32 @gather_reduce_8x16_i32(ptr nocapture readonly %a, ptr nocapture read
; GENERIC-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B:%.*]], align 2
; GENERIC-NEXT: [[TMP3:%.*]] = zext <8 x i16> [[TMP2]] to <8 x i32>
; GENERIC-NEXT: [[TMP4:%.*]] = sub nsw <8 x i32> [[TMP1]], [[TMP3]]
-; GENERIC-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP4]], i32 0
+; GENERIC-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP4]], i64 0
; GENERIC-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[G:%.*]], i32 [[TMP5]]
; GENERIC-NEXT: [[TMP7:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
; GENERIC-NEXT: [[CONV3:%.*]] = zext i16 [[TMP7]] to i32
; GENERIC-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV3]], [[SUM_0102]]
-; GENERIC-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP4]], i32 1
+; GENERIC-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP4]], i64 1
; GENERIC-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP8]]
; GENERIC-NEXT: [[TMP10:%.*]] = load i16, ptr [[ARRAYIDX10]], align 2
; GENERIC-NEXT: [[CONV11:%.*]] = zext i16 [[TMP10]] to i32
; GENERIC-NEXT: [[ADD12:%.*]] = add nsw i32 [[ADD]], [[CONV11]]
-; GENERIC-NEXT: [[TMP9:%.*]] = extractelement <8 x i32> [[TMP4]], i32 2
+; GENERIC-NEXT: [[TMP9:%.*]] = extractelement <8 x i32> [[TMP4]], i64 2
; GENERIC-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP9]]
; GENERIC-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX19]], align 2
; GENERIC-NEXT: [[CONV20:%.*]] = zext i16 [[TMP13]] to i32
; GENERIC-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD12]], [[CONV20]]
-; GENERIC-NEXT: [[TMP11:%.*]] = extractelement <8 x i32> [[TMP4]], i32 3
+; GENERIC-NEXT: [[TMP11:%.*]] = extractelement <8 x i32> [[TMP4]], i64 3
; GENERIC-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP11]]
; GENERIC-NEXT: [[TMP16:%.*]] = load i16, ptr [[ARRAYIDX28]], align 2
; GENERIC-NEXT: [[CONV29:%.*]] = zext i16 [[TMP16]] to i32
; GENERIC-NEXT: [[ADD30:%.*]] = add nsw i32 [[ADD21]], [[CONV29]]
-; GENERIC-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP4]], i32 4
+; GENERIC-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP4]], i64 4
; GENERIC-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP14]]
; GENERIC-NEXT: [[TMP19:%.*]] = load i16, ptr [[ARRAYIDX37]], align 2
; GENERIC-NEXT: [[CONV38:%.*]] = zext i16 [[TMP19]] to i32
; GENERIC-NEXT: [[ADD39:%.*]] = add nsw i32 [[ADD30]], [[CONV38]]
-; GENERIC-NEXT: [[TMP15:%.*]] = extractelement <8 x i32> [[TMP4]], i32 5
+; GENERIC-NEXT: [[TMP15:%.*]] = extractelement <8 x i32> [[TMP4]], i64 5
; GENERIC-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP15]]
; GENERIC-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX46]], align 2
; GENERIC-NEXT: [[CONV47:%.*]] = zext i16 [[TMP22]] to i32
; GENERIC-NEXT: [[ADD48:%.*]] = add nsw i32 [[ADD39]], [[CONV47]]
-; GENERIC-NEXT: [[TMP17:%.*]] = extractelement <8 x i32> [[TMP4]], i32 6
+; GENERIC-NEXT: [[TMP17:%.*]] = extractelement <8 x i32> [[TMP4]], i64 6
; GENERIC-NEXT: [[ARRAYIDX55:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP17]]
; GENERIC-NEXT: [[TMP25:%.*]] = load i16, ptr [[ARRAYIDX55]], align 2
; GENERIC-NEXT: [[CONV56:%.*]] = zext i16 [[TMP25]] to i32
; GENERIC-NEXT: [[ADD57:%.*]] = add nsw i32 [[ADD48]], [[CONV56]]
-; GENERIC-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP4]], i32 7
+; GENERIC-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP4]], i64 7
; GENERIC-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP20]]
; GENERIC-NEXT: [[TMP28:%.*]] = load i16, ptr [[ARRAYIDX64]], align 2
; GENERIC-NEXT: [[CONV65:%.*]] = zext i16 [[TMP28]] to i32
@@ -107,42 +107,42 @@ define i32 @gather_reduce_8x16_i32(ptr nocapture readonly %a, ptr nocapture read
; KRYO-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B:%.*]], align 2
; KRYO-NEXT: [[TMP3:%.*]] = zext <8 x i16> [[TMP2]] to <8 x i32>
; KRYO-NEXT: [[TMP4:%.*]] = sub nsw <8 x i32> [[TMP1]], [[TMP3]]
-; KRYO-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP4]], i32 0
+; KRYO-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP4]], i64 0
; KRYO-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[G:%.*]], i32 [[TMP5]]
; KRYO-NEXT: [[TMP7:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
; KRYO-NEXT: [[CONV3:%.*]] = zext i16 [[TMP7]] to i32
; KRYO-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV3]], [[SUM_0102]]
-; KRYO-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP4]], i32 1
+; KRYO-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP4]], i64 1
; KRYO-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP8]]
; KRYO-NEXT: [[TMP10:%.*]] = load i16, ptr [[ARRAYIDX10]], align 2
; KRYO-NEXT: [[CONV11:%.*]] = zext i16 [[TMP10]] to i32
; KRYO-NEXT: [[ADD12:%.*]] = add nsw i32 [[ADD]], [[CONV11]]
-; KRYO-NEXT: [[TMP9:%.*]] = extractelement <8 x i32> [[TMP4]], i32 2
+; KRYO-NEXT: [[TMP9:%.*]] = extractelement <8 x i32> [[TMP4]], i64 2
; KRYO-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP9]]
; KRYO-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX19]], align 2
; KRYO-NEXT: [[CONV20:%.*]] = zext i16 [[TMP13]] to i32
; KRYO-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD12]], [[CONV20]]
-; KRYO-NEXT: [[TMP11:%.*]] = extractelement <8 x i32> [[TMP4]], i32 3
+; KRYO-NEXT: [[TMP11:%.*]] = extractelement <8 x i32> [[TMP4]], i64 3
; KRYO-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP11]]
; KRYO-NEXT: [[TMP16:%.*]] = load i16, ptr [[ARRAYIDX28]], align 2
; KRYO-NEXT: [[CONV29:%.*]] = zext i16 [[TMP16]] to i32
; KRYO-NEXT: [[ADD30:%.*]] = add nsw i32 [[ADD21]], [[CONV29]]
-; KRYO-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP4]], i32 4
+; KRYO-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP4]], i64 4
; KRYO-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP14]]
; KRYO-NEXT: [[TMP19:%.*]] = load i16, ptr [[ARRAYIDX37]], align 2
; KRYO-NEXT: [[CONV38:%.*]] = zext i16 [[TMP19]] to i32
; KRYO-NEXT: [[ADD39:%.*]] = add nsw i32 [[ADD30]], [[CONV38]]
-; KRYO-NEXT: [[TMP15:%.*]] = extractelement <8 x i32> [[TMP4]], i32 5
+; KRYO-NEXT: [[TMP15:%.*]] = extractelement <8 x i32> [[TMP4]], i64 5
; KRYO-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP15]]
; KRYO-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX46]], align 2
; KRYO-NEXT: [[CONV47:%.*]] = zext i16 [[TMP22]] to i32
; KRYO-NEXT: [[ADD48:%.*]] = add nsw i32 [[ADD39]], [[CONV47]]
-; KRYO-NEXT: [[TMP17:%.*]] = extractelement <8 x i32> [[TMP4]], i32 6
+; KRYO-NEXT: [[TMP17:%.*]] = extractelement <8 x i32> [[TMP4]], i64 6
; KRYO-NEXT: [[ARRAYIDX55:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP17]]
; KRYO-NEXT: [[TMP25:%.*]] = load i16, ptr [[ARRAYIDX55]], align 2
; KRYO-NEXT: [[CONV56:%.*]] = zext i16 [[TMP25]] to i32
; KRYO-NEXT: [[ADD57:%.*]] = add nsw i32 [[ADD48]], [[CONV56]]
-; KRYO-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP4]], i32 7
+; KRYO-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP4]], i64 7
; KRYO-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds i16, ptr [[G]], i32 [[TMP20]]
; KRYO-NEXT: [[TMP28:%.*]] = load i16, ptr [[ARRAYIDX64]], align 2
; KRYO-NEXT: [[CONV65:%.*]] = zext i16 [[TMP28]] to i32
@@ -283,49 +283,49 @@ define i32 @gather_reduce_8x16_i64(ptr nocapture readonly %a, ptr nocapture read
; GENERIC-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B:%.*]], align 2
; GENERIC-NEXT: [[TMP3:%.*]] = zext <8 x i16> [[TMP2]] to <8 x i32>
; GENERIC-NEXT: [[TMP4:%.*]] = sub <8 x i32> [[TMP1]], [[TMP3]]
-; GENERIC-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP4]], i32 0
+; GENERIC-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP4]], i64 0
; GENERIC-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; GENERIC-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[G:%.*]], i64 [[TMP6]]
; GENERIC-NEXT: [[TMP7:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
; GENERIC-NEXT: [[CONV3:%.*]] = zext i16 [[TMP7]] to i32
; GENERIC-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV3]], [[SUM_0102]]
-; GENERIC-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP4]], i32 1
+; GENERIC-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP4]], i64 1
; GENERIC-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
; GENERIC-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP9]]
; GENERIC-NEXT: [[TMP10:%.*]] = load i16, ptr [[ARRAYIDX10]], align 2
; GENERIC-NEXT: [[CONV11:%.*]] = zext i16 [[TMP10]] to i32
; GENERIC-NEXT: [[ADD12:%.*]] = add nsw i32 [[ADD]], [[CONV11]]
-; GENERIC-NEXT: [[TMP11:%.*]] = extractelement <8 x i32> [[TMP4]], i32 2
+; GENERIC-NEXT: [[TMP11:%.*]] = extractelement <8 x i32> [[TMP4]], i64 2
; GENERIC-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64
; GENERIC-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP12]]
; GENERIC-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX19]], align 2
; GENERIC-NEXT: [[CONV20:%.*]] = zext i16 [[TMP13]] to i32
; GENERIC-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD12]], [[CONV20]]
-; GENERIC-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP4]], i32 3
+; GENERIC-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP4]], i64 3
; GENERIC-NEXT: [[TMP15:%.*]] = sext i32 [[TMP14]] to i64
; GENERIC-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP15]]
; GENERIC-NEXT: [[TMP16:%.*]] = load i16, ptr [[ARRAYIDX28]], align 2
; GENERIC-NEXT: [[CONV29:%.*]] = zext i16 [[TMP16]] to i32
; GENERIC-NEXT: [[ADD30:%.*]] = add nsw i32 [[ADD21]], [[CONV29]]
-; GENERIC-NEXT: [[TMP17:%.*]] = extractelement <8 x i32> [[TMP4]], i32 4
+; GENERIC-NEXT: [[TMP17:%.*]] = extractelement <8 x i32> [[TMP4]], i64 4
; GENERIC-NEXT: [[TMP18:%.*]] = sext i32 [[TMP17]] to i64
; GENERIC-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP18]]
; GENERIC-NEXT: [[TMP19:%.*]] = load i16, ptr [[ARRAYIDX37]], align 2
; GENERIC-NEXT: [[CONV38:%.*]] = zext i16 [[TMP19]] to i32
; GENERIC-NEXT: [[ADD39:%.*]] = add nsw i32 [[ADD30]], [[CONV38]]
-; GENERIC-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP4]], i32 5
+; GENERIC-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP4]], i64 5
; GENERIC-NEXT: [[TMP21:%.*]] = sext i32 [[TMP20]] to i64
; GENERIC-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP21]]
; GENERIC-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX46]], align 2
; GENERIC-NEXT: [[CONV47:%.*]] = zext i16 [[TMP22]] to i32
; GENERIC-NEXT: [[ADD48:%.*]] = add nsw i32 [[ADD39]], [[CONV47]]
-; GENERIC-NEXT: [[TMP23:%.*]] = extractelement <8 x i32> [[TMP4]], i32 6
+; GENERIC-NEXT: [[TMP23:%.*]] = extractelement <8 x i32> [[TMP4]], i64 6
; GENERIC-NEXT: [[TMP24:%.*]] = sext i32 [[TMP23]] to i64
; GENERIC-NEXT: [[ARRAYIDX55:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP24]]
; GENERIC-NEXT: [[TMP25:%.*]] = load i16, ptr [[ARRAYIDX55]], align 2
; GENERIC-NEXT: [[CONV56:%.*]] = zext i16 [[TMP25]] to i32
; GENERIC-NEXT: [[ADD57:%.*]] = add nsw i32 [[ADD48]], [[CONV56]]
-; GENERIC-NEXT: [[TMP26:%.*]] = extractelement <8 x i32> [[TMP4]], i32 7
+; GENERIC-NEXT: [[TMP26:%.*]] = extractelement <8 x i32> [[TMP4]], i64 7
; GENERIC-NEXT: [[TMP27:%.*]] = sext i32 [[TMP26]] to i64
; GENERIC-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP27]]
; GENERIC-NEXT: [[TMP28:%.*]] = load i16, ptr [[ARRAYIDX64]], align 2
@@ -356,49 +356,49 @@ define i32 @gather_reduce_8x16_i64(ptr nocapture readonly %a, ptr nocapture read
; KRYO-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B:%.*]], align 2
; KRYO-NEXT: [[TMP3:%.*]] = zext <8 x i16> [[TMP2]] to <8 x i32>
; KRYO-NEXT: [[TMP4:%.*]] = sub <8 x i32> [[TMP1]], [[TMP3]]
-; KRYO-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP4]], i32 0
+; KRYO-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP4]], i64 0
; KRYO-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; KRYO-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[G:%.*]], i64 [[TMP6]]
; KRYO-NEXT: [[TMP7:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
; KRYO-NEXT: [[CONV3:%.*]] = zext i16 [[TMP7]] to i32
; KRYO-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV3]], [[SUM_0102]]
-; KRYO-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP4]], i32 1
+; KRYO-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP4]], i64 1
; KRYO-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
; KRYO-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP9]]
; KRYO-NEXT: [[TMP10:%.*]] = load i16, ptr [[ARRAYIDX10]], align 2
; KRYO-NEXT: [[CONV11:%.*]] = zext i16 [[TMP10]] to i32
; KRYO-NEXT: [[ADD12:%.*]] = add nsw i32 [[ADD]], [[CONV11]]
-; KRYO-NEXT: [[TMP11:%.*]] = extractelement <8 x i32> [[TMP4]], i32 2
+; KRYO-NEXT: [[TMP11:%.*]] = extractelement <8 x i32> [[TMP4]], i64 2
; KRYO-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64
; KRYO-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP12]]
; KRYO-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX19]], align 2
; KRYO-NEXT: [[CONV20:%.*]] = zext i16 [[TMP13]] to i32
; KRYO-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD12]], [[CONV20]]
-; KRYO-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP4]], i32 3
+; KRYO-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP4]], i64 3
; KRYO-NEXT: [[TMP15:%.*]] = sext i32 [[TMP14]] to i64
; KRYO-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP15]]
; KRYO-NEXT: [[TMP16:%.*]] = load i16, ptr [[ARRAYIDX28]], align 2
; KRYO-NEXT: [[CONV29:%.*]] = zext i16 [[TMP16]] to i32
; KRYO-NEXT: [[ADD30:%.*]] = add nsw i32 [[ADD21]], [[CONV29]]
-; KRYO-NEXT: [[TMP17:%.*]] = extractelement <8 x i32> [[TMP4]], i32 4
+; KRYO-NEXT: [[TMP17:%.*]] = extractelement <8 x i32> [[TMP4]], i64 4
; KRYO-NEXT: [[TMP18:%.*]] = sext i32 [[TMP17]] to i64
; KRYO-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP18]]
; KRYO-NEXT: [[TMP19:%.*]] = load i16, ptr [[ARRAYIDX37]], align 2
; KRYO-NEXT: [[CONV38:%.*]] = zext i16 [[TMP19]] to i32
; KRYO-NEXT: [[ADD39:%.*]] = add nsw i32 [[ADD30]], [[CONV38]]
-; KRYO-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP4]], i32 5
+; KRYO-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP4]], i64 5
; KRYO-NEXT: [[TMP21:%.*]] = sext i32 [[TMP20]] to i64
; KRYO-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP21]]
; KRYO-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX46]], align 2
; KRYO-NEXT: [[CONV47:%.*]] = zext i16 [[TMP22]] to i32
; KRYO-NEXT: [[ADD48:%.*]] = add nsw i32 [[ADD39]], [[CONV47]]
-; KRYO-NEXT: [[TMP23:%.*]] = extractelement <8 x i32> [[TMP4]], i32 6
+; KRYO-NEXT: [[TMP23:%.*]] = extractelement <8 x i32> [[TMP4]], i64 6
; KRYO-NEXT: [[TMP24:%.*]] = sext i32 [[TMP23]] to i64
; KRYO-NEXT: [[ARRAYIDX55:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP24]]
; KRYO-NEXT: [[TMP25:%.*]] = load i16, ptr [[ARRAYIDX55]], align 2
; KRYO-NEXT: [[CONV56:%.*]] = zext i16 [[TMP25]] to i32
; KRYO-NEXT: [[ADD57:%.*]] = add nsw i32 [[ADD48]], [[CONV56]]
-; KRYO-NEXT: [[TMP26:%.*]] = extractelement <8 x i32> [[TMP4]], i32 7
+; KRYO-NEXT: [[TMP26:%.*]] = extractelement <8 x i32> [[TMP4]], i64 7
; KRYO-NEXT: [[TMP27:%.*]] = sext i32 [[TMP26]] to i64
; KRYO-NEXT: [[ARRAYIDX64:%.*]] = getelementptr inbounds i16, ptr [[G]], i64 [[TMP27]]
; KRYO-NEXT: [[TMP28:%.*]] = load i16, ptr [[ARRAYIDX64]], align 2
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
index 1cef13c9cf1b7..6df79461fb914 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
@@ -46,9 +46,9 @@ define i32 @getelementptr_4x32(ptr nocapture readonly %g, i32 %n, i32 %x, i32 %y
; CHECK-NEXT: [[CMP31:%.*]] = icmp sgt i32 [[N:%.*]], 0
; CHECK-NEXT: br i1 [[CMP31]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
; CHECK: for.body.preheader:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[X:%.*]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[Y:%.*]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[Z:%.*]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[X:%.*]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[Y:%.*]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[Z:%.*]], i64 1
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.cond.cleanup.loopexit:
; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
@@ -59,26 +59,26 @@ define i32 @getelementptr_4x32(ptr nocapture readonly %g, i32 %n, i32 %x, i32 %y
; CHECK-NEXT: [[TMP15:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[SUM_032:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[ADD16]], [[FOR_BODY]] ]
; CHECK-NEXT: [[T4:%.*]] = shl nsw i32 [[TMP15]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[T4]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[T4]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i32> [[TMP2]], [[TMP0]]
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i32> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i32> [[TMP3]], i64 0
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[G:%.*]], i32 [[TMP12]]
; CHECK-NEXT: [[T6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[TMP3]], i64 1
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[G]], i32 [[TMP11]]
; CHECK-NEXT: [[T8:%.*]] = load i32, ptr [[ARRAYIDX5]], align 4
; CHECK-NEXT: [[TMP16:%.*]] = add nsw <2 x i32> [[TMP2]], [[TMP5]]
-; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i32> [[TMP16]], i32 0
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i32> [[TMP16]], i64 0
; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[G]], i32 [[TMP13]]
; CHECK-NEXT: [[T10:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i32> [[TMP16]], i32 1
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i32> [[TMP16]], i64 1
; CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, ptr [[G]], i32 [[TMP14]]
; CHECK-NEXT: [[T12:%.*]] = load i32, ptr [[ARRAYIDX15]], align 4
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[T6]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[T8]], i32 1
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[T10]], i32 2
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[T12]], i32 3
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x i32> poison, i32 [[T6]], i64 0
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x i32> [[TMP17]], i32 [[T8]], i64 1
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i32> [[TMP18]], i32 [[T10]], i64 2
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP19]], i32 [[T12]], i64 3
; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP9]])
; CHECK-NEXT: [[ADD16]] = add i32 [[TMP10]], [[SUM_032]]
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i32 [[TMP15]], 1
@@ -141,7 +141,7 @@ define i32 @getelementptr_2x32(ptr nocapture readonly %g, i32 %n, i32 %x, i32 %y
; CHECK-NEXT: [[CMP31:%.*]] = icmp sgt i32 [[N:%.*]], 0
; CHECK-NEXT: br i1 [[CMP31]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
; CHECK: for.body.preheader:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[Y:%.*]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[Y:%.*]], i64 1
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.cond.cleanup.loopexit:
; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
@@ -152,20 +152,20 @@ define i32 @getelementptr_2x32(ptr nocapture readonly %g, i32 %n, i32 %x, i32 %y
; CHECK-NEXT: [[TMP12:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[SUM_032:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[OP_RDX]], [[FOR_BODY]] ]
; CHECK-NEXT: [[T4:%.*]] = shl nsw i32 [[TMP12]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[T4]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[T4]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i32> [[TMP2]], [[TMP0]]
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i32> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i32> [[TMP3]], i64 0
; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[G:%.*]], i32 [[TMP9]]
; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr [[ARRAYIDX11]], align 4
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP3]], i64 1
; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[G]], i32 [[TMP6]]
; CHECK-NEXT: [[T10:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4
; CHECK-NEXT: [[TMP10:%.*]] = add nsw i32 [[T4]], [[Z:%.*]]
; CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, ptr [[G]], i32 [[TMP10]]
; CHECK-NEXT: [[T12:%.*]] = load i32, ptr [[ARRAYIDX15]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[T10]], i32 2
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[T12]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[T10]], i64 2
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[T12]], i64 3
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> [[TMP13]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP14]])
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr2.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr2.ll
index 4847149c87a18..440a4198e2004 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr2.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr2.ll
@@ -32,35 +32,35 @@ define void @test_i16_extend(ptr %p.1, ptr %p.2, i32 %idx.i32) {
; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr [[T56]], align 2
; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i16> [[TMP3]] to <8 x i32>
; CHECK-NEXT: [[TMP5:%.*]] = sub <8 x i32> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i32> [[TMP5]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i32> [[TMP5]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = sext i32 [[TMP6]] to i64
; CHECK-NEXT: [[T60:%.*]] = getelementptr inbounds i32, ptr [[P_0]], i64 [[TMP7]]
; CHECK-NEXT: [[L_1:%.*]] = load i32, ptr [[T60]], align 4
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[TMP5]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
; CHECK-NEXT: [[T71:%.*]] = getelementptr inbounds i32, ptr [[P_0]], i64 [[TMP9]]
; CHECK-NEXT: [[L_2:%.*]] = load i32, ptr [[T71]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i32> [[TMP5]], i32 2
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i32> [[TMP5]], i64 2
; CHECK-NEXT: [[TMP11:%.*]] = sext i32 [[TMP10]] to i64
; CHECK-NEXT: [[T82:%.*]] = getelementptr inbounds i32, ptr [[P_0]], i64 [[TMP11]]
; CHECK-NEXT: [[L_3:%.*]] = load i32, ptr [[T82]], align 4
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i32> [[TMP5]], i32 3
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i32> [[TMP5]], i64 3
; CHECK-NEXT: [[TMP13:%.*]] = sext i32 [[TMP12]] to i64
; CHECK-NEXT: [[T93:%.*]] = getelementptr inbounds i32, ptr [[P_0]], i64 [[TMP13]]
; CHECK-NEXT: [[L_4:%.*]] = load i32, ptr [[T93]], align 4
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP5]], i32 4
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <8 x i32> [[TMP5]], i64 4
; CHECK-NEXT: [[TMP15:%.*]] = sext i32 [[TMP14]] to i64
; CHECK-NEXT: [[T104:%.*]] = getelementptr inbounds i32, ptr [[P_0]], i64 [[TMP15]]
; CHECK-NEXT: [[L_5:%.*]] = load i32, ptr [[T104]], align 4
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i32> [[TMP5]], i32 5
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <8 x i32> [[TMP5]], i64 5
; CHECK-NEXT: [[TMP17:%.*]] = sext i32 [[TMP16]] to i64
; CHECK-NEXT: [[T115:%.*]] = getelementptr inbounds i32, ptr [[P_0]], i64 [[TMP17]]
; CHECK-NEXT: [[L_6:%.*]] = load i32, ptr [[T115]], align 4
-; CHECK-NEXT: [[TMP18:%.*]] = extractelement <8 x i32> [[TMP5]], i32 6
+; CHECK-NEXT: [[TMP18:%.*]] = extractelement <8 x i32> [[TMP5]], i64 6
; CHECK-NEXT: [[TMP19:%.*]] = sext i32 [[TMP18]] to i64
; CHECK-NEXT: [[T126:%.*]] = getelementptr inbounds i32, ptr [[P_0]], i64 [[TMP19]]
; CHECK-NEXT: [[L_7:%.*]] = load i32, ptr [[T126]], align 4
-; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP5]], i32 7
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP5]], i64 7
; CHECK-NEXT: [[TMP21:%.*]] = sext i32 [[TMP20]] to i64
; CHECK-NEXT: [[T137:%.*]] = getelementptr inbounds i32, ptr [[P_0]], i64 [[TMP21]]
; CHECK-NEXT: [[L_8:%.*]] = load i32, ptr [[T137]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/landing_pad.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/landing_pad.ll
index 5143265bb3ce0..f8ea0286c2242 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/landing_pad.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/landing_pad.ll
@@ -44,8 +44,8 @@ define void @foo() personality ptr @bar {
; CHECK-NEXT: ret void
; CHECK: bb3:
; CHECK-NEXT: [[TMP2:%.*]] = phi <2 x i64> [ [[TMP4:%.*]], [[BB6:%.*]] ], [ poison, [[BB1:%.*]] ]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP2]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = invoke i64 poison(ptr addrspace(1) nonnull poison, i64 0, i64 0, i64 poison) [ "deopt"() ]
; CHECK-NEXT: to label [[BB4:%.*]] unwind label [[BB10:%.*]]
; CHECK: bb4:
@@ -70,8 +70,8 @@ define void @foo() personality ptr @bar {
; CHECK-NEXT: [[LOCAL_5_33118_LCSSA:%.*]] = phi i64 [ [[TMP5]], [[BB3]] ]
; CHECK-NEXT: [[LANDING_PAD68:%.*]] = landingpad { ptr, i64 }
; CHECK-NEXT: cleanup
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i64> poison, i64 [[LOCAL_10_38123_LCSSA]], i32 0
-; CHECK-NEXT: [[TMP8]] = insertelement <2 x i64> [[TMP12]], i64 [[LOCAL_5_33118_LCSSA]], i32 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i64> poison, i64 [[LOCAL_10_38123_LCSSA]], i64 0
+; CHECK-NEXT: [[TMP8]] = insertelement <2 x i64> [[TMP12]], i64 [[LOCAL_5_33118_LCSSA]], i64 1
; CHECK-NEXT: br label [[BB9]]
; CHECK: bb11:
; CHECK-NEXT: ret void
@@ -80,8 +80,8 @@ define void @foo() personality ptr @bar {
; CHECK-NEXT: [[LOCAL_5_84111_LCSSA:%.*]] = phi i64 [ [[LOCAL_5_84111]], [[BB7]] ]
; CHECK-NEXT: [[LANDING_PAD149:%.*]] = landingpad { ptr, i64 }
; CHECK-NEXT: cleanup
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i64> poison, i64 [[LOCAL_10_89113_LCSSA]], i32 0
-; CHECK-NEXT: [[TMP9]] = insertelement <2 x i64> [[TMP11]], i64 [[LOCAL_5_84111_LCSSA]], i32 1
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i64> poison, i64 [[LOCAL_10_89113_LCSSA]], i64 0
+; CHECK-NEXT: [[TMP9]] = insertelement <2 x i64> [[TMP11]], i64 [[LOCAL_5_84111_LCSSA]], i64 1
; CHECK-NEXT: br label [[BB9]]
;
bb1:
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
index a5371cd051a5b..91a560f7782ac 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/loadi8.ll
@@ -14,10 +14,10 @@ define void @f_noalias(ptr noalias nocapture %dst, ptr noalias nocapture readonl
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[OFFSET]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[SRC:%.*]], align 1
; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = mul nsw <4 x i32> [[TMP5]], [[TMP3]]
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP9:%.*]] = add nsw <4 x i32> [[TMP6]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = icmp ult <4 x i32> [[TMP9]], splat (i32 256)
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
index 9a66b2ca84810..e1ca81edd2b39 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/long-non-power-of-2.ll
@@ -26,27 +26,27 @@ define i1 @test(ptr %arg, ptr %arg1, i64 %arg2, ptr %arg3) {
; CHECK-NEXT: [[AND22:%.*]] = and i1 false, [[ICMP21]]
; CHECK-NEXT: [[ICMP24:%.*]] = icmp ult ptr null, [[GETELEMENTPTR8]]
; CHECK-NEXT: [[AND25:%.*]] = and i1 false, [[ICMP24]]
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x ptr> <ptr poison, ptr poison, ptr null, ptr null>, ptr [[ARG]], i32 1
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x ptr> [[TMP17]], ptr [[GETELEMENTPTR7]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x ptr> <ptr poison, ptr poison, ptr null, ptr null>, ptr [[GETELEMENTPTR5]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x ptr> [[TMP2]], ptr [[GETELEMENTPTR8]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x ptr> <ptr poison, ptr poison, ptr null, ptr null>, ptr [[ARG]], i64 1
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x ptr> [[TMP0]], ptr [[GETELEMENTPTR7]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x ptr> <ptr poison, ptr poison, ptr null, ptr null>, ptr [[GETELEMENTPTR5]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x ptr> [[TMP2]], ptr [[GETELEMENTPTR8]], i64 1
; CHECK-NEXT: [[TMP20:%.*]] = icmp ult <4 x ptr> [[TMP19]], [[TMP7]]
; CHECK-NEXT: [[ICMP58:%.*]] = icmp ult ptr [[GETELEMENTPTR]], null
; CHECK-NEXT: [[ICMP62:%.*]] = icmp ult ptr [[GETELEMENTPTR]], null
; CHECK-NEXT: [[ICMP84:%.*]] = icmp ult ptr null, [[TMP32]]
; CHECK-NEXT: [[ICMP70:%.*]] = icmp ult ptr [[ARG]], [[GETELEMENTPTR5]]
; CHECK-NEXT: [[ICMP75:%.*]] = icmp ult ptr [[ARG1]], [[TMP32]]
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x ptr> <ptr poison, ptr poison, ptr poison, ptr poison, ptr null, ptr null, ptr poison, ptr poison, ptr poison, ptr poison, ptr poison, ptr null, ptr null, ptr null, ptr poison, ptr poison>, ptr [[GETELEMENTPTR8]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x ptr> [[TMP5]], ptr [[TMP32]], i32 8
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x ptr> <ptr poison, ptr poison, ptr poison, ptr poison, ptr null, ptr null, ptr poison, ptr poison, ptr poison, ptr poison, ptr poison, ptr null, ptr null, ptr null, ptr poison, ptr poison>, ptr [[GETELEMENTPTR8]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x ptr> [[TMP5]], ptr [[TMP32]], i64 8
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <16 x ptr> [[TMP6]], <16 x ptr> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 5, i32 0, i32 0, i32 8, i32 8, i32 8, i32 11, i32 12, i32 13, i32 8, i32 8>
; CHECK-NEXT: [[TMP8:%.*]] = icmp ult <16 x ptr> splat (ptr null), [[TMP18]]
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i1> [[TMP20]], <4 x i1> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i1> <i1 false, i1 false, i1 false, i1 false, i1 poison, i1 poison, i1 poison, i1 poison, i1 false, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 false, i1 false>, <16 x i1> [[TMP9]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 14, i32 15>
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i1> [[TMP10]], i1 [[ICMP58]], i32 9
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i1> [[TMP11]], i1 [[ICMP62]], i32 10
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i1> [[TMP12]], i1 [[ICMP84]], i32 11
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i1> [[TMP13]], i1 [[ICMP70]], i32 12
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i1> [[TMP14]], i1 [[ICMP75]], i32 13
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i1> [[TMP10]], i1 [[ICMP58]], i64 9
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i1> [[TMP11]], i1 [[ICMP62]], i64 10
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x i1> [[TMP12]], i1 [[ICMP84]], i64 11
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x i1> [[TMP13]], i1 [[ICMP70]], i64 12
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x i1> [[TMP14]], i1 [[ICMP75]], i64 13
; CHECK-NEXT: [[TMP16:%.*]] = and <16 x i1> [[TMP15]], [[TMP8]]
; CHECK-NEXT: [[ICMP85:%.*]] = icmp ult ptr null, [[TMP32]]
; CHECK-NEXT: [[AND86:%.*]] = and i1 false, [[ICMP85]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/matmul.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/matmul.ll
index 88b5d58f4d301..28ac7624e2488 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/matmul.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/matmul.ll
@@ -19,20 +19,20 @@ define void @wrap_mul4(ptr nocapture %Out, ptr nocapture readonly %A, ptr nocapt
; CHECK-NEXT: [[ARRAYIDX52_I:%.*]] = getelementptr inbounds [2 x double], ptr [[A]], i64 1, i64 1
; CHECK-NEXT: [[TEMP11:%.*]] = load double, ptr [[ARRAYIDX52_I]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr [[B]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> poison, double [[TEMP]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> poison, double [[TEMP]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fmul <4 x double> [[TMP3]], [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr [[ARRAYIDX7_I]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x double> poison, double [[TEMP2]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x double> poison, double [[TEMP2]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x double> [[TMP6]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = fmul <4 x double> [[TMP7]], [[TMP5]]
; CHECK-NEXT: [[TMP9:%.*]] = fadd <4 x double> [[TMP4]], [[TMP8]]
; CHECK-NEXT: store <4 x double> [[TMP9]], ptr [[OUT:%.*]], align 8
; CHECK-NEXT: [[RES_I_SROA_7_0_OUT2_I_SROA_IDX8:%.*]] = getelementptr inbounds double, ptr [[OUT]], i64 4
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x double> poison, double [[TEMP10]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x double> poison, double [[TEMP10]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP10]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP12:%.*]] = fmul <4 x double> [[TMP1]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x double> poison, double [[TEMP11]], i32 0
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x double> poison, double [[TEMP11]], i64 0
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x double> [[TMP13]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP15:%.*]] = fmul <4 x double> [[TMP5]], [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = fadd <4 x double> [[TMP12]], [[TMP15]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/memory-runtime-checks.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/memory-runtime-checks.ll
index 929fb29a4a679..44225f708b5bc 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/memory-runtime-checks.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/memory-runtime-checks.ll
@@ -673,8 +673,8 @@ define void @single_membound(ptr %arg, ptr %arg1, double %x) {
; CHECK-NEXT: [[TMP13:%.*]] = fsub double 1.000000e+00, [[TMP12]]
; CHECK-NEXT: br label [[BB15:%.*]]
; CHECK: bb15:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[TMP]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[TMP13]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[TMP]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[TMP13]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP1]], <double 2.000000e+01, double 3.000000e+01>
; CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[TMP9]], align 8
; CHECK-NEXT: ret void
@@ -1243,13 +1243,13 @@ define void @crash_no_tracked_instructions(ptr %arg, ptr %arg.2, ptr %arg.3, i1
; CHECK-NEXT: entry:
; CHECK-NEXT: [[T19:%.*]] = load ptr, ptr [[ARG:%.*]], align 8
; CHECK-NEXT: [[T20:%.*]] = load float, ptr [[ARG_3:%.*]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[T20]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[T20]], i64 1
; CHECK-NEXT: br i1 [[C:%.*]], label [[BB22:%.*]], label [[BB30:%.*]]
; CHECK: bb22:
; CHECK-NEXT: [[T23:%.*]] = fmul float [[T20]], 9.900000e+01
; CHECK-NEXT: [[T25:%.*]] = getelementptr inbounds float, ptr [[T19]], i64 2
; CHECK-NEXT: [[T26:%.*]] = fmul float [[T23]], 1.000000e+01
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[T23]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[T23]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP2]], <float 9.900000e+01, float 1.000000e+01>
; CHECK-NEXT: store float [[T26]], ptr [[T25]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/non-inst-abs-sub-copyable-value.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/non-inst-abs-sub-copyable-value.ll
index 329e4d2debcf6..205918b92724e 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/non-inst-abs-sub-copyable-value.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/non-inst-abs-sub-copyable-value.ll
@@ -5,12 +5,12 @@ define i1 @test(i32 %shr.i.i90, i32 %x) {
; CHECK-LABEL: define i1 @test(
; CHECK-SAME: i32 [[SHR_I_I90:%.*]], i32 [[X:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[X]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[SHR_I_I90]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[X]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[SHR_I_I90]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> [[TMP6]], <i32 2, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[TMP1]], i1 true)
; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt <2 x i32> [[TMP2]], <i32 100, i32 300>
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i64 0
; CHECK-NEXT: ret i1 [[TMP5]]
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
index 7a426a9d861d1..ef92fe5d782ae 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
@@ -7,10 +7,10 @@ define i1 @test(ptr %arg, ptr %arg1, i1 %arg2, i1 %arg3, i1 %arg4) {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr i8, ptr [[ARG1]], i64 3684
; CHECK-NEXT: [[GETELEMENTPTR5:%.*]] = getelementptr i8, ptr [[ARG]], i64 21
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr [[ARG1]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr [[ARG1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x ptr> [[TMP0]], <8 x ptr> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, <8 x ptr> [[TMP1]], <8 x i64> <i64 8484, i64 8484, i64 8484, i64 5284, i64 8484, i64 8484, i64 8484, i64 8484>
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x ptr> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x ptr> [[TMP2]], i64 0
; CHECK-NEXT: [[ICMP:%.*]] = icmp ult ptr [[TMP3]], null
; CHECK-NEXT: [[ICMP7:%.*]] = icmp ult ptr null, null
; CHECK-NEXT: [[AND:%.*]] = and i1 false, [[ICMP7]]
@@ -19,9 +19,9 @@ define i1 @test(ptr %arg, ptr %arg1, i1 %arg2, i1 %arg3, i1 %arg4) {
; CHECK-NEXT: [[ICMP14:%.*]] = icmp ult ptr null, null
; CHECK-NEXT: [[AND15:%.*]] = and i1 false, [[ICMP14]]
; CHECK-NEXT: [[TMP4:%.*]] = icmp ult <8 x ptr> [[TMP2]], splat (ptr null)
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i1> <i1 false, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, i1 [[ARG2]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i1> <i1 false, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, i1 [[ARG2]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = and <8 x i1> [[TMP4]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x ptr> [[TMP2]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x ptr> [[TMP2]], i64 3
; CHECK-NEXT: [[ICMP46:%.*]] = icmp ult ptr [[TMP7]], null
; CHECK-NEXT: [[AND47:%.*]] = and i1 false, [[ICMP46]]
; CHECK-NEXT: [[ICMP49:%.*]] = icmp ult ptr [[ARG]], null
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/phi-node-bitwidt-op-not.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/phi-node-bitwidt-op-not.ll
index 15f4cffe77910..6d7b7e489be0d 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/phi-node-bitwidt-op-not.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/phi-node-bitwidt-op-not.ll
@@ -7,18 +7,18 @@ define i32 @test(ptr %b, ptr %c, i32 %0, ptr %a, i1 %tobool3.not) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[TOBOOL3_NOT]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[TMP2]], splat (i32 16)
; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <4 x i32> [[TMP3]], [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i1> [[TMP4]] to <4 x i16>
; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i32> [[TMP7]], zeroinitializer
; CHECK-NEXT: [[TMP9:%.*]] = zext <4 x i1> [[TMP8]] to <4 x i32>
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i1> poison, i1 [[TOBOOL3_NOT]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i1> poison, i1 [[TOBOOL3_NOT]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i1> [[TMP10]], <4 x i1> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP7]], <4 x i32> [[TMP9]]
; CHECK-NEXT: [[TMP13:%.*]] = shl <4 x i32> [[TMP12]], splat (i32 16)
@@ -27,16 +27,16 @@ define i32 @test(ptr %b, ptr %c, i32 %0, ptr %a, i1 %tobool3.not) {
; CHECK-NEXT: br i1 true, label [[BB3]], label [[BB2]]
; CHECK: bb3:
; CHECK-NEXT: [[TMP16:%.*]] = phi <4 x i16> [ [[TMP5]], [[BB1]] ], [ [[TMP15]], [[BB2]] ]
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i16> [[TMP16]], i32 0
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i16> [[TMP16]], i64 0
; CHECK-NEXT: [[TMP18:%.*]] = sext i16 [[TMP17]] to i32
; CHECK-NEXT: store i32 [[TMP18]], ptr [[B]], align 16
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i16> [[TMP16]], i32 1
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i16> [[TMP16]], i64 1
; CHECK-NEXT: [[TMP20:%.*]] = sext i16 [[TMP19]] to i32
; CHECK-NEXT: store i32 [[TMP20]], ptr [[A]], align 8
-; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i16> [[TMP16]], i32 2
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i16> [[TMP16]], i64 2
; CHECK-NEXT: [[TMP22:%.*]] = sext i16 [[TMP21]] to i32
; CHECK-NEXT: store i32 [[TMP22]], ptr [[C]], align 16
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i16> [[TMP16]], i32 3
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i16> [[TMP16]], i64 3
; CHECK-NEXT: [[TMP24:%.*]] = sext i16 [[TMP23]] to i32
; CHECK-NEXT: store i32 [[TMP24]], ptr [[B]], align 8
; CHECK-NEXT: ret i32 0
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-node.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-node.ll
index f5de6e4c33037..0500c00537a32 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-node.ll
@@ -5,14 +5,14 @@ define { double, double } @test1(ptr %0, double %.unpack753, double %factor828)
; CHECK-LABEL: define { double, double } @test1(
; CHECK-SAME: ptr [[TMP0:%.*]], double [[DOTUNPACK753:%.*]], double [[FACTOR828:%.*]]) {
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[TMP0]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double 1.000000e+00>, double [[DOTUNPACK753]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double 1.000000e+00>, double [[DOTUNPACK753]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP3]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> <double 0.000000e+00, double poison>, <2 x i32> <i32 2, i32 0>
; CHECK-NEXT: [[TMP7:%.*]] = fmul <2 x double> [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = fmul <2 x double> [[TMP7]], zeroinitializer
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x double> [[TMP7]], <2 x double> [[TMP5]], <2 x i32> <i32 1, i32 2>
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x double> <double poison, double f0xC1502A98AE76C8B4>, double [[FACTOR828]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x double> <double poison, double f0xC1502A98AE76C8B4>, double [[FACTOR828]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = fmul <2 x double> [[TMP9]], [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = fadd contract <2 x double> [[TMP11]], zeroinitializer
; CHECK-NEXT: [[TMP13:%.*]] = fmul <2 x double> [[TMP12]], zeroinitializer
@@ -26,21 +26,21 @@ define { double, double } @test1(ptr %0, double %.unpack753, double %factor828)
; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <4 x double> <double poison, double poison, double -0.000000e+00, double poison>, <4 x double> [[TMP20]], <4 x i32> <i32 4, i32 5, i32 2, i32 poison>
; CHECK-NEXT: [[TMP22:%.*]] = shufflevector <4 x double> [[TMP21]], <4 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 1>
; CHECK-NEXT: [[TMP23:%.*]] = fadd contract <4 x double> [[TMP19]], [[TMP22]]
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x double> <double poison, double 1.000000e+00, double poison, double poison>, double [[DOTUNPACK753]], i32 0
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x double> <double poison, double 1.000000e+00, double poison, double poison>, double [[DOTUNPACK753]], i64 0
; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x double> [[TMP24]], <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 0>
; CHECK-NEXT: [[TMP26:%.*]] = fmul <4 x double> [[TMP23]], [[TMP25]]
; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <4 x double> [[TMP24]], <4 x double> <double 0.000000e+00, double poison, double poison, double poison>, <4 x i32> <i32 4, i32 0, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP28:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP29:%.*]] = shufflevector <4 x double> [[TMP27]], <4 x double> [[TMP28]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: [[TMP30:%.*]] = fadd <4 x double> [[TMP29]], [[TMP26]]
-; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x double> [[TMP30]], i32 0
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x double> [[TMP30]], i64 0
; CHECK-NEXT: [[TMP32:%.*]] = call { double, double } @__divdc3(double [[TMP31]])
; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr null)
-; CHECK-NEXT: [[TMP33:%.*]] = extractelement <4 x double> [[TMP30]], i32 1
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <4 x double> [[TMP30]], i64 1
; CHECK-NEXT: [[TMP34:%.*]] = call { double, double } @__divdc3(double [[TMP33]])
-; CHECK-NEXT: [[TMP35:%.*]] = extractelement <4 x double> [[TMP30]], i32 2
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <4 x double> [[TMP30]], i64 2
; CHECK-NEXT: [[TMP36:%.*]] = call { double, double } @__divdc3(double [[TMP35]])
-; CHECK-NEXT: [[TMP37:%.*]] = extractelement <4 x double> [[TMP30]], i32 3
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <4 x double> [[TMP30]], i64 3
; CHECK-NEXT: [[TMP38:%.*]] = call { double, double } @__divdc3(double [[TMP37]])
; CHECK-NEXT: ret { double, double } [[TMP38]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
index 8d7d7b0f4e9e6..3ddb6978b7aa1 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/reduce-fadd.ll
@@ -603,8 +603,8 @@ define float @reduce_float_case2(ptr %a, ptr %b) {
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x float> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[ADD2:%.*]] = fadd float [[LOADA3]], [[LOADB2]]
; CHECK-NEXT: [[ADD3:%.*]] = fadd float [[LOADA2]], [[LOADB3]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; CHECK-NEXT: [[RED1:%.*]] = fadd float [[TMP3]], [[TMP4]]
; CHECK-NEXT: [[RED2:%.*]] = fadd float [[ADD2]], [[RED1]]
; CHECK-NEXT: [[RED3:%.*]] = fadd float [[ADD3]], [[RED2]]
@@ -802,8 +802,8 @@ define half @reduce_unordered_half4(<4 x half> %vec4) {
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x half> [[VEC4]], <4 x half> poison, <2 x i32> <i32 1, i32 2>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x half> [[VEC4]], <4 x half> poison, <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x half> [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x half> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x half> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x half> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x half> [[TMP2]], i64 1
; CHECK-NEXT: [[ADD3:%.*]] = fadd half [[TMP3]], [[TMP4]]
; CHECK-NEXT: ret half [[ADD3]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/reorder-fmuladd-crash.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/reorder-fmuladd-crash.ll
index b1bd2546c26f4..6d19cb2f4f09b 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/reorder-fmuladd-crash.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/reorder-fmuladd-crash.ll
@@ -4,7 +4,7 @@
define i32 @foo(i32 %v1, double %v2, i1 %arg, i32 %arg2) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[V1:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[V1:%.*]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = sitofp <2 x i32> [[TMP0]] to <2 x double>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; CHECK-NEXT: br label [[FOR_COND15_PREHEADER:%.*]]
@@ -21,7 +21,7 @@ define i32 @foo(i32 %v1, double %v2, i1 %arg, i32 %arg2) {
; CHECK-NEXT: ]
; CHECK: sw.bb:
; CHECK-NEXT: [[ARRAYIDX43:%.*]] = getelementptr inbounds [4 x [2 x double]], ptr undef, i32 0, i64 1, i64 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[V2:%.*]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[V2:%.*]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP3]], [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[TMP6:%.*]] = load <4 x double>, ptr [[ARRAYIDX43]], align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
index ebb1f4de65561..43b2c732127e0 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/reused-scalar-repeated-in-node.ll
@@ -24,24 +24,24 @@ define void @test() {
; CHECK-NEXT: [[I74:%.*]] = load float, ptr poison, align 4
; CHECK-NEXT: [[I75:%.*]] = load float, ptr poison, align 16
; CHECK-NEXT: [[I76:%.*]] = load float, ptr poison, align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x float> poison, float [[I76]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x float> [[TMP1]], float [[I75]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x float> [[TMP2]], float [[I74]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x float> [[TMP3]], float [[I73]], i32 3
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x float> [[TMP4]], float [[I71]], i32 4
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x float> [[TMP5]], float [[I70]], i32 5
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x float> [[TMP6]], float [[I68]], i32 6
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x float> [[TMP7]], float [[I66]], i32 7
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x float> [[TMP8]], float [[I72]], i32 13
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x float> [[TMP9]], float [[I67]], i32 14
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x float> [[TMP10]], float [[I69]], i32 15
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x float> poison, float [[I76]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x float> [[TMP1]], float [[I75]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x float> [[TMP2]], float [[I74]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x float> [[TMP3]], float [[I73]], i64 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x float> [[TMP4]], float [[I71]], i64 4
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x float> [[TMP5]], float [[I70]], i64 5
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x float> [[TMP6]], float [[I68]], i64 6
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x float> [[TMP7]], float [[I66]], i64 7
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x float> [[TMP8]], float [[I72]], i64 13
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x float> [[TMP9]], float [[I67]], i64 14
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x float> [[TMP10]], float [[I69]], i64 15
; CHECK-NEXT: br i1 poison, label %[[BB167:.*]], label %[[BB77:.*]]
; CHECK: [[BB77]]:
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x float> poison, float [[I66]], i32 1
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x float> [[TMP12]], float [[I70]], i32 2
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x float> [[TMP13]], float [[I68]], i32 3
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x float> [[TMP14]], float [[I67]], i32 6
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x float> [[TMP15]], float [[I69]], i32 7
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x float> poison, float [[I66]], i64 1
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x float> [[TMP12]], float [[I70]], i64 2
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x float> [[TMP13]], float [[I68]], i64 3
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x float> [[TMP14]], float [[I67]], i64 6
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x float> [[TMP15]], float [[I69]], i64 7
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <16 x i32> <i32 poison, i32 poison, i32 3, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <16 x float> [[TMP20]], <16 x float> [[TMP0]], <16 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 18, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 19, i32 poison, i32 poison>
; CHECK-NEXT: br label %[[BB78:.*]]
@@ -61,19 +61,19 @@ define void @test() {
; CHECK-NEXT: [[TMP31]] = shufflevector <16 x float> [[TMP30]], <16 x float> poison, <8 x i32> <i32 12, i32 7, i32 5, i32 6, i32 11, i32 10, i32 14, i32 15>
; CHECK-NEXT: br i1 poison, label %[[BB78]], label %[[BB167]]
; CHECK: [[BB167]]:
-; CHECK-NEXT: [[TMP35:%.*]] = phi <16 x float> [ [[TMP11]], %[[BB64]] ], [ [[TMP30]], %[[BB78]] ]
-; CHECK-NEXT: [[TMP33:%.*]] = extractelement <16 x float> [[TMP35]], i32 14
+; CHECK-NEXT: [[TMP36:%.*]] = phi <16 x float> [ [[TMP11]], %[[BB64]] ], [ [[TMP30]], %[[BB78]] ]
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <16 x float> [[TMP36]], i64 14
; CHECK-NEXT: store float [[TMP33]], ptr poison, align 1
-; CHECK-NEXT: [[TMP34:%.*]] = extractelement <16 x float> [[TMP35]], i32 13
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <16 x float> [[TMP36]], i64 13
; CHECK-NEXT: store float [[TMP34]], ptr poison, align 1
-; CHECK-NEXT: [[TMP36:%.*]] = extractelement <16 x float> [[TMP35]], i32 15
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <16 x float> [[TMP36]], i64 15
; CHECK-NEXT: br i1 poison, label %[[BB186:.*]], label %[[BB184:.*]]
; CHECK: [[BB184]]:
; CHECK-NEXT: br label %[[BB185:.*]]
; CHECK: [[BB185]]:
; CHECK-NEXT: br i1 poison, label %[[BB185]], label %[[BB186]]
; CHECK: [[BB186]]:
-; CHECK-NEXT: [[I187:%.*]] = phi nsz float [ [[TMP36]], %[[BB167]] ], [ poison, %[[BB185]] ]
+; CHECK-NEXT: [[I187:%.*]] = phi nsz float [ [[TMP35]], %[[BB167]] ], [ poison, %[[BB185]] ]
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/scalarization-overhead.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/scalarization-overhead.ll
index 5fb468c0b0962..e436f739ba208 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/scalarization-overhead.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/scalarization-overhead.ll
@@ -9,11 +9,11 @@ define fastcc i64 @zot(float %arg, float %arg1, float %arg2, float %arg3, float
; CHECK-LABEL: @zot(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[VAL9:%.*]] = fmul fast float 0.000000e+00, [[ARG:%.*]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> <float 0.000000e+00, float poison, float poison, float poison>, float [[ARG]], i32 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[ARG3:%.*]], i32 2
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> <float 0.000000e+00, float poison, float poison, float poison>, float [[ARG]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[ARG3:%.*]], i64 2
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <4 x float> <float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, float 1.000000e+00>, [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[ARG3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[ARG3]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = fadd fast <2 x float> [[TMP4]], <float 1.000000e+00, float 0.000000e+00>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x float> [[TMP5]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[TMP6]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
@@ -21,9 +21,9 @@ define fastcc i64 @zot(float %arg, float %arg1, float %arg2, float %arg3, float
; CHECK-NEXT: br i1 [[ARG6:%.*]], label [[BB18:%.*]], label [[BB57:%.*]]
; CHECK: bb18:
; CHECK-NEXT: [[TMP9:%.*]] = phi <4 x float> [ [[TMP8]], [[BB:%.*]] ]
-; CHECK-NEXT: [[VAL16:%.*]] = extractelement <4 x float> [[TMP8]], i32 2
+; CHECK-NEXT: [[VAL16:%.*]] = extractelement <4 x float> [[TMP8]], i64 2
; CHECK-NEXT: [[VAL23:%.*]] = fmul fast float [[VAL16]], 2.000000e+00
-; CHECK-NEXT: [[VAL17:%.*]] = extractelement <4 x float> [[TMP8]], i32 3
+; CHECK-NEXT: [[VAL17:%.*]] = extractelement <4 x float> [[TMP8]], i64 3
; CHECK-NEXT: [[VAL24:%.*]] = fmul fast float [[VAL17]], 3.000000e+00
; CHECK-NEXT: br i1 [[ARG7:%.*]], label [[BB25:%.*]], label [[BB57]]
; CHECK: bb25:
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/shuffle-vectors-mask-size.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/shuffle-vectors-mask-size.ll
index 961662c664a31..fa30a266c187f 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/shuffle-vectors-mask-size.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/shuffle-vectors-mask-size.ll
@@ -5,7 +5,7 @@ define void @p(double %0) {
; CHECK-LABEL: define void @p(
; CHECK-SAME: double [[TMP0:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double poison>, double [[TMP0]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double poison>, double [[TMP0]], i64 3
; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x double> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fadd <4 x double> zeroinitializer, [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = fadd <4 x double> [[TMP3]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/slp-extval-struct-operand-no-scalar-reuse.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/slp-extval-struct-operand-no-scalar-reuse.ll
index 2f84803994136..84b2f45b80bbf 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/slp-extval-struct-operand-no-scalar-reuse.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/slp-extval-struct-operand-no-scalar-reuse.ll
@@ -8,9 +8,9 @@ define [2 x i64] @test() {
; CHECK-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> zeroinitializer, <2 x i32> zeroinitializer)
; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.ssub.with.overflow.v2i32(<2 x i32> zeroinitializer, <2 x i32> [[TMP0]])
; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP1]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP2]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP1]], 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i64 0
; CHECK-NEXT: [[RETVAL_SROA_5_8_INSERT_SHIFT_I52_I:%.*]] = select i1 [[TMP5]], i64 0, i64 0
; CHECK-NEXT: [[TMP6:%.*]] = zext <2 x i1> [[TMP4]] to <2 x i64>
; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr getelementptr inbounds nuw (i8, ptr null, i64 104), align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll
index c836b29117f4c..ae549838774b8 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/slp-fma-loss.ll
@@ -211,9 +211,9 @@ define float @slp_not_profitable_in_loop(float %x, ptr %A) {
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x float> [[TMP0]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[L_3:%.*]] = load float, ptr [[A]], align 4
; CHECK-NEXT: [[L_4:%.*]] = load float, ptr [[A]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> <float 3.000000e+00, float 3.000000e+00, float poison, float 3.000000e+00>, float [[X:%.*]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[L_3]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[L_4]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> <float 3.000000e+00, float 3.000000e+00, float poison, float 3.000000e+00>, float [[X:%.*]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[L_3]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[L_4]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: br label [[LOOP:%.*]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-loop-backedge.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-loop-backedge.ll
index fb3ef2102aae1..29e6a3a354354 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-loop-backedge.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-loop-backedge.ll
@@ -18,8 +18,8 @@ define void @test_spillcost_backedge(ptr noalias %res, ptr noalias %in, double %
; CHECK-LABEL: define void @test_spillcost_backedge(
; CHECK-SAME: ptr noalias [[RES:%.*]], ptr noalias [[IN:%.*]], double [[X:%.*]], double [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[X]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[Y]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[X]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[Y]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fdiv <2 x double> splat (double 1.000000e+00), [[TMP1]]
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
; CHECK: [[LOOP_HEADER]]:
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-noreturn-block.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-noreturn-block.ll
index 36f56ac2774d5..8961093b01626 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-noreturn-block.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/spillcost-noreturn-block.ll
@@ -18,13 +18,13 @@ declare void @abort() noreturn
define void @test_noreturn_in_loop_body(ptr noalias %res, ptr noalias %in, double %x, double %y, i1 %err) {
; CHECK-LABEL: define void @test_noreturn_in_loop_body(
; CHECK-SAME: ptr noalias [[RES:%.*]], ptr noalias [[IN:%.*]], double [[X:%.*]], double [[Y:%.*]], i1 [[ERR:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[X]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[Y]], i32 1
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[X]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[Y]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fdiv <2 x double> splat (double 1.000000e+00), [[TMP1]]
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
; CHECK: [[LOOP_HEADER]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY:.*]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[IV]], 100
; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP_BODY:.*]], label %[[EXIT:.*]]
; CHECK: [[LOOP_BODY]]:
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/splat-loads.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/splat-loads.ll
index 094d60b66b393..b6dc4735a0be4 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/splat-loads.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/splat-loads.ll
@@ -12,10 +12,10 @@ define void @splat_loads_double(ptr %array1, ptr %array2, ptr %ptrA, ptr %ptrB)
; CHECK-NEXT: [[LD_2_0:%.*]] = load double, ptr [[ARRAY2]], align 8
; CHECK-NEXT: [[LD_2_1:%.*]] = load double, ptr [[GEP_2_1]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[ARRAY1:%.*]], align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[LD_2_0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[LD_2_0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP0]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[LD_2_1]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[LD_2_1]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x double> [[TMP0]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = fadd <2 x double> [[TMP3]], [[TMP6]]
@@ -53,10 +53,10 @@ define void @splat_loads_float(ptr %array1, ptr %array2, ptr %ptrA, ptr %ptrB) {
; CHECK-NEXT: [[LD_2_0:%.*]] = load float, ptr [[ARRAY2]], align 8
; CHECK-NEXT: [[LD_2_1:%.*]] = load float, ptr [[GEP_2_1]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[ARRAY1:%.*]], align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[LD_2_0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[LD_2_0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP0]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> poison, float [[LD_2_1]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> poison, float [[LD_2_1]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x float> [[TMP0]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = fadd <2 x float> [[TMP3]], [[TMP6]]
@@ -94,10 +94,10 @@ define void @splat_loads_i64(ptr %array1, ptr %array2, ptr %ptrA, ptr %ptrB) {
; CHECK-NEXT: [[LD_2_2:%.*]] = load i64, ptr [[ARRAY3]], align 8
; CHECK-NEXT: [[LD_2_3:%.*]] = load i64, ptr [[GEP_2_2]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[ARRAY1:%.*]], align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[LD_2_2]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[LD_2_2]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP0]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> poison, i64 [[LD_2_3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> poison, i64 [[LD_2_3]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP0]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = add <2 x i64> [[TMP3]], [[TMP6]]
@@ -135,10 +135,10 @@ define void @splat_loads_i32(ptr %array1, ptr %array2, ptr %ptrA, ptr %ptrB) {
; CHECK-NEXT: [[LD_2_2:%.*]] = load i32, ptr [[ARRAY3]], align 8
; CHECK-NEXT: [[LD_2_3:%.*]] = load i32, ptr [[GEP_2_2]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[ARRAY1:%.*]], align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[LD_2_2]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[LD_2_2]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP0]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[LD_2_3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[LD_2_3]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i32> [[TMP0]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = add <2 x i32> [[TMP3]], [[TMP6]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/transpose-with-constants.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/transpose-with-constants.ll
index 66461c9d91064..8f18ccde8ebba 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/transpose-with-constants.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/transpose-with-constants.ll
@@ -7,7 +7,7 @@ target triple = "aarch64--linux-gnu"
define dso_local <16 x i8> @transpose_splat_constants(i8 noundef %x) {
; CHECK-LABEL: @transpose_splat_constants(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 1, i32 poison, i32 2, i32 poison, i32 3, i32 poison, i32 4, i32 poison, i32 5, i32 poison, i32 6, i32 poison, i32 7, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> <i8 poison, i8 0, i8 poison, i8 1, i8 poison, i8 2, i8 poison, i8 3, i8 poison, i8 4, i8 poison, i8 5, i8 poison, i8 6, i8 poison, i8 7>, <16 x i8> [[TMP2]], <16 x i32> <i32 16, i32 1, i32 18, i32 3, i32 20, i32 5, i32 22, i32 7, i32 24, i32 9, i32 26, i32 11, i32 28, i32 13, i32 30, i32 15>
@@ -28,7 +28,7 @@ entry:
define dso_local <16 x i8> @transpose_constants_splat(i8 noundef %x) {
; CHECK-LABEL: @transpose_constants_splat(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> poison, <16 x i32> <i32 0, i32 poison, i32 1, i32 poison, i32 2, i32 poison, i32 3, i32 poison, i32 4, i32 poison, i32 5, i32 poison, i32 6, i32 poison, i32 7, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> <i8 0, i8 poison, i8 1, i8 poison, i8 2, i8 poison, i8 3, i8 poison, i8 4, i8 poison, i8 5, i8 poison, i8 6, i8 poison, i8 7, i8 poison>, <16 x i8> [[TMP2]], <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll
index e091063130e03..a25c0e6d21fac 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll
@@ -27,10 +27,10 @@ define dso_local void @l(i1 %arg) local_unnamed_addr {
; CHECK-NEXT: [[I28:%.*]] = phi i32 [ [[I12]], [[BB11]] ], [ [[I4]], [[BB3]] ]
; CHECK-NEXT: [[TMP8:%.*]] = phi <2 x i1> [ [[TMP7]], [[BB11]] ], [ [[TMP2]], [[BB3]] ]
; CHECK-NEXT: [[TMP9]] = phi <2 x i16> [ [[TMP3]], [[BB11]] ], [ [[TMP1]], [[BB3]] ]
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP8]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = zext i1 [[TMP10]] to i32
; CHECK-NEXT: [[I31:%.*]] = and i32 undef, [[TMP11]]
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP8]], i64 1
; CHECK-NEXT: [[TMP13:%.*]] = zext i1 [[TMP12]] to i32
; CHECK-NEXT: [[I32:%.*]] = and i32 [[I31]], [[TMP13]]
; CHECK-NEXT: [[I33:%.*]] = and i32 [[I32]], [[I28]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
index 92027d0043f76..39855162a995b 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s116.ll
@@ -21,7 +21,7 @@ define void @s116_modified(ptr %a) {
; CHECK-NEXT: [[LD0:%.*]] = load float, ptr [[A]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[GEP1]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 0, i32 2, i32 3, i32 poison>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP2]], float [[LD0]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP2]], float [[LD0]], i64 3
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 1, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP8:%.*]] = fmul fast <4 x float> [[TMP6]], [[TMP7]]
; CHECK-NEXT: store <4 x float> [[TMP8]], ptr [[GEP1]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s352.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s352.ll
index c9a2219b12a8a..6876ea4f2de65 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s352.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/tsc-s352.ll
@@ -34,13 +34,13 @@ define i32 @s352() {
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[ARRAYIDX6]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x float> [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP2]], i64 0
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[DOT_115]], [[TMP5]]
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP2]], i64 1
; CHECK-NEXT: [[ADD15:%.*]] = fadd float [[ADD]], [[TMP6]]
-; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP2]], i32 2
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP2]], i64 2
; CHECK-NEXT: [[ADD23:%.*]] = fadd float [[ADD15]], [[TMP13]]
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x float> [[TMP2]], i32 3
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x float> [[TMP2]], i64 3
; CHECK-NEXT: [[ADD31:%.*]] = fadd float [[ADD23]], [[TMP14]]
; CHECK-NEXT: [[TMP15:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 4
; CHECK-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [[STRUCT_GLOBALDATA]], ptr @global_data, i64 0, i32 0, i64 [[TMP15]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/unique_values.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/unique_values.ll
index a5882b251dab5..fffa66859fff2 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/unique_values.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/unique_values.ll
@@ -15,7 +15,7 @@ define void @foo(ptr noalias %A, ptr noalias %B) {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = udiv <2 x i32> [[TMP1]], <i32 3, i32 8>
; CHECK-NEXT: store <2 x i32> [[TMP4]], ptr [[A1]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP4]], i64 0
; CHECK-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX2_2]], align 4
; CHECK-NEXT: store i32 [[ADD_3]], ptr [[ARRAYIDX2_3]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/uselistorder.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/uselistorder.ll
index 3a68a37c9f82c..337bce76c23af 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/uselistorder.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/uselistorder.ll
@@ -7,8 +7,8 @@ target triple = "aarch64-unknown-linux-gnu"
; This test has UB but the crash in #95016 only happens with it
define void @uselistorder_test() {
; CHECK-LABEL: @uselistorder_test(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double 0.000000e+00, i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 0.000000e+00, i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double 0.000000e+00, i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 0.000000e+00, i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> zeroinitializer, [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
index d91ad0621fbfe..21ce38cd2bd8c 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
@@ -336,7 +336,7 @@ define void @vec3_fpext_cost(ptr %Colour, float %0) {
; CHECK-LABEL: @vec3_fpext_cost(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ARRAYIDX80:%.*]] = getelementptr float, ptr [[COLOUR:%.*]], i64 2
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0:%.*]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fpext <2 x float> [[TMP2]] to <2 x double>
; CHECK-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP3]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
index 833bc56c4ec6b..577fad27a5340 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-calls.ll
@@ -6,7 +6,7 @@ define void @vec3_vectorize_call(ptr %Colour, float %0) {
; NON-POWER-OF-2-LABEL: @vec3_vectorize_call(
; NON-POWER-OF-2-NEXT: entry:
; NON-POWER-OF-2-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[COLOUR:%.*]], align 4
-; NON-POWER-OF-2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP0:%.*]], i32 2
+; NON-POWER-OF-2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP0:%.*]], i64 2
; NON-POWER-OF-2-NEXT: [[TMP3:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; NON-POWER-OF-2-NEXT: [[TMP4:%.*]] = shufflevector <3 x float> [[TMP2]], <3 x float> [[TMP3]], <3 x i32> <i32 3, i32 4, i32 2>
; NON-POWER-OF-2-NEXT: [[TMP5:%.*]] = call <3 x float> @llvm.fmuladd.v3f32(<3 x float> [[TMP4]], <3 x float> zeroinitializer, <3 x float> zeroinitializer)
@@ -41,7 +41,7 @@ define void @vec3_fmuladd_64(ptr %Colour, double %0) {
; CHECK-LABEL: @vec3_fmuladd_64(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ARRAYIDX80:%.*]] = getelementptr float, ptr [[COLOUR:%.*]], i64 2
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP2]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
; CHECK-NEXT: [[TMP4:%.*]] = fptrunc <2 x double> [[TMP3]] to <2 x float>
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
index f616964584d98..0d333ac022d1a 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
@@ -74,13 +74,13 @@ define void @extract_mask(ptr %object, double %conv503, double %conv520) {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[BBOX483]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[CONV503]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[CONV503]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = fcmp ogt <2 x double> [[TMP4]], <double 0.000000e+00, double -2.000000e+10>
; CHECK-NEXT: [[TMP6:%.*]] = select <2 x i1> [[TMP5]], <2 x double> [[TMP3]], <2 x double> <double 0.000000e+00, double -2.000000e+10>
; CHECK-NEXT: [[TMP7:%.*]] = fsub <2 x double> zeroinitializer, [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = fptrunc <2 x double> [[TMP7]] to <2 x float>
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP8]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x float> [[TMP8]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP8]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x float> [[TMP8]], i64 1
; CHECK-NEXT: [[MUL646:%.*]] = fmul float [[TMP9]], [[TMP10]]
; CHECK-NEXT: [[CMP663:%.*]] = fcmp olt float [[MUL646]], 0.000000e+00
; CHECK-NEXT: br i1 [[CMP663]], label [[IF_THEN665:%.*]], label [[IF_END668:%.*]]
@@ -89,7 +89,7 @@ define void @extract_mask(ptr %object, double %conv503, double %conv520) {
; CHECK-NEXT: [[BBOX651:%.*]] = getelementptr float, ptr [[OBJECT]]
; CHECK-NEXT: [[CONV621:%.*]] = fptrunc double [[CONV520]] to float
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> poison, <2 x i32> <i32 poison, i32 0>
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x double> [[TMP11]], double [[CONV503]], i32 0
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x double> [[TMP11]], double [[CONV503]], i64 0
; CHECK-NEXT: [[TMP13:%.*]] = fptrunc <2 x double> [[TMP12]] to <2 x float>
; CHECK-NEXT: store <2 x float> [[TMP13]], ptr [[BBOX651]], align 8
; CHECK-NEXT: [[BBOX_SROA_8_0_BBOX666_SROA_IDX:%.*]] = getelementptr float, ptr [[OBJECT]], i64 2
@@ -143,9 +143,9 @@ define void @gather_2(ptr %mat1, float %0, float %1) {
; NON-POW2-LABEL: define void @gather_2(
; NON-POW2-SAME: ptr [[MAT1:%.*]], float [[TMP0:%.*]], float [[TMP1:%.*]]) {
; NON-POW2-NEXT: entry:
-; NON-POW2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP0]], i32 0
+; NON-POW2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP0]], i64 0
; NON-POW2-NEXT: [[TMP3:%.*]] = shufflevector <3 x float> [[TMP2]], <3 x float> poison, <3 x i32> zeroinitializer
-; NON-POW2-NEXT: [[TMP4:%.*]] = insertelement <3 x float> <float 0.000000e+00, float poison, float poison>, float [[TMP1]], i32 1
+; NON-POW2-NEXT: [[TMP4:%.*]] = insertelement <3 x float> <float 0.000000e+00, float poison, float poison>, float [[TMP1]], i64 1
; NON-POW2-NEXT: [[TMP5:%.*]] = shufflevector <3 x float> [[TMP4]], <3 x float> poison, <3 x i32> <i32 0, i32 1, i32 1>
; NON-POW2-NEXT: [[TMP6:%.*]] = call <3 x float> @llvm.fmuladd.v3f32(<3 x float> [[TMP3]], <3 x float> [[TMP5]], <3 x float> zeroinitializer)
; NON-POW2-NEXT: [[ARRAYIDX163:%.*]] = getelementptr [4 x [4 x float]], ptr [[MAT1]], i64 0, i64 1
@@ -156,9 +156,9 @@ define void @gather_2(ptr %mat1, float %0, float %1) {
; POW2-ONLY-LABEL: define void @gather_2(
; POW2-ONLY-SAME: ptr [[MAT1:%.*]], float [[TMP0:%.*]], float [[TMP1:%.*]]) {
; POW2-ONLY-NEXT: entry:
-; POW2-ONLY-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 0
+; POW2-ONLY-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i64 0
; POW2-ONLY-NEXT: [[TMP3:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <2 x i32> zeroinitializer
-; POW2-ONLY-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP1]], i32 1
+; POW2-ONLY-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP1]], i64 1
; POW2-ONLY-NEXT: [[TMP5:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[TMP3]], <2 x float> [[TMP4]], <2 x float> zeroinitializer)
; POW2-ONLY-NEXT: [[TMP6:%.*]] = call float @llvm.fmuladd.f32(float [[TMP0]], float [[TMP1]], float 0.000000e+00)
; POW2-ONLY-NEXT: [[TMP7:%.*]] = fmul float [[TMP6]], 0.000000e+00
@@ -193,7 +193,7 @@ define i32 @reorder_indices_1(float %0) {
; NON-POW2-NEXT: [[TMP1:%.*]] = load <3 x float>, ptr [[NOR1]], align 4
; NON-POW2-NEXT: [[TMP2:%.*]] = shufflevector <3 x float> [[TMP1]], <3 x float> poison, <3 x i32> <i32 1, i32 2, i32 0>
; NON-POW2-NEXT: [[TMP3:%.*]] = fneg <3 x float> [[TMP2]]
-; NON-POW2-NEXT: [[TMP4:%.*]] = insertelement <3 x float> poison, float [[TMP0]], i32 0
+; NON-POW2-NEXT: [[TMP4:%.*]] = insertelement <3 x float> poison, float [[TMP0]], i64 0
; NON-POW2-NEXT: [[TMP5:%.*]] = shufflevector <3 x float> [[TMP4]], <3 x float> poison, <3 x i32> zeroinitializer
; NON-POW2-NEXT: [[TMP6:%.*]] = fmul <3 x float> [[TMP3]], [[TMP5]]
; NON-POW2-NEXT: [[TMP7:%.*]] = call <3 x float> @llvm.fmuladd.v3f32(<3 x float> [[TMP1]], <3 x float> zeroinitializer, <3 x float> [[TMP6]])
@@ -211,12 +211,12 @@ define i32 @reorder_indices_1(float %0) {
; POW2-ONLY-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX2_I265]], align 4
; POW2-ONLY-NEXT: [[TMP7:%.*]] = load <2 x float>, ptr [[ARRAYIDX_I]], align 4
; POW2-ONLY-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[NOR1]], align 4
-; POW2-ONLY-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
+; POW2-ONLY-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
; POW2-ONLY-NEXT: [[TMP4:%.*]] = fneg float [[TMP3]]
; POW2-ONLY-NEXT: [[NEG11_I:%.*]] = fmul float [[TMP4]], [[TMP0]]
; POW2-ONLY-NEXT: [[TMP5:%.*]] = call float @llvm.fmuladd.f32(float [[TMP1]], float 0.000000e+00, float [[NEG11_I]])
; POW2-ONLY-NEXT: [[TMP8:%.*]] = fneg <2 x float> [[TMP7]]
-; POW2-ONLY-NEXT: [[TMP9:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 0
+; POW2-ONLY-NEXT: [[TMP9:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i64 0
; POW2-ONLY-NEXT: [[TMP10:%.*]] = shufflevector <2 x float> [[TMP9]], <2 x float> poison, <2 x i32> zeroinitializer
; POW2-ONLY-NEXT: [[TMP11:%.*]] = fmul <2 x float> [[TMP8]], [[TMP10]]
; POW2-ONLY-NEXT: [[TMP12:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[TMP2]], <2 x float> zeroinitializer, <2 x float> [[TMP11]])
@@ -334,8 +334,8 @@ define void @reuse_shuffle_indidces_1(ptr %col, float %0, float %1) {
; NON-POW2-LABEL: define void @reuse_shuffle_indidces_1(
; NON-POW2-SAME: ptr [[COL:%.*]], float [[TMP0:%.*]], float [[TMP1:%.*]]) {
; NON-POW2-NEXT: entry:
-; NON-POW2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP1]], i32 0
-; NON-POW2-NEXT: [[TMP3:%.*]] = insertelement <3 x float> [[TMP2]], float [[TMP0]], i32 1
+; NON-POW2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP1]], i64 0
+; NON-POW2-NEXT: [[TMP3:%.*]] = insertelement <3 x float> [[TMP2]], float [[TMP0]], i64 1
; NON-POW2-NEXT: [[TMP4:%.*]] = shufflevector <3 x float> [[TMP3]], <3 x float> poison, <3 x i32> <i32 0, i32 1, i32 1>
; NON-POW2-NEXT: [[TMP5:%.*]] = fmul <3 x float> [[TMP4]], zeroinitializer
; NON-POW2-NEXT: [[TMP6:%.*]] = fadd <3 x float> [[TMP5]], zeroinitializer
@@ -345,8 +345,8 @@ define void @reuse_shuffle_indidces_1(ptr %col, float %0, float %1) {
; POW2-ONLY-LABEL: define void @reuse_shuffle_indidces_1(
; POW2-ONLY-SAME: ptr [[COL:%.*]], float [[TMP0:%.*]], float [[TMP1:%.*]]) {
; POW2-ONLY-NEXT: entry:
-; POW2-ONLY-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i32 0
-; POW2-ONLY-NEXT: [[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[TMP0]], i32 1
+; POW2-ONLY-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i64 0
+; POW2-ONLY-NEXT: [[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[TMP0]], i64 1
; POW2-ONLY-NEXT: [[TMP4:%.*]] = fmul <2 x float> [[TMP3]], zeroinitializer
; POW2-ONLY-NEXT: [[TMP5:%.*]] = fadd <2 x float> [[TMP4]], zeroinitializer
; POW2-ONLY-NEXT: store <2 x float> [[TMP5]], ptr [[COL]], align 4
@@ -406,9 +406,9 @@ define void @reuse_shuffle_indices_cost_crash_2(ptr %bezt, float %0) {
; NON-POW2-SAME: ptr [[BEZT:%.*]], float [[TMP0:%.*]]) {
; NON-POW2-NEXT: entry:
; NON-POW2-NEXT: [[FNEG:%.*]] = fmul float [[TMP0]], 0.000000e+00
-; NON-POW2-NEXT: [[TMP1:%.*]] = insertelement <3 x float> poison, float [[FNEG]], i32 0
+; NON-POW2-NEXT: [[TMP1:%.*]] = insertelement <3 x float> poison, float [[FNEG]], i64 0
; NON-POW2-NEXT: [[TMP2:%.*]] = shufflevector <3 x float> [[TMP1]], <3 x float> poison, <3 x i32> zeroinitializer
-; NON-POW2-NEXT: [[TMP3:%.*]] = insertelement <3 x float> <float poison, float poison, float 0.000000e+00>, float [[TMP0]], i32 0
+; NON-POW2-NEXT: [[TMP3:%.*]] = insertelement <3 x float> <float poison, float poison, float 0.000000e+00>, float [[TMP0]], i64 0
; NON-POW2-NEXT: [[TMP4:%.*]] = shufflevector <3 x float> [[TMP3]], <3 x float> poison, <3 x i32> <i32 0, i32 0, i32 2>
; NON-POW2-NEXT: [[TMP5:%.*]] = call <3 x float> @llvm.fmuladd.v3f32(<3 x float> [[TMP2]], <3 x float> [[TMP4]], <3 x float> zeroinitializer)
; NON-POW2-NEXT: store <3 x float> [[TMP5]], ptr [[BEZT]], align 4
@@ -445,8 +445,8 @@ define void @reuse_shuffle_indices_cost_crash_3(ptr %m, double %conv, double %co
; CHECK-LABEL: define void @reuse_shuffle_indices_cost_crash_3(
; CHECK-SAME: ptr [[M:%.*]], double [[CONV:%.*]], double [[CONV2:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[CONV]], i32 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double -0.000000e+00>, double [[CONV2]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[CONV]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double -0.000000e+00>, double [[CONV2]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = fptrunc <2 x double> [[TMP2]] to <2 x float>
; CHECK-NEXT: store <2 x float> [[TMP3]], ptr [[M]], align 4
@@ -479,7 +479,7 @@ define void @reuse_shuffle_indices_cost_crash_4(double %conv7.i) {
; CHECK-NEXT: [[ARRAYIDX_2_I:%.*]] = getelementptr [3 x float], ptr [[DATA_I111]], i64 0, i64 2
; CHECK-NEXT: [[MUL17_I_US:%.*]] = fmul double [[CONV7_I]], 0.000000e+00
; CHECK-NEXT: [[MUL_2_I_I_US:%.*]] = fmul double [[MUL17_I_US]], 0.000000e+00
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV7_I]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV7_I]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[ADD_2_I_I_US:%.*]] = fadd double [[MUL_2_I_I_US]], 0.000000e+00
@@ -523,8 +523,8 @@ define void @common_mask(ptr %m, double %conv, double %conv2) {
; CHECK-NEXT: [[CONV20:%.*]] = fptrunc double [[SUB19]] to float
; CHECK-NEXT: store float [[CONV20]], ptr [[M]], align 4
; CHECK-NEXT: [[ARRAYIDX25:%.*]] = getelementptr [4 x float], ptr [[M]], i64 0, i64 1
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[CONV2]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double -0.000000e+00, double poison>, double [[CONV]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[CONV2]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double -0.000000e+00, double poison>, double [[CONV]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = fptrunc <2 x double> [[TMP2]] to <2 x float>
; CHECK-NEXT: store <2 x float> [[TMP3]], ptr [[ARRAYIDX25]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
index 58a7beb594513..6db8b04edd36d 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/vectorizable-selects-uniform-cmps.ll
@@ -108,7 +108,7 @@ define void @select_uniform_ugt_7xi8(ptr %ptr, i8 %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i8> [[TMP0]], splat (i8 -1)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i8> [[TMP2]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP1]], <4 x i8> [[TMP0]], <4 x i8> [[TMP3]]
; CHECK-NEXT: store <4 x i8> [[TMP4]], ptr [[PTR]], align 2
@@ -182,7 +182,7 @@ define void @select_uniform_ugt_8xi8(ptr %ptr, i8 %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <8 x i8> [[TMP0]], splat (i8 -1)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i8> poison, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i8> [[TMP2]], <8 x i8> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP1]], <8 x i8> [[TMP0]], <8 x i8> [[TMP3]]
; CHECK-NEXT: store <8 x i8> [[TMP4]], ptr [[PTR]], align 2
@@ -252,7 +252,7 @@ define void @select_uniform_ugt_16xi8(ptr %ptr, i8 %x) {
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <7 x i8> [[TMP3]], <7 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP2]], <15 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt <15 x i8> [[TMP7]], splat (i8 -1)
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <15 x i8> poison, i8 [[X]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <15 x i8> poison, i8 [[X]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <15 x i8> [[TMP5]], <15 x i8> poison, <15 x i32> zeroinitializer
; CHECK-NEXT: [[TMP11:%.*]] = select <15 x i1> [[TMP4]], <15 x i8> [[TMP7]], <15 x i8> [[TMP6]]
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <15 x i8> [[TMP11]], <15 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
@@ -364,7 +364,7 @@ define void @select_uniform_ugt_4xi16(ptr %ptr, i16 %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[PTR:%.*]], align 2
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i16> [[TMP0]], splat (i16 16383)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> poison, i16 [[X:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> poison, i16 [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP1]], <4 x i16> [[TMP0]], <4 x i16> [[TMP3]]
; CHECK-NEXT: store <4 x i16> [[TMP4]], ptr [[PTR]], align 2
@@ -402,7 +402,7 @@ define void @select_uniform_ult_8xi16(ptr %ptr, i16 %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[PTR:%.*]], align 2
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <8 x i16> [[TMP0]], splat (i16 16383)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> poison, i16 [[X:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> poison, i16 [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> [[TMP0]], <8 x i16> [[TMP3]]
; CHECK-NEXT: store <8 x i16> [[TMP4]], ptr [[PTR]], align 2
@@ -463,7 +463,7 @@ define void @select_uniform_eq_2xi32(ptr %ptr, i32 %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[TMP0]], splat (i32 16383)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[TMP0]], <2 x i32> [[TMP3]]
; CHECK-NEXT: store <2 x i32> [[TMP4]], ptr [[PTR]], align 2
@@ -489,7 +489,7 @@ define void @select_uniform_eq_4xi32(ptr %ptr, i32 %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[TMP0]], splat (i32 16383)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP0]], <4 x i32> [[TMP3]]
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[PTR]], align 2
@@ -526,7 +526,7 @@ define void @select_uniform_ne_2xi64(ptr %ptr, i64 %x) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[PTR:%.*]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i64> [[TMP0]], splat (i64 16383)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[X:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = select <2 x i1> [[TMP1]], <2 x i64> [[TMP0]], <2 x i64> [[TMP3]]
; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr [[PTR]], align 2
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
index 3ddc0d66f370b..4bd7f30d8f2a5 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/horizontal-store.ll
@@ -16,8 +16,8 @@
define i32 @smaxv6() {
; GFX9-LABEL: @smaxv6(
; GFX9-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @arr, align 16
-; GFX9-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; GFX9-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
+; GFX9-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; GFX9-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
; GFX9-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP2]], [[TMP3]]
; GFX9-NEXT: [[LOAD5:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 16), align 16
; GFX9-NEXT: [[LOAD6:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @arr, i64 20), align 4
@@ -48,8 +48,8 @@ define i32 @smaxv6() {
define i64 @sminv6() {
; GFX9-LABEL: @sminv6(
; GFX9-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @arr64, align 16
-; GFX9-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[TMP1]], i32 0
-; GFX9-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP1]], i32 1
+; GFX9-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[TMP1]], i64 0
+; GFX9-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP1]], i64 1
; GFX9-NEXT: [[CMP1:%.*]] = icmp slt i64 [[TMP2]], [[TMP3]]
; GFX9-NEXT: [[LOAD5:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @arr64, i64 32), align 16
; GFX9-NEXT: [[LOAD6:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @arr64, i64 40), align 8
@@ -82,8 +82,8 @@ define i64 @sminv6() {
define float @fmaxv6() {
; GFX9-LABEL: @fmaxv6(
; GFX9-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr @farr, align 16
-; GFX9-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[TMP1]], i32 0
-; GFX9-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP1]], i32 1
+; GFX9-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[TMP1]], i64 0
+; GFX9-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP1]], i64 1
; GFX9-NEXT: [[CMP1:%.*]] = fcmp fast ogt float [[TMP2]], [[TMP3]]
; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], float [[TMP2]], float [[TMP3]]
; GFX9-NEXT: [[LOAD3:%.*]] = load float, ptr getelementptr inbounds ([32 x float], ptr @farr, i64 0, i64 2), align 8
@@ -133,8 +133,8 @@ define float @fmaxv6() {
define double @dminv6() {
; GFX9-LABEL: @dminv6(
; GFX9-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @darr, align 16
-; GFX9-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
-; GFX9-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; GFX9-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i64 0
+; GFX9-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i64 1
; GFX9-NEXT: [[CMP1:%.*]] = fcmp fast olt double [[TMP2]], [[TMP3]]
; GFX9-NEXT: [[SELECT1:%.*]] = select i1 [[CMP1]], double [[TMP2]], double [[TMP3]]
; GFX9-NEXT: [[LOAD3:%.*]] = load double, ptr getelementptr inbounds ([32 x double], ptr @darr, i64 0, i64 2), align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
index ff77b7392a997..35cf9655929b3 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/inst-count-heuristic.ll
@@ -12,14 +12,14 @@ define amdgpu_kernel void @phi5_rotate(
; GFX950-LABEL: define amdgpu_kernel void @phi5_rotate(
; GFX950-SAME: ptr addrspace(1) captures(none) [[OUT:%.*]], i32 [[N:%.*]], i32 [[S0:%.*]], i32 [[S1:%.*]], i32 [[S2:%.*]], i32 [[S3:%.*]], i32 [[S4:%.*]]) #[[ATTR0:[0-9]+]] {
; GFX950-NEXT: [[ENTRY:.*]]:
-; GFX950-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[S0]], i32 0
-; GFX950-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[S1]], i32 1
-; GFX950-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[S4]], i32 0
-; GFX950-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[S0]], i32 1
-; GFX950-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[S3]], i32 0
-; GFX950-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[S4]], i32 1
-; GFX950-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[S2]], i32 0
-; GFX950-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[S3]], i32 1
+; GFX950-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[S0]], i64 0
+; GFX950-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[S1]], i64 1
+; GFX950-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[S4]], i64 0
+; GFX950-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[S0]], i64 1
+; GFX950-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[S3]], i64 0
+; GFX950-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[S4]], i64 1
+; GFX950-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[S2]], i64 0
+; GFX950-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[S3]], i64 1
; GFX950-NEXT: br label %[[LOOP:.*]]
; GFX950: [[LOOP]]:
; GFX950-NEXT: [[I1:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[LOOP]] ]
@@ -39,14 +39,14 @@ define amdgpu_kernel void @phi5_rotate(
; GFX942-LABEL: define amdgpu_kernel void @phi5_rotate(
; GFX942-SAME: ptr addrspace(1) captures(none) [[OUT:%.*]], i32 [[N:%.*]], i32 [[S0:%.*]], i32 [[S1:%.*]], i32 [[S2:%.*]], i32 [[S3:%.*]], i32 [[S4:%.*]]) #[[ATTR0:[0-9]+]] {
; GFX942-NEXT: [[ENTRY:.*]]:
-; GFX942-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[S0]], i32 0
-; GFX942-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[S1]], i32 1
-; GFX942-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[S4]], i32 0
-; GFX942-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[S0]], i32 1
-; GFX942-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[S3]], i32 0
-; GFX942-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[S4]], i32 1
-; GFX942-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[S2]], i32 0
-; GFX942-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[S3]], i32 1
+; GFX942-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[S0]], i64 0
+; GFX942-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[S1]], i64 1
+; GFX942-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[S4]], i64 0
+; GFX942-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[S0]], i64 1
+; GFX942-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[S3]], i64 0
+; GFX942-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[S4]], i64 1
+; GFX942-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[S2]], i64 0
+; GFX942-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[S3]], i64 1
; GFX942-NEXT: br label %[[LOOP:.*]]
; GFX942: [[LOOP]]:
; GFX942-NEXT: [[I1:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[LOOP]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
index 1f3d51006b4d4..48e14dbf70a99 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/notriviallyvectorizableintrinsicoperands.ll
@@ -67,10 +67,10 @@ define amdgpu_kernel void @test_amdgcn_exp_log(ptr addrspace(1) %input, ptr addr
; GCN-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr addrspace(1) [[SCALES]], align 4
; GCN-NEXT: [[TMP2:%.*]] = fmul contract <2 x float> [[TMP0]], splat (float f0x3E0293EE)
; GCN-NEXT: [[TMP3:%.*]] = fsub contract <2 x float> [[TMP2]], [[TMP1]]
-; GCN-NEXT: [[SUB0:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
+; GCN-NEXT: [[SUB0:%.*]] = extractelement <2 x float> [[TMP3]], i64 0
; GCN-NEXT: [[EXP0:%.*]] = tail call float @llvm.amdgcn.exp2.f32(float [[SUB0]])
; GCN-NEXT: [[LOG0:%.*]] = tail call float @llvm.amdgcn.log.f32(float [[EXP0]])
-; GCN-NEXT: [[SUB1:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; GCN-NEXT: [[SUB1:%.*]] = extractelement <2 x float> [[TMP3]], i64 1
; GCN-NEXT: [[EXP1:%.*]] = tail call float @llvm.amdgcn.exp2.f32(float [[SUB1]])
; GCN-NEXT: [[LOG1:%.*]] = tail call float @llvm.amdgcn.log.f32(float [[EXP1]])
; GCN-NEXT: [[SUM:%.*]] = fadd fast float [[LOG0]], [[LOG1]]
@@ -105,9 +105,9 @@ define amdgpu_kernel void @test_amdgcn_exp_f16(ptr addrspace(1) %input, ptr addr
; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(1) [[SCALES]], align 2
; GCN-NEXT: [[TMP2:%.*]] = fmul contract <2 x half> [[TMP0]], splat (half 1.519530e+00)
; GCN-NEXT: [[TMP3:%.*]] = fsub contract <2 x half> [[TMP2]], [[TMP1]]
-; GCN-NEXT: [[SUB0:%.*]] = extractelement <2 x half> [[TMP3]], i32 0
+; GCN-NEXT: [[SUB0:%.*]] = extractelement <2 x half> [[TMP3]], i64 0
; GCN-NEXT: [[EXP0:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[SUB0]])
-; GCN-NEXT: [[SUB1:%.*]] = extractelement <2 x half> [[TMP3]], i32 1
+; GCN-NEXT: [[SUB1:%.*]] = extractelement <2 x half> [[TMP3]], i64 1
; GCN-NEXT: [[EXP1:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[SUB1]])
; GCN-NEXT: [[SUM:%.*]] = fadd fast half [[EXP0]], [[EXP1]]
; GCN-NEXT: store half [[SUM]], ptr addrspace(1) [[OUTPUT]], align 2
@@ -139,9 +139,9 @@ define amdgpu_kernel void @kernel_f16(ptr addrspace(1) %input, ptr addrspace(1)
; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(1) [[SCALES]], align 2
; GCN-NEXT: [[TMP2:%.*]] = fmul contract <2 x half> [[TMP0]], splat (half 1.519530e+00)
; GCN-NEXT: [[TMP3:%.*]] = fsub contract <2 x half> [[TMP2]], [[TMP1]]
-; GCN-NEXT: [[SUB0:%.*]] = extractelement <2 x half> [[TMP3]], i32 0
+; GCN-NEXT: [[SUB0:%.*]] = extractelement <2 x half> [[TMP3]], i64 0
; GCN-NEXT: [[EXP0:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[SUB0]])
-; GCN-NEXT: [[SUB1:%.*]] = extractelement <2 x half> [[TMP3]], i32 1
+; GCN-NEXT: [[SUB1:%.*]] = extractelement <2 x half> [[TMP3]], i64 1
; GCN-NEXT: [[EXP1:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[SUB1]])
; GCN-NEXT: [[LOG0:%.*]] = tail call half @llvm.amdgcn.log.f16(half [[EXP0]])
; GCN-NEXT: [[LOG1:%.*]] = tail call half @llvm.amdgcn.log.f16(half [[EXP1]])
@@ -177,12 +177,12 @@ define amdgpu_kernel void @look_through_reuse_shuffle(
; GCN-NEXT: [[TMP5:%.*]] = load <2 x half>, ptr addrspace(1) [[SCALES]], align 2
; GCN-NEXT: [[TMP6:%.*]] = fadd contract <2 x half> [[TMP4]], splat (half 1.519530e+00)
; GCN-NEXT: [[TMP3:%.*]] = fmul contract <2 x half> [[TMP6]], [[TMP5]]
-; GCN-NEXT: [[MUL0:%.*]] = extractelement <2 x half> [[TMP3]], i32 0
+; GCN-NEXT: [[MUL0:%.*]] = extractelement <2 x half> [[TMP3]], i64 0
; GCN-NEXT: [[EXP0:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[MUL0]])
-; GCN-NEXT: [[MUL1:%.*]] = extractelement <2 x half> [[TMP3]], i32 1
+; GCN-NEXT: [[MUL1:%.*]] = extractelement <2 x half> [[TMP3]], i64 1
; GCN-NEXT: [[EXP1:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[MUL1]])
-; GCN-NEXT: [[TMP0:%.*]] = insertelement <4 x half> poison, half [[EXP0]], i32 0
-; GCN-NEXT: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half [[EXP1]], i32 1
+; GCN-NEXT: [[TMP7:%.*]] = insertelement <4 x half> poison, half [[EXP0]], i64 0
+; GCN-NEXT: [[TMP1:%.*]] = insertelement <4 x half> [[TMP7]], half [[EXP1]], i64 1
; GCN-NEXT: [[TMP2:%.*]] = shufflevector <4 x half> [[TMP1]], <4 x half> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; GCN-NEXT: store <4 x half> [[TMP2]], ptr addrspace(1) [[OUTPUT]], align 2
; GCN-NEXT: ret void
@@ -231,13 +231,13 @@ define amdgpu_kernel void @wider_exp2_f32(ptr addrspace(1) %input, ptr addrspace
; GCN-NEXT: [[TMP5:%.*]] = load <2 x float>, ptr addrspace(1) [[SPTR2]], align 4
; GCN-NEXT: [[TMP6:%.*]] = fmul contract <2 x float> [[TMP4]], splat (float f0x3E0293EE)
; GCN-NEXT: [[TMP7:%.*]] = fsub contract <2 x float> [[TMP6]], [[TMP5]]
-; GCN-NEXT: [[SUB0:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
+; GCN-NEXT: [[SUB0:%.*]] = extractelement <2 x float> [[TMP3]], i64 0
; GCN-NEXT: [[EXP0:%.*]] = tail call float @llvm.amdgcn.exp2.f32(float [[SUB0]])
-; GCN-NEXT: [[SUB1:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; GCN-NEXT: [[SUB1:%.*]] = extractelement <2 x float> [[TMP3]], i64 1
; GCN-NEXT: [[EXP1:%.*]] = tail call float @llvm.amdgcn.exp2.f32(float [[SUB1]])
-; GCN-NEXT: [[SUB2:%.*]] = extractelement <2 x float> [[TMP7]], i32 0
+; GCN-NEXT: [[SUB2:%.*]] = extractelement <2 x float> [[TMP7]], i64 0
; GCN-NEXT: [[EXP2:%.*]] = tail call float @llvm.amdgcn.exp2.f32(float [[SUB2]])
-; GCN-NEXT: [[SUB3:%.*]] = extractelement <2 x float> [[TMP7]], i32 1
+; GCN-NEXT: [[SUB3:%.*]] = extractelement <2 x float> [[TMP7]], i64 1
; GCN-NEXT: [[EXP3:%.*]] = tail call float @llvm.amdgcn.exp2.f32(float [[SUB3]])
; GCN-NEXT: [[SUM01:%.*]] = fadd fast float [[EXP0]], [[EXP1]]
; GCN-NEXT: [[SUM23:%.*]] = fadd fast float [[EXP2]], [[EXP3]]
@@ -299,13 +299,13 @@ define amdgpu_kernel void @wider_exp2_half(ptr addrspace(1) %input, ptr addrspac
; GCN-NEXT: [[TMP5:%.*]] = load <2 x half>, ptr addrspace(1) [[SPTR2]], align 2
; GCN-NEXT: [[TMP6:%.*]] = fmul contract <2 x half> [[TMP4]], splat (half 1.519530e+00)
; GCN-NEXT: [[TMP7:%.*]] = fsub contract <2 x half> [[TMP6]], [[TMP5]]
-; GCN-NEXT: [[SUB0:%.*]] = extractelement <2 x half> [[TMP3]], i32 0
+; GCN-NEXT: [[SUB0:%.*]] = extractelement <2 x half> [[TMP3]], i64 0
; GCN-NEXT: [[EXP0:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[SUB0]])
-; GCN-NEXT: [[SUB1:%.*]] = extractelement <2 x half> [[TMP3]], i32 1
+; GCN-NEXT: [[SUB1:%.*]] = extractelement <2 x half> [[TMP3]], i64 1
; GCN-NEXT: [[EXP1:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[SUB1]])
-; GCN-NEXT: [[SUB2:%.*]] = extractelement <2 x half> [[TMP7]], i32 0
+; GCN-NEXT: [[SUB2:%.*]] = extractelement <2 x half> [[TMP7]], i64 0
; GCN-NEXT: [[EXP2:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[SUB2]])
-; GCN-NEXT: [[SUB3:%.*]] = extractelement <2 x half> [[TMP7]], i32 1
+; GCN-NEXT: [[SUB3:%.*]] = extractelement <2 x half> [[TMP7]], i64 1
; GCN-NEXT: [[EXP3:%.*]] = tail call half @llvm.amdgcn.exp2.f16(half [[SUB3]])
; GCN-NEXT: [[SUM01:%.*]] = fadd fast half [[EXP0]], [[EXP1]]
; GCN-NEXT: [[SUM23:%.*]] = fadd fast half [[EXP2]], [[EXP3]]
@@ -369,11 +369,11 @@ define amdgpu_kernel void @kernel_div_scale(ptr addrspace(1) %num, ptr addrspace
; GCN-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr addrspace(1) [[DEN]], align 4
; GCN-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP2]], splat (float 4.000000e+00)
; GCN-NEXT: [[MUL_D2:%.*]] = fmul float [[D2]], 4.000000e+00
-; GCN-NEXT: [[MUL_N0:%.*]] = extractelement <2 x float> [[TMP1]], i32 0
-; GCN-NEXT: [[MUL_D0:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
+; GCN-NEXT: [[MUL_N0:%.*]] = extractelement <2 x float> [[TMP1]], i64 0
+; GCN-NEXT: [[MUL_D0:%.*]] = extractelement <2 x float> [[TMP3]], i64 0
; GCN-NEXT: [[DS0:%.*]] = call { float, i1 } @llvm.amdgcn.div.scale.f32(float [[MUL_N0]], float [[MUL_D0]], i1 false)
-; GCN-NEXT: [[MUL_N1:%.*]] = extractelement <2 x float> [[TMP1]], i32 1
-; GCN-NEXT: [[MUL_D1:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; GCN-NEXT: [[MUL_N1:%.*]] = extractelement <2 x float> [[TMP1]], i64 1
+; GCN-NEXT: [[MUL_D1:%.*]] = extractelement <2 x float> [[TMP3]], i64 1
; GCN-NEXT: [[DS1:%.*]] = call { float, i1 } @llvm.amdgcn.div.scale.f32(float [[MUL_N1]], float [[MUL_D1]], i1 false)
; GCN-NEXT: [[DS2:%.*]] = call { float, i1 } @llvm.amdgcn.div.scale.f32(float [[MUL_N2]], float [[MUL_D2]], i1 false)
; GCN-NEXT: [[R0:%.*]] = extractvalue { float, i1 } [[DS0]], 0
@@ -425,9 +425,9 @@ define amdgpu_kernel void @kernel_fmed3(ptr addrspace(1) %a, ptr addrspace(1) %b
; GCN-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr addrspace(1) [[B]], align 4
; GCN-NEXT: [[TMP2:%.*]] = fadd <2 x float> [[TMP0]], [[TMP1]]
; GCN-NEXT: [[ADD2:%.*]] = fadd float [[A2]], [[B2]]
-; GCN-NEXT: [[ADD0:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
+; GCN-NEXT: [[ADD0:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
; GCN-NEXT: [[MED0:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ADD0]], float [[ADD0]], float 1.000000e+00)
-; GCN-NEXT: [[ADD1:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; GCN-NEXT: [[ADD1:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; GCN-NEXT: [[MED1:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ADD1]], float [[ADD1]], float 1.000000e+00)
; GCN-NEXT: [[MED2:%.*]] = call float @llvm.amdgcn.fmed3.f32(float [[ADD2]], float [[ADD2]], float 1.000000e+00)
; GCN-NEXT: [[SUM01:%.*]] = fadd float [[MED0]], [[MED1]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll
index 388e317278ee5..49d7ee569c871 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/packed-math.ll
@@ -100,7 +100,7 @@ define amdgpu_kernel void @test1_fma_v2f16(ptr addrspace(3) %a, ptr addrspace(3)
define amdgpu_kernel void @mul_scalar_v2f16(ptr addrspace(3) %a, half %scalar, ptr addrspace(3) %c) {
; GCN-LABEL: @mul_scalar_v2f16(
; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(3) [[A:%.*]], align 2
-; GCN-NEXT: [[TMP2:%.*]] = insertelement <2 x half> poison, half [[SCALAR:%.*]], i32 0
+; GCN-NEXT: [[TMP2:%.*]] = insertelement <2 x half> poison, half [[SCALAR:%.*]], i64 0
; GCN-NEXT: [[TMP3:%.*]] = shufflevector <2 x half> [[TMP2]], <2 x half> poison, <2 x i32> zeroinitializer
; GCN-NEXT: [[TMP4:%.*]] = fmul <2 x half> [[TMP1]], [[TMP3]]
; GCN-NEXT: store <2 x half> [[TMP4]], ptr addrspace(3) [[C:%.*]], align 2
@@ -174,8 +174,8 @@ define amdgpu_kernel void @test1_fabs_scalar_fma_v2f16(ptr addrspace(3) %a, ptr
; GCN-NEXT: [[I4:%.*]] = load half, ptr addrspace(3) [[ARRAYIDX4]], align 2
; GCN-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(3) [[A:%.*]], align 2
; GCN-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr addrspace(3) [[C:%.*]], align 2
-; GCN-NEXT: [[TMP3:%.*]] = insertelement <2 x half> poison, half [[I1_FABS]], i32 0
-; GCN-NEXT: [[TMP4:%.*]] = insertelement <2 x half> [[TMP3]], half [[I4]], i32 1
+; GCN-NEXT: [[TMP3:%.*]] = insertelement <2 x half> poison, half [[I1_FABS]], i64 0
+; GCN-NEXT: [[TMP4:%.*]] = insertelement <2 x half> [[TMP3]], half [[I4]], i64 1
; GCN-NEXT: [[TMP5:%.*]] = call <2 x half> @llvm.fma.v2f16(<2 x half> [[TMP1]], <2 x half> [[TMP4]], <2 x half> [[TMP2]])
; GCN-NEXT: store <2 x half> [[TMP5]], ptr addrspace(3) [[D:%.*]], align 2
; GCN-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
index e6384bec97398..7a93e90696f6b 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/slp-v2f16.ll
@@ -441,7 +441,7 @@ define void @copysign_combine_v2f16(ptr addrspace(1) %arg, half %sign) {
; GCN-NEXT: [[ITMP1:%.*]] = zext i32 [[TMP]] to i64
; GCN-NEXT: [[ITMP2:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP1]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = insertelement <2 x half> poison, half [[SIGN]], i32 0
+; GCN-NEXT: [[TMP1:%.*]] = insertelement <2 x half> poison, half [[SIGN]], i64 0
; GCN-NEXT: [[TMP2:%.*]] = shufflevector <2 x half> [[TMP1]], <2 x half> poison, <2 x i32> zeroinitializer
; GCN-NEXT: [[TMP3:%.*]] = call <2 x half> @llvm.copysign.v2f16(<2 x half> [[TMP0]], <2 x half> [[TMP2]])
; GCN-NEXT: store <2 x half> [[TMP3]], ptr addrspace(1) [[ITMP2]], align 2
@@ -474,7 +474,7 @@ define void @copysign_combine_v4f16(ptr addrspace(1) %arg, half %sign) {
; GCN-NEXT: [[ITMP5:%.*]] = add nuw nsw i64 [[ITMP1]], 1
; GCN-NEXT: [[ITMP6:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP5]]
; GCN-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr addrspace(1) [[ITMP2]], align 2
-; GCN-NEXT: [[TMP1:%.*]] = insertelement <2 x half> poison, half [[SIGN]], i32 0
+; GCN-NEXT: [[TMP1:%.*]] = insertelement <2 x half> poison, half [[SIGN]], i64 0
; GCN-NEXT: [[TMP2:%.*]] = shufflevector <2 x half> [[TMP1]], <2 x half> poison, <2 x i32> zeroinitializer
; GCN-NEXT: [[TMP3:%.*]] = call <2 x half> @llvm.copysign.v2f16(<2 x half> [[TMP0]], <2 x half> [[TMP2]])
; GCN-NEXT: store <2 x half> [[TMP3]], ptr addrspace(1) [[ITMP2]], align 2
@@ -561,8 +561,8 @@ define void @canonicalize_combine_v4f16(ptr addrspace(1) %arg) {
; GFX9-NEXT: [[ITMP13:%.*]] = add nuw nsw i64 [[ITMP1]], 3
; GFX9-NEXT: [[ITMP14:%.*]] = getelementptr inbounds half, ptr addrspace(1) [[ARG]], i64 [[ITMP13]]
; GFX9-NEXT: [[ITMP15:%.*]] = load half, ptr addrspace(1) [[ITMP14]], align 2
-; GFX9-NEXT: [[TMP2:%.*]] = insertelement <2 x half> poison, half [[ITMP11]], i32 0
-; GFX9-NEXT: [[TMP3:%.*]] = insertelement <2 x half> [[TMP2]], half [[ITMP15]], i32 1
+; GFX9-NEXT: [[TMP2:%.*]] = insertelement <2 x half> poison, half [[ITMP11]], i64 0
+; GFX9-NEXT: [[TMP3:%.*]] = insertelement <2 x half> [[TMP2]], half [[ITMP15]], i64 1
; GFX9-NEXT: [[TMP4:%.*]] = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> [[TMP3]])
; GFX9-NEXT: store <2 x half> [[TMP4]], ptr addrspace(1) [[ITMP10]], align 2
; GFX9-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-loads.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-loads.ll
index 8ca98c50f31a9..b2729cba17a01 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-loads.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/basic-strided-loads.ll
@@ -909,10 +909,10 @@ define void @rt_stride_mul_scev(ptr %pl, i64 %base_stride, ptr %ps) {
; CHECK-SAME: ptr [[PL:%.*]], i64 [[BASE_STRIDE:%.*]], ptr [[PS:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[STRIDE:%.*]] = mul i64 [[BASE_STRIDE]], 2
; CHECK-NEXT: [[GEP_S0:%.*]] = getelementptr inbounds i8, ptr [[PS]], i64 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i64> poison, i64 [[STRIDE]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i64> poison, i64 [[STRIDE]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> [[TMP1]], <8 x i64> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = mul nsw <8 x i64> [[TMP2]], <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x ptr> poison, ptr [[PL]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x ptr> poison, ptr [[PL]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x ptr> [[TMP4]], <8 x ptr> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, <8 x ptr> [[TMP5]], <8 x i64> [[TMP3]]
; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> align 1 [[TMP6]], <8 x i1> splat (i1 true), <8 x i8> poison)
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll
index 97ac1f612caf5..6fce8a7524adf 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll
@@ -6,14 +6,14 @@ define void @test(ptr %__last.addr.011.i.i, ptr %call3) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[__LAST_ADDR_011_I_I:%.*]], ptr [[CALL3:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[NEWFUNCROOT:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr> poison, ptr [[__LAST_ADDR_011_I_I]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP0]], ptr [[CALL3]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr> poison, ptr [[__LAST_ADDR_011_I_I]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP0]], ptr [[CALL3]], i64 1
; CHECK-NEXT: br label %[[WHILE_BODY_I_I:.*]]
; CHECK: [[WHILE_BODY_I_I]]:
; CHECK-NEXT: [[TMP2:%.*]] = phi <2 x ptr> [ [[TMP1]], %[[NEWFUNCROOT]] ], [ [[TMP76:%.*]], %[[WHILE_BODY_I_I]] ]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x ptr> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x ptr> [[TMP2]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[TMP3]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x ptr> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x ptr> [[TMP2]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[TMP4]], align 4
; CHECK-NEXT: store float [[TMP6]], ptr [[TMP3]], align 4
; CHECK-NEXT: store float [[TMP5]], ptr [[TMP4]], align 4
@@ -204,8 +204,8 @@ define void @test(ptr %__last.addr.011.i.i, ptr %call3) {
; CHECK-NEXT: store float [[TMP101]], ptr [[__LAST_ADDR_0_I_I_20]], align 4
; CHECK-NEXT: store float [[TMP102]], ptr [[INCDEC_PTR2_I_I_20]], align 4
; CHECK-NEXT: [[__LAST_ADDR_0_I_I_31:%.*]] = getelementptr inbounds i8, ptr [[INCDEC_PTR2_I_I_20]], i32 -4
-; CHECK-NEXT: [[TMP52:%.*]] = insertelement <2 x ptr> poison, ptr [[__LAST_ADDR_0_I_I_20]], i32 0
-; CHECK-NEXT: [[TMP53:%.*]] = insertelement <2 x ptr> [[TMP52]], ptr [[INCDEC_PTR2_I_I_20]], i32 1
+; CHECK-NEXT: [[TMP93:%.*]] = insertelement <2 x ptr> poison, ptr [[__LAST_ADDR_0_I_I_20]], i64 0
+; CHECK-NEXT: [[TMP53:%.*]] = insertelement <2 x ptr> [[TMP93]], ptr [[INCDEC_PTR2_I_I_20]], i64 1
; CHECK-NEXT: [[TMP92:%.*]] = getelementptr inbounds i8, <2 x ptr> [[TMP53]], <2 x i32> <i32 4, i32 -4>
; CHECK-NEXT: [[INCDEC_PTR2_I_I_31:%.*]] = getelementptr inbounds nuw i8, ptr [[__LAST_ADDR_0_I_I_20]], i32 4
; CHECK-NEXT: [[CMP1_I_I_31:%.*]] = icmp ult ptr [[INCDEC_PTR2_I_I_31]], [[__LAST_ADDR_0_I_I_31]]
@@ -217,14 +217,14 @@ define void @test(ptr %__last.addr.011.i.i, ptr %call3) {
; EXP-LABEL: define void @test(
; EXP-SAME: ptr [[__LAST_ADDR_011_I_I:%.*]], ptr [[CALL3:%.*]]) #[[ATTR0:[0-9]+]] {
; EXP-NEXT: [[NEWFUNCROOT:.*]]:
-; EXP-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr> poison, ptr [[__LAST_ADDR_011_I_I]], i32 0
-; EXP-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP0]], ptr [[CALL3]], i32 1
+; EXP-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr> poison, ptr [[__LAST_ADDR_011_I_I]], i64 0
+; EXP-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP0]], ptr [[CALL3]], i64 1
; EXP-NEXT: br label %[[WHILE_BODY_I_I:.*]]
; EXP: [[WHILE_BODY_I_I]]:
; EXP-NEXT: [[TMP2:%.*]] = phi <2 x ptr> [ [[TMP1]], %[[NEWFUNCROOT]] ], [ [[TMP94:%.*]], %[[WHILE_BODY_I_I]] ]
-; EXP-NEXT: [[TMP3:%.*]] = extractelement <2 x ptr> [[TMP2]], i32 1
+; EXP-NEXT: [[TMP3:%.*]] = extractelement <2 x ptr> [[TMP2]], i64 1
; EXP-NEXT: [[TMP4:%.*]] = load float, ptr [[TMP3]], align 4
-; EXP-NEXT: [[TMP5:%.*]] = extractelement <2 x ptr> [[TMP2]], i32 0
+; EXP-NEXT: [[TMP5:%.*]] = extractelement <2 x ptr> [[TMP2]], i64 0
; EXP-NEXT: [[TMP6:%.*]] = load float, ptr [[TMP5]], align 4
; EXP-NEXT: store float [[TMP6]], ptr [[TMP3]], align 4
; EXP-NEXT: store float [[TMP4]], ptr [[TMP5]], align 4
@@ -349,16 +349,16 @@ define void @test(ptr %__last.addr.011.i.i, ptr %call3) {
; EXP-NEXT: store float [[TMP46]], ptr [[INCDEC_PTR2_I_I_19]], align 4
; EXP-NEXT: store float [[TMP45]], ptr [[__LAST_ADDR_0_I_I_19]], align 4
; EXP-NEXT: [[__LAST_ADDR_0_I_I_20:%.*]] = getelementptr inbounds i8, ptr [[__LAST_ADDR_0_I_I_19]], i32 -4
-; EXP-NEXT: [[TMP47:%.*]] = insertelement <2 x ptr> poison, ptr [[INCDEC_PTR2_I_I_19]], i32 0
-; EXP-NEXT: [[TMP48:%.*]] = insertelement <2 x ptr> [[TMP47]], ptr [[__LAST_ADDR_0_I_I_19]], i32 1
+; EXP-NEXT: [[TMP47:%.*]] = insertelement <2 x ptr> poison, ptr [[INCDEC_PTR2_I_I_19]], i64 0
+; EXP-NEXT: [[TMP48:%.*]] = insertelement <2 x ptr> [[TMP47]], ptr [[__LAST_ADDR_0_I_I_19]], i64 1
; EXP-NEXT: [[TMP49:%.*]] = getelementptr inbounds i8, <2 x ptr> [[TMP48]], <2 x i32> <i32 4, i32 -4>
; EXP-NEXT: [[INCDEC_PTR2_I_I_20:%.*]] = getelementptr inbounds nuw i8, ptr [[INCDEC_PTR2_I_I_19]], i32 4
; EXP-NEXT: [[TMP50:%.*]] = load float, ptr [[INCDEC_PTR2_I_I_20]], align 4
; EXP-NEXT: [[TMP51:%.*]] = load float, ptr [[__LAST_ADDR_0_I_I_20]], align 4
; EXP-NEXT: store float [[TMP51]], ptr [[INCDEC_PTR2_I_I_20]], align 4
; EXP-NEXT: store float [[TMP50]], ptr [[__LAST_ADDR_0_I_I_20]], align 4
-; EXP-NEXT: [[TMP52:%.*]] = insertelement <2 x ptr> poison, ptr [[__LAST_ADDR_0_I_I_20]], i32 0
-; EXP-NEXT: [[TMP53:%.*]] = insertelement <2 x ptr> [[TMP52]], ptr [[INCDEC_PTR2_I_I_20]], i32 1
+; EXP-NEXT: [[TMP52:%.*]] = insertelement <2 x ptr> poison, ptr [[__LAST_ADDR_0_I_I_20]], i64 0
+; EXP-NEXT: [[TMP53:%.*]] = insertelement <2 x ptr> [[TMP52]], ptr [[INCDEC_PTR2_I_I_20]], i64 1
; EXP-NEXT: [[TMP54:%.*]] = getelementptr inbounds i8, <2 x ptr> [[TMP53]], <2 x i32> <i32 -4, i32 4>
; EXP-NEXT: [[__LAST_ADDR_0_I_I_21:%.*]] = getelementptr inbounds i8, ptr [[__LAST_ADDR_0_I_I_20]], i32 -4
; EXP-NEXT: [[TMP55:%.*]] = getelementptr inbounds i8, <2 x ptr> [[TMP49]], <2 x i32> <i32 4, i32 -4>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
index 09be099fcf709..a431560023ba1 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
@@ -87,8 +87,8 @@ define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.pt
; CHECK-NEXT: [[TMP67:%.*]] = sub <4 x i32> [[TMP64]], [[TMP66]]
; CHECK-NEXT: [[TMP68:%.*]] = shufflevector <4 x i32> [[TMP67]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP71:%.*]] = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i64(ptr align 1 null, i64 4, <2 x i1> splat (i1 true), i32 2)
-; CHECK-NEXT: [[TMP69:%.*]] = insertelement <2 x i8> poison, i8 [[TMP115]], i32 0
-; CHECK-NEXT: [[TMP70:%.*]] = insertelement <2 x i8> [[TMP69]], i8 [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP69:%.*]] = insertelement <2 x i8> poison, i8 [[TMP115]], i64 0
+; CHECK-NEXT: [[TMP70:%.*]] = insertelement <2 x i8> [[TMP69]], i8 [[TMP0]], i64 1
; CHECK-NEXT: [[TMP73:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_3]], align 1
; CHECK-NEXT: [[TMP74:%.*]] = zext <4 x i8> [[TMP73]] to <4 x i32>
; CHECK-NEXT: [[TMP75:%.*]] = shufflevector <4 x i32> [[TMP74]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
@@ -322,15 +322,15 @@ define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.pt
; UNALIGNED_VEC_MEM-NEXT: [[TMP42:%.*]] = load i8, ptr [[ARRAYIDX5_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV38_3:%.*]] = zext i8 [[TMP61]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[CONV40_2:%.*]] = zext i8 [[TMP42]] to i32
-; UNALIGNED_VEC_MEM-NEXT: [[TMP33:%.*]] = insertelement <2 x i8> poison, i8 [[TMP106]], i32 0
-; UNALIGNED_VEC_MEM-NEXT: [[TMP34:%.*]] = insertelement <2 x i8> [[TMP33]], i8 [[TMP57]], i32 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP33:%.*]] = insertelement <2 x i8> poison, i8 [[TMP106]], i64 0
+; UNALIGNED_VEC_MEM-NEXT: [[TMP34:%.*]] = insertelement <2 x i8> [[TMP33]], i8 [[TMP57]], i64 1
; UNALIGNED_VEC_MEM-NEXT: [[TMP35:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_4]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[TMP36:%.*]] = zext <4 x i8> [[TMP35]] to <4 x i32>
-; UNALIGNED_VEC_MEM-NEXT: [[TMP37:%.*]] = insertelement <4 x i32> poison, i32 [[CONV40_2]], i32 0
+; UNALIGNED_VEC_MEM-NEXT: [[TMP37:%.*]] = insertelement <4 x i32> poison, i32 [[CONV40_2]], i64 0
; UNALIGNED_VEC_MEM-NEXT: [[TMP38:%.*]] = zext <2 x i8> [[TMP34]] to <2 x i32>
; UNALIGNED_VEC_MEM-NEXT: [[TMP39:%.*]] = shufflevector <2 x i32> [[TMP38]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; UNALIGNED_VEC_MEM-NEXT: [[TMP40:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> [[TMP39]], <4 x i32> <i32 0, i32 4, i32 5, i32 poison>
-; UNALIGNED_VEC_MEM-NEXT: [[TMP41:%.*]] = insertelement <4 x i32> [[TMP40]], i32 [[CONV38_3]], i32 3
+; UNALIGNED_VEC_MEM-NEXT: [[TMP41:%.*]] = insertelement <4 x i32> [[TMP40]], i32 [[CONV38_3]], i64 3
; UNALIGNED_VEC_MEM-NEXT: [[TMP58:%.*]] = sub <4 x i32> [[TMP41]], [[TMP36]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP43:%.*]] = shl <4 x i32> [[TMP58]], splat (i32 16)
; UNALIGNED_VEC_MEM-NEXT: [[TMP44:%.*]] = add <4 x i32> [[TMP43]], [[TMP30]]
@@ -346,38 +346,38 @@ define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.pt
; UNALIGNED_VEC_MEM-NEXT: [[TMP54:%.*]] = sub <4 x i32> [[TMP52]], [[TMP53]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP55:%.*]] = shl <4 x i32> [[TMP54]], splat (i32 16)
; UNALIGNED_VEC_MEM-NEXT: [[TMP56:%.*]] = add <4 x i32> [[TMP55]], [[TMP51]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD_3:%.*]] = extractelement <4 x i32> [[TMP13]], i32 0
-; UNALIGNED_VEC_MEM-NEXT: [[ADD31_3:%.*]] = extractelement <4 x i32> [[TMP13]], i32 1
-; UNALIGNED_VEC_MEM-NEXT: [[SUB45:%.*]] = sub i32 [[ADD_3]], [[ADD31_3]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD_2:%.*]] = extractelement <4 x i32> [[TMP25]], i32 0
-; UNALIGNED_VEC_MEM-NEXT: [[ADD31_2:%.*]] = extractelement <4 x i32> [[TMP25]], i32 1
-; UNALIGNED_VEC_MEM-NEXT: [[SUB45_1:%.*]] = sub i32 [[ADD_2]], [[ADD31_2]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD19_3:%.*]] = extractelement <4 x i32> [[TMP44]], i32 0
-; UNALIGNED_VEC_MEM-NEXT: [[ADD43_4:%.*]] = extractelement <4 x i32> [[TMP44]], i32 1
-; UNALIGNED_VEC_MEM-NEXT: [[SUB45_3:%.*]] = sub i32 [[ADD19_3]], [[ADD43_4]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD19_2:%.*]] = extractelement <4 x i32> [[TMP56]], i32 0
-; UNALIGNED_VEC_MEM-NEXT: [[ADD43_2:%.*]] = extractelement <4 x i32> [[TMP56]], i32 1
-; UNALIGNED_VEC_MEM-NEXT: [[SUB45_2:%.*]] = sub i32 [[ADD19_2]], [[ADD43_2]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD44:%.*]] = add i32 [[ADD31_3]], [[ADD_3]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD44_1:%.*]] = add i32 [[ADD31_2]], [[ADD_2]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD44_3:%.*]] = add i32 [[ADD43_4]], [[ADD19_3]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD44_2:%.*]] = add i32 [[ADD43_2]], [[ADD19_2]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD31:%.*]] = extractelement <4 x i32> [[TMP13]], i32 2
-; UNALIGNED_VEC_MEM-NEXT: [[ADD43:%.*]] = extractelement <4 x i32> [[TMP13]], i32 3
-; UNALIGNED_VEC_MEM-NEXT: [[SUB47:%.*]] = sub i32 [[ADD31]], [[ADD43]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD31_1:%.*]] = extractelement <4 x i32> [[TMP25]], i32 2
-; UNALIGNED_VEC_MEM-NEXT: [[ADD43_1:%.*]] = extractelement <4 x i32> [[TMP25]], i32 3
-; UNALIGNED_VEC_MEM-NEXT: [[SUB47_1:%.*]] = sub i32 [[ADD31_1]], [[ADD43_1]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD31_4:%.*]] = extractelement <4 x i32> [[TMP44]], i32 2
-; UNALIGNED_VEC_MEM-NEXT: [[ADD43_3:%.*]] = extractelement <4 x i32> [[TMP44]], i32 3
-; UNALIGNED_VEC_MEM-NEXT: [[SUB47_3:%.*]] = sub i32 [[ADD31_4]], [[ADD43_3]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD31_5:%.*]] = extractelement <4 x i32> [[TMP56]], i32 2
-; UNALIGNED_VEC_MEM-NEXT: [[ADD43_5:%.*]] = extractelement <4 x i32> [[TMP56]], i32 3
-; UNALIGNED_VEC_MEM-NEXT: [[SUB47_2:%.*]] = sub i32 [[ADD31_5]], [[ADD43_5]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD46:%.*]] = add i32 [[ADD43]], [[ADD31]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD46_1:%.*]] = add i32 [[ADD43_1]], [[ADD31_1]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD46_3:%.*]] = add i32 [[ADD43_3]], [[ADD31_4]]
-; UNALIGNED_VEC_MEM-NEXT: [[ADD46_2:%.*]] = add i32 [[ADD43_5]], [[ADD31_5]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP75:%.*]] = extractelement <4 x i32> [[TMP13]], i64 0
+; UNALIGNED_VEC_MEM-NEXT: [[TMP84:%.*]] = extractelement <4 x i32> [[TMP13]], i64 1
+; UNALIGNED_VEC_MEM-NEXT: [[SUB45:%.*]] = sub i32 [[TMP75]], [[TMP84]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP59:%.*]] = extractelement <4 x i32> [[TMP25]], i64 0
+; UNALIGNED_VEC_MEM-NEXT: [[TMP60:%.*]] = extractelement <4 x i32> [[TMP25]], i64 1
+; UNALIGNED_VEC_MEM-NEXT: [[SUB45_1:%.*]] = sub i32 [[TMP59]], [[TMP60]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP85:%.*]] = extractelement <4 x i32> [[TMP44]], i64 0
+; UNALIGNED_VEC_MEM-NEXT: [[TMP62:%.*]] = extractelement <4 x i32> [[TMP44]], i64 1
+; UNALIGNED_VEC_MEM-NEXT: [[SUB45_3:%.*]] = sub i32 [[TMP85]], [[TMP62]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP63:%.*]] = extractelement <4 x i32> [[TMP56]], i64 0
+; UNALIGNED_VEC_MEM-NEXT: [[TMP64:%.*]] = extractelement <4 x i32> [[TMP56]], i64 1
+; UNALIGNED_VEC_MEM-NEXT: [[SUB45_2:%.*]] = sub i32 [[TMP63]], [[TMP64]]
+; UNALIGNED_VEC_MEM-NEXT: [[ADD44:%.*]] = add i32 [[TMP84]], [[TMP75]]
+; UNALIGNED_VEC_MEM-NEXT: [[ADD44_1:%.*]] = add i32 [[TMP60]], [[TMP59]]
+; UNALIGNED_VEC_MEM-NEXT: [[ADD44_3:%.*]] = add i32 [[TMP62]], [[TMP85]]
+; UNALIGNED_VEC_MEM-NEXT: [[ADD44_2:%.*]] = add i32 [[TMP64]], [[TMP63]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP65:%.*]] = extractelement <4 x i32> [[TMP13]], i64 2
+; UNALIGNED_VEC_MEM-NEXT: [[TMP86:%.*]] = extractelement <4 x i32> [[TMP13]], i64 3
+; UNALIGNED_VEC_MEM-NEXT: [[SUB47:%.*]] = sub i32 [[TMP65]], [[TMP86]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[TMP25]], i64 2
+; UNALIGNED_VEC_MEM-NEXT: [[TMP68:%.*]] = extractelement <4 x i32> [[TMP25]], i64 3
+; UNALIGNED_VEC_MEM-NEXT: [[SUB47_1:%.*]] = sub i32 [[TMP87]], [[TMP68]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP88:%.*]] = extractelement <4 x i32> [[TMP44]], i64 2
+; UNALIGNED_VEC_MEM-NEXT: [[TMP70:%.*]] = extractelement <4 x i32> [[TMP44]], i64 3
+; UNALIGNED_VEC_MEM-NEXT: [[SUB47_3:%.*]] = sub i32 [[TMP88]], [[TMP70]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP89:%.*]] = extractelement <4 x i32> [[TMP56]], i64 2
+; UNALIGNED_VEC_MEM-NEXT: [[TMP72:%.*]] = extractelement <4 x i32> [[TMP56]], i64 3
+; UNALIGNED_VEC_MEM-NEXT: [[SUB47_2:%.*]] = sub i32 [[TMP89]], [[TMP72]]
+; UNALIGNED_VEC_MEM-NEXT: [[ADD46:%.*]] = add i32 [[TMP86]], [[TMP65]]
+; UNALIGNED_VEC_MEM-NEXT: [[ADD46_1:%.*]] = add i32 [[TMP68]], [[TMP87]]
+; UNALIGNED_VEC_MEM-NEXT: [[ADD46_3:%.*]] = add i32 [[TMP70]], [[TMP88]]
+; UNALIGNED_VEC_MEM-NEXT: [[ADD46_2:%.*]] = add i32 [[TMP72]], [[TMP89]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB59:%.*]] = sub i32 [[SUB45]], [[SUB47]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB59_1:%.*]] = sub i32 [[SUB45_1]], [[SUB47_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB59_3:%.*]] = sub i32 [[SUB45_3]], [[SUB47_3]]
@@ -426,39 +426,39 @@ define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.pt
; UNALIGNED_VEC_MEM-NEXT: [[SUB104:%.*]] = sub i32 [[ADD78]], [[ADD94]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD103:%.*]] = add i32 [[ADD94]], [[ADD78]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD105:%.*]] = add i32 [[SUB102]], [[SUB86]]
-; UNALIGNED_VEC_MEM-NEXT: [[TMP66:%.*]] = insertelement <16 x i32> poison, i32 [[ADD46_2]], i32 0
+; UNALIGNED_VEC_MEM-NEXT: [[TMP66:%.*]] = insertelement <16 x i32> poison, i32 [[ADD46_2]], i64 0
; UNALIGNED_VEC_MEM-NEXT: [[TMP74:%.*]] = shufflevector <4 x i32> [[TMP27]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_VEC_MEM-NEXT: [[TMP67:%.*]] = shufflevector <16 x i32> [[TMP66]], <16 x i32> [[TMP74]], <16 x i32> <i32 0, i32 16, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; UNALIGNED_VEC_MEM-NEXT: [[TMP68:%.*]] = insertelement <16 x i32> [[TMP67]], i32 [[ADD46_1]], i32 2
-; UNALIGNED_VEC_MEM-NEXT: [[TMP69:%.*]] = insertelement <16 x i32> [[TMP68]], i32 [[ADD46]], i32 3
+; UNALIGNED_VEC_MEM-NEXT: [[TMP105:%.*]] = insertelement <16 x i32> [[TMP67]], i32 [[ADD46_1]], i64 2
+; UNALIGNED_VEC_MEM-NEXT: [[TMP69:%.*]] = insertelement <16 x i32> [[TMP105]], i32 [[ADD46]], i64 3
; UNALIGNED_VEC_MEM-NEXT: [[TMP78:%.*]] = shufflevector <4 x i32> [[TMP49]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_VEC_MEM-NEXT: [[TMP71:%.*]] = shufflevector <16 x i32> [[TMP69]], <16 x i32> [[TMP78]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; UNALIGNED_VEC_MEM-NEXT: [[TMP72:%.*]] = insertelement <16 x i32> [[TMP71]], i32 [[SUB47_1]], i32 6
-; UNALIGNED_VEC_MEM-NEXT: [[TMP73:%.*]] = insertelement <16 x i32> [[TMP72]], i32 [[SUB47]], i32 7
+; UNALIGNED_VEC_MEM-NEXT: [[TMP107:%.*]] = insertelement <16 x i32> [[TMP71]], i32 [[SUB47_1]], i64 6
+; UNALIGNED_VEC_MEM-NEXT: [[TMP73:%.*]] = insertelement <16 x i32> [[TMP107]], i32 [[SUB47]], i64 7
; UNALIGNED_VEC_MEM-NEXT: [[TMP118:%.*]] = shufflevector <4 x i32> [[TMP18]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_VEC_MEM-NEXT: [[TMP76:%.*]] = shufflevector <16 x i32> [[TMP73]], <16 x i32> [[TMP118]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; UNALIGNED_VEC_MEM-NEXT: [[TMP77:%.*]] = insertelement <16 x i32> [[TMP76]], i32 [[ADD44]], i32 11
+; UNALIGNED_VEC_MEM-NEXT: [[TMP77:%.*]] = insertelement <16 x i32> [[TMP76]], i32 [[ADD44]], i64 11
; UNALIGNED_VEC_MEM-NEXT: [[TMP79:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; UNALIGNED_VEC_MEM-NEXT: [[TMP80:%.*]] = shufflevector <16 x i32> [[TMP77]], <16 x i32> [[TMP79]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
; UNALIGNED_VEC_MEM-NEXT: [[TMP81:%.*]] = lshr <16 x i32> [[TMP80]], splat (i32 15)
; UNALIGNED_VEC_MEM-NEXT: [[TMP82:%.*]] = and <16 x i32> [[TMP81]], splat (i32 65537)
; UNALIGNED_VEC_MEM-NEXT: [[TMP83:%.*]] = mul <16 x i32> [[TMP82]], splat (i32 65535)
-; UNALIGNED_VEC_MEM-NEXT: [[TMP84:%.*]] = insertelement <16 x i32> poison, i32 [[ADD105]], i32 0
-; UNALIGNED_VEC_MEM-NEXT: [[TMP85:%.*]] = insertelement <16 x i32> [[TMP84]], i32 [[ADD103]], i32 1
-; UNALIGNED_VEC_MEM-NEXT: [[TMP86:%.*]] = insertelement <16 x i32> [[TMP85]], i32 [[SUB104]], i32 2
-; UNALIGNED_VEC_MEM-NEXT: [[TMP87:%.*]] = insertelement <16 x i32> [[TMP86]], i32 [[SUB106]], i32 3
-; UNALIGNED_VEC_MEM-NEXT: [[TMP88:%.*]] = insertelement <16 x i32> [[TMP87]], i32 [[ADD105_1]], i32 4
-; UNALIGNED_VEC_MEM-NEXT: [[TMP89:%.*]] = insertelement <16 x i32> [[TMP88]], i32 [[ADD103_1]], i32 5
-; UNALIGNED_VEC_MEM-NEXT: [[TMP90:%.*]] = insertelement <16 x i32> [[TMP89]], i32 [[SUB104_1]], i32 6
-; UNALIGNED_VEC_MEM-NEXT: [[TMP91:%.*]] = insertelement <16 x i32> [[TMP90]], i32 [[SUB106_1]], i32 7
-; UNALIGNED_VEC_MEM-NEXT: [[TMP92:%.*]] = insertelement <16 x i32> [[TMP91]], i32 [[ADD105_2]], i32 8
-; UNALIGNED_VEC_MEM-NEXT: [[TMP93:%.*]] = insertelement <16 x i32> [[TMP92]], i32 [[ADD103_2]], i32 9
-; UNALIGNED_VEC_MEM-NEXT: [[TMP94:%.*]] = insertelement <16 x i32> [[TMP93]], i32 [[SUB104_2]], i32 10
-; UNALIGNED_VEC_MEM-NEXT: [[TMP95:%.*]] = insertelement <16 x i32> [[TMP94]], i32 [[SUB106_2]], i32 11
-; UNALIGNED_VEC_MEM-NEXT: [[TMP96:%.*]] = insertelement <16 x i32> [[TMP95]], i32 [[ADD105_3]], i32 12
-; UNALIGNED_VEC_MEM-NEXT: [[TMP97:%.*]] = insertelement <16 x i32> [[TMP96]], i32 [[ADD103_3]], i32 13
-; UNALIGNED_VEC_MEM-NEXT: [[TMP98:%.*]] = insertelement <16 x i32> [[TMP97]], i32 [[SUB104_3]], i32 14
-; UNALIGNED_VEC_MEM-NEXT: [[TMP99:%.*]] = insertelement <16 x i32> [[TMP98]], i32 [[SUB106_3]], i32 15
+; UNALIGNED_VEC_MEM-NEXT: [[TMP90:%.*]] = insertelement <16 x i32> poison, i32 [[ADD105]], i64 0
+; UNALIGNED_VEC_MEM-NEXT: [[TMP91:%.*]] = insertelement <16 x i32> [[TMP90]], i32 [[ADD103]], i64 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP92:%.*]] = insertelement <16 x i32> [[TMP91]], i32 [[SUB104]], i64 2
+; UNALIGNED_VEC_MEM-NEXT: [[TMP93:%.*]] = insertelement <16 x i32> [[TMP92]], i32 [[SUB106]], i64 3
+; UNALIGNED_VEC_MEM-NEXT: [[TMP94:%.*]] = insertelement <16 x i32> [[TMP93]], i32 [[ADD105_1]], i64 4
+; UNALIGNED_VEC_MEM-NEXT: [[TMP95:%.*]] = insertelement <16 x i32> [[TMP94]], i32 [[ADD103_1]], i64 5
+; UNALIGNED_VEC_MEM-NEXT: [[TMP96:%.*]] = insertelement <16 x i32> [[TMP95]], i32 [[SUB104_1]], i64 6
+; UNALIGNED_VEC_MEM-NEXT: [[TMP97:%.*]] = insertelement <16 x i32> [[TMP96]], i32 [[SUB106_1]], i64 7
+; UNALIGNED_VEC_MEM-NEXT: [[TMP98:%.*]] = insertelement <16 x i32> [[TMP97]], i32 [[ADD105_2]], i64 8
+; UNALIGNED_VEC_MEM-NEXT: [[TMP108:%.*]] = insertelement <16 x i32> [[TMP98]], i32 [[ADD103_2]], i64 9
+; UNALIGNED_VEC_MEM-NEXT: [[TMP109:%.*]] = insertelement <16 x i32> [[TMP108]], i32 [[SUB104_2]], i64 10
+; UNALIGNED_VEC_MEM-NEXT: [[TMP110:%.*]] = insertelement <16 x i32> [[TMP109]], i32 [[SUB106_2]], i64 11
+; UNALIGNED_VEC_MEM-NEXT: [[TMP102:%.*]] = insertelement <16 x i32> [[TMP110]], i32 [[ADD105_3]], i64 12
+; UNALIGNED_VEC_MEM-NEXT: [[TMP103:%.*]] = insertelement <16 x i32> [[TMP102]], i32 [[ADD103_3]], i64 13
+; UNALIGNED_VEC_MEM-NEXT: [[TMP104:%.*]] = insertelement <16 x i32> [[TMP103]], i32 [[SUB104_3]], i64 14
+; UNALIGNED_VEC_MEM-NEXT: [[TMP99:%.*]] = insertelement <16 x i32> [[TMP104]], i32 [[SUB106_3]], i64 15
; UNALIGNED_VEC_MEM-NEXT: [[TMP100:%.*]] = add <16 x i32> [[TMP83]], [[TMP99]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP101:%.*]] = xor <16 x i32> [[TMP100]], [[TMP80]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP117:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP101]])
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/fmuladd_width_prop.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/fmuladd_width_prop.ll
index 398ac84051af4..9facc83c2840a 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/fmuladd_width_prop.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/fmuladd_width_prop.ll
@@ -21,16 +21,16 @@ define void @bar(ptr %0, i64 %1, double %2, i64 %3, double %4, double %5, double
; CHECK-NEXT: [[TMP19:%.*]] = fmul nnan double [[TMP18]], f0x3EF0001000100010
; CHECK-NEXT: [[TMP20:%.*]] = fmul double [[TMP2]], [[TMP19]]
; CHECK-NEXT: [[TMP21:%.*]] = fadd double [[TMP4]], [[TMP20]]
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <2 x double> poison, double [[TMP20]], i32 0
+; CHECK-NEXT: [[TMP22:%.*]] = insertelement <2 x double> poison, double [[TMP20]], i64 0
; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <2 x double> [[TMP22]], <2 x double> poison, <2 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <2 x double> poison, double [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <2 x double> [[TMP24]], double [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <2 x double> poison, double [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP25:%.*]] = insertelement <2 x double> [[TMP24]], double [[TMP5]], i64 1
; CHECK-NEXT: [[TMP26:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP23]], <2 x double> [[TMP14]], <2 x double> [[TMP25]])
; CHECK-NEXT: [[TMP27:%.*]] = uitofp <2 x i16> [[TMP15]] to <2 x double>
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i32 1
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <2 x double> [[TMP28]], double [[TMP20]], i32 0
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <2 x double> poison, double [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <2 x double> [[TMP30]], double [[TMP8]], i32 1
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i64 1
+; CHECK-NEXT: [[TMP29:%.*]] = insertelement <2 x double> [[TMP28]], double [[TMP20]], i64 0
+; CHECK-NEXT: [[TMP30:%.*]] = insertelement <2 x double> poison, double [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP31:%.*]] = insertelement <2 x double> [[TMP30]], double [[TMP8]], i64 1
; CHECK-NEXT: [[TMP32:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP29]], <2 x double> [[TMP27]], <2 x double> [[TMP31]])
; CHECK-NEXT: br label %[[R:.*]]
; CHECK: [[R]]:
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/gather-insert-point-restore.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/gather-insert-point-restore.ll
index d7d3aa4d7c73b..1b389baadc9ed 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/gather-insert-point-restore.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/gather-insert-point-restore.ll
@@ -5,7 +5,7 @@ define i16 @test(ptr %i) {
; CHECK-LABEL: define i16 @test(
; CHECK-SAME: ptr [[I:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x ptr> poison, ptr [[I]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x ptr> poison, ptr [[I]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x ptr> [[TMP0]], <4 x ptr> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <4 x ptr> [[TMP1]], <4 x i64> <i64 132860, i64 137774, i64 132860, i64 137774>
; CHECK-NEXT: [[GEP_US154_2:%.*]] = getelementptr i8, ptr [[I]], i64 142688
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/gather-node-with-no-users.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/gather-node-with-no-users.ll
index 5697292efa319..9c9e4210bb4db 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/gather-node-with-no-users.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/gather-node-with-no-users.ll
@@ -5,7 +5,7 @@ define void @test(ptr %c) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[C:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr [[C]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr [[C]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x ptr> [[TMP0]], <8 x ptr> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, <8 x ptr> [[TMP1]], <8 x i64> <i64 222, i64 228, i64 276, i64 279, i64 282, i64 285, i64 288, i64 0>
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <8 x ptr> [[TMP1]], <8 x i64> <i64 0, i64 345, i64 348, i64 351, i64 354, i64 357, i64 360, i64 363>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/loads-ordering.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/loads-ordering.ll
index b6a40f0162bbd..b54d557dd09cb 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/loads-ordering.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/loads-ordering.ll
@@ -10,7 +10,7 @@ define fastcc void @rephase(ptr %phases_in, ptr %157, i64 %158) {
; CHECK-NEXT: [[IMAG_247:%.*]] = getelementptr i8, ptr [[IND_END11]], i64 408
; CHECK-NEXT: [[IMAG_1_251:%.*]] = getelementptr i8, ptr [[IND_END11]], i64 424
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[IMAG_1_251]], align 8
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> poison, double [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> poison, double [[TMP2]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[TMP4]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x double> <double 0.000000e+00, double 0.000000e+00, double poison, double poison>, <4 x double> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/mixed-extracts-types.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/mixed-extracts-types.ll
index 56555efb063ed..4566c8ae4a486 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/mixed-extracts-types.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/mixed-extracts-types.ll
@@ -11,8 +11,8 @@ define i32 @test() {
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i8> [[TMP0]], zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i16>
; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr getelementptr ([0 x i16], ptr null, i64 0, i64 -14), align 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i8> poison, i8 [[VECTOR_RECUR_EXTRACT]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i8> [[TMP4]], i8 [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i8> poison, i8 [[VECTOR_RECUR_EXTRACT]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i8> [[TMP4]], i8 [[TMP3]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i8> [[TMP5]] to <2 x i32>
; CHECK-NEXT: store <2 x i32> [[TMP6]], ptr getelementptr ([0 x i32], ptr null, i64 0, i64 -14), align 4
; CHECK-NEXT: ret i32 0
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/non-commutative-second-arg-only-copyable.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/non-commutative-second-arg-only-copyable.ll
index 0561466b564be..442b86733fe96 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/non-commutative-second-arg-only-copyable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/non-commutative-second-arg-only-copyable.ll
@@ -6,8 +6,8 @@ define i32 @main(ptr %q, ptr %a, i8 %.pre) {
; CHECK-SAME: ptr [[Q:%.*]], ptr [[A:%.*]], i8 [[DOTPRE:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[DOTPRE1:%.*]] = load i8, ptr [[Q]], align 1
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[DOTPRE]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[DOTPRE1]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[DOTPRE]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[DOTPRE1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP2]], <i32 0, i32 1>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> <i32 poison, i32 1>, <2 x i32> <i32 0, i32 3>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
index 4caa9949d3319..aee0c64522eef 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
@@ -10,10 +10,10 @@ define void @partial_vec_invalid_cost() #0 {
; CHECK-NEXT: [[LSHR_2:%.*]] = lshr i96 0, 0
; CHECK-NEXT: [[LSHR_1:%.*]] = lshr i96 0, 1
; CHECK-NEXT: [[ADD_1:%.*]] = add i96 -1, 1
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i96> poison, i96 [[LSHR_1]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i96> [[TMP0]], i96 [[LSHR_2]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i96> [[TMP1]], i96 0, i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i96> [[TMP2]], i96 [[ADD_1]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i96> poison, i96 [[LSHR_1]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i96> [[TMP0]], i96 [[LSHR_2]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i96> [[TMP1]], i96 0, i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i96> [[TMP2]], i96 [[ADD_1]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = trunc <4 x i96> [[TMP3]] to <4 x i32>
; CHECK-NEXT: [[RDX_OP:%.*]] = or <4 x i32> zeroinitializer, [[TMP4]]
; CHECK-NEXT: [[OP_RDX3:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[RDX_OP]])
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
index bc05cc40bd549..2cbb99284a088 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
@@ -337,9 +337,9 @@ entry:
define void @reduce_or_2() {
; ZVFHMIN-LABEL: @reduce_or_2(
; ZVFHMIN-NEXT: [[TMP6:%.*]] = shl i64 0, 0
-; ZVFHMIN-NEXT: [[TMP7:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, i64 [[TMP6]], i32 15
+; ZVFHMIN-NEXT: [[TMP7:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, i64 [[TMP6]], i64 15
; ZVFHMIN-NEXT: [[TMP8:%.*]] = icmp ult <16 x i64> [[TMP7]], zeroinitializer
-; ZVFHMIN-NEXT: [[TMP4:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP6]], i32 6
+; ZVFHMIN-NEXT: [[TMP4:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP6]], i64 6
; ZVFHMIN-NEXT: [[TMP5:%.*]] = icmp ult <16 x i64> [[TMP4]], zeroinitializer
; ZVFHMIN-NEXT: [[RDX_OP:%.*]] = or <16 x i1> [[TMP8]], [[TMP5]]
; ZVFHMIN-NEXT: [[TMP1:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[RDX_OP]])
@@ -351,9 +351,9 @@ define void @reduce_or_2() {
;
; ZVFHDEFAULT-LABEL: @reduce_or_2(
; ZVFHDEFAULT-NEXT: [[TMP6:%.*]] = shl i64 0, 0
-; ZVFHDEFAULT-NEXT: [[TMP7:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, i64 [[TMP6]], i32 15
+; ZVFHDEFAULT-NEXT: [[TMP7:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, i64 [[TMP6]], i64 15
; ZVFHDEFAULT-NEXT: [[TMP8:%.*]] = icmp ult <16 x i64> [[TMP7]], zeroinitializer
-; ZVFHDEFAULT-NEXT: [[TMP4:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP6]], i32 6
+; ZVFHDEFAULT-NEXT: [[TMP4:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP6]], i64 6
; ZVFHDEFAULT-NEXT: [[TMP5:%.*]] = icmp ult <16 x i64> [[TMP4]], zeroinitializer
; ZVFHDEFAULT-NEXT: [[RDX_OP:%.*]] = or <16 x i1> [[TMP8]], [[TMP5]]
; ZVFHDEFAULT-NEXT: [[TMP1:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[RDX_OP]])
@@ -372,7 +372,7 @@ define void @reduce_or_2() {
;
; ZVFH512-LABEL: @reduce_or_2(
; ZVFH512-NEXT: [[TMP5:%.*]] = shl i64 0, 0
-; ZVFH512-NEXT: [[TMP6:%.*]] = insertelement <32 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, i64 [[TMP5]], i32 15
+; ZVFH512-NEXT: [[TMP6:%.*]] = insertelement <32 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, i64 [[TMP5]], i64 15
; ZVFH512-NEXT: [[TMP7:%.*]] = shufflevector <32 x i64> [[TMP6]], <32 x i64> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 15, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
; ZVFH512-NEXT: [[TMP4:%.*]] = icmp ult <32 x i64> [[TMP7]], zeroinitializer
; ZVFH512-NEXT: [[TMP1:%.*]] = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> [[TMP4]])
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
index 09c11bbefd4a3..5ef40a3f6d2f7 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
@@ -16,10 +16,10 @@ define i32 @test(i32 %a, i8 %b, i8 %c) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[A:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[C]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[C]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[TMP1]], <i8 -1, i8 -2, i8 -3, i8 -4>
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>
; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i8> [[TMP4]] to <4 x i16>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll
index 0d9b9dd987b81..dc77f91beab78 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/remarks-insert-into-small-vector.ll
@@ -18,7 +18,7 @@ define void @test() {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr null, align 4
; CHECK-NEXT: [[TMP5:%.*]] = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> align 4 splat (ptr null), <2 x i1> splat (i1 true), <2 x float> poison)
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[TMP2]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = fcmp ogt <2 x float> [[TMP3]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i1> [[TMP6]], <2 x i1> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP5]], <2 x float> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
index 6c09ce4bc73fe..9a9fcd1b259c3 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
@@ -14,31 +14,31 @@ define fastcc i32 @test(i32 %0, i32 %add111.i.i, <4 x i32> %PredPel.i.sroa.86.72
; CHECK-NEXT: [[MUL1445_I:%.*]] = shl i32 [[TMP0]], 1
; CHECK-NEXT: [[ADD2235_I17:%.*]] = or i32 [[TMP0]], 1
; CHECK-NEXT: [[ADD2323_I1:%.*]] = add i32 [[TMP0]], 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i32> poison, i32 [[ADD111_I_I]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <3 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i32> poison, i32 [[ADD111_I_I]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <3 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <3 x i32> [[TMP5]], <3 x i32> poison, <3 x i32> zeroinitializer
; CHECK-NEXT: [[ADD1392_I:%.*]] = add i32 [[TMP0]], 1
; CHECK-NEXT: [[SHR143_5_I_I9:%.*]] = ashr i32 [[TMP0]], 1
; CHECK-NEXT: [[LOOPARRAY_SROA_24_0_I_I3:%.*]] = ashr i32 [[TMP0]], 1
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <3 x i32> [[TMP2]], i32 [[LOOPARRAY_SROA_24_0_I_I3]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <3 x i32> [[TMP10]], i32 [[ADD2323_I1]], i32 2
+; CHECK-NEXT: [[TMP30:%.*]] = insertelement <3 x i32> [[TMP2]], i32 [[LOOPARRAY_SROA_24_0_I_I3]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <3 x i32> [[TMP30]], i32 [[ADD2323_I1]], i64 2
; CHECK-NEXT: [[TMP7:%.*]] = or <3 x i32> [[TMP4]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[PREDPEL_I_SROA_86_72_VEC_EXTRACT]], <4 x i32> [[TMP1]], <8 x i32> <i32 0, i32 poison, i32 poison, i32 4, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 [[TMP0]], i32 4
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i32> [[TMP9]], i32 [[ADD111_I_I]], i32 6
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i32> [[TMP11]], i32 [[ADD2235_I17]], i32 1
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <8 x i32> [[TMP12]], i32 [[LOOPARRAY_SROA_24_0_I_I3]], i32 2
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i32> [[TMP30]], i32 [[MUL1445_I]], i32 5
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i32> [[TMP13]], i32 [[SHR143_5_I_I9]], i32 7
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 [[TMP0]], i64 4
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i32> [[TMP9]], i32 [[ADD111_I_I]], i64 6
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i32> [[TMP10]], i32 [[ADD2235_I17]], i64 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i32> [[TMP11]], i32 [[LOOPARRAY_SROA_24_0_I_I3]], i64 2
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i32> [[TMP12]], i32 [[MUL1445_I]], i64 5
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i32> [[TMP13]], i32 [[SHR143_5_I_I9]], i64 7
; CHECK-NEXT: [[TMP15:%.*]] = add <8 x i32> [[TMP14]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 2, i32 1, i32 1>
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <8 x i32> [[TMP15]], <8 x i32> poison, <11 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <3 x i32> [[TMP7]], <3 x i32> poison, <11 x i32> <i32 0, i32 1, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <11 x i32> [[TMP16]], <11 x i32> [[TMP17]], <11 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 11, i32 12, i32 13>
; CHECK-NEXT: [[TMP19:%.*]] = lshr <11 x i32> [[TMP18]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 2, i32 1, i32 1, i32 1, i32 1, i32 1>
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 2
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i32> [[TMP31]], i32 [[LOOPARRAY_SROA_24_0_I_I3]], i32 0
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> [[TMP20]], i32 [[ADD1392_I]], i32 1
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <4 x i32> [[TMP21]], i32 [[SHR143_5_I_I9]], i32 3
+; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 2
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> [[TMP20]], i32 [[LOOPARRAY_SROA_24_0_I_I3]], i64 0
+; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i32> [[TMP21]], i32 [[ADD1392_I]], i64 1
+; CHECK-NEXT: [[TMP32:%.*]] = insertelement <4 x i32> [[TMP31]], i32 [[SHR143_5_I_I9]], i64 3
; CHECK-NEXT: [[TMP22:%.*]] = or <4 x i32> [[TMP32]], splat (i32 1)
; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <3 x i32> [[TMP6]], <3 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP24:%.*]] = add <4 x i32> [[TMP22]], [[TMP23]]
@@ -56,24 +56,24 @@ define fastcc i32 @test(i32 %0, i32 %add111.i.i, <4 x i32> %PredPel.i.sroa.86.72
; THRESH-NEXT: [[MUL1445_I:%.*]] = shl i32 [[TMP0]], 1
; THRESH-NEXT: [[ADD2235_I16:%.*]] = or i32 [[TMP0]], 1
; THRESH-NEXT: [[ADD2323_I:%.*]] = add i32 [[TMP0]], 1
-; THRESH-NEXT: [[TMP30:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0
+; THRESH-NEXT: [[TMP30:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i64 0
; THRESH-NEXT: [[TMP31:%.*]] = shufflevector <2 x i32> [[TMP30]], <2 x i32> poison, <2 x i32> zeroinitializer
; THRESH-NEXT: [[TMP32:%.*]] = add <2 x i32> [[TMP31]], <i32 0, i32 1>
; THRESH-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP32]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 0>
; THRESH-NEXT: [[TMP21:%.*]] = ashr <4 x i32> [[TMP5]], <i32 1, i32 0, i32 0, i32 1>
-; THRESH-NEXT: [[TMP2:%.*]] = insertelement <3 x i32> poison, i32 [[ADD111_I_I]], i32 0
+; THRESH-NEXT: [[TMP2:%.*]] = insertelement <3 x i32> poison, i32 [[ADD111_I_I]], i64 0
; THRESH-NEXT: [[TMP33:%.*]] = shufflevector <4 x i32> [[TMP21]], <4 x i32> poison, <3 x i32> <i32 0, i32 poison, i32 poison>
; THRESH-NEXT: [[TMP34:%.*]] = shufflevector <3 x i32> [[TMP2]], <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
; THRESH-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP34]], <4 x i32> [[TMP21]], <3 x i32> <i32 0, i32 4, i32 poison>
-; THRESH-NEXT: [[TMP4:%.*]] = insertelement <3 x i32> [[TMP3]], i32 [[ADD2323_I]], i32 2
+; THRESH-NEXT: [[TMP4:%.*]] = insertelement <3 x i32> [[TMP3]], i32 [[ADD2323_I]], i64 2
; THRESH-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP31]], <2 x i32> poison, <3 x i32> zeroinitializer
; THRESH-NEXT: [[TMP7:%.*]] = or <3 x i32> [[TMP4]], [[TMP6]]
; THRESH-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[PREDPEL_I_SROA_86_72_VEC_EXTRACT]], <4 x i32> [[TMP1]], <8 x i32> <i32 0, i32 poison, i32 poison, i32 4, i32 poison, i32 poison, i32 poison, i32 poison>
; THRESH-NEXT: [[TMP9:%.*]] = shufflevector <3 x i32> [[TMP4]], <3 x i32> poison, <8 x i32> <i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 0, i32 poison>
; THRESH-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> [[TMP9]], <8 x i32> <i32 0, i32 poison, i32 10, i32 3, i32 poison, i32 poison, i32 14, i32 poison>
-; THRESH-NEXT: [[TMP11:%.*]] = insertelement <8 x i32> [[TMP10]], i32 [[TMP0]], i32 4
-; THRESH-NEXT: [[TMP12:%.*]] = insertelement <8 x i32> [[TMP11]], i32 [[ADD2235_I16]], i32 1
-; THRESH-NEXT: [[TMP13:%.*]] = insertelement <8 x i32> [[TMP12]], i32 [[MUL1445_I]], i32 5
+; THRESH-NEXT: [[TMP35:%.*]] = insertelement <8 x i32> [[TMP10]], i32 [[TMP0]], i64 4
+; THRESH-NEXT: [[TMP36:%.*]] = insertelement <8 x i32> [[TMP35]], i32 [[ADD2235_I16]], i64 1
+; THRESH-NEXT: [[TMP13:%.*]] = insertelement <8 x i32> [[TMP36]], i32 [[MUL1445_I]], i64 5
; THRESH-NEXT: [[TMP20:%.*]] = shufflevector <4 x i32> [[TMP21]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; THRESH-NEXT: [[TMP14:%.*]] = shufflevector <8 x i32> [[TMP13]], <8 x i32> [[TMP20]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 11>
; THRESH-NEXT: [[TMP15:%.*]] = add <8 x i32> [[TMP14]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 2, i32 1, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-interleaved-loads.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-interleaved-loads.ll
index a4b3c8e4b53af..7d761244d3f30 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-interleaved-loads.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/reordered-interleaved-loads.ll
@@ -10,53 +10,53 @@ define i1 @test(i32 %conv15.12, i16 %0, ptr %1, i16 %2, i16 %3, i16 %4, i16 %5,
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP1]], align 2
; CHECK-NEXT: [[TMP8:%.*]] = load i16, ptr @h, align 2
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i16> [[TMP9]], i16 [[TMP0]], i32 2
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i16> [[TMP10]], i16 [[TMP8]], i32 1
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i16> [[TMP11]], i16 [[TMP7]], i32 3
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i16> [[TMP9]], i16 [[TMP0]], i64 2
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i16> [[TMP10]], i16 [[TMP8]], i64 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i16> [[TMP11]], i16 [[TMP7]], i64 3
; CHECK-NEXT: [[TMP13:%.*]] = sext <4 x i16> [[TMP12]] to <4 x i32>
; CHECK-NEXT: [[TMP14:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP13]], <4 x i32> zeroinitializer)
; CHECK-NEXT: [[TMP15:%.*]] = icmp eq <4 x i16> [[TMP12]], zeroinitializer
; CHECK-NEXT: [[TMP16:%.*]] = select <4 x i1> [[TMP15]], <4 x i32> splat (i32 8), <4 x i32> [[TMP13]]
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[CONV15_12]], i32 3
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[CONV15_12]], i64 3
; CHECK-NEXT: [[TMP18:%.*]] = xor <4 x i32> [[TMP16]], [[TMP17]]
; CHECK-NEXT: [[TMP19:%.*]] = icmp sgt <4 x i32> [[TMP14]], [[TMP18]]
-; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x i1> [[TMP19]], i32 3
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x i1> [[TMP19]], i64 3
; CHECK-NEXT: [[CONV30_18:%.*]] = zext i1 [[TMP29]] to i16
; CHECK-NEXT: store i16 [[CONV30_18]], ptr @a, align 2
-; CHECK-NEXT: [[TMP30:%.*]] = extractelement <4 x i1> [[TMP19]], i32 2
+; CHECK-NEXT: [[TMP30:%.*]] = extractelement <4 x i1> [[TMP19]], i64 2
; CHECK-NEXT: [[CONV30_219:%.*]] = zext i1 [[TMP30]] to i16
; CHECK-NEXT: store i16 [[CONV30_219]], ptr @a, align 2
-; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i1> [[TMP19]], i32 1
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i1> [[TMP19]], i64 1
; CHECK-NEXT: [[CONV30_330:%.*]] = zext i1 [[TMP31]] to i16
; CHECK-NEXT: store i16 [[CONV30_330]], ptr @a, align 2
-; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x i1> [[TMP19]], i32 0
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x i1> [[TMP19]], i64 0
; CHECK-NEXT: [[CONV30_4:%.*]] = zext i1 [[TMP32]] to i16
; CHECK-NEXT: store i16 [[CONV30_4]], ptr @a, align 2
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i16> poison, i16 [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i16> [[TMP24]], i16 [[TMP4]], i32 1
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x i16> [[TMP25]], i16 [[TMP5]], i32 2
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i16> [[TMP26]], i16 [[TMP6]], i32 3
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i16> poison, i16 [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i16> [[TMP24]], i16 [[TMP4]], i64 1
+; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x i16> [[TMP25]], i16 [[TMP5]], i64 2
+; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i16> [[TMP26]], i16 [[TMP6]], i64 3
; CHECK-NEXT: [[TMP28:%.*]] = sext <4 x i16> [[TMP27]] to <4 x i32>
; CHECK-NEXT: [[TMP38:%.*]] = load <16 x i16>, ptr getelementptr inbounds nuw (i8, ptr @h, i64 6), align 2
; CHECK-NEXT: [[TMP39:%.*]] = shufflevector <16 x i16> [[TMP38]], <16 x i16> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
; CHECK-NEXT: [[TMP40:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP28]], <4 x i32> zeroinitializer)
; CHECK-NEXT: [[TMP41:%.*]] = icmp eq <4 x i16> [[TMP39]], zeroinitializer
; CHECK-NEXT: [[TMP42:%.*]] = select <4 x i1> [[TMP41]], <4 x i32> splat (i32 8), <4 x i32> [[TMP28]]
-; CHECK-NEXT: [[TMP43:%.*]] = insertelement <4 x i32> [[TMP28]], i32 [[CONV15_1_3]], i32 2
-; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i32> [[TMP43]], i32 [[CONV15_1_4]], i32 3
+; CHECK-NEXT: [[TMP43:%.*]] = insertelement <4 x i32> [[TMP28]], i32 [[CONV15_1_3]], i64 2
+; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i32> [[TMP43]], i32 [[CONV15_1_4]], i64 3
; CHECK-NEXT: [[TMP45:%.*]] = xor <4 x i32> [[TMP42]], [[TMP44]]
; CHECK-NEXT: [[TMP37:%.*]] = icmp sgt <4 x i32> [[TMP40]], [[TMP45]]
-; CHECK-NEXT: [[TMP33:%.*]] = extractelement <4 x i1> [[TMP37]], i32 0
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <4 x i1> [[TMP37]], i64 0
; CHECK-NEXT: [[CONV30_1_1:%.*]] = zext i1 [[TMP33]] to i16
; CHECK-NEXT: store i16 [[CONV30_1_1]], ptr @a, align 2
-; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x i1> [[TMP37]], i32 1
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x i1> [[TMP37]], i64 1
; CHECK-NEXT: [[CONV30_1_2:%.*]] = zext i1 [[TMP34]] to i16
; CHECK-NEXT: store i16 [[CONV30_1_2]], ptr @a, align 2
-; CHECK-NEXT: [[TMP35:%.*]] = extractelement <4 x i1> [[TMP37]], i32 2
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <4 x i1> [[TMP37]], i64 2
; CHECK-NEXT: [[CONV30_1_3:%.*]] = zext i1 [[TMP35]] to i16
; CHECK-NEXT: store i16 [[CONV30_1_3]], ptr @a, align 2
-; CHECK-NEXT: [[TMP36:%.*]] = extractelement <4 x i1> [[TMP37]], i32 3
+; CHECK-NEXT: [[TMP36:%.*]] = extractelement <4 x i1> [[TMP37]], i64 3
; CHECK-NEXT: ret i1 [[TMP36]]
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll
index 6220e493f85ca..920f39c1cb762 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll
@@ -126,8 +126,8 @@ define void @too_wide(ptr %in0, ptr %out0) {
; CHECK-LABEL: @too_wide(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[IN1:%.*]] = getelementptr i16, ptr [[IN0:%.*]], i64 16
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x ptr> poison, ptr [[IN0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP4]], ptr [[IN1]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x ptr> poison, ptr [[IN0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP4]], ptr [[IN1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x ptr> [[TMP1]], <2 x ptr> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i16, <16 x ptr> [[TMP2]], <16 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
; CHECK-NEXT: [[TMP0:%.*]] = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> align 2 [[TMP3]], <16 x i1> splat (i1 true), <16 x i16> poison)
@@ -171,8 +171,8 @@ define void @non_aligned_stride(ptr %in0, ptr %out0) {
; CHECK-LABEL: @non_aligned_stride(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[IN1:%.*]] = getelementptr i8, ptr [[IN0:%.*]], i64 3
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr> poison, ptr [[IN0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP0]], ptr [[IN1]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr> poison, ptr [[IN0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP0]], ptr [[IN1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x ptr> [[TMP1]], <2 x ptr> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <4 x ptr> [[TMP2]], <4 x i64> <i64 0, i64 1, i64 0, i64 1>
; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> align 2 [[TMP3]], <4 x i1> splat (i1 true), <4 x i8> poison)
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
index 66cf7dd956c3a..3025c1085d4e7 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/revec.ll
@@ -147,17 +147,17 @@ define ptr @test4() {
; POWEROF2-NEXT: [[TMP13:%.*]] = fmul <2 x float> [[TMP12]], zeroinitializer
; POWEROF2-NEXT: [[TMP14:%.*]] = shufflevector <4 x float> [[TMP10]], <4 x float> poison, <2 x i32> <i32 2, i32 3>
; POWEROF2-NEXT: [[TMP15:%.*]] = fmul <2 x float> zeroinitializer, [[TMP14]]
-; POWEROF2-NEXT: [[TMP30:%.*]] = extractelement <2 x float> [[TMP9]], i32 0
+; POWEROF2-NEXT: [[TMP30:%.*]] = extractelement <2 x float> [[TMP9]], i64 0
; POWEROF2-NEXT: [[TMP17:%.*]] = fmul float 0.000000e+00, [[TMP30]]
-; POWEROF2-NEXT: [[TMP18:%.*]] = extractelement <2 x float> [[TMP9]], i32 1
+; POWEROF2-NEXT: [[TMP18:%.*]] = extractelement <2 x float> [[TMP9]], i64 1
; POWEROF2-NEXT: [[TMP19:%.*]] = fmul float [[TMP18]], 0.000000e+00
-; POWEROF2-NEXT: [[TMP20:%.*]] = extractelement <2 x float> [[TMP13]], i32 0
+; POWEROF2-NEXT: [[TMP20:%.*]] = extractelement <2 x float> [[TMP13]], i64 0
; POWEROF2-NEXT: [[TMP21:%.*]] = fadd reassoc nsz float [[TMP20]], [[TMP17]]
-; POWEROF2-NEXT: [[TMP22:%.*]] = extractelement <2 x float> [[TMP15]], i32 0
+; POWEROF2-NEXT: [[TMP22:%.*]] = extractelement <2 x float> [[TMP15]], i64 0
; POWEROF2-NEXT: [[TMP23:%.*]] = fadd reassoc nsz float [[TMP22]], [[TMP19]]
-; POWEROF2-NEXT: [[TMP24:%.*]] = extractelement <2 x float> [[TMP13]], i32 1
+; POWEROF2-NEXT: [[TMP24:%.*]] = extractelement <2 x float> [[TMP13]], i64 1
; POWEROF2-NEXT: [[TMP25:%.*]] = fadd reassoc nsz float [[TMP21]], [[TMP24]]
-; POWEROF2-NEXT: [[TMP26:%.*]] = extractelement <2 x float> [[TMP15]], i32 1
+; POWEROF2-NEXT: [[TMP26:%.*]] = extractelement <2 x float> [[TMP15]], i64 1
; POWEROF2-NEXT: [[TMP27:%.*]] = fadd reassoc nsz float [[TMP23]], [[TMP26]]
; POWEROF2-NEXT: [[TMP28:%.*]] = tail call float @llvm.sqrt.f32(float [[TMP25]])
; POWEROF2-NEXT: [[TMP29:%.*]] = tail call float @llvm.sqrt.f32(float [[TMP27]])
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
index a0930a2fa1317..2b487bd0392c3 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
@@ -5,14 +5,14 @@ define void @test(ptr %a, i64 %0) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[A:%.*]], i64 [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[A]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[A]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x ptr> [[TMP1]], <2 x ptr> poison, <2 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> <i64 poison, i64 0>, i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> <i64 poison, i64 0>, i64 [[TMP0]], i64 0
; CHECK-NEXT: br label %[[BB:.*]]
; CHECK: [[BB]]:
; CHECK-NEXT: [[TMP5:%.*]] = or disjoint <2 x i64> [[TMP3]], <i64 1, i64 0>
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr double, <2 x ptr> [[TMP2]], <2 x i64> [[TMP5]]
-; CHECK-NEXT: [[ARRAYIDX17_I28_1:%.*]] = extractelement <2 x ptr> [[TMP6]], i32 0
+; CHECK-NEXT: [[ARRAYIDX17_I28_1:%.*]] = extractelement <2 x ptr> [[TMP6]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> align 8 [[TMP6]], <2 x i1> splat (i1 true), <2 x double> poison)
; CHECK-NEXT: [[TMP8:%.*]] = load <2 x double>, ptr [[A]], align 8
; CHECK-NEXT: [[TMP9:%.*]] = load <2 x double>, ptr [[A]], align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/rotated-strided-loads.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/rotated-strided-loads.ll
index c2daaffdc499f..dcd3d830428de 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/rotated-strided-loads.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/rotated-strided-loads.ll
@@ -6,7 +6,7 @@ define void @constant_stride_widen_rotated1(ptr %pl, i64 %stride, ptr %ps) {
; %gep_l0 = getelementptr inbounds i8, ptr %pl, i64 0
; CHECK-LABEL: define void @constant_stride_widen_rotated1(
; CHECK-SAME: ptr [[PL:%.*]], i64 [[STRIDE:%.*]], ptr [[PS:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x ptr> poison, ptr [[PL]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x ptr> poison, ptr [[PL]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x ptr> [[TMP1]], <8 x ptr> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, <8 x ptr> [[TMP2]], <8 x i64> <i64 1, i64 2, i64 3, i64 100, i64 101, i64 102, i64 103, i64 200>
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, <8 x ptr> [[TMP2]], <8 x i64> <i64 201, i64 202, i64 203, i64 300, i64 301, i64 302, i64 303, i64 400>
@@ -99,7 +99,7 @@ define void @constant_stride_widen_rotatedn_1(ptr %pl, i64 %stride, ptr %ps) {
; %gep_l2 = getelementptr inbounds i8, ptr %pl, i64 2
; CHECK-LABEL: define void @constant_stride_widen_rotatedn_1(
; CHECK-SAME: ptr [[PL:%.*]], i64 [[STRIDE:%.*]], ptr [[PS:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x ptr> poison, ptr [[PL]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x ptr> poison, ptr [[PL]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x ptr> [[TMP1]], <8 x ptr> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, <8 x ptr> [[TMP2]], <8 x i64> <i64 3, i64 100, i64 101, i64 102, i64 103, i64 200, i64 201, i64 202>
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, <8 x ptr> [[TMP2]], <8 x i64> <i64 203, i64 300, i64 301, i64 302, i64 303, i64 400, i64 401, i64 402>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/runtime-strided-stores.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/runtime-strided-stores.ll
index 0d5b1271bc86e..397c45192a526 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/runtime-strided-stores.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/runtime-strided-stores.ll
@@ -15,21 +15,21 @@ define void @runtime_stride(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S5:%.*]] = getelementptr i8, ptr [[GEP_S4]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S6:%.*]] = getelementptr i8, ptr [[GEP_S5]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S7:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 [[STRIDE]]
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i64 0
; CHECK-NEXT: store i8 [[TMP2]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i64 1
; CHECK-NEXT: store i8 [[TMP3]], ptr [[GEP_S1]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S2]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i64 3
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_S3]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i32 4
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i64 4
; CHECK-NEXT: store i8 [[TMP6]], ptr [[GEP_S4]], align 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i32 5
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i64 5
; CHECK-NEXT: store i8 [[TMP7]], ptr [[GEP_S5]], align 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i32 6
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i64 6
; CHECK-NEXT: store i8 [[TMP8]], ptr [[GEP_S6]], align 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i32 7
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i64 7
; CHECK-NEXT: store i8 [[TMP9]], ptr [[GEP_S7]], align 1
; CHECK-NEXT: ret void
;
@@ -93,21 +93,21 @@ define void @runtime_stride_complex_scev(ptr %pl, ptr %ps, i64 %stride, i64 %str
; CHECK-NEXT: [[GEP_SS5:%.*]] = getelementptr i8, ptr [[GEP_S5]], i64 [[STRIDE1]]
; CHECK-NEXT: [[GEP_SS6:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 [[STRIDE1]]
; CHECK-NEXT: [[GEP_SS7:%.*]] = getelementptr i8, ptr [[GEP_S7]], i64 [[STRIDE1]]
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i64 0
; CHECK-NEXT: store i8 [[TMP2]], ptr [[GEP_SS0]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i64 1
; CHECK-NEXT: store i8 [[TMP3]], ptr [[GEP_SS1]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_SS2]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i64 3
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_SS3]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i32 4
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i64 4
; CHECK-NEXT: store i8 [[TMP6]], ptr [[GEP_SS4]], align 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i32 5
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i64 5
; CHECK-NEXT: store i8 [[TMP7]], ptr [[GEP_SS5]], align 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i32 6
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i64 6
; CHECK-NEXT: store i8 [[TMP8]], ptr [[GEP_SS6]], align 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i32 7
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i64 7
; CHECK-NEXT: store i8 [[TMP9]], ptr [[GEP_SS7]], align 1
; CHECK-NEXT: ret void
;
@@ -174,21 +174,21 @@ define void @two_runtime_strides(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S5:%.*]] = getelementptr i8, ptr [[GEP_S4]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S6:%.*]] = getelementptr i8, ptr [[GEP_S5]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S7:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 [[STRIDE]]
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i64 0
; CHECK-NEXT: store i8 [[TMP2]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i64 1
; CHECK-NEXT: store i8 [[TMP3]], ptr [[GEP_S1]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S2]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i64 3
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_S3]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i32 4
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i64 4
; CHECK-NEXT: store i8 [[TMP6]], ptr [[GEP_S4]], align 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i32 5
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i64 5
; CHECK-NEXT: store i8 [[TMP7]], ptr [[GEP_S5]], align 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i32 6
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i64 6
; CHECK-NEXT: store i8 [[TMP8]], ptr [[GEP_S6]], align 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i32 7
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i64 7
; CHECK-NEXT: store i8 [[TMP9]], ptr [[GEP_S7]], align 1
; CHECK-NEXT: ret void
;
@@ -245,21 +245,21 @@ define void @runtime_strides_constant_gap(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S5:%.*]] = getelementptr i8, ptr [[GEP_S4]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S6:%.*]] = getelementptr i8, ptr [[GEP_S5]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S7:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 [[STRIDE]]
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i64 0
; CHECK-NEXT: store i8 [[TMP2]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i64 1
; CHECK-NEXT: store i8 [[TMP3]], ptr [[GEP_S1]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S2]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i64 3
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_S3]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i32 4
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i64 4
; CHECK-NEXT: store i8 [[TMP6]], ptr [[GEP_S4]], align 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i32 5
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i64 5
; CHECK-NEXT: store i8 [[TMP7]], ptr [[GEP_S5]], align 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i32 6
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i64 6
; CHECK-NEXT: store i8 [[TMP8]], ptr [[GEP_S6]], align 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i32 7
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i64 7
; CHECK-NEXT: store i8 [[TMP9]], ptr [[GEP_S7]], align 1
; CHECK-NEXT: ret void
;
@@ -317,21 +317,21 @@ define void @overlapping_strides(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S5:%.*]] = getelementptr i8, ptr [[GEP_S4]], i64 [[STRIDE2]]
; CHECK-NEXT: [[GEP_S6:%.*]] = getelementptr i8, ptr [[GEP_S5]], i64 [[STRIDE2]]
; CHECK-NEXT: [[GEP_S7:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 [[STRIDE2]]
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i64 0
; CHECK-NEXT: store i8 [[TMP2]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i64 1
; CHECK-NEXT: store i8 [[TMP3]], ptr [[GEP_S1]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S2]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i64 3
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_S3]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i32 4
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i64 4
; CHECK-NEXT: store i8 [[TMP6]], ptr [[GEP_S4]], align 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i32 5
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i64 5
; CHECK-NEXT: store i8 [[TMP7]], ptr [[GEP_S5]], align 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i32 6
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i64 6
; CHECK-NEXT: store i8 [[TMP8]], ptr [[GEP_S6]], align 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i32 7
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i64 7
; CHECK-NEXT: store i8 [[TMP9]], ptr [[GEP_S7]], align 1
; CHECK-NEXT: ret void
;
@@ -392,14 +392,14 @@ define void @runtime_stride_unit_stride(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S6:%.*]] = getelementptr i8, ptr [[GEP_S5]], i64 1
; CHECK-NEXT: [[GEP_S7:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[GEP_L3]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i8> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i8> [[TMP2]], i64 0
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i8> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i8> [[TMP2]], i64 1
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_S1]], align 1
-; CHECK-NEXT: [[LOAD2:%.*]] = extractelement <4 x i8> [[TMP2]], i32 2
+; CHECK-NEXT: [[LOAD2:%.*]] = extractelement <4 x i8> [[TMP2]], i64 2
; CHECK-NEXT: store i8 [[LOAD2]], ptr [[GEP_S2]], align 1
; CHECK-NEXT: store <4 x i8> [[TMP1]], ptr [[GEP_S3]], align 1
-; CHECK-NEXT: [[LOAD7:%.*]] = extractelement <4 x i8> [[TMP2]], i32 3
+; CHECK-NEXT: [[LOAD7:%.*]] = extractelement <4 x i8> [[TMP2]], i64 3
; CHECK-NEXT: store i8 [[LOAD7]], ptr [[GEP_S7]], align 1
; CHECK-NEXT: ret void
;
@@ -458,13 +458,13 @@ define void @unit_stride_runtime_stride(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S7:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 [[STRIDE]]
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[GEP_L0]], align 1
; CHECK-NEXT: store <4 x i8> [[TMP1]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i8> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i8> [[TMP2]], i64 0
; CHECK-NEXT: store i8 [[TMP3]], ptr [[GEP_S4]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i8> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i8> [[TMP2]], i64 1
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S5]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i8> [[TMP2]], i32 2
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i8> [[TMP2]], i64 2
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_S6]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i8> [[TMP2]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i8> [[TMP2]], i64 3
; CHECK-NEXT: store i8 [[TMP6]], ptr [[GEP_S7]], align 1
; CHECK-NEXT: ret void
;
@@ -519,13 +519,13 @@ define void @runtime_stride_constant_stride(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S3:%.*]] = getelementptr i8, ptr [[GEP_S2]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S4:%.*]] = getelementptr i8, ptr [[GEP_S3]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr [[GEP_L4]], align 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i8> [[TMP1]], i64 0
; CHECK-NEXT: store i8 [[TMP7]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i8> [[TMP1]], i64 1
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S1]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i8> [[TMP1]], i64 2
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_S2]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i8> [[TMP1]], i64 3
; CHECK-NEXT: store i8 [[TMP6]], ptr [[GEP_S3]], align 1
; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.v4i8.p0.i64(<4 x i8> [[TMP3]], ptr align 1 [[GEP_S4]], i64 2, <4 x i1> splat (i1 true), i32 4)
; CHECK-NEXT: ret void
@@ -585,13 +585,13 @@ define void @constant_stride_runtime_stride(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S7:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 [[STRIDE]]
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[GEP_L0]], align 1
; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.v4i8.p0.i64(<4 x i8> [[TMP1]], ptr align 1 [[GEP_S0]], i64 2, <4 x i1> splat (i1 true), i32 4)
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i8> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i8> [[TMP2]], i64 0
; CHECK-NEXT: store i8 [[TMP3]], ptr [[GEP_S4]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i8> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i8> [[TMP2]], i64 1
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S5]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i8> [[TMP2]], i32 2
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i8> [[TMP2]], i64 2
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_S6]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i8> [[TMP2]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i8> [[TMP2]], i64 3
; CHECK-NEXT: store i8 [[TMP6]], ptr [[GEP_S7]], align 1
; CHECK-NEXT: ret void
;
@@ -647,9 +647,9 @@ define void @overlap(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S2:%.*]] = getelementptr i8, ptr [[GEP_S1]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S3:%.*]] = getelementptr i8, ptr [[GEP_S2]], i64 [[STRIDE]]
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[GEP_L3]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i64 0
; CHECK-NEXT: store i8 [[TMP3]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i8> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i8> [[TMP2]], i64 1
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S1]], align 1
; CHECK-NEXT: store i8 [[LOAD2]], ptr [[GEP_S2]], align 1
; CHECK-NEXT: store <4 x i8> [[TMP1]], ptr [[GEP_S3]], align 1
@@ -703,9 +703,9 @@ define void @overlap_constant_stride(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S2:%.*]] = getelementptr i8, ptr [[GEP_S1]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S3:%.*]] = getelementptr i8, ptr [[GEP_S2]], i64 [[STRIDE]]
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[GEP_L3]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i64 0
; CHECK-NEXT: store i8 [[TMP3]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i8> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i8> [[TMP2]], i64 1
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S1]], align 1
; CHECK-NEXT: store i8 [[LOAD2]], ptr [[GEP_S2]], align 1
; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.v4i8.p0.i64(<4 x i8> [[TMP1]], ptr align 1 [[GEP_S3]], i64 2, <4 x i1> splat (i1 true), i32 4)
@@ -759,21 +759,21 @@ define void @runtime_stride_reorder(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S5:%.*]] = getelementptr i8, ptr [[GEP_S4]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S6:%.*]] = getelementptr i8, ptr [[GEP_S5]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S7:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 [[STRIDE]]
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i8> [[TMP1]], i64 0
; CHECK-NEXT: store i8 [[TMP2]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
; CHECK-NEXT: store i8 [[TMP3]], ptr [[GEP_S1]], align 1
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i64 1
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S2]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i32 4
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i64 4
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_S3]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i32 7
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i64 7
; CHECK-NEXT: store i8 [[TMP6]], ptr [[GEP_S4]], align 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i32 5
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i64 5
; CHECK-NEXT: store i8 [[TMP7]], ptr [[GEP_S5]], align 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i32 6
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i64 6
; CHECK-NEXT: store i8 [[TMP8]], ptr [[GEP_S6]], align 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i64 3
; CHECK-NEXT: store i8 [[TMP9]], ptr [[GEP_S7]], align 1
; CHECK-NEXT: ret void
;
@@ -829,21 +829,21 @@ define void @runtime_stride_unschedulable(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S5:%.*]] = getelementptr i8, ptr [[GEP_S4]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S6:%.*]] = getelementptr i8, ptr [[GEP_S5]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S7:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 [[STRIDE]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i8> [[TMP1]], i64 0
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i8> [[TMP1]], i64 1
; CHECK-NEXT: store i8 [[TMP5]], ptr [[GEP_S6]], align 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
; CHECK-NEXT: store i8 [[TMP9]], ptr [[GEP_S2]], align 1
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i8> [[TMP1]], i64 3
; CHECK-NEXT: store i8 [[TMP10]], ptr [[GEP_S3]], align 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i32 4
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i8> [[TMP1]], i64 4
; CHECK-NEXT: store i8 [[TMP6]], ptr [[GEP_S4]], align 1
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i8> [[TMP1]], i32 5
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i8> [[TMP1]], i64 5
; CHECK-NEXT: store i8 [[TMP11]], ptr [[GEP_S5]], align 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i32 6
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i8> [[TMP1]], i64 6
; CHECK-NEXT: store i8 [[TMP7]], ptr [[GEP_S1]], align 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i32 7
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i8> [[TMP1]], i64 7
; CHECK-NEXT: store i8 [[TMP8]], ptr [[GEP_S7]], align 1
; CHECK-NEXT: ret void
;
@@ -934,18 +934,18 @@ define void @runtime_stride_diff_types(ptr %pl, ptr %ps, i64 %stride) {
; CHECK-NEXT: [[GEP_S5:%.*]] = getelementptr i8, ptr [[GEP_S4]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S6:%.*]] = getelementptr i8, ptr [[GEP_S5]], i64 [[STRIDE]]
; CHECK-NEXT: [[GEP_S7:%.*]] = getelementptr i8, ptr [[GEP_S6]], i64 [[STRIDE]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i8> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i8> [[TMP2]], i64 0
; CHECK-NEXT: store i8 [[TMP4]], ptr [[GEP_S0]], align 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP3]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i16
; CHECK-NEXT: store i16 [[TMP6]], ptr [[GEP_S1]], align 2
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i8> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i8> [[TMP2]], i64 1
; CHECK-NEXT: store i8 [[TMP7]], ptr [[GEP_S2]], align 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i8> [[TMP2]], i32 2
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i8> [[TMP2]], i64 2
; CHECK-NEXT: store i8 [[TMP8]], ptr [[GEP_S3]], align 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i8> [[TMP2]], i32 3
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i8> [[TMP2]], i64 3
; CHECK-NEXT: store i8 [[TMP9]], ptr [[GEP_S4]], align 1
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i8> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i8> [[TMP3]], i64 1
; CHECK-NEXT: [[TMP11:%.*]] = zext i8 [[TMP10]] to i16
; CHECK-NEXT: store i16 [[TMP11]], ptr [[GEP_S5]], align 2
; CHECK-NEXT: store i8 [[LOAD6]], ptr [[GEP_S6]], align 1
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/scatter-vectorize-reversed.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/scatter-vectorize-reversed.ll
index 16423e87d0814..9be2d602a9301 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/scatter-vectorize-reversed.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/scatter-vectorize-reversed.ll
@@ -6,7 +6,7 @@ define <4 x i32> @test(<2 x i64> %v, ptr %p) {
; CHECK-SAME: <2 x i64> [[V:%.*]], ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[V]], <2 x i64> poison, <2 x i32> <i32 1, i32 0>
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr> poison, ptr [[P]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr> poison, ptr [[P]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x ptr> [[TMP0]], <2 x ptr> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i16, <2 x ptr> [[TMP1]], <2 x i64> [[TMP4]]
; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> align 2 [[TMP2]], <2 x i1> splat (i1 true), <2 x i16> poison)
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll
index 063bc0458cadc..f257d34353410 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll
@@ -4,10 +4,10 @@
define i32 @pow2_zero_constant_shift(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
; CHECK-LABEL: define i32 @pow2_zero_constant_shift(
; CHECK-SAME: i16 zeroext [[A:%.*]], i16 zeroext [[B:%.*]], i16 zeroext [[C:%.*]], i16 zeroext [[D:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[B]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[C]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i16> [[TMP3]], i16 [[D]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[B]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[C]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i16> [[TMP3]], i16 [[D]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <4 x i16> [[TMP4]], splat (i16 1)
; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> splat (i32 65536), <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP6]])
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll
index 9701b1f9fc397..af08fe245538a 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll
@@ -6,7 +6,7 @@ define i32 @test(ptr %p) {
; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[D_0:%.*]] = load i16, ptr [[P]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, i16 [[D_0]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, i16 [[D_0]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i16> [[TMP0]], zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i16> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i16> [[TMP0]] to <4 x i32>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/smax-reduction-unsigned-missing-sign.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/smax-reduction-unsigned-missing-sign.ll
index a8efc2622aa80..c9e4f53a113ee 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/smax-reduction-unsigned-missing-sign.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/smax-reduction-unsigned-missing-sign.ll
@@ -5,7 +5,7 @@ define i32 @test(i8 %0) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i8 [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> <i8 poison, i8 0, i8 0, i8 0>, i8 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> <i8 poison, i8 0, i8 0, i8 0>, i8 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i8> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[TMP2]] to <4 x i8>
; CHECK-NEXT: [[TMP5:%.*]] = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> [[TMP3]])
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll
index cf7127e3baf48..be180f30c2ad3 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/smin-reduction-unsigned-missing-sign.ll
@@ -5,7 +5,7 @@ define i32 @test(i8 %0) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i8 [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> <i8 poison, i8 0, i8 0, i8 0>, i8 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> <i8 poison, i8 0, i8 0, i8 0>, i8 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i8> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i1> [[TMP2]] to <4 x i8>
; CHECK-NEXT: [[TMP5:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[TMP3]])
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll
index 8b409851d1eb1..57208cb6788a5 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/smin-signed-zextended.ll
@@ -5,12 +5,12 @@ define <4 x i32> @test(i16 %0, i16 %1) {
; CHECK-LABEL: define <4 x i32> @test(
; CHECK-SAME: i16 [[TMP0:%.*]], i16 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> <i16 poison, i16 poison, i16 poison, i16 0>, i16 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> <i16 poison, i16 poison, i16 poison, i16 0>, i16 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 3>
; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i16> [[TMP3]] to <4 x i32>
; CHECK-NEXT: [[CONV15_I:%.*]] = sext i16 [[TMP0]] to i32
; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i32> [[TMP4]], splat (i32 -1)
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, i32 [[CONV15_I]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, i32 [[CONV15_I]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP5]], <4 x i32> [[TMP7]])
; CHECK-NEXT: [[TMP9:%.*]] = and <4 x i32> [[TMP8]], splat (i32 65535)
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/split-vectorize-parent-for-copyables.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/split-vectorize-parent-for-copyables.ll
index 0eaa3a672446e..17da8cf2929aa 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/split-vectorize-parent-for-copyables.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/split-vectorize-parent-for-copyables.ll
@@ -5,7 +5,7 @@ define i1 @test(i32 %0, i32 %add21.i, i32 %1) #0 {
; CHECK-LABEL: define i1 @test(
; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[ADD21_I:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> zeroinitializer, [[TMP6]]
; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP0]], 1
@@ -13,7 +13,7 @@ define i1 @test(i32 %0, i32 %add21.i, i32 %1) #0 {
; CHECK-NEXT: [[DIFF_CHECK138:%.*]] = icmp ult i32 [[TMP3]], [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP0]], [[TMP0]]
; CHECK-NEXT: [[DIFF_CHECK142:%.*]] = icmp eq i32 [[TMP5]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[ADD21_I]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[ADD21_I]], i64 0
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP9:%.*]] = icmp ugt <4 x i32> [[TMP8]], [[TMP4]]
; CHECK-NEXT: [[DIFF_CHECK149:%.*]] = icmp ult i32 [[TMP3]], [[ADD21_I]]
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
index 4b1f75b324796..b1d045b22a730 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
@@ -11,8 +11,8 @@ define void @test() {
; CHECK-NEXT: br label [[BODY:%.*]]
; CHECK: body:
; CHECK-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> align 4 getelementptr ([[CLASS_A:%.*]], <2 x ptr> splat (ptr null), <2 x i64> <i64 0, i64 1>), <2 x i1> splat (i1 true), <2 x i32> poison)
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1
; CHECK-NEXT: [[CMP_I_I_I_I67_US:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[SPEC_SELECT_I_I68_US:%.*]] = select i1 false, i64 [[SUB4_I_I65_US]], i64 0
; CHECK-NEXT: br label [[BODY]]
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll
index 8fddb2e21e248..7e20cb383384d 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll
@@ -17,8 +17,8 @@ define i16 @test() {
; CHECK-NEXT: [[PPREV_0_I]] = getelementptr [[S]], ptr [[PPREV_062_I]], i64 -1
; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i16> @llvm.masked.load.v3i16.p0(ptr align 2 [[PPREV_0_I]], <3 x i1> <i1 true, i1 false, i1 true>, <3 x i16> poison)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <3 x i16> [[TMP1]], <3 x i16> poison, <2 x i32> <i32 0, i32 2>
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i16> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i16> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i16> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i16> [[TMP2]], i64 1
; CHECK-NEXT: [[CMP_I178:%.*]] = icmp ult i16 [[TMP4]], [[TMP3]]
; CHECK-NEXT: br label [[WHILE_BODY_I]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/strided-unsupported-type.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/strided-unsupported-type.ll
index 0131d173fb70e..a6fd52ef434bd 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/strided-unsupported-type.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/strided-unsupported-type.ll
@@ -29,9 +29,9 @@ define void @stores(ptr noalias %p) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x fp128>, ptr null, align 16
; CHECK-NEXT: [[P1:%.*]] = getelementptr fp128, ptr [[P]], i64 1
-; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x fp128> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x fp128> [[TMP2]], i64 0
; CHECK-NEXT: store fp128 [[TMP0]], ptr [[P1]], align 16
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x fp128> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x fp128> [[TMP2]], i64 1
; CHECK-NEXT: store fp128 [[TMP1]], ptr [[P]], align 16
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll
index 89539739ebcb9..63e0e39f68f34 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll
@@ -5,14 +5,14 @@ define i32 @test(i64 %v1, i64 %v2) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i64 [[V1:%.*]], i64 [[V2:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[V1]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[V2]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[V1]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[V2]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = lshr <2 x i64> [[TMP1]], splat (i64 32)
; CHECK-NEXT: [[TMP5:%.*]] = trunc <2 x i64> [[TMP4]] to <2 x i32>
; CHECK-NEXT: [[TMP6:%.*]] = add <2 x i32> [[TMP2]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i32> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i32> [[TMP6]], i64 1
; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[TMP7]], [[TMP8]]
; CHECK-NEXT: ret i32 [[MUL]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-icmp-signed-op.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-icmp-signed-op.ll
index 550360da216b2..89832abe14a8b 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-icmp-signed-op.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-icmp-signed-op.ll
@@ -6,8 +6,8 @@ define i32 @test(ptr %f, i16 %0) {
; CHECK-SAME: ptr [[F:%.*]], i16 [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[F]], align 2
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, i16 [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, i16 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, i16 [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, i16 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i16> [[TMP3]] to <4 x i32>
; CHECK-NEXT: [[TMP7:%.*]] = sext <4 x i16> [[TMP2]] to <4 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = icmp ule <4 x i32> [[TMP6]], [[TMP7]]
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-node-trunc-with-signed-users.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-node-trunc-with-signed-users.ll
index 21312c28891d5..84b68956e9bfd 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-node-trunc-with-signed-users.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/unsigned-node-trunc-with-signed-users.ll
@@ -12,7 +12,7 @@ define void @test(ptr %p, i16 %load794) {
; CHECK-NEXT: [[TMP4:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32>
; CHECK-NEXT: [[TMP7:%.*]] = sub nsw <2 x i32> [[TMP4]], [[TMP3]]
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <2 x i32> [[TMP7]], splat (i32 3329)
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[ZEXT795]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[ZEXT795]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP12:%.*]] = mul <2 x i32> [[TMP8]], [[TMP6]]
; CHECK-NEXT: [[TMP9:%.*]] = zext <2 x i32> [[TMP12]] to <2 x i64>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
index 473a399cc3303..ed9447cb5b421 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
@@ -340,7 +340,7 @@ entry:
define void @vec3_fpext_cost(ptr %Colour, float %0) {
; NON-POW2-LABEL: @vec3_fpext_cost(
; NON-POW2-NEXT: entry:
-; NON-POW2-NEXT: [[TMP1:%.*]] = insertelement <3 x float> poison, float [[TMP0:%.*]], i32 0
+; NON-POW2-NEXT: [[TMP1:%.*]] = insertelement <3 x float> poison, float [[TMP0:%.*]], i64 0
; NON-POW2-NEXT: [[TMP2:%.*]] = shufflevector <3 x float> [[TMP1]], <3 x float> poison, <3 x i32> zeroinitializer
; NON-POW2-NEXT: [[TMP3:%.*]] = fpext <3 x float> [[TMP2]] to <3 x double>
; NON-POW2-NEXT: [[TMP4:%.*]] = call <3 x double> @llvm.fmuladd.v3f64(<3 x double> [[TMP3]], <3 x double> zeroinitializer, <3 x double> zeroinitializer)
@@ -351,7 +351,7 @@ define void @vec3_fpext_cost(ptr %Colour, float %0) {
; POW2-ONLY-LABEL: @vec3_fpext_cost(
; POW2-ONLY-NEXT: entry:
; POW2-ONLY-NEXT: [[ARRAYIDX80:%.*]] = getelementptr float, ptr [[COLOUR:%.*]], i64 2
-; POW2-ONLY-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0:%.*]], i32 0
+; POW2-ONLY-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0:%.*]], i64 0
; POW2-ONLY-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
; POW2-ONLY-NEXT: [[TMP3:%.*]] = fpext <2 x float> [[TMP2]] to <2 x double>
; POW2-ONLY-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP3]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll
index 81837bdf99eaf..08257a47ce06c 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll
@@ -9,17 +9,17 @@ define i1 @test(i64 %0, i64 %1, ptr %2) {
; CHECK-NEXT: [[GEP45:%.*]] = getelementptr i8, ptr null, i64 [[TMP1]]
; CHECK-NEXT: [[GEP48:%.*]] = getelementptr i8, ptr null, i64 [[TMP0]]
; CHECK-NEXT: [[GEP49:%.*]] = getelementptr i8, ptr null, i64 [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x ptr> poison, ptr [[GEP44]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x ptr> [[TMP3]], ptr [[GEP48]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x ptr> poison, ptr [[GEP45]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x ptr> [[TMP5]], ptr [[GEP49]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x ptr> poison, ptr [[GEP44]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x ptr> [[TMP3]], ptr [[GEP48]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x ptr> poison, ptr [[GEP45]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x ptr> [[TMP5]], ptr [[GEP49]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = icmp ult <2 x ptr> [[TMP4]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP7]], <2 x ptr> [[TMP4]], <2 x ptr> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP2]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x ptr> [[TMP9]], <2 x ptr> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP11:%.*]] = icmp ult <2 x ptr> [[TMP8]], [[TMP10]]
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP11]], i32 0
-; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP11]], i32 1
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP11]], i64 0
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP11]], i64 1
; CHECK-NEXT: [[RES:%.*]] = and i1 [[TMP12]], [[TMP13]]
; CHECK-NEXT: ret i1 [[RES]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/ext-alt-node-must-ext.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/ext-alt-node-must-ext.ll
index d0c50b4dc3e4d..aaa58d30c566a 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/ext-alt-node-must-ext.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/ext-alt-node-must-ext.ll
@@ -8,15 +8,15 @@ define i32 @test(ptr %0, ptr %1) {
; CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 32
; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i64> poison, i64 [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x i64> [[TMP7]], i64 [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i64> poison, i64 [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x i64> [[TMP7]], i64 [[TMP3]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = icmp ne <2 x i64> [[TMP14]], zeroinitializer
; CHECK-NEXT: [[TMP16:%.*]] = sext <2 x i1> [[TMP9]] to <2 x i8>
; CHECK-NEXT: [[TMP11:%.*]] = zext <2 x i1> [[TMP9]] to <2 x i8>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x i8> [[TMP16]], <2 x i8> [[TMP11]], <2 x i32> <i32 0, i32 3>
-; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i8> [[TMP12]], i32 0
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i8> [[TMP12]], i64 0
; CHECK-NEXT: [[DOTNEG:%.*]] = sext i8 [[TMP13]] to i32
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i8> [[TMP12]], i32 1
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i8> [[TMP12]], i64 1
; CHECK-NEXT: [[TMP8:%.*]] = zext i8 [[TMP15]] to i32
; CHECK-NEXT: [[TMP10:%.*]] = add nsw i32 [[DOTNEG]], [[TMP8]]
; CHECK-NEXT: ret i32 [[TMP10]]
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/ext-not-resized-op-resized.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/ext-not-resized-op-resized.ll
index ca93cbd698ada..6d2e2637b7731 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/ext-not-resized-op-resized.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/ext-not-resized-op-resized.ll
@@ -4,11 +4,11 @@
define void @test(i64 %0, i1 %.cmp.i.2, i1 %1, ptr %a) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i64 [[TMP0:%.*]], i1 [[DOTCMP_I_2:%.*]], i1 [[TMP1:%.*]], ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> poison, i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> poison, i64 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i64> [[TMP3]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = lshr <4 x i64> [[TMP4]], splat (i64 63)
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i1> poison, i1 [[DOTCMP_I_2]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i1> [[TMP6]], i1 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i1> poison, i1 [[DOTCMP_I_2]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i1> [[TMP6]], i1 [[TMP1]], i64 1
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i1> [[TMP7]], <4 x i1> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 0>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i1> [[TMP7]], <4 x i1> poison, <4 x i32> <i32 1, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP10:%.*]] = trunc <4 x i64> [[TMP5]] to <4 x i1>
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll
index 3c8e98485ffc1..e66d36e953f31 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll
@@ -4,10 +4,10 @@
define void @test(ptr %a, i8 %0, i16 %b.promoted.i) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[A:%.*]], i8 [[TMP0:%.*]], i16 [[B_PROMOTED_I:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[B_PROMOTED_I]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[B_PROMOTED_I]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP0]] to i16
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[TMP5]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[TMP5]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[TMP6]], <4 x i16> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP4]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> [[TMP8]])
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-trunc.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-trunc.ll
index c9bd95f83d22d..c3e2eda7b6744 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-trunc.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-trunc.ll
@@ -6,7 +6,7 @@ define void @test() {
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 0 to i32
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 0 to i32
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, i32 [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, i32 [[TMP2]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = select i1 false, i32 0, i32 0
; CHECK-NEXT: [[TMP6:%.*]] = select i1 false, i32 0, i32 [[TMP1]]
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
index 6006bf9cb262d..bde56da998c0b 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
@@ -9,22 +9,22 @@ define void @p() {
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr getelementptr inbounds nuw (i8, ptr @c, i64 52), align 4
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0]], i64 2
; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i32> [[TMP0]], splat (i32 1)
; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr getelementptr inbounds nuw (i8, ptr @c, i64 52), align 4
; CHECK-NEXT: [[TMP4:%.*]] = load <7 x i32>, ptr getelementptr inbounds nuw (i8, ptr @c, i64 200), align 4
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <7 x i32> [[TMP4]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <7 x i32> [[TMP4]], i64 3
; CHECK-NEXT: [[OR_1_5_I_3:%.*]] = or i32 [[TMP1]], [[TMP5]]
; CHECK-NEXT: store i32 [[OR_1_5_I_3]], ptr @j.0, align 4
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <7 x i32> [[TMP4]], i32 5
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <7 x i32> [[TMP4]], i64 5
; CHECK-NEXT: [[TMP7:%.*]] = xor <7 x i32> [[TMP4]], splat (i32 1)
; CHECK-NEXT: store <7 x i32> [[TMP7]], ptr getelementptr inbounds nuw (i8, ptr @c, i64 200), align 4
; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr inbounds nuw (i8, ptr @c, i64 252), align 4
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP8]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP8]], i64 1
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP2]]
; CHECK-NEXT: [[OR_1_5_I_5:%.*]] = or i32 [[TMP10]], [[TMP6]]
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> [[TMP8]], i32 2
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> [[TMP8]], i64 2
; CHECK-NEXT: [[OR_1_6_I_5:%.*]] = or i32 [[OR_1_5_I_5]], [[TMP11]]
; CHECK-NEXT: store i32 [[OR_1_6_I_5]], ptr @j.0, align 4
; CHECK-NEXT: [[TMP12:%.*]] = xor <4 x i32> [[TMP8]], splat (i32 1)
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/pr34619.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/pr34619.ll
index 0d1de729bf18c..02f4afd1a46d9 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/pr34619.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/pr34619.ll
@@ -12,10 +12,10 @@ define void @foo() {
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ([4 x [4 x i32]], ptr @bar, i64 0, i64 3, i64 0), align 4
; CHECK-NEXT: [[ARRAYIDX372:%.*]] = getelementptr inbounds [4 x [4 x i32]], ptr @dct_luma, i64 0, i64 3, i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([4 x [4 x i32]], ptr @bar, i64 0, i64 3, i64 2), align 4
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 poison, i32 undef, i32 poison, i32 poison>, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 poison, i32 undef, i32 poison, i32 poison>, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP7]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> <i32 undef, i32 poison, i32 undef, i32 undef>, i32 [[ADD277]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> <i32 undef, i32 poison, i32 undef, i32 undef>, i32 [[ADD277]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[TMP3]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = ashr <4 x i32> [[TMP5]], splat (i32 6)
; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr [[ARRAYIDX372]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fadd.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fadd.ll
index 5f8dfa370dacb..510ad8410bad2 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fadd.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fadd.ll
@@ -46,14 +46,14 @@ define double @fadd_double_8_addends_nonseq(ptr nocapture noundef readonly %x)
; CHECK-NEXT: [[TMP6:%.*]] = load double, ptr [[ARRAYIDX10]], align 8
; CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[X]], i64 14
; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr [[ARRAYIDX12]], align 8
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x double> poison, double [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x double> [[TMP8]], double [[TMP0]], i32 1
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x double> [[TMP9]], double [[TMP2]], i32 2
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x double> [[TMP10]], double [[TMP3]], i32 3
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x double> [[TMP11]], double [[TMP4]], i32 4
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x double> [[TMP12]], double [[TMP5]], i32 5
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x double> [[TMP13]], double [[TMP6]], i32 6
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x double> [[TMP14]], double [[TMP7]], i32 7
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x double> poison, double [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x double> [[TMP8]], double [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x double> [[TMP9]], double [[TMP2]], i64 2
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x double> [[TMP10]], double [[TMP3]], i64 3
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x double> [[TMP11]], double [[TMP4]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x double> [[TMP12]], double [[TMP5]], i64 5
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x double> [[TMP13]], double [[TMP6]], i64 6
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x double> [[TMP14]], double [[TMP7]], i64 7
; CHECK-NEXT: [[TMP16:%.*]] = call reassoc nsz arcp contract afn double @llvm.vector.reduce.fadd.v8f64(double 0.000000e+00, <8 x double> [[TMP15]])
; CHECK-NEXT: ret double [[TMP16]]
;
@@ -118,22 +118,22 @@ define float @fadd_float_16_addends_nonseq(ptr nocapture noundef readonly %x) {
; CHECK-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX26]], align 4
; CHECK-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[X]], i64 30
; CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX28]], align 4
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <16 x float> poison, float [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <16 x float> [[TMP16]], float [[TMP0]], i32 1
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <16 x float> [[TMP17]], float [[TMP2]], i32 2
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <16 x float> [[TMP18]], float [[TMP3]], i32 3
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <16 x float> [[TMP19]], float [[TMP4]], i32 4
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <16 x float> [[TMP20]], float [[TMP5]], i32 5
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x float> [[TMP21]], float [[TMP6]], i32 6
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x float> [[TMP22]], float [[TMP7]], i32 7
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <16 x float> [[TMP23]], float [[TMP8]], i32 8
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x float> [[TMP24]], float [[TMP9]], i32 9
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x float> [[TMP25]], float [[TMP10]], i32 10
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x float> [[TMP26]], float [[TMP11]], i32 11
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x float> [[TMP27]], float [[TMP12]], i32 12
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x float> [[TMP28]], float [[TMP13]], i32 13
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x float> [[TMP29]], float [[TMP14]], i32 14
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x float> [[TMP30]], float [[TMP15]], i32 15
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <16 x float> poison, float [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <16 x float> [[TMP16]], float [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <16 x float> [[TMP17]], float [[TMP2]], i64 2
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <16 x float> [[TMP18]], float [[TMP3]], i64 3
+; CHECK-NEXT: [[TMP20:%.*]] = insertelement <16 x float> [[TMP19]], float [[TMP4]], i64 4
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <16 x float> [[TMP20]], float [[TMP5]], i64 5
+; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x float> [[TMP21]], float [[TMP6]], i64 6
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x float> [[TMP22]], float [[TMP7]], i64 7
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <16 x float> [[TMP23]], float [[TMP8]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x float> [[TMP24]], float [[TMP9]], i64 9
+; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x float> [[TMP25]], float [[TMP10]], i64 10
+; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x float> [[TMP26]], float [[TMP11]], i64 11
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x float> [[TMP27]], float [[TMP12]], i64 12
+; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x float> [[TMP28]], float [[TMP13]], i64 13
+; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x float> [[TMP29]], float [[TMP14]], i64 14
+; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x float> [[TMP30]], float [[TMP15]], i64 15
; CHECK-NEXT: [[TMP32:%.*]] = call reassoc nsz arcp contract afn float @llvm.vector.reduce.fadd.v16f32(float 0.000000e+00, <16 x float> [[TMP31]])
; CHECK-NEXT: ret float [[TMP32]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmin-fmax.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmin-fmax.ll
index 1b05f31cfe4b1..ae41036c73253 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmin-fmax.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmin-fmax.ll
@@ -59,22 +59,22 @@ define double @fmin_double_16_nums_nonseq(ptr nocapture noundef readonly %x) {
; CHECK-NEXT: [[T13:%.*]] = load double, ptr [[G13]], align 4
; CHECK-NEXT: [[T14:%.*]] = load double, ptr [[G14]], align 4
; CHECK-NEXT: [[T15:%.*]] = load double, ptr [[G15]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x double> poison, double [[T1]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x double> [[TMP1]], double [[T0]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x double> [[TMP2]], double [[T2]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x double> [[TMP3]], double [[T3]], i32 3
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x double> [[TMP4]], double [[T4]], i32 4
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x double> [[TMP5]], double [[T5]], i32 5
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x double> [[TMP6]], double [[T6]], i32 6
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x double> [[TMP7]], double [[T7]], i32 7
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x double> [[TMP8]], double [[T8]], i32 8
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x double> [[TMP9]], double [[T9]], i32 9
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x double> [[TMP10]], double [[T10]], i32 10
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x double> [[TMP11]], double [[T11]], i32 11
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x double> [[TMP12]], double [[T12]], i32 12
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x double> [[TMP13]], double [[T13]], i32 13
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x double> [[TMP14]], double [[T14]], i32 14
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <16 x double> [[TMP15]], double [[T15]], i32 15
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x double> poison, double [[T1]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x double> [[TMP1]], double [[T0]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x double> [[TMP2]], double [[T2]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x double> [[TMP3]], double [[T3]], i64 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x double> [[TMP4]], double [[T4]], i64 4
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x double> [[TMP5]], double [[T5]], i64 5
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x double> [[TMP6]], double [[T6]], i64 6
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x double> [[TMP7]], double [[T7]], i64 7
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x double> [[TMP8]], double [[T8]], i64 8
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x double> [[TMP9]], double [[T9]], i64 9
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x double> [[TMP10]], double [[T10]], i64 10
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x double> [[TMP11]], double [[T11]], i64 11
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x double> [[TMP12]], double [[T12]], i64 12
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x double> [[TMP13]], double [[T13]], i64 13
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x double> [[TMP14]], double [[T14]], i64 14
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <16 x double> [[TMP15]], double [[T15]], i64 15
; CHECK-NEXT: [[TMP17:%.*]] = call fast double @llvm.vector.reduce.fmin.v16f64(<16 x double> [[TMP16]])
; CHECK-NEXT: ret double [[TMP17]]
;
@@ -153,18 +153,18 @@ define float @fmin_float_12_nums_nonseq(ptr nocapture noundef readonly %x) {
; CHECK-NEXT: [[T9:%.*]] = load float, ptr [[G9]], align 4
; CHECK-NEXT: [[T10:%.*]] = load float, ptr [[G10]], align 4
; CHECK-NEXT: [[T11:%.*]] = load float, ptr [[G11]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <12 x float> poison, float [[T1]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <12 x float> [[TMP1]], float [[T0]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <12 x float> [[TMP2]], float [[T2]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <12 x float> [[TMP3]], float [[T3]], i32 3
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <12 x float> [[TMP4]], float [[T4]], i32 4
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <12 x float> [[TMP5]], float [[T5]], i32 5
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <12 x float> [[TMP6]], float [[T6]], i32 6
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <12 x float> [[TMP7]], float [[T7]], i32 7
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <12 x float> [[TMP8]], float [[T8]], i32 8
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <12 x float> [[TMP9]], float [[T9]], i32 9
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <12 x float> [[TMP10]], float [[T10]], i32 10
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <12 x float> [[TMP11]], float [[T11]], i32 11
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <12 x float> poison, float [[T1]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <12 x float> [[TMP1]], float [[T0]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <12 x float> [[TMP2]], float [[T2]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <12 x float> [[TMP3]], float [[T3]], i64 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <12 x float> [[TMP4]], float [[T4]], i64 4
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <12 x float> [[TMP5]], float [[T5]], i64 5
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <12 x float> [[TMP6]], float [[T6]], i64 6
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <12 x float> [[TMP7]], float [[T7]], i64 7
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <12 x float> [[TMP8]], float [[T8]], i64 8
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <12 x float> [[TMP9]], float [[T9]], i64 9
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <12 x float> [[TMP10]], float [[T10]], i64 10
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <12 x float> [[TMP11]], float [[T11]], i64 11
; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.vector.reduce.fmin.v12f32(<12 x float> [[TMP12]])
; CHECK-NEXT: ret float [[TMP13]]
;
@@ -259,22 +259,22 @@ define double @fmax_double_16_nums_nonseq(ptr nocapture noundef readonly %x) {
; CHECK-NEXT: [[T13:%.*]] = load double, ptr [[G13]], align 4
; CHECK-NEXT: [[T14:%.*]] = load double, ptr [[G14]], align 4
; CHECK-NEXT: [[T15:%.*]] = load double, ptr [[G15]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x double> poison, double [[T1]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x double> [[TMP1]], double [[T0]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x double> [[TMP2]], double [[T2]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x double> [[TMP3]], double [[T3]], i32 3
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x double> [[TMP4]], double [[T4]], i32 4
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x double> [[TMP5]], double [[T5]], i32 5
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x double> [[TMP6]], double [[T6]], i32 6
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x double> [[TMP7]], double [[T7]], i32 7
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x double> [[TMP8]], double [[T8]], i32 8
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x double> [[TMP9]], double [[T9]], i32 9
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x double> [[TMP10]], double [[T10]], i32 10
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x double> [[TMP11]], double [[T11]], i32 11
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x double> [[TMP12]], double [[T12]], i32 12
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x double> [[TMP13]], double [[T13]], i32 13
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x double> [[TMP14]], double [[T14]], i32 14
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <16 x double> [[TMP15]], double [[T15]], i32 15
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x double> poison, double [[T1]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x double> [[TMP1]], double [[T0]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x double> [[TMP2]], double [[T2]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x double> [[TMP3]], double [[T3]], i64 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x double> [[TMP4]], double [[T4]], i64 4
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x double> [[TMP5]], double [[T5]], i64 5
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x double> [[TMP6]], double [[T6]], i64 6
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x double> [[TMP7]], double [[T7]], i64 7
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x double> [[TMP8]], double [[T8]], i64 8
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <16 x double> [[TMP9]], double [[T9]], i64 9
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x double> [[TMP10]], double [[T10]], i64 10
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x double> [[TMP11]], double [[T11]], i64 11
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <16 x double> [[TMP12]], double [[T12]], i64 12
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <16 x double> [[TMP13]], double [[T13]], i64 13
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <16 x double> [[TMP14]], double [[T14]], i64 14
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <16 x double> [[TMP15]], double [[T15]], i64 15
; CHECK-NEXT: [[TMP17:%.*]] = call fast double @llvm.vector.reduce.fmax.v16f64(<16 x double> [[TMP16]])
; CHECK-NEXT: ret double [[TMP17]]
;
@@ -353,18 +353,18 @@ define float @fmax_float_12_nums_nonseq(ptr nocapture noundef readonly %x) {
; CHECK-NEXT: [[T9:%.*]] = load float, ptr [[G9]], align 4
; CHECK-NEXT: [[T10:%.*]] = load float, ptr [[G10]], align 4
; CHECK-NEXT: [[T11:%.*]] = load float, ptr [[G11]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <12 x float> poison, float [[T1]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <12 x float> [[TMP1]], float [[T0]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <12 x float> [[TMP2]], float [[T2]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <12 x float> [[TMP3]], float [[T3]], i32 3
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <12 x float> [[TMP4]], float [[T4]], i32 4
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <12 x float> [[TMP5]], float [[T5]], i32 5
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <12 x float> [[TMP6]], float [[T6]], i32 6
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <12 x float> [[TMP7]], float [[T7]], i32 7
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <12 x float> [[TMP8]], float [[T8]], i32 8
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <12 x float> [[TMP9]], float [[T9]], i32 9
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <12 x float> [[TMP10]], float [[T10]], i32 10
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <12 x float> [[TMP11]], float [[T11]], i32 11
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <12 x float> poison, float [[T1]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <12 x float> [[TMP1]], float [[T0]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <12 x float> [[TMP2]], float [[T2]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <12 x float> [[TMP3]], float [[T3]], i64 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <12 x float> [[TMP4]], float [[T4]], i64 4
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <12 x float> [[TMP5]], float [[T5]], i64 5
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <12 x float> [[TMP6]], float [[T6]], i64 6
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <12 x float> [[TMP7]], float [[T7]], i64 7
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <12 x float> [[TMP8]], float [[T8]], i64 8
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <12 x float> [[TMP9]], float [[T9]], i64 9
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <12 x float> [[TMP10]], float [[T10]], i64 10
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <12 x float> [[TMP11]], float [[T11]], i64 11
; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.vector.reduce.fmax.v12f32(<12 x float> [[TMP12]])
; CHECK-NEXT: ret float [[TMP13]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmul.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmul.ll
index fbdca10ca6ced..99dae219c17b7 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmul.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/reductions-fmul.ll
@@ -46,14 +46,14 @@ define double @fmul_double_8_factors_nonseq(ptr nocapture noundef readonly %x) {
; CHECK-NEXT: [[TMP6:%.*]] = load double, ptr [[ARRAYIDX10]], align 8
; CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, ptr [[X]], i64 14
; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr [[ARRAYIDX12]], align 8
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x double> poison, double [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x double> [[TMP8]], double [[TMP0]], i32 1
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x double> [[TMP9]], double [[TMP2]], i32 2
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x double> [[TMP10]], double [[TMP3]], i32 3
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x double> [[TMP11]], double [[TMP4]], i32 4
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x double> [[TMP12]], double [[TMP5]], i32 5
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x double> [[TMP13]], double [[TMP6]], i32 6
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x double> [[TMP14]], double [[TMP7]], i32 7
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x double> poison, double [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x double> [[TMP8]], double [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x double> [[TMP9]], double [[TMP2]], i64 2
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x double> [[TMP10]], double [[TMP3]], i64 3
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x double> [[TMP11]], double [[TMP4]], i64 4
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x double> [[TMP12]], double [[TMP5]], i64 5
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x double> [[TMP13]], double [[TMP6]], i64 6
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x double> [[TMP14]], double [[TMP7]], i64 7
; CHECK-NEXT: [[TMP16:%.*]] = call reassoc nsz arcp contract afn double @llvm.vector.reduce.fmul.v8f64(double 1.000000e+00, <8 x double> [[TMP15]])
; CHECK-NEXT: ret double [[TMP16]]
;
@@ -118,22 +118,22 @@ define float @fmul_float_16_factors_nonseq(float noundef %m, ptr nocapture nound
; CHECK-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX26]], align 4
; CHECK-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[X]], i64 30
; CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[ARRAYIDX28]], align 4
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <16 x float> poison, float [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <16 x float> [[TMP16]], float [[TMP0]], i32 1
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <16 x float> [[TMP17]], float [[TMP2]], i32 2
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <16 x float> [[TMP18]], float [[TMP3]], i32 3
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <16 x float> [[TMP19]], float [[TMP4]], i32 4
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <16 x float> [[TMP20]], float [[TMP5]], i32 5
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x float> [[TMP21]], float [[TMP6]], i32 6
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x float> [[TMP22]], float [[TMP7]], i32 7
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <16 x float> [[TMP23]], float [[TMP8]], i32 8
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x float> [[TMP24]], float [[TMP9]], i32 9
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x float> [[TMP25]], float [[TMP10]], i32 10
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x float> [[TMP26]], float [[TMP11]], i32 11
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x float> [[TMP27]], float [[TMP12]], i32 12
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x float> [[TMP28]], float [[TMP13]], i32 13
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x float> [[TMP29]], float [[TMP14]], i32 14
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x float> [[TMP30]], float [[TMP15]], i32 15
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <16 x float> poison, float [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <16 x float> [[TMP16]], float [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <16 x float> [[TMP17]], float [[TMP2]], i64 2
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <16 x float> [[TMP18]], float [[TMP3]], i64 3
+; CHECK-NEXT: [[TMP20:%.*]] = insertelement <16 x float> [[TMP19]], float [[TMP4]], i64 4
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <16 x float> [[TMP20]], float [[TMP5]], i64 5
+; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x float> [[TMP21]], float [[TMP6]], i64 6
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x float> [[TMP22]], float [[TMP7]], i64 7
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <16 x float> [[TMP23]], float [[TMP8]], i64 8
+; CHECK-NEXT: [[TMP25:%.*]] = insertelement <16 x float> [[TMP24]], float [[TMP9]], i64 9
+; CHECK-NEXT: [[TMP26:%.*]] = insertelement <16 x float> [[TMP25]], float [[TMP10]], i64 10
+; CHECK-NEXT: [[TMP27:%.*]] = insertelement <16 x float> [[TMP26]], float [[TMP11]], i64 11
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <16 x float> [[TMP27]], float [[TMP12]], i64 12
+; CHECK-NEXT: [[TMP29:%.*]] = insertelement <16 x float> [[TMP28]], float [[TMP13]], i64 13
+; CHECK-NEXT: [[TMP30:%.*]] = insertelement <16 x float> [[TMP29]], float [[TMP14]], i64 14
+; CHECK-NEXT: [[TMP31:%.*]] = insertelement <16 x float> [[TMP30]], float [[TMP15]], i64 15
; CHECK-NEXT: [[TMP32:%.*]] = call reassoc nsz arcp contract afn float @llvm.vector.reduce.fmul.v16f32(float 1.000000e+00, <16 x float> [[TMP31]])
; CHECK-NEXT: ret float [[TMP32]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/reuse-non-power-of-2-reorder.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/reuse-non-power-of-2-reorder.ll
index 64de6033a4875..e3455eb666432 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/reuse-non-power-of-2-reorder.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/reuse-non-power-of-2-reorder.ll
@@ -5,16 +5,16 @@ define void @test(i32 %0, i64 %1, i32 %2, i32 %3, ptr %4) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[TMP0:%.*]], i64 [[TMP1:%.*]], i32 [[TMP2:%.*]], i32 [[TMP3:%.*]], ptr [[TMP4:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP73:%.*]] = trunc i64 [[TMP1]] to i32
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> poison, i32 [[TMP73]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> poison, i32 [[TMP73]], i64 0
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP98:%.*]] = trunc i64 [[TMP1]] to i32
; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP1]] to i32
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <60 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 [[TMP0]], i32 7
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <60 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 [[TMP0]], i64 7
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <60 x i32> [[TMP11]], <60 x i32> poison, <60 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 7, i32 7, i32 7, i32 7, i32 7>
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <60 x i32> poison, i32 [[TMP3]], i32 1
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <60 x i32> [[TMP13]], i32 [[TMP2]], i32 7
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <60 x i32> [[TMP14]], i32 [[TMP10]], i32 0
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <60 x i32> [[TMP15]], i32 [[TMP98]], i32 6
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <60 x i32> poison, i32 [[TMP3]], i64 1
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <60 x i32> [[TMP13]], i32 [[TMP2]], i64 7
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <60 x i32> [[TMP14]], i32 [[TMP10]], i64 0
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <60 x i32> [[TMP15]], i32 [[TMP98]], i64 6
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <60 x i32> [[TMP16]], <60 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 6, i32 7>
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> poison, <60 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/vec-elt-insertion.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/vec-elt-insertion.ll
index d50f2109298a5..75aa87d744b3c 100644
--- a/llvm/test/Transforms/SLPVectorizer/SystemZ/vec-elt-insertion.ll
+++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/vec-elt-insertion.ll
@@ -14,14 +14,14 @@ define void @fun0(ptr %0, double %1) {
; CHECK-LABEL: define void @fun0(
; CHECK-SAME: ptr [[TMP0:%.*]], double [[TMP1:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: [[TMP3:%.*]] = load double, ptr [[TMP0]], align 8
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> [[TMP4]], double [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> [[TMP4]], double [[TMP3]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x double> [[TMP5]], splat (double 2.000000e+00)
; CHECK-NEXT: [[TMP7:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP6]], <2 x double> [[TMP6]], <2 x double> zeroinitializer)
; CHECK-NEXT: [[TMP8:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP6]], <2 x double> [[TMP6]], <2 x double> [[TMP7]])
; CHECK-NEXT: [[TMP9:%.*]] = call <2 x double> @llvm.sqrt.v2f64(<2 x double> [[TMP8]])
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x double> [[TMP9]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x double> [[TMP9]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x double> [[TMP9]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x double> [[TMP9]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = fadd double [[TMP10]], [[TMP11]]
; CHECK-NEXT: store double [[TMP12]], ptr [[TMP0]], align 8
; CHECK-NEXT: ret void
@@ -50,7 +50,7 @@ define void @fun0(ptr %0, double %1) {
define void @fun1(double %0) {
; CHECK-LABEL: define void @fun1(
; CHECK-SAME: double [[TMP0:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP0]], i64 1
; CHECK-NEXT: br label %[[BB3:.*]]
; CHECK: [[BB3]]:
; CHECK-NEXT: [[TMP4:%.*]] = phi <2 x double> [ <double poison, double undef>, [[TMP1:%.*]] ], [ poison, %[[BB3]] ]
@@ -64,10 +64,10 @@ define void @fun1(double %0) {
; CHECK-NEXT: [[TMP12:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP8]], <2 x double> [[TMP8]], <2 x double> [[TMP11]])
; CHECK-NEXT: [[TMP13:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP9]], <2 x double> [[TMP9]], <2 x double> [[TMP12]])
; CHECK-NEXT: [[TMP14:%.*]] = fcmp olt <2 x double> [[TMP13]], [[TMP2]]
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i1> [[TMP14]], i32 0
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i1> [[TMP14]], i32 1
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i1> [[TMP14]], i64 0
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i1> [[TMP14]], i64 1
; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP15]], [[TMP16]]
-; CHECK-NEXT: [[TMP18]] = insertelement <2 x double> poison, double [[TMP10]], i32 1
+; CHECK-NEXT: [[TMP18]] = insertelement <2 x double> poison, double [[TMP10]], i64 1
; CHECK-NEXT: br label %[[BB3]]
;
; REMARK-LABEL: Function: fun1
diff --git a/llvm/test/Transforms/SLPVectorizer/WebAssembly/or-reduction-zero-test.ll b/llvm/test/Transforms/SLPVectorizer/WebAssembly/or-reduction-zero-test.ll
index b7d0c2694af7f..34ab34d8a2538 100644
--- a/llvm/test/Transforms/SLPVectorizer/WebAssembly/or-reduction-zero-test.ll
+++ b/llvm/test/Transforms/SLPVectorizer/WebAssembly/or-reduction-zero-test.ll
@@ -21,8 +21,8 @@ define i1 @or_reduction_nonzero(ptr %p) {
; CHECK-NEXT: [[TMP13:%.*]] = or <2 x i8> [[TMP3]], [[TMP6]]
; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i8> [[TMP9]], [[TMP12]]
; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i8> [[TMP13]], [[TMP14]]
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i8> [[TMP15]], i32 0
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i8> [[TMP15]], i32 1
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i8> [[TMP15]], i64 0
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i8> [[TMP15]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[TMP16]], [[TMP17]]
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
@@ -98,8 +98,8 @@ define i1 @or_reduction_zero(ptr %p) {
; CHECK-NEXT: [[TMP13:%.*]] = or <2 x i8> [[TMP3]], [[TMP6]]
; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i8> [[TMP9]], [[TMP12]]
; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i8> [[TMP13]], [[TMP14]]
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i8> [[TMP15]], i32 0
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i8> [[TMP15]], i32 1
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i8> [[TMP15]], i64 0
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i8> [[TMP15]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[TMP16]], [[TMP17]]
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[CMP]]
@@ -175,8 +175,8 @@ define i1 @or_reduction_nonzero_multiuse(ptr %p, ptr %out) {
; CHECK-NEXT: [[TMP13:%.*]] = or <2 x i8> [[TMP3]], [[TMP6]]
; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i8> [[TMP9]], [[TMP12]]
; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i8> [[TMP13]], [[TMP14]]
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i8> [[TMP15]], i32 0
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i8> [[TMP15]], i32 1
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i8> [[TMP15]], i64 0
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i8> [[TMP15]], i64 1
; CHECK-NEXT: [[O:%.*]] = or i8 [[TMP16]], [[TMP17]]
; CHECK-NEXT: store i8 [[O]], ptr [[OUT]], align 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[O]], 0
diff --git a/llvm/test/Transforms/SLPVectorizer/WebAssembly/simd-splat-shuffle-cost.ll b/llvm/test/Transforms/SLPVectorizer/WebAssembly/simd-splat-shuffle-cost.ll
index 52732350b6be6..45783900fadd5 100644
--- a/llvm/test/Transforms/SLPVectorizer/WebAssembly/simd-splat-shuffle-cost.ll
+++ b/llvm/test/Transforms/SLPVectorizer/WebAssembly/simd-splat-shuffle-cost.ll
@@ -8,7 +8,7 @@
define void @splat_i8x16(i8 %v, ptr noalias %p) {
; SIMD128-LABEL: @splat_i8x16(
; SIMD128-NEXT: entry:
-; SIMD128-NEXT: [[TMP0:%.*]] = insertelement <16 x i8> poison, i8 [[V:%.*]], i32 0
+; SIMD128-NEXT: [[TMP0:%.*]] = insertelement <16 x i8> poison, i8 [[V:%.*]], i64 0
; SIMD128-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> poison, <16 x i32> zeroinitializer
; SIMD128-NEXT: store <16 x i8> [[TMP1]], ptr [[P:%.*]], align 1
; SIMD128-NEXT: ret void
@@ -86,7 +86,7 @@ entry:
define void @splat_i16x8(i16 %v, ptr noalias %p) {
; SIMD128-LABEL: @splat_i16x8(
; SIMD128-NEXT: entry:
-; SIMD128-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> poison, i16 [[V:%.*]], i32 0
+; SIMD128-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> poison, i16 [[V:%.*]], i64 0
; SIMD128-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <8 x i32> zeroinitializer
; SIMD128-NEXT: store <8 x i16> [[TMP1]], ptr [[P:%.*]], align 1
; SIMD128-NEXT: ret void
@@ -245,7 +245,7 @@ entry:
define void @splat_i32x8(i32 %v, ptr noalias %p) {
; SIMD128-LABEL: @splat_i32x8(
; SIMD128-NEXT: entry:
-; SIMD128-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[V:%.*]], i32 0
+; SIMD128-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[V:%.*]], i64 0
; SIMD128-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[TMP0]], <8 x i32> poison, <8 x i32> zeroinitializer
; SIMD128-NEXT: store <8 x i32> [[TMP1]], ptr [[P:%.*]], align 1
; SIMD128-NEXT: ret void
@@ -349,7 +349,7 @@ entry:
define void @splat_i8x8(i8 %v, ptr noalias %p) {
; SIMD128-LABEL: @splat_i8x8(
; SIMD128-NEXT: entry:
-; SIMD128-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[V:%.*]], i32 0
+; SIMD128-NEXT: [[TMP0:%.*]] = insertelement <8 x i8> poison, i8 [[V:%.*]], i64 0
; SIMD128-NEXT: [[TMP1:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <8 x i32> zeroinitializer
; SIMD128-NEXT: store <8 x i8> [[TMP1]], ptr [[P:%.*]], align 1
; SIMD128-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
index e9aa434dec03d..89c0dd2f26c74 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
@@ -11,8 +11,8 @@ define void @mainTest(ptr %ptr) #0 {
; CHECK-NEXT: [[DUMMY_PHI:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[OP_RDX3:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[PTR]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = mul <4 x i32> [[TMP1]], [[TMP1]]
; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP3]] to i64
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
index 5ebbb76f3d6c3..8319a97958a65 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
@@ -9,12 +9,12 @@ define void @test() #0 {
; CHECK: loop:
; CHECK-NEXT: [[DUMMY_PHI:%.*]] = phi i64 [ 1, [[ENTRY:%.*]] ], [ [[OP_RDX1:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ 2, [[ENTRY]] ], [ [[TMP4:%.*]], [[LOOP]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> poison, i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> poison, i64 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i64> [[TMP2]], <i64 3, i64 2, i64 1, i64 0>
-; CHECK-NEXT: [[TMP4]] = extractelement <4 x i64> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP4]] = extractelement <4 x i64> [[TMP3]], i64 3
; CHECK-NEXT: [[DUMMY_ADD:%.*]] = add i16 0, 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i64 0
; CHECK-NEXT: [[DUMMY_SHL:%.*]] = shl i64 [[TMP5]], 32
; CHECK-NEXT: [[TMP6:%.*]] = add <4 x i64> splat (i64 1), [[TMP3]]
; CHECK-NEXT: [[TMP7:%.*]] = ashr exact <4 x i64> [[TMP6]], splat (i64 32)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
index bc0022253c23b..4cdd3a1851991 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR35777.ll
@@ -9,7 +9,7 @@ define { i64, i64 } @patatino(double %arg) {
; CHECK-NEXT: [[VEC2STRUCT_SLOT:%.*]] = alloca { i64, i64 }, align 16
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr @global, align 16
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr getelementptr inbounds ([6 x double], ptr @global, i64 0, i64 2), align 16
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[ARG:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[ARG:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP0]], [[TMP4]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
index 53a2d51b15afc..ccdf33525d92e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
@@ -14,8 +14,8 @@ define void @Test(i32) {
; CHECK-NEXT: [[OP_RDX:%.*]] = and i32 [[TMP0:%.*]], [[TMP4]]
; CHECK-NEXT: [[OP_RDX1:%.*]] = and i32 [[OP_RDX]], [[LOCAL_8_43_US1]]
; CHECK-NEXT: [[VAL_44]] = add i32 [[LOCAL_8_43_US1]], 14910
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> poison, i32 [[OP_RDX1]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[VAL_44]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> poison, i32 [[OP_RDX1]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[VAL_44]], i64 1
; CHECK-NEXT: [[TMP6]] = shufflevector <8 x i32> [[TMP5]], <8 x i32> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: br label [[LOOP]]
;
@@ -30,8 +30,8 @@ define void @Test(i32) {
; FORCE_REDUCTION-NEXT: [[OP_RDX:%.*]] = and i32 [[TMP0:%.*]], [[TMP4]]
; FORCE_REDUCTION-NEXT: [[VAL_43:%.*]] = and i32 [[OP_RDX]], [[LOCAL_8_43_US1]]
; FORCE_REDUCTION-NEXT: [[VAL_44]] = add i32 [[LOCAL_8_43_US1]], 14910
-; FORCE_REDUCTION-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> poison, i32 [[VAL_43]], i32 0
-; FORCE_REDUCTION-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[VAL_44]], i32 1
+; FORCE_REDUCTION-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> poison, i32 [[VAL_43]], i64 0
+; FORCE_REDUCTION-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[VAL_44]], i64 1
; FORCE_REDUCTION-NEXT: [[TMP6]] = shufflevector <8 x i32> [[TMP5]], <8 x i32> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; FORCE_REDUCTION-NEXT: br label [[LOOP]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
index d7c68004dccb9..d7d2013905215 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
@@ -4,10 +4,10 @@
define void @mainTest(i32 %param, ptr %vals, i32 %len) {
; CHECK-LABEL: @mainTest(
; CHECK-NEXT: bci_15.preheader:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i32> <i32 poison, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>, i32 [[PARAM:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i32> <i32 poison, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>, i32 [[PARAM:%.*]], i64 0
; CHECK-NEXT: br label [[BCI_15:%.*]]
; CHECK: bci_15:
-; CHECK-NEXT: [[LOCAL_0_:%.*]] = phi i32 [ [[OP_RDX:%.*]], [[BCI_15]] ], [ [[PARAM:%.*]], [[BCI_15_PREHEADER:%.*]] ]
+; CHECK-NEXT: [[LOCAL_0_:%.*]] = phi i32 [ [[OP_RDX:%.*]], [[BCI_15]] ], [ [[PARAM]], [[BCI_15_PREHEADER:%.*]] ]
; CHECK-NEXT: [[LOCAL_4_:%.*]] = phi i32 [ [[V44:%.*]], [[BCI_15]] ], [ 31, [[BCI_15_PREHEADER]] ]
; CHECK-NEXT: [[TMP2:%.*]] = phi <16 x i32> [ [[TMP6:%.*]], [[BCI_15]] ], [ [[TMP0]], [[BCI_15_PREHEADER]] ]
; CHECK-NEXT: [[TMP3:%.*]] = add <16 x i32> [[TMP2]], <i32 -1, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -15,8 +15,8 @@ define void @mainTest(i32 %param, ptr %vals, i32 %len) {
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> [[TMP3]])
; CHECK-NEXT: [[OP_RDX]] = and i32 [[TMP4]], [[LOCAL_4_]]
; CHECK-NEXT: [[V44]] = add i32 [[LOCAL_4_]], 16
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i32> poison, i32 [[OP_RDX]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x i32> [[TMP7]], i32 [[V44]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i32> poison, i32 [[OP_RDX]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x i32> [[TMP7]], i32 [[V44]], i64 1
; CHECK-NEXT: [[TMP6]] = shufflevector <16 x i32> [[TMP5]], <16 x i32> poison, <16 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: br i1 true, label [[BCI_15]], label [[LOOPEXIT:%.*]]
; CHECK: loopexit:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/add-sub-nsw-intmin.ll b/llvm/test/Transforms/SLPVectorizer/X86/add-sub-nsw-intmin.ll
index f9782dc7785ff..5e5aef46f78f3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/add-sub-nsw-intmin.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/add-sub-nsw-intmin.ll
@@ -6,8 +6,8 @@
; not be nsw.
define void @add_intmin_converted_to_sub(ptr %p, i32 %x, i32 %y) {
; CHECK-LABEL: @add_intmin_converted_to_sub(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = sub <2 x i32> [[TMP2]], <i32 -2147483648, i32 7>
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr [[P:%.*]], align 4
; CHECK-NEXT: ret void
@@ -24,8 +24,8 @@ define void @add_intmin_converted_to_sub(ptr %p, i32 %x, i32 %y) {
; be dropped.
define void @sub_intmin_converted_to_add(ptr %p, i32 %x, i32 %y) {
; CHECK-LABEL: @sub_intmin_converted_to_add(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP2]], <i32 -2147483648, i32 7>
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr [[P:%.*]], align 4
; CHECK-NEXT: ret void
@@ -41,8 +41,8 @@ define void @sub_intmin_converted_to_add(ptr %p, i32 %x, i32 %y) {
; The negated constant is not INT_MIN, so the conversion preserves nsw.
define void @keep_nsw_non_intmin(ptr %p, i32 %x, i32 %y) {
; CHECK-LABEL: @keep_nsw_non_intmin(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = sub nsw <2 x i32> [[TMP2]], <i32 -5, i32 7>
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr [[P:%.*]], align 4
; CHECK-NEXT: ret void
@@ -58,8 +58,8 @@ define void @keep_nsw_non_intmin(ptr %p, i32 %x, i32 %y) {
; The INT_MIN lane keeps its own opcode (no conversion), so nsw stays valid.
define void @keep_nsw_same_opcode(ptr %p, i32 %x, i32 %y) {
; CHECK-LABEL: @keep_nsw_same_opcode(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i32> [[TMP2]], <i32 -2147483648, i32 7>
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr [[P:%.*]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
index f00b846bf4f5b..7a1d47f879ebf 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
@@ -5,8 +5,8 @@ define i16 @test(i16 %call37) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CALL:%.*]] = load i16, ptr undef, align 2
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> <i16 poison, i16 0, i16 0, i16 poison, i16 poison, i16 0, i16 poison, i16 0>, i16 [[CALL37:%.*]], i32 3
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[CALL]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> <i16 poison, i16 0, i16 0, i16 poison, i16 poison, i16 0, i16 poison, i16 0>, i16 [[CALL37:%.*]], i64 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[CALL]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 3, i32 7>
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <8 x i16> [[SHUFFLE]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <8 x i16> [[SHUFFLE]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
index 174be55bd7b0a..b126083d9b0f8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
@@ -592,7 +592,7 @@ define <8 x i32> @sdiv_v8i32_undefs(<8 x i32> %a) {
define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
; SSE-LABEL: @add_sub_v8i32_splat(
; SSE-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; SSE-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i32 0
+; SSE-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i64 0
; SSE-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; SSE-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMP1]], [[TMP3]]
; SSE-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -604,7 +604,7 @@ define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
;
; SLM-LABEL: @add_sub_v8i32_splat(
; SLM-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; SLM-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i32 0
+; SLM-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i64 0
; SLM-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; SLM-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMP1]], [[TMP3]]
; SLM-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -615,7 +615,7 @@ define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
; SLM-NEXT: ret <8 x i32> [[TMP7]]
;
; AVX1-LABEL: @add_sub_v8i32_splat(
-; AVX1-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i32 0
+; AVX1-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i64 0
; AVX1-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer
; AVX1-NEXT: [[TMP3:%.*]] = add <8 x i32> [[TMP2]], [[A:%.*]]
; AVX1-NEXT: [[TMP4:%.*]] = sub <8 x i32> [[TMP2]], [[A]]
@@ -623,7 +623,7 @@ define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
; AVX1-NEXT: ret <8 x i32> [[TMP5]]
;
; AVX2-LABEL: @add_sub_v8i32_splat(
-; AVX2-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i32 0
+; AVX2-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i64 0
; AVX2-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer
; AVX2-NEXT: [[TMP3:%.*]] = add <8 x i32> [[TMP2]], [[A:%.*]]
; AVX2-NEXT: [[TMP4:%.*]] = sub <8 x i32> [[TMP2]], [[A]]
@@ -631,7 +631,7 @@ define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
; AVX2-NEXT: ret <8 x i32> [[TMP5]]
;
; AVX512-LABEL: @add_sub_v8i32_splat(
-; AVX512-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i32 0
+; AVX512-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i64 0
; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer
; AVX512-NEXT: [[TMP3:%.*]] = add <8 x i32> [[TMP2]], [[A:%.*]]
; AVX512-NEXT: [[TMP4:%.*]] = sub <8 x i32> [[TMP2]], [[A]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
index 8a5e278e2b03a..3dc47e7a362e5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
@@ -592,7 +592,7 @@ define <8 x i32> @sdiv_v8i32_undefs(<8 x i32> %a) {
define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
; SSE-LABEL: @add_sub_v8i32_splat(
; SSE-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; SSE-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i32 0
+; SSE-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i64 0
; SSE-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; SSE-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMP1]], [[TMP3]]
; SSE-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -604,7 +604,7 @@ define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
;
; SLM-LABEL: @add_sub_v8i32_splat(
; SLM-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; SLM-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i32 0
+; SLM-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i64 0
; SLM-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; SLM-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMP1]], [[TMP3]]
; SLM-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -615,7 +615,7 @@ define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
; SLM-NEXT: ret <8 x i32> [[TMP7]]
;
; AVX1-LABEL: @add_sub_v8i32_splat(
-; AVX1-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i32 0
+; AVX1-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i64 0
; AVX1-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer
; AVX1-NEXT: [[TMP3:%.*]] = add <8 x i32> [[TMP2]], [[A:%.*]]
; AVX1-NEXT: [[TMP4:%.*]] = sub <8 x i32> [[TMP2]], [[A]]
@@ -623,7 +623,7 @@ define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
; AVX1-NEXT: ret <8 x i32> [[TMP5]]
;
; AVX2-LABEL: @add_sub_v8i32_splat(
-; AVX2-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i32 0
+; AVX2-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i64 0
; AVX2-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer
; AVX2-NEXT: [[TMP3:%.*]] = add <8 x i32> [[TMP2]], [[A:%.*]]
; AVX2-NEXT: [[TMP4:%.*]] = sub <8 x i32> [[TMP2]], [[A]]
@@ -631,7 +631,7 @@ define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
; AVX2-NEXT: ret <8 x i32> [[TMP5]]
;
; AVX512-LABEL: @add_sub_v8i32_splat(
-; AVX512-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i32 0
+; AVX512-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[B:%.*]], i64 0
; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer
; AVX512-NEXT: [[TMP3:%.*]] = add <8 x i32> [[TMP2]], [[A:%.*]]
; AVX512-NEXT: [[TMP4:%.*]] = sub <8 x i32> [[TMP2]], [[A]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-strict-bitwidth-than-main.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-strict-bitwidth-than-main.ll
index 959b2350d9d78..161285e398d73 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-strict-bitwidth-than-main.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-opcode-strict-bitwidth-than-main.ll
@@ -5,13 +5,13 @@ define float @test(i8 %0) {
; CHECK-LABEL: define float @test(
; CHECK-SAME: i8 [[TMP0:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> <i8 poison, i8 0>, i8 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> <i8 poison, i8 0>, i8 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = mul <2 x i32> [[TMP2]], <i32 2, i32 27>
; CHECK-NEXT: [[TMP4:%.*]] = lshr <2 x i32> [[TMP2]], <i32 2, i32 27>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> <i32 0, i32 3>
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP5]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP5]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP5]], i64 1
; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: switch i32 [[TMP8]], label %[[EXIT:.*]] [
; CHECK-NEXT: i32 0, label %[[EXIT]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll b/llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll
index d3eaaa850711c..11782c92afeb9 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/ashr-main-opcode-copyables.ll
@@ -6,8 +6,8 @@ define void @test_main_opcode(ptr %dst, i32 %x, i32 %y) {
; CHECK-LABEL: define void @test_main_opcode(
; CHECK-SAME: ptr [[DST:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[Y]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[Y]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[TMP2]], <i32 1, i32 2, i32 0, i32 0>
; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr [[DST]], align 4
@@ -35,8 +35,8 @@ define void @test_minbitwidth_trunc(ptr %dst, ptr %src) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[SRC]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[SRC]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[TMP1]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP5:%.*]] = ashr <4 x i32> [[TMP4]], <i32 8, i32 8, i32 0, i32 0>
; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[TMP5]] to <4 x i16>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll b/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
index 8978d4273f305..45d3405417b0e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
@@ -559,7 +559,7 @@ define void @PR47450(ptr nocapture readonly %p) {
; CHECK-NEXT: [[X:%.*]] = load i16, ptr [[P:%.*]], align 2
; CHECK-NEXT: [[Z:%.*]] = zext i16 [[X]] to i32
; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i32 [[Z]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[S]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[S]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr @output, align 16
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll b/llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
index a39e602e2da71..30407befc625f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
@@ -8,7 +8,7 @@ define i32 @foo(ptr nocapture %A, i32 %n) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CALL:%.*]] = tail call i32 (...) @bar()
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> [[SHUFFLE]], <i32 5, i32 9, i32 8, i32 10>
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], splat (i32 9)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
index c2bd9e648e4fd..e2a7966703c9d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
@@ -86,8 +86,8 @@ define i8 @j(<4 x i8> %x, <4 x i8> %y) {
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[Y]], <2 x i32> <i32 3, i32 6>
; CHECK-NEXT: [[TMP4:%.*]] = mul <2 x i8> [[TMP3]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i8> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[TMP5]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[TMP5]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP5]], i64 1
; CHECK-NEXT: [[TMP8:%.*]] = sdiv i8 [[TMP6]], [[TMP7]]
; CHECK-NEXT: ret i8 [[TMP8]]
;
@@ -113,8 +113,8 @@ define i8 @k(<4 x i8> %x) {
; CHECK-NEXT: [[TMP4:%.*]] = mul <2 x i8> [[TMP3]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i8> [[TMP4]], <2 x i8> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP6:%.*]] = add <2 x i8> [[TMP10]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i8> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i8> [[TMP6]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = sdiv i8 [[TMP7]], [[TMP8]]
; CHECK-NEXT: ret i8 [[TMP9]]
;
@@ -142,8 +142,8 @@ define i8 @k_bb(<4 x i8> %x) {
; CHECK-NEXT: [[TMP4:%.*]] = mul <2 x i8> [[TMP3]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i8> [[TMP4]], <2 x i8> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP6:%.*]] = add <2 x i8> [[TMP10]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i8> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i8> [[TMP6]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = sdiv i8 [[TMP7]], [[TMP8]]
; CHECK-NEXT: ret i8 [[TMP9]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
index cdaede4fc2143..397d70dfc2455 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
@@ -41,7 +41,7 @@ define <4 x i8> @h_undef(<4 x i8> %x, <4 x i8> %y) {
; CHECK-LABEL: @h_undef(
; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x i8> [[X:%.*]], i32 3
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> undef, <4 x i8> [[Y:%.*]], <4 x i32> <i32 0, i32 poison, i32 5, i32 6>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[X3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[X3]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i8> [[TMP4]], [[TMP4]]
; CHECK-NEXT: ret <4 x i8> [[TMP3]]
;
@@ -88,8 +88,8 @@ define i8 @j(<4 x i8> %x, <4 x i8> %y) {
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[Y]], <2 x i32> <i32 3, i32 6>
; CHECK-NEXT: [[TMP4:%.*]] = mul <2 x i8> [[TMP3]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i8> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[TMP5]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[TMP5]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP5]], i64 1
; CHECK-NEXT: [[TMP8:%.*]] = sdiv i8 [[TMP6]], [[TMP7]]
; CHECK-NEXT: ret i8 [[TMP8]]
;
@@ -115,8 +115,8 @@ define i8 @k(<4 x i8> %x) {
; CHECK-NEXT: [[TMP4:%.*]] = mul <2 x i8> [[TMP3]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i8> [[TMP4]], <2 x i8> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP6:%.*]] = add <2 x i8> [[TMP10]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i8> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i8> [[TMP6]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = sdiv i8 [[TMP7]], [[TMP8]]
; CHECK-NEXT: ret i8 [[TMP9]]
;
@@ -144,8 +144,8 @@ define i8 @k_bb(<4 x i8> %x) {
; CHECK-NEXT: [[TMP4:%.*]] = mul <2 x i8> [[TMP3]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i8> [[TMP4]], <2 x i8> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP6:%.*]] = add <2 x i8> [[TMP10]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i8> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i8> [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i8> [[TMP6]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = sdiv i8 [[TMP7]], [[TMP8]]
; CHECK-NEXT: ret i8 [[TMP9]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/broadcast-load-cost.ll b/llvm/test/Transforms/SLPVectorizer/X86/broadcast-load-cost.ll
index 6ee5fc8adef27..2c9c55b3acacc 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/broadcast-load-cost.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/broadcast-load-cost.ll
@@ -23,10 +23,10 @@ define void @bcast_v2f64_load(ptr %A, double %y, double %z, ptr %S) {
; CHECK-LABEL: define void @bcast_v2f64_load(
; CHECK-SAME: ptr [[A:%.*]], double [[Y:%.*]], double [[Z:%.*]], ptr [[S:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[X:%.*]] = load double, ptr [[A]], align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[X]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[X]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[Y]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[Z]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[Y]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[Z]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP2]], [[TMP4]]
; CHECK-NEXT: store <2 x double> [[TMP5]], ptr [[S]], align 8
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/broadcast.ll b/llvm/test/Transforms/SLPVectorizer/X86/broadcast.ll
index c76bf1500c46e..0e3d51b88e4aa 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/broadcast.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/broadcast.ll
@@ -17,9 +17,9 @@ define void @bcast_vals(ptr %A, ptr %B, ptr %S) {
; CHECK-NEXT: [[B0:%.*]] = load i64, ptr [[B:%.*]], align 8
; CHECK-NEXT: [[V1:%.*]] = sub i64 [[A0]], 1
; CHECK-NEXT: [[V2:%.*]] = sub i64 [[B0]], 1
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[V1]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[V1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[TMP0]], <4 x i64> poison, <4 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> poison, i64 [[V2]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> poison, i64 [[V2]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i64> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <4 x i64> [[TMP4]], ptr [[S:%.*]], align 8
@@ -65,12 +65,12 @@ define void @bcast_vals2(ptr %A, ptr %B, ptr %C, ptr %D, ptr %E, ptr %S) {
; CHECK-NEXT: [[D0:%.*]] = load i16, ptr [[D:%.*]], align 8
; CHECK-NEXT: [[E0:%.*]] = load i16, ptr [[E:%.*]], align 8
; CHECK-NEXT: [[V1:%.*]] = sext i16 [[A0]] to i32
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[B0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[C0]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[E0]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[D0]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[B0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[C0]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[E0]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[D0]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i16> [[TMP3]] to <4 x i32>
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[V1]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[V1]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = add <4 x i32> [[TMP6]], [[TMP4]]
; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr [[S:%.*]], align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/broadcast_long.ll b/llvm/test/Transforms/SLPVectorizer/X86/broadcast_long.ll
index 5f14cea1d6164..18490fe1884e2 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/broadcast_long.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/broadcast_long.ll
@@ -16,7 +16,7 @@ define void @bcast_long(ptr %A, ptr %S) {
; CHECK-LABEL: @bcast_long(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A0:%.*]] = load i32, ptr [[A:%.*]], align 8
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[A0]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[A0]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i32> [[TMP0]], <8 x i32> poison, <8 x i32> <i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0>
; CHECK-NEXT: [[TMP1:%.*]] = freeze <8 x i32> [[SHUFFLE]]
; CHECK-NEXT: store <8 x i32> [[TMP1]], ptr [[S:%.*]], align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
index da6a399370613..a90ac50a37a5a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-reused-with-bv-subvector.ll
@@ -4,7 +4,7 @@
define void @test(ptr %0, i64 %1, i64 %2) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[TMP0:%.*]], i64 [[TMP1:%.*]], i64 [[TMP2:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP0]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x ptr> [[TMP4]], <4 x ptr> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint <4 x ptr> [[TMP5]] to <4 x i64>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <8 x i32> <i32 0, i32 0, i32 1, i32 2, i32 2, i32 1, i32 3, i32 1>
@@ -13,8 +13,8 @@ define void @test(ptr %0, i64 %1, i64 %2) {
; CHECK: [[_PREHEADER_LR_PH:.*:]]
; CHECK-NEXT: br [[DOTPREHEADER_US_US_PREHEADER:label %.*]]
; CHECK: [[_PREHEADER_US_US_PREHEADER:.*:]]
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i64> poison, i64 [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i64> [[TMP9]], i64 [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i64> poison, i64 [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i64> [[TMP9]], i64 [[TMP2]], i64 1
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <8 x i64> [[TMP10]], <8 x i64> poison, <8 x i32> <i32 0, i32 1, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <4 x i64> [[TMP16]], <4 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <8 x i64> [[TMP11]], <8 x i64> [[TMP17]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-same-lane-insert.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-same-lane-insert.ll
index 6077c376251ef..d65f9e8cef3ae 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-same-lane-insert.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-same-lane-insert.ll
@@ -7,8 +7,8 @@ define void @test() {
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr undef, align 4
; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x float> [[TMP2]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = fcmp olt float [[TMP6]], [[TMP5]]
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x float> zeroinitializer, float 0.000000e+00, i64 0
; CHECK-NEXT: store <2 x float> zeroinitializer, ptr null, align 4
@@ -40,8 +40,8 @@ define void @test1() {
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr undef, align 4
; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x float> [[TMP2]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = fcmp olt float [[TMP6]], [[TMP5]]
; CHECK-NEXT: store <2 x float> [[TMP3]], ptr null, align 4
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP2]], <2 x i32> <i32 0, i32 3>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
index c791a07993440..d7f7ef65239f7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-schedule-for-subvector.ll
@@ -10,7 +10,7 @@ define void @test() {
; CHECK-NEXT: store ptr addrspace(1) null, ptr addrspace(1) [[GETELEMENTPTR]], align 8
; CHECK-NEXT: store volatile i32 0, ptr addrspace(1) null, align 4
; CHECK-NEXT: [[CALL:%.*]] = call i32 null(<2 x double> zeroinitializer)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 poison>, i32 [[CALL]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 poison>, i32 [[CALL]], i64 3
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <4 x i32> [[TMP2]], zeroinitializer
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle-with-root.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle-with-root.ll
index d9ce53a86f32d..20a09d800cecf 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle-with-root.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle-with-root.ll
@@ -5,7 +5,7 @@ define void @test(i16 %arg) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i16 [[ARG:%.*]]) {
; CHECK-NEXT: [[BB:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i16> <i16 0, i16 poison>, i16 [[ARG]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i16> <i16 0, i16 poison>, i16 [[ARG]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = sitofp <2 x i16> [[TMP0]] to <2 x float>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> <float -0.000000e+00, float poison, float poison, float poison>, <4 x i32> <i32 4, i32 1, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle.ll
index 9d0c980ac98a1..a586a4d25a053 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-shuffle.ll
@@ -6,15 +6,15 @@ define void @b(float %a, ptr %b) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[A:%.*]], 2.000000e+00
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A]], 1.000000e+00
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[ADD]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[MUL]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[ADD]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[MUL]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = fneg <2 x float> [[TMP1]]
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> poison, float [[MUL]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> poison, float [[MUL]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x float> [[TMP7]], <4 x float> [[TMP10]], <4 x i32> <i32 0, i32 4, i32 5, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP11]], float [[ADD]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP11]], float [[ADD]], i64 3
; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP2]], <4 x float> zeroinitializer, <4 x float> zeroinitializer)
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> <float poison, float 2.000000e+00, float poison, float poison>, float [[A]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> <float poison, float 2.000000e+00, float poison, float poison>, float [[A]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x float> [[TMP8]], <4 x float> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT: [[TMP4:%.*]] = fmul <4 x float> [[TMP3]], [[TMP9]]
; CHECK-NEXT: [[TMP5:%.*]] = fdiv <4 x float> [[TMP4]], zeroinitializer
@@ -53,7 +53,7 @@ declare float @llvm.fmuladd.f32(float, float, float)
define void @test(float %a) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[A:%.*]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x float> [[TMP0]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-store-chains.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-store-chains.ll
index ad55b6dd445c3..5d55ef9dadd81 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-store-chains.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-store-chains.ll
@@ -11,14 +11,14 @@ define void @buildvector_store_middle(ptr %p, float %a0, float %a1, float %a2, f
; CHECK-LABEL: define void @buildvector_store_middle(
; CHECK-SAME: ptr [[P:%.*]], float [[A0:%.*]], float [[A1:%.*]], float [[A2:%.*]], float [[A3:%.*]], float [[A4:%.*]], float [[A5:%.*]], float [[A6:%.*]], float [[A7:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[A0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[A1]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[A0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[A1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x float> [[TMP1]], splat (float 1.000000e+00)
; CHECK-NEXT: [[V2:%.*]] = fadd float [[A2]], 1.000000e+00
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[A3]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[A4]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[A5]], i32 2
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[A6]], i32 3
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[A3]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[A4]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[A5]], i64 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[A6]], i64 3
; CHECK-NEXT: [[TMP7:%.*]] = fadd <4 x float> [[TMP6]], splat (float 1.000000e+00)
; CHECK-NEXT: [[V7:%.*]] = fadd float [[A7]], 1.000000e+00
; CHECK-NEXT: store <2 x float> [[TMP2]], ptr [[P]], align 4
@@ -59,15 +59,15 @@ define void @buildvector_store_start(ptr %p, float %a0, float %a1, float %a2, fl
; CHECK-LABEL: define void @buildvector_store_start(
; CHECK-SAME: ptr [[P:%.*]], float [[A0:%.*]], float [[A1:%.*]], float [[A2:%.*]], float [[A3:%.*]], float [[A4:%.*]], float [[A5:%.*]], float [[A6:%.*]], float [[A7:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[A0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[A1]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A2]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[A3]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[A0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[A1]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A2]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[A3]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = fadd <4 x float> [[TMP3]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> poison, float [[A4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[A5]], i32 1
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[TMP6]], float [[A6]], i32 2
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[A7]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> poison, float [[A4]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[A5]], i64 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[TMP6]], float [[A6]], i64 2
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[A7]], i64 3
; CHECK-NEXT: [[TMP9:%.*]] = fadd <4 x float> [[TMP8]], splat (float 1.000000e+00)
; CHECK-NEXT: store <4 x float> [[TMP4]], ptr [[P]], align 4
; CHECK-NEXT: [[P4:%.*]] = getelementptr inbounds float, ptr [[P]], i64 4
@@ -103,15 +103,15 @@ define void @buildvector_store_end(ptr %p, float %a0, float %a1, float %a2, floa
; CHECK-LABEL: define void @buildvector_store_end(
; CHECK-SAME: ptr [[P:%.*]], float [[A0:%.*]], float [[A1:%.*]], float [[A2:%.*]], float [[A3:%.*]], float [[A4:%.*]], float [[A5:%.*]], float [[A6:%.*]], float [[A7:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[A0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[A1]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A2]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[A3]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[A0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[A1]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A2]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[A3]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = fadd <4 x float> [[TMP3]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> poison, float [[A4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[A5]], i32 1
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[TMP6]], float [[A6]], i32 2
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[A7]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> poison, float [[A4]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[A5]], i64 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[TMP6]], float [[A6]], i64 2
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[A7]], i64 3
; CHECK-NEXT: [[TMP9:%.*]] = fadd <4 x float> [[TMP8]], splat (float 1.000000e+00)
; CHECK-NEXT: store <4 x float> [[TMP4]], ptr [[P]], align 4
; CHECK-NEXT: [[P4:%.*]] = getelementptr inbounds float, ptr [[P]], i64 4
@@ -147,14 +147,14 @@ define void @buildvector_store_duplicate_offset(ptr %p, float %a0, float %a1, fl
; CHECK-LABEL: define void @buildvector_store_duplicate_offset(
; CHECK-SAME: ptr [[P:%.*]], float [[A0:%.*]], float [[A1:%.*]], float [[A2:%.*]], float [[A3:%.*]], float [[A4:%.*]], float [[A5:%.*]], float [[A6:%.*]], float [[A7:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[A0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[A1]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[A0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[A1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x float> [[TMP1]], splat (float 1.000000e+00)
; CHECK-NEXT: [[V2:%.*]] = fadd float [[A2]], 1.000000e+00
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[A3]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[A4]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[A5]], i32 2
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[A6]], i32 3
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[A3]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[A4]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[A5]], i64 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[A6]], i64 3
; CHECK-NEXT: [[TMP7:%.*]] = fadd <4 x float> [[TMP6]], splat (float 1.000000e+00)
; CHECK-NEXT: [[V7:%.*]] = fadd float [[A7]], 1.000000e+00
; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds float, ptr [[P]], i64 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
index 579239bc659bd..f46a2428ce6ee 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvector-with-reuses.ll
@@ -11,12 +11,12 @@ define <4 x double> @test(ptr %ia, ptr %ib, ptr %ic, ptr %id, ptr %ie, ptr %x) {
; CHECK-NEXT: [[I4277:%.*]] = load double, ptr [[IE]], align 8
; CHECK-NEXT: [[I4326:%.*]] = load <4 x double>, ptr [[X]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[I4326]], <4 x double> poison, <2 x i32> <i32 0, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[I4275]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[I4275]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> poison, double [[I4238]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x double> [[TMP4]], double [[I4252]], i32 1
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x double> [[TMP5]], double [[I4264]], i32 2
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x double> [[TMP6]], double [[I4277]], i32 3
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> poison, double [[I4238]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x double> [[TMP4]], double [[I4252]], i64 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x double> [[TMP5]], double [[I4264]], i64 2
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x double> [[TMP6]], double [[I4277]], i64 3
; CHECK-NEXT: [[TMP8:%.*]] = fmul fast <4 x double> [[TMP3]], [[TMP7]]
; CHECK-NEXT: ret <4 x double> [[TMP8]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvectors-parent-phi-nodes.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvectors-parent-phi-nodes.ll
index 6e85c44711acd..2a4da7f834434 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/buildvectors-parent-phi-nodes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvectors-parent-phi-nodes.ll
@@ -5,9 +5,9 @@ define void @test(ptr %0, float %1) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[TMP0]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP3]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP3]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label %[[BB5:.*]]
; CHECK: [[BB5]]:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/buildvectors-with-same-parents.ll b/llvm/test/Transforms/SLPVectorizer/X86/buildvectors-with-same-parents.ll
index daf9501f1b4ea..e09031fda0ed4 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/buildvectors-with-same-parents.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/buildvectors-with-same-parents.ll
@@ -5,7 +5,7 @@ define i32 @test(i32 %0) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[TMP0:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[TMP0]], i64 1
; CHECK-NEXT: switch i32 0, label %[[BCI_130:.*]] [
; CHECK-NEXT: i32 -4, label %[[BCI_96:.*]]
; CHECK-NEXT: i32 3, label %[[BCI_130]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/bv-root-part-of-graph.ll b/llvm/test/Transforms/SLPVectorizer/X86/bv-root-part-of-graph.ll
index 0cc4d3db5c537..85139cf019018 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/bv-root-part-of-graph.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/bv-root-part-of-graph.ll
@@ -10,7 +10,7 @@ define void @test() {
; CHECK: [[BB1]]:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 0, %[[BB]] ], [ [[TMP9:%.*]], %[[BB1]] ]
; CHECK-NEXT: [[FMUL:%.*]] = fmul float 0.000000e+00, 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[FMUL]], i32 2
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[FMUL]], i64 2
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
; CHECK-NEXT: [[TMP4:%.*]] = fadd <4 x float> [[TMP0]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x float> [[TMP4]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll b/llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
index b5d9915b690c0..8b4f045d903d1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/bv-shuffle-mask.ll
@@ -5,12 +5,12 @@ define i16 @test(i16 %v1, i16 %v2) {
; CHECK-LABEL: define i16 @test(
; CHECK-SAME: i16 [[V1:%.*]], i16 [[V2:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i16> poison, i16 [[V1]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i16> [[TMP4]], i16 [[V2]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i16> poison, i16 [[V1]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i16> [[TMP4]], i16 [[V2]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i16> [[TMP5]], <4 x i16> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> <i16 -1, i16 -1, i16 -1, i16 poison>, <4 x i32> <i32 4, i32 5, i32 6, i32 3>
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> <i16 0, i16 0, i16 0, i16 poison>, i16 [[V1]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> <i16 0, i16 0, i16 0, i16 poison>, i16 [[V1]], i64 3
; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i16> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i16> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP9:%.*]] = and <4 x i16> [[TMP7]], zeroinitializer
@@ -23,15 +23,15 @@ define i16 @test(i16 %v1, i16 %v2) {
; CHECK-NEXT: [[TMP16:%.*]] = icmp ne <4 x i16> [[TMP15]], zeroinitializer
; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i1> zeroinitializer, [[TMP16]]
; CHECK-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP12]], [[TMP17]]
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i1> [[TMP18]], i32 2
-; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i1> [[TMP18]], i32 3
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i1> [[TMP18]], i64 2
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i1> [[TMP18]], i64 3
; CHECK-NEXT: [[TMP21:%.*]] = or i1 [[TMP20]], [[TMP19]]
-; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i1> [[TMP18]], i32 1
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i1> [[TMP18]], i64 1
; CHECK-NEXT: [[TMP23:%.*]] = or i1 false, [[TMP22]]
; CHECK-NEXT: [[TMP24:%.*]] = freeze <4 x i1> [[TMP18]]
; CHECK-NEXT: [[TMP25:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP24]])
; CHECK-NEXT: [[SPEC_SELECT31:%.*]] = select i1 [[TMP25]], i32 0, i32 0
-; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[TMP18]], i32 0
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[TMP18]], i64 0
; CHECK-NEXT: [[TMP27:%.*]] = or i1 false, [[TMP26]]
; CHECK-NEXT: store i32 [[SPEC_SELECT31]], ptr null, align 4
; CHECK-NEXT: ret i16 0
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll b/llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
index a052f85ca3963..f80db40aef3a4 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/c-ray.ll
@@ -65,24 +65,24 @@ define i32 @ray_sphere(ptr nocapture noundef readonly %sph, ptr nocapture nounde
; SSE2-NEXT: [[CALL:%.*]] = tail call double @sqrt(double noundef [[TMP25]])
; SSE2-NEXT: [[FNEG87:%.*]] = fneg double [[TMP12]]
; SSE2-NEXT: [[MUL88:%.*]] = fmul double [[TMP4]], 2.000000e+00
-; SSE2-NEXT: [[TMP26:%.*]] = insertelement <2 x double> poison, double [[FNEG87]], i32 0
-; SSE2-NEXT: [[TMP27:%.*]] = insertelement <2 x double> [[TMP26]], double [[CALL]], i32 1
+; SSE2-NEXT: [[TMP26:%.*]] = insertelement <2 x double> poison, double [[FNEG87]], i64 0
+; SSE2-NEXT: [[TMP27:%.*]] = insertelement <2 x double> [[TMP26]], double [[CALL]], i64 1
; SSE2-NEXT: [[TMP28:%.*]] = shufflevector <2 x double> [[TMP27]], <2 x double> poison, <2 x i32> <i32 1, i32 poison>
-; SSE2-NEXT: [[TMP29:%.*]] = insertelement <2 x double> [[TMP28]], double [[TMP12]], i32 1
+; SSE2-NEXT: [[TMP29:%.*]] = insertelement <2 x double> [[TMP28]], double [[TMP12]], i64 1
; SSE2-NEXT: [[TMP30:%.*]] = fsub <2 x double> [[TMP27]], [[TMP29]]
-; SSE2-NEXT: [[TMP31:%.*]] = insertelement <2 x double> poison, double [[MUL88]], i32 0
+; SSE2-NEXT: [[TMP31:%.*]] = insertelement <2 x double> poison, double [[MUL88]], i64 0
; SSE2-NEXT: [[TMP32:%.*]] = shufflevector <2 x double> [[TMP31]], <2 x double> poison, <2 x i32> zeroinitializer
; SSE2-NEXT: [[TMP33:%.*]] = fdiv <2 x double> [[TMP30]], [[TMP32]]
-; SSE2-NEXT: [[TMP34:%.*]] = extractelement <2 x double> [[TMP33]], i32 1
+; SSE2-NEXT: [[TMP34:%.*]] = extractelement <2 x double> [[TMP33]], i64 1
; SSE2-NEXT: [[CMP93:%.*]] = fcmp olt double [[TMP34]], f0x3EB0C6F7A0B5ED8D
-; SSE2-NEXT: [[TMP35:%.*]] = extractelement <2 x double> [[TMP33]], i32 0
+; SSE2-NEXT: [[TMP35:%.*]] = extractelement <2 x double> [[TMP33]], i64 0
; SSE2-NEXT: [[CMP94:%.*]] = fcmp olt double [[TMP35]], f0x3EB0C6F7A0B5ED8D
; SSE2-NEXT: [[OR_COND:%.*]] = select i1 [[CMP93]], i1 [[CMP94]], i1 false
; SSE2-NEXT: br i1 [[OR_COND]], label [[CLEANUP]], label [[LOR_LHS_FALSE:%.*]]
; SSE2: lor.lhs.false:
; SSE2-NEXT: [[TMP36:%.*]] = fcmp ule <2 x double> [[TMP33]], splat (double 1.000000e+00)
-; SSE2-NEXT: [[TMP37:%.*]] = extractelement <2 x i1> [[TMP36]], i32 0
-; SSE2-NEXT: [[TMP38:%.*]] = extractelement <2 x i1> [[TMP36]], i32 1
+; SSE2-NEXT: [[TMP37:%.*]] = extractelement <2 x i1> [[TMP36]], i64 0
+; SSE2-NEXT: [[TMP38:%.*]] = extractelement <2 x i1> [[TMP36]], i64 1
; SSE2-NEXT: [[OR_COND106:%.*]] = select i1 [[TMP38]], i1 true, i1 [[TMP37]]
; SSE2-NEXT: [[SPEC_SELECT:%.*]] = zext i1 [[OR_COND106]] to i32
; SSE2-NEXT: br label [[CLEANUP]]
@@ -148,21 +148,21 @@ define i32 @ray_sphere(ptr nocapture noundef readonly %sph, ptr nocapture nounde
; AVX-NEXT: [[MUL88:%.*]] = fmul double [[TMP4]], 2.000000e+00
; AVX-NEXT: [[ADD:%.*]] = fsub double [[CALL]], [[TMP12]]
; AVX-NEXT: [[SUB90:%.*]] = fsub double [[FNEG87]], [[CALL]]
-; AVX-NEXT: [[TMP26:%.*]] = insertelement <2 x double> poison, double [[SUB90]], i32 0
-; AVX-NEXT: [[TMP27:%.*]] = insertelement <2 x double> [[TMP26]], double [[ADD]], i32 1
-; AVX-NEXT: [[TMP28:%.*]] = insertelement <2 x double> poison, double [[MUL88]], i32 0
+; AVX-NEXT: [[TMP26:%.*]] = insertelement <2 x double> poison, double [[SUB90]], i64 0
+; AVX-NEXT: [[TMP27:%.*]] = insertelement <2 x double> [[TMP26]], double [[ADD]], i64 1
+; AVX-NEXT: [[TMP28:%.*]] = insertelement <2 x double> poison, double [[MUL88]], i64 0
; AVX-NEXT: [[TMP29:%.*]] = shufflevector <2 x double> [[TMP28]], <2 x double> poison, <2 x i32> zeroinitializer
; AVX-NEXT: [[TMP30:%.*]] = fdiv <2 x double> [[TMP27]], [[TMP29]]
-; AVX-NEXT: [[TMP31:%.*]] = extractelement <2 x double> [[TMP30]], i32 1
+; AVX-NEXT: [[TMP31:%.*]] = extractelement <2 x double> [[TMP30]], i64 1
; AVX-NEXT: [[CMP93:%.*]] = fcmp olt double [[TMP31]], f0x3EB0C6F7A0B5ED8D
-; AVX-NEXT: [[TMP32:%.*]] = extractelement <2 x double> [[TMP30]], i32 0
+; AVX-NEXT: [[TMP32:%.*]] = extractelement <2 x double> [[TMP30]], i64 0
; AVX-NEXT: [[CMP94:%.*]] = fcmp olt double [[TMP32]], f0x3EB0C6F7A0B5ED8D
; AVX-NEXT: [[OR_COND:%.*]] = select i1 [[CMP93]], i1 [[CMP94]], i1 false
; AVX-NEXT: br i1 [[OR_COND]], label [[CLEANUP]], label [[LOR_LHS_FALSE:%.*]]
; AVX: lor.lhs.false:
; AVX-NEXT: [[TMP33:%.*]] = fcmp ule <2 x double> [[TMP30]], splat (double 1.000000e+00)
-; AVX-NEXT: [[TMP34:%.*]] = extractelement <2 x i1> [[TMP33]], i32 0
-; AVX-NEXT: [[TMP35:%.*]] = extractelement <2 x i1> [[TMP33]], i32 1
+; AVX-NEXT: [[TMP34:%.*]] = extractelement <2 x i1> [[TMP33]], i64 0
+; AVX-NEXT: [[TMP35:%.*]] = extractelement <2 x i1> [[TMP33]], i64 1
; AVX-NEXT: [[OR_COND106:%.*]] = select i1 [[TMP35]], i1 true, i1 [[TMP34]]
; AVX-NEXT: [[SPEC_SELECT:%.*]] = zext i1 [[OR_COND106]] to i32
; AVX-NEXT: br label [[CLEANUP]]
@@ -228,21 +228,21 @@ define i32 @ray_sphere(ptr nocapture noundef readonly %sph, ptr nocapture nounde
; AVX2-NEXT: [[MUL88:%.*]] = fmul double [[TMP4]], 2.000000e+00
; AVX2-NEXT: [[ADD:%.*]] = fsub double [[CALL]], [[TMP12]]
; AVX2-NEXT: [[SUB90:%.*]] = fsub double [[FNEG87]], [[CALL]]
-; AVX2-NEXT: [[TMP26:%.*]] = insertelement <2 x double> poison, double [[SUB90]], i32 0
-; AVX2-NEXT: [[TMP27:%.*]] = insertelement <2 x double> [[TMP26]], double [[ADD]], i32 1
-; AVX2-NEXT: [[TMP28:%.*]] = insertelement <2 x double> poison, double [[MUL88]], i32 0
+; AVX2-NEXT: [[TMP26:%.*]] = insertelement <2 x double> poison, double [[SUB90]], i64 0
+; AVX2-NEXT: [[TMP27:%.*]] = insertelement <2 x double> [[TMP26]], double [[ADD]], i64 1
+; AVX2-NEXT: [[TMP28:%.*]] = insertelement <2 x double> poison, double [[MUL88]], i64 0
; AVX2-NEXT: [[TMP29:%.*]] = shufflevector <2 x double> [[TMP28]], <2 x double> poison, <2 x i32> zeroinitializer
; AVX2-NEXT: [[TMP30:%.*]] = fdiv <2 x double> [[TMP27]], [[TMP29]]
-; AVX2-NEXT: [[TMP31:%.*]] = extractelement <2 x double> [[TMP30]], i32 1
+; AVX2-NEXT: [[TMP31:%.*]] = extractelement <2 x double> [[TMP30]], i64 1
; AVX2-NEXT: [[CMP93:%.*]] = fcmp olt double [[TMP31]], f0x3EB0C6F7A0B5ED8D
-; AVX2-NEXT: [[TMP32:%.*]] = extractelement <2 x double> [[TMP30]], i32 0
+; AVX2-NEXT: [[TMP32:%.*]] = extractelement <2 x double> [[TMP30]], i64 0
; AVX2-NEXT: [[CMP94:%.*]] = fcmp olt double [[TMP32]], f0x3EB0C6F7A0B5ED8D
; AVX2-NEXT: [[OR_COND:%.*]] = select i1 [[CMP93]], i1 [[CMP94]], i1 false
; AVX2-NEXT: br i1 [[OR_COND]], label [[CLEANUP]], label [[LOR_LHS_FALSE:%.*]]
; AVX2: lor.lhs.false:
; AVX2-NEXT: [[TMP33:%.*]] = fcmp ule <2 x double> [[TMP30]], splat (double 1.000000e+00)
-; AVX2-NEXT: [[TMP34:%.*]] = extractelement <2 x i1> [[TMP33]], i32 0
-; AVX2-NEXT: [[TMP35:%.*]] = extractelement <2 x i1> [[TMP33]], i32 1
+; AVX2-NEXT: [[TMP34:%.*]] = extractelement <2 x i1> [[TMP33]], i64 0
+; AVX2-NEXT: [[TMP35:%.*]] = extractelement <2 x i1> [[TMP33]], i64 1
; AVX2-NEXT: [[OR_COND106:%.*]] = select i1 [[TMP35]], i1 true, i1 [[TMP34]]
; AVX2-NEXT: [[SPEC_SELECT:%.*]] = zext i1 [[OR_COND106]] to i32
; AVX2-NEXT: br label [[CLEANUP]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/call.ll b/llvm/test/Transforms/SLPVectorizer/X86/call.ll
index 9e19aa9e93095..081c96a4efc15 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/call.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/call.ll
@@ -132,9 +132,9 @@ define void @sqrt_libm_no_errno(ptr %a, ptr %b) {
define void @sqrt_libm_errno(ptr %a, ptr %b) {
; CHECK-LABEL: @sqrt_libm_errno(
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i64 0
; CHECK-NEXT: [[SQRT1:%.*]] = tail call nnan double @sqrt(double [[TMP2]]) #[[ATTR4:[0-9]+]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i64 1
; CHECK-NEXT: [[SQRT2:%.*]] = tail call nnan double @sqrt(double [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: store double [[SQRT1]], ptr [[B:%.*]], align 8
; CHECK-NEXT: [[IDX2:%.*]] = getelementptr inbounds double, ptr [[B]], i64 1
@@ -156,9 +156,9 @@ define void @sqrt_libm_errno(ptr %a, ptr %b) {
define void @round_custom(ptr %a, ptr %b) {
; CHECK-LABEL: @round_custom(
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
; CHECK-NEXT: [[ROUND1:%.*]] = tail call i64 @round(i64 [[TMP2]]) #[[ATTR5:[0-9]+]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP1]], i64 1
; CHECK-NEXT: [[ROUND2:%.*]] = tail call i64 @round(i64 [[TMP3]]) #[[ATTR5]]
; CHECK-NEXT: store i64 [[ROUND1]], ptr [[B:%.*]], align 8
; CHECK-NEXT: [[IDX2:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cast-operand-extracted.ll b/llvm/test/Transforms/SLPVectorizer/X86/cast-operand-extracted.ll
index 2d4077f82621a..09965862dabe6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/cast-operand-extracted.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/cast-operand-extracted.ll
@@ -20,11 +20,11 @@ define void @test(ptr %0, i32 %add651) {
; CHECK-NEXT: [[ARRAYIDX689:%.*]] = getelementptr i8, ptr [[TMP4]], i64 7816
; CHECK-NEXT: [[TMP6:%.*]] = add <2 x i32> [[TMP3]], splat (i32 1)
; CHECK-NEXT: [[TMP10:%.*]] = add <2 x i32> [[TMP6]], [[TMP7]]
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[ADD651]], i32 0
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> poison, i32 [[ADD651]], i64 0
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[TMP2]], i64 1
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <2 x i32> [[TMP10]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP13]], <4 x i32> [[TMP19]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 1, i32 poison>, i32 [[TMP5]], i32 3
+; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 1, i32 poison>, i32 [[TMP5]], i64 3
; CHECK-NEXT: [[TMP21:%.*]] = add <4 x i32> [[TMP14]], [[TMP20]]
; CHECK-NEXT: [[TMP15:%.*]] = lshr <4 x i32> [[TMP21]], splat (i32 1)
; CHECK-NEXT: [[SHR685:%.*]] = lshr i32 [[TMP2]], 1
@@ -32,9 +32,9 @@ define void @test(ptr %0, i32 %add651) {
; CHECK-NEXT: [[CONV686:%.*]] = trunc i32 [[SHR685]] to i16
; CHECK-NEXT: store i16 [[CONV686]], ptr [[ARRAYIDX689]], align 8
; CHECK-NEXT: [[ARRAYIDX727:%.*]] = getelementptr i8, ptr [[TMP4]], i64 7818
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i16> [[TMP16]], i32 2
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i16> [[TMP16]], i64 2
; CHECK-NEXT: store i16 [[TMP17]], ptr [[ARRAYIDX727]], align 2
-; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i16> [[TMP16]], i32 3
+; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i16> [[TMP16]], i64 3
; CHECK-NEXT: store i16 [[TMP18]], ptr [[TMP4]], align 8
; CHECK-NEXT: store <4 x i16> [[TMP16]], ptr [[ARRAYIDX660]], align 8
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll
index a05d4fdd6315b..47fb3a904e57c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll
@@ -8,9 +8,9 @@ define void @test() {
; CHECK-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> zeroinitializer, <2 x i32> zeroinitializer)
; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> [[TMP0]]
; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], zeroinitializer
-; CHECK-NEXT: [[ADD:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; CHECK-NEXT: [[ADD:%.*]] = extractelement <2 x i32> [[TMP2]], i64 1
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[ADD]], 0
-; CHECK-NEXT: [[ADD45:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; CHECK-NEXT: [[ADD45:%.*]] = extractelement <2 x i32> [[TMP2]], i64 0
; CHECK-NEXT: [[ADD152:%.*]] = or i32 [[ADD45]], [[ADD]]
; CHECK-NEXT: [[IDXPROM153:%.*]] = sext i32 [[ADD152]] to i64
; CHECK-NEXT: [[ARRAYIDX154:%.*]] = getelementptr i8, ptr null, i64 [[IDXPROM153]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cmp-as-alternate-ops.ll b/llvm/test/Transforms/SLPVectorizer/X86/cmp-as-alternate-ops.ll
index d275931c77eab..edecf9f5db0a0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/cmp-as-alternate-ops.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/cmp-as-alternate-ops.ll
@@ -6,11 +6,11 @@ define void @test(ptr %0, double %1) {
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, ptr [[TMP0:%.*]], i32 6
; CHECK-NEXT: br label [[TMP4:%.*]]
; CHECK: 4:
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP1:%.*]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP1:%.*]], i64 1
; CHECK-NEXT: br label [[TMP6:%.*]]
; CHECK: 6:
; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr null, align 8
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP7]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = fcmp olt <2 x double> [[TMP5]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[TMP9]], <2 x double> zeroinitializer, <2 x double> zeroinitializer
; CHECK-NEXT: [[TMP11:%.*]] = fmul <2 x double> [[TMP10]], zeroinitializer
@@ -44,9 +44,9 @@ define { <2 x float>, <2 x float> } @test1(i32 %conv.i32.i.i.i) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CONV_I32_I_I_I1:%.*]] = fptosi float 0.000000e+00 to i32
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[CONV_I32_I_I_I1]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[CONV_I32_I_I_I1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i32> [[TMP0]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[CONV_I32_I_I_I:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[CONV_I32_I_I_I:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <2 x i32> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i1> [[TMP3]], <2 x i1> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i1> [[TMP1]], <2 x i1> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cmp_sel.ll b/llvm/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
index 926cc7b906efe..9dbe44265c13b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
@@ -12,7 +12,7 @@ define i32 @foo(ptr noalias nocapture %A, ptr noalias nocapture %B, double %G) {
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[B:%.*]], i64 10
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = fcmp une <2 x double> [[TMP1]], zeroinitializer
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[G:%.*]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[G:%.*]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = select <2 x i1> [[TMP2]], <2 x double> [[SHUFFLE]], <2 x double> splat (double 1.000000e+00)
; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[A:%.*]], align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/commutable-member-in-non-commutable-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/commutable-member-in-non-commutable-node.ll
index adceef172864d..d464ae26f60e4 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/commutable-member-in-non-commutable-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/commutable-member-in-non-commutable-node.ll
@@ -7,7 +7,7 @@ define i64 @test(i32 %arg) {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) null, i64 896), align 4
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[TMP0]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = sub <2 x i32> [[TMP1]], [[TMP2]]
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) null, i64 896), align 4
; CHECK-NEXT: ret i64 0
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll b/llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll
index c5857bef1caff..a9852497720fc 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/commutable-node-with-non-sched-parent.ll
@@ -6,7 +6,7 @@ define void @test() {
; CHECK-NEXT: [[BB:.*]]:
; CHECK-NEXT: br i1 false, label %[[BB1:.*]], label %[[BB9:.*]]
; CHECK: [[BB1]]:
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> poison, i32 0, i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> poison, i32 0, i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP9]], <4 x i32> <i32 0, i32 -1, i32 undef, i32 undef>, <4 x i32> <i32 0, i32 4, i32 5, i32 poison>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
; CHECK-NEXT: br label %[[BB6:.*]]
@@ -14,8 +14,8 @@ define void @test() {
; CHECK-NEXT: [[TMP5:%.*]] = phi <4 x i32> [ [[TMP4]], %[[BB1]] ]
; CHECK-NEXT: br label %[[BB9]]
; CHECK: [[BB9]]:
-; CHECK-NEXT: [[TMP7:%.*]] = phi <4 x i32> [ <i32 0, i32 0, i32 poison, i32 0>, %[[BB]] ], [ [[TMP5]], %[[BB6]] ]
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP7]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = phi <4 x i32> [ <i32 0, i32 0, i32 poison, i32 0>, %[[BB]] ], [ [[TMP5]], %[[BB6]] ]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP6]], i64 3
; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP8]], 0
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll b/llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
index aa00686d399ff..be98b9004ceb1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/commutative-copyable-external-phi-use.ll
@@ -5,7 +5,7 @@ define void @test(i32 %arg) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[ARG:%.*]]) {
; CHECK-NEXT: [[BB:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> zeroinitializer, [[TMP0]]
; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i32> zeroinitializer, [[TMP0]]
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 0, i32 3>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/commutativity.ll b/llvm/test/Transforms/SLPVectorizer/X86/commutativity.ll
index b21ba424a63c7..0b6a59c0af45e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/commutativity.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/commutativity.ll
@@ -16,20 +16,20 @@
define void @splat(i8 %a, i8 %b, i8 %c) {
; SSE-LABEL: @splat(
-; SSE-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[A:%.*]], i32 0
-; SSE-NEXT: [[TMP2:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[B:%.*]], i32 1
+; SSE-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[A:%.*]], i64 0
+; SSE-NEXT: [[TMP2:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[B:%.*]], i64 1
; SSE-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> [[TMP2]], <16 x i8> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
-; SSE-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> poison, i8 [[C:%.*]], i32 0
+; SSE-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> poison, i8 [[C:%.*]], i64 0
; SSE-NEXT: [[TMP5:%.*]] = shufflevector <16 x i8> [[TMP4]], <16 x i8> poison, <16 x i32> zeroinitializer
; SSE-NEXT: [[TMP6:%.*]] = xor <16 x i8> [[TMP3]], [[TMP5]]
; SSE-NEXT: store <16 x i8> [[TMP6]], ptr @cle, align 16
; SSE-NEXT: ret void
;
; AVX-LABEL: @splat(
-; AVX-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[A:%.*]], i32 0
-; AVX-NEXT: [[TMP2:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[B:%.*]], i32 1
+; AVX-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[A:%.*]], i64 0
+; AVX-NEXT: [[TMP2:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[B:%.*]], i64 1
; AVX-NEXT: [[TMP3:%.*]] = shufflevector <16 x i8> [[TMP2]], <16 x i8> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
-; AVX-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> poison, i8 [[C:%.*]], i32 0
+; AVX-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> poison, i8 [[C:%.*]], i64 0
; AVX-NEXT: [[TMP5:%.*]] = shufflevector <16 x i8> [[TMP4]], <16 x i8> poison, <16 x i32> zeroinitializer
; AVX-NEXT: [[TMP6:%.*]] = xor <16 x i8> [[TMP3]], [[TMP5]]
; AVX-NEXT: store <16 x i8> [[TMP6]], ptr @cle, align 16
@@ -90,13 +90,13 @@ define void @same_opcode_on_one_side(i32 %a, i32 %b, i32 %c) {
; SSE-NEXT: ret void
;
; AVX-LABEL: @same_opcode_on_one_side(
-; AVX-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[C:%.*]], i32 0
+; AVX-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[C:%.*]], i64 0
; AVX-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
-; AVX-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> poison, i32 [[A:%.*]], i32 0
+; AVX-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> poison, i32 [[A:%.*]], i64 0
; AVX-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <4 x i32> zeroinitializer
; AVX-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP2]], [[TMP4]]
; AVX-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 poison, i32 4, i32 0>
-; AVX-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[B:%.*]], i32 1
+; AVX-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[B:%.*]], i64 1
; AVX-NEXT: [[TMP8:%.*]] = xor <4 x i32> [[TMP5]], [[TMP7]]
; AVX-NEXT: store <4 x i32> [[TMP8]], ptr @cle32, align 16
; AVX-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/compare-node-with-reuses.ll b/llvm/test/Transforms/SLPVectorizer/X86/compare-node-with-reuses.ll
index 69dfba41b5006..588df0e6755a5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/compare-node-with-reuses.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/compare-node-with-reuses.ll
@@ -13,17 +13,17 @@ define i16 @test_inc_1(i16 %tnr.coerce) {
; CHECK-NEXT: [[CALL101:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext [[CALL80]])
; CHECK-NEXT: [[CALL123:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext 2147483647)
; CHECK-NEXT: [[CALL144:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext [[CALL123]])
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[CALL]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[CALL37]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[CALL80]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[CALL123]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[CALL]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[CALL37]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[CALL80]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[CALL123]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[TMP3]], <4 x i32> splat (i32 2147483647))
; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i32> [[TMP4]], splat (i32 2147483647)
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <8 x i32> <i32 0, i32 poison, i32 1, i32 poison, i32 2, i32 poison, i32 3, i32 poison>
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[CALL15]], i32 1
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[CALL58]], i32 3
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 [[CALL101]], i32 5
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i32> [[TMP9]], i32 [[CALL144]], i32 7
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[CALL15]], i64 1
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[CALL58]], i64 3
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 [[CALL101]], i64 5
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i32> [[TMP9]], i32 [[CALL144]], i64 7
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <8 x i32> [[TMP10]], <8 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <12 x i32> [[TMP11]], <12 x i32> [[TMP12]], <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll b/llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
index 0b6c8f3d2562b..6bf16b3669a51 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
@@ -10,7 +10,7 @@ define void @reduce_compare(ptr nocapture %A, i32 %n) {
; CHECK-LABEL: @reduce_compare(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[N:%.*]] to double
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
@@ -21,8 +21,8 @@ define void @reduce_compare(ptr nocapture %A, i32 %n) {
; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], <double 7.000000e+00, double 4.000000e+00>
; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[TMP5]], <double 5.000000e+00, double 9.000000e+00>
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP6]], i64 1
; CHECK-NEXT: [[CMP11:%.*]] = fcmp ogt double [[TMP7]], [[TMP8]]
; CHECK-NEXT: br i1 [[CMP11]], label [[IF_THEN:%.*]], label [[FOR_INC]]
; CHECK: if.then:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/complex-fma-combine.ll b/llvm/test/Transforms/SLPVectorizer/X86/complex-fma-combine.ll
index 9cc139e8a02a5..4d93883a976f8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/complex-fma-combine.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/complex-fma-combine.ll
@@ -7,7 +7,7 @@ define <2 x float> @fma_f32(ptr %A, float %B) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[A]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x float> [[TMP0]], splat (float 2.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> <float poison, float -0.000000e+00>, float [[B]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> <float poison, float -0.000000e+00>, float [[B]], i64 0
; CHECK-NEXT: [[RETVAL_SROA_0_0_VEC_INSERT_I6:%.*]] = fadd <2 x float> [[TMP2]], [[TMP1]]
; CHECK-NEXT: ret <2 x float> [[RETVAL_SROA_0_0_VEC_INSERT_I6]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/control-dependence.ll b/llvm/test/Transforms/SLPVectorizer/X86/control-dependence.ll
index 69cfdd44ff6e7..27817ea7f3b31 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/control-dependence.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/control-dependence.ll
@@ -35,8 +35,8 @@ define void @test1(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[C1:%.*]] = load i64, ptr [[C:%.*]], align 8
; CHECK-NEXT: [[C2:%.*]] = call i64 @may_inf_loop_ro()
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[C1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[C2]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[C1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[C2]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i64> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -61,8 +61,8 @@ define void @test2(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[C1:%.*]] = load i64, ptr [[C:%.*]], align 8
; CHECK-NEXT: [[C2:%.*]] = call i64 @may_inf_loop_ro()
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[C1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[C2]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[C1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[C2]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i64> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -88,8 +88,8 @@ define void @test3(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[C1:%.*]] = load i64, ptr [[C:%.*]], align 8
; CHECK-NEXT: [[C2:%.*]] = call i64 @may_inf_loop_ro()
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[C1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[C2]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[C1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[C2]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i64> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -114,8 +114,8 @@ define void @test4(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[C1:%.*]] = load i64, ptr [[C:%.*]], align 8
; CHECK-NEXT: [[C2:%.*]] = call i64 @may_inf_loop_ro()
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[C1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[C2]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[C1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[C2]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i64> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -140,8 +140,8 @@ define void @test5(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[C2:%.*]] = call i64 @may_inf_loop_ro()
; CHECK-NEXT: [[C1:%.*]] = load i64, ptr [[C:%.*]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[C1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[C2]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[C1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[C2]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i64> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -201,8 +201,8 @@ define void @test7(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @may_inf_loop_ro()
; CHECK-NEXT: [[V2:%.*]] = load i64, ptr [[A2]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[C:%.*]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[V1]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[V2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[V1]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[V2]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP4]], [[TMP2]]
; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -234,8 +234,8 @@ define void @test8(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @may_throw() #[[ATTR4:[0-9]+]]
; CHECK-NEXT: [[V2:%.*]] = load i64, ptr [[A2]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[C:%.*]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[V1]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[V2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[V1]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[V2]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP4]], [[TMP2]]
; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -267,8 +267,8 @@ define void @test9(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @may_throw()
; CHECK-NEXT: [[V2:%.*]] = load i64, ptr [[A2]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[C:%.*]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[V1]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[V2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[V1]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[V2]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP4]], [[TMP2]]
; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -302,8 +302,8 @@ define void @test10(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @may_inf_loop_ro()
; CHECK-NEXT: [[U2:%.*]] = udiv i64 200, [[V2]]
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[C:%.*]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[U1]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[U2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[U1]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[U2]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP4]], [[TMP2]]
; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -338,8 +338,8 @@ define void @test11(i64 %x, i64 %y, ptr %b, ptr %c) {
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @may_inf_loop_ro()
; CHECK-NEXT: [[U2:%.*]] = udiv i64 200, [[Y:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[C:%.*]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[U1]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[U2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[U1]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[U2]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP4]], [[TMP2]]
; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr [[B]], align 8
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll b/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll
index 07442eaef7d7f..756324cd35526 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll
@@ -568,9 +568,9 @@ define void @fpround_v2xf64_v2xf16(ptr %s0, ptr %d0) {
; CHECK-F16C-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[S0]], align 4
; CHECK-F16C-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x half>
; CHECK-F16C-NEXT: [[D1:%.*]] = getelementptr inbounds half, ptr [[D0]], i64 1
-; CHECK-F16C-NEXT: [[T0:%.*]] = extractelement <2 x half> [[TMP2]], i32 0
+; CHECK-F16C-NEXT: [[T0:%.*]] = extractelement <2 x half> [[TMP2]], i64 0
; CHECK-F16C-NEXT: store half [[T0]], ptr [[D0]], align 2
-; CHECK-F16C-NEXT: [[T1:%.*]] = extractelement <2 x half> [[TMP2]], i32 1
+; CHECK-F16C-NEXT: [[T1:%.*]] = extractelement <2 x half> [[TMP2]], i64 1
; CHECK-F16C-NEXT: store half [[T1]], ptr [[D1]], align 2
; CHECK-F16C-NEXT: ret void
;
@@ -579,9 +579,9 @@ define void @fpround_v2xf64_v2xf16(ptr %s0, ptr %d0) {
; CHECK-AVX512-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[S0]], align 4
; CHECK-AVX512-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x half>
; CHECK-AVX512-NEXT: [[D1:%.*]] = getelementptr inbounds half, ptr [[D0]], i64 1
-; CHECK-AVX512-NEXT: [[T0:%.*]] = extractelement <2 x half> [[TMP2]], i32 0
+; CHECK-AVX512-NEXT: [[T0:%.*]] = extractelement <2 x half> [[TMP2]], i64 0
; CHECK-AVX512-NEXT: store half [[T0]], ptr [[D0]], align 2
-; CHECK-AVX512-NEXT: [[T1:%.*]] = extractelement <2 x half> [[TMP2]], i32 1
+; CHECK-AVX512-NEXT: [[T1:%.*]] = extractelement <2 x half> [[TMP2]], i64 1
; CHECK-AVX512-NEXT: store half [[T1]], ptr [[D1]], align 2
; CHECK-AVX512-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-child-node-used-outside.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-child-node-used-outside.ll
index cb0fd96856262..d56524133ce2a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-child-node-used-outside.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-child-node-used-outside.ll
@@ -8,7 +8,7 @@ define <4 x i32> @test() {
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
; CHECK-NEXT: [[OR:%.*]] = or i32 [[TRUNC]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 poison, i32 poison>, i32 [[TRUNC]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 poison, i32 poison>, i32 [[TRUNC]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 0>
; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i32> <i32 -1, i32 0, i32 -1, i32 -1>, [[TMP2]]
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[OR]] to i64
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-non-inst-in-stores.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-non-inst-in-stores.ll
index efdbdb2ea867e..edb033f46170b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-non-inst-in-stores.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-non-inst-in-stores.ll
@@ -5,7 +5,7 @@ define void @test(i32 %a, ptr %out) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[A:%.*]], ptr [[OUT:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[A]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[A]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[TMP0]], <8 x i32> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = lshr <8 x i32> [[TMP1]], <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: store <8 x i32> [[TMP2]], ptr [[OUT]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
index cdd7e64d4a3cb..e1a0a1af8858d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-operand-non-scheduled-parent-node.ll
@@ -5,7 +5,7 @@ define void @test(i32 %arg) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[ARG:%.*]]) {
; CHECK-NEXT: [[BB:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[ARG]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[ARG]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> zeroinitializer, [[TMP0]]
; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i32> zeroinitializer, [[TMP0]]
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 2, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-operands-reordering.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-operands-reordering.ll
index cf50c19edf1c9..52399974d31c6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-operands-reordering.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-operands-reordering.ll
@@ -12,14 +12,14 @@ define i64 @test(ptr %buf) {
; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[ARRAYIDX22]], align 1
; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw i8, ptr [[BUF]], i64 3
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP0]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 poison, i32 1, i32 1, i32 1>, i32 [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 poison, i32 1, i32 1, i32 1>, i32 [[TMP3]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = mul <4 x i32> <i32 24, i32 0, i32 0, i32 0>, [[TMP5]]
; CHECK-NEXT: [[TMP17:%.*]] = zext i8 [[TMP8]] to i32
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i32> <i32 poison, i32 1, i32 1, i32 1>, i32 [[TMP17]], i32 0
+; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i32> <i32 poison, i32 1, i32 1, i32 1>, i32 [[TMP17]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = mul <4 x i32> <i32 16, i32 0, i32 0, i32 0>, [[TMP20]]
; CHECK-NEXT: [[TMP7:%.*]] = or disjoint <4 x i32> [[TMP4]], [[TMP6]]
; CHECK-NEXT: [[TMP21:%.*]] = zext i8 [[TMP10]] to i32
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i32> <i32 poison, i32 1, i32 1, i32 1>, i32 [[TMP21]], i32 0
+; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i32> <i32 poison, i32 1, i32 1, i32 1>, i32 [[TMP21]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = mul <4 x i32> <i32 8, i32 0, i32 0, i32 0>, [[TMP22]]
; CHECK-NEXT: [[TMP18:%.*]] = or disjoint <4 x i32> [[TMP7]], [[TMP9]]
; CHECK-NEXT: [[TMP19:%.*]] = load <4 x i8>, ptr [[ARRAYIDX8]], align 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-scheduled-non-copyable.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-scheduled-non-copyable.ll
index 762366cb3b623..14075a029a2d4 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-scheduled-non-copyable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-scheduled-non-copyable.ll
@@ -7,7 +7,7 @@ define void @test(i32 %arg) {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> <i32 0, i32 poison>, <2 x i32> <i32 2, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <4 x i32> <i32 0, i32 poison, i32 1, i32 poison>
@@ -15,7 +15,7 @@ define void @test(i32 %arg) {
; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> zeroinitializer, [[TMP4]]
; CHECK-NEXT: [[ICMP:%.*]] = icmp sgt i32 0, 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> <i32 poison, i32 poison, i32 poison, i32 1>, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 0, i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 0, i64 1
; CHECK-NEXT: br i1 false, label %[[BB5:.*]], label %[[BB4:.*]]
; CHECK: [[BB4]]:
; CHECK-NEXT: br label %[[BB5]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-used-non-copyable.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-used-non-copyable.ll
index 4880a02543a21..2321bf9fd3a89 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-used-non-copyable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-phi-used-non-copyable.ll
@@ -5,7 +5,7 @@ define void @test(i32 %arg) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[ARG:%.*]]) {
; CHECK-NEXT: [[BB:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[ARG]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[ARG]], i64 1
; CHECK-NEXT: br label %[[BB4:.*]]
; CHECK: [[BB1:.*]]:
; CHECK-NEXT: [[SUB2:%.*]] = sub i32 0, 0
@@ -15,7 +15,7 @@ define void @test(i32 %arg) {
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> zeroinitializer, [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 6, i32 poison>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[OR]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[OR]], i64 3
; CHECK-NEXT: br i1 false, label %[[BB8:.*]], label %[[BB4]]
; CHECK: [[BB4]]:
; CHECK-NEXT: [[TMP7:%.*]] = phi <4 x i32> [ zeroinitializer, %[[BB]] ], [ [[TMP4]], %[[BB1]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-reduced-erased.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-reduced-erased.ll
index 121592d05be17..e6cfde1452d0a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-reduced-erased.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-reduced-erased.ll
@@ -5,11 +5,11 @@ define i32 @test(i32 %v7.0.v7.0.2979.fr.1) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[V7_0_V7_0_2979_FR_1:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 [[V7_0_V7_0_2979_FR_1]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 [[V7_0_V7_0_2979_FR_1]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = srem <4 x i32> [[TMP0]], splat (i32 46337)
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 2
; CHECK-NEXT: [[TMP5:%.*]] = urem <4 x i32> [[TMP3]], splat (i32 46337)
; CHECK-NEXT: [[TMP6:%.*]] = icmp ult <4 x i32> [[TMP5]], zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> zeroinitializer, <4 x i32> zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-used-outside-with-immediate-op.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-used-outside-with-immediate-op.ll
index 1f9fc9efab11f..5b811e7e2f267 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-used-outside-with-immediate-op.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-used-outside-with-immediate-op.ll
@@ -22,8 +22,8 @@ define void @test() {
; CHECK: [[BB14]]:
; CHECK-NEXT: [[OR:%.*]] = or i32 [[PHI13]], [[PHI11]]
; CHECK-NEXT: [[OR15]] = or i32 [[OR]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> poison, i32 [[PHI11]], i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[OR]], i32 3
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> poison, i32 [[PHI11]], i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[OR]], i64 3
; CHECK-NEXT: [[TMP6]] = or <4 x i32> [[TMP5]], <i32 poison, i32 poison, i32 0, i32 0>
; CHECK-NEXT: br i1 false, label %[[BB1]], label %[[BB10]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
index 4c931e46bd8fd..9ef2a9d83b0e9 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll
@@ -5,7 +5,7 @@ define i64 @test(ptr %a) {
; CHECK-LABEL: define i64 @test(
; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[A]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i64> <i64 poison, i64 0, i64 0, i64 0>, i64 [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i64> <i64 poison, i64 0, i64 0, i64 0>, i64 [[TMP2]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i64> zeroinitializer, [[TMP7]]
; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i64> <i64 0, i64 0, i64 0, i64 1>, [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-used-outside-bb.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-used-outside-bb.ll
index 7f13b30e35b21..ed3ed3d1af1f8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-used-outside-bb.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable-with-used-outside-bb.ll
@@ -7,9 +7,9 @@ define void @test(i32 %arg) {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[ARG]], i32 2
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[ARG]], i64 2
; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> <i32 7, i32 7, i32 0, i32 7>, [[TMP0]]
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i32 [[TMP2]], 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> <i32 poison, i32 0, i32 poison, i32 0>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; CHECK-NEXT: br i1 false, label %[[BB2:.*]], label %[[BB3:.*]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
index 5e8ac402307f2..d39fb8557a16d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyable_reorder.ll
@@ -20,10 +20,10 @@ define void @test_commutative(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i32> [[TMP2]], [[TMP2]]
; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> poison, i32 [[T0]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> poison, i32 [[T0]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x i32> [[TMP4]], <8 x i32> [[TMP5]], <8 x i32> <i32 0, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[T3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[T3]], i64 3
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP7]], <8 x i32> [[TMP8]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> <i32 poison, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -96,11 +96,11 @@ define void @test_add_udiv(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i32
; CHECK-LABEL: @test_add_udiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i32 2
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i64 2
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 1, i32 42, i32 1>
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> <i32 1146, i32 146, i32 0, i32 0>, [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = udiv <4 x i32> [[TMP0]], [[TMP2]]
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[TMP7]], [[TMP6]]
@@ -137,11 +137,11 @@ define void @test_add_udiv_reorder_add(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i
; CHECK-LABEL: @test_add_udiv_reorder_add(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i32 2
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i64 2
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 1, i32 42, i32 1>
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[V3:%.*]], i32 3
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> <i32 1146, i32 146, i32 0, i32 0>, [[TMP6]]
; CHECK-NEXT: [[TMP7:%.*]] = udiv <4 x i32> [[TMP0]], [[TMP2]]
; CHECK-NEXT: [[TMP10:%.*]] = add nsw <4 x i32> [[TMP7]], [[TMP8]]
@@ -178,11 +178,11 @@ define void @test_add_udiv_commuted(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32
; CHECK-LABEL: @test_add_udiv_commuted(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i64 2
; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[TMP4]], <i32 1, i32 1, i32 42, i32 1>
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> <i32 1146, i32 146, i32 0, i32 0>, [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = udiv <4 x i32> [[TMP0]], [[TMP6]]
; CHECK-NEXT: [[TMP9:%.*]] = add nsw <4 x i32> [[TMP5]], [[TMP8]]
@@ -218,10 +218,10 @@ entry:
define void @test_add_mul(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
; CHECK-LABEL: @test_add_mul(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A2:%.*]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A2:%.*]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMP3]], <i32 1146, i32 146, i32 42, i32 0>
; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[TMP6]], [[TMP4]]
@@ -259,10 +259,10 @@ entry:
define void @test_add_mul_commuted(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
; CHECK-LABEL: @test_add_mul_commuted(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A2:%.*]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A2:%.*]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP8:%.*]] = add <4 x i32> <i32 1146, i32 146, i32 42, i32 0>, [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4
; CHECK-NEXT: [[TMP9:%.*]] = add nsw <4 x i32> [[TMP5]], [[TMP8]]
@@ -301,11 +301,11 @@ define void @test_add_udiv_sub(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2,
; CHECK-LABEL: @test_add_udiv_sub(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 1, i32 1, i32 poison, i32 1>, i32 [[A2:%.*]], i32 2
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 1, i32 1, i32 poison, i32 1>, i32 [[A2:%.*]], i64 2
; CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> [[TMP1]], <i32 0, i32 0, i32 42, i32 0>
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> <i32 1146, i32 146, i32 0, i32 0>, [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = udiv <4 x i32> [[TMP0]], [[TMP2]]
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[TMP7]], [[TMP6]]
@@ -342,11 +342,11 @@ define void @test_add_udiv_sub_commuted(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1,
; CHECK-LABEL: @test_add_udiv_sub_commuted(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> <i32 1, i32 1, i32 poison, i32 1>, i32 [[A2:%.*]], i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> <i32 1, i32 1, i32 poison, i32 1>, i32 [[A2:%.*]], i64 2
; CHECK-NEXT: [[TMP6:%.*]] = sub <4 x i32> [[TMP4]], <i32 0, i32 0, i32 42, i32 0>
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> <i32 1146, i32 146, i32 0, i32 0>, [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = udiv <4 x i32> [[TMP0]], [[TMP6]]
; CHECK-NEXT: [[TMP9:%.*]] = add nsw <4 x i32> [[TMP5]], [[TMP8]]
@@ -393,10 +393,10 @@ define void @test_sub_zero_copyable_not_swapped(ptr %z) {
; CHECK-NEXT: [[V3:%.*]] = load i32, ptr [[GEP_SRC_NEAR1]], align 4
; CHECK-NEXT: [[NEG0:%.*]] = sub nsw i32 0, [[V0]]
; CHECK-NEXT: [[NEG2:%.*]] = sub nsw i32 0, [[V2]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[NEG0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[V1]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[NEG2]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[V3]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[NEG0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[V1]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[NEG2]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[V3]], i64 3
; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr [[GEP_DST0]], align 4
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/copyables-with-parent-scalars-in-phis.ll b/llvm/test/Transforms/SLPVectorizer/X86/copyables-with-parent-scalars-in-phis.ll
index 347dff468bdb3..31479419f01b8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/copyables-with-parent-scalars-in-phis.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/copyables-with-parent-scalars-in-phis.ll
@@ -12,9 +12,9 @@ define i32 @test() {
; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x i32> [ zeroinitializer, %[[BB]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT: [[LOAD:%.*]] = load i64, ptr null, align 8
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[LOAD]] to i32
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[TRUNC]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[TRUNC]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP10]], <i32 0, i32 -1>
-; CHECK-NEXT: [[AND:%.*]] = extractelement <2 x i32> [[TMP3]], i32 0
+; CHECK-NEXT: [[AND:%.*]] = extractelement <2 x i32> [[TMP3]], i64 0
; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 0, [[AND]]
; CHECK-NEXT: [[TMP4:%.*]] = ashr <2 x i32> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i32> [[TMP1]], [[TMP3]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_bullet.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
index 291edbbc925bd..af2db28211974 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
@@ -9,14 +9,14 @@ target triple = "x86_64-apple-macosx10.8.0"
define void @_ZN23btGeneric6DofConstraint8getInfo1EPN17btTypedConstraint17btConstraintInfo1E(ptr nocapture %info, i1 %arg) {
; CHECK-LABEL: @_ZN23btGeneric6DofConstraint8getInfo1EPN17btTypedConstraint17btConstraintInfo1E(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 %arg, label [[IF_ELSE:%.*]], label [[IF_THEN:%.*]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[IF_ELSE:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then:
; CHECK-NEXT: ret void
; CHECK: if.else:
; CHECK-NEXT: [[NUB5:%.*]] = getelementptr inbounds %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960", ptr [[INFO:%.*]], i64 0, i32 1
-; CHECK-NEXT: br i1 %arg, label [[LAND_LHS_TRUE_I_1:%.*]], label [[IF_THEN7_1:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[LAND_LHS_TRUE_I_1:%.*]], label [[IF_THEN7_1:%.*]]
; CHECK: land.lhs.true.i.1:
-; CHECK-NEXT: br i1 %arg, label [[FOR_INC_1:%.*]], label [[IF_THEN7_1]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_INC_1:%.*]], label [[IF_THEN7_1]]
; CHECK: if.then7.1:
; CHECK-NEXT: store <2 x i32> <i32 1, i32 5>, ptr [[INFO]], align 4
; CHECK-NEXT: br label [[FOR_INC_1]]
@@ -69,16 +69,16 @@ define void @_ZN30GIM_TRIANGLE_CALCULATION_CACHE18triangle_collisionERK9btVector
; CHECK-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [[CLASS_GIM_TRIANGLE_CALCULATION_CACHE_9_34_69_94_119_144_179_189_264_284_332:%.*]], ptr [[THIS:%.*]], i64 0, i32 2, i64 0, i32 0, i64 1
; CHECK-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [[CLASS_GIM_TRIANGLE_CALCULATION_CACHE_9_34_69_94_119_144_179_189_264_284_332]], ptr [[THIS]], i64 0, i32 2, i64 0, i32 0, i64 2
; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX36]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[TMP0]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x float> [[TMP1]], undef
; CHECK-NEXT: [[TMP3:%.*]] = fsub <2 x float> [[TMP2]], undef
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i64 0
; CHECK-NEXT: store float [[TMP4]], ptr undef, align 4
; CHECK-NEXT: [[TMP5:%.*]] = fsub <2 x float> [[TMP2]], [[TMP3]]
; CHECK-NEXT: store <2 x float> [[TMP5]], ptr [[ARRAYIDX26]], align 4
-; CHECK-NEXT: br i1 %arg, label [[IF_ELSE1609:%.*]], label [[IF_THEN1595:%.*]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[IF_ELSE1609:%.*]], label [[IF_THEN1595:%.*]]
; CHECK: if.then1595:
-; CHECK-NEXT: br i1 %arg, label [[RETURN:%.*]], label [[FOR_BODY_LR_PH_I_I1702:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[RETURN:%.*]], label [[FOR_BODY_LR_PH_I_I1702:%.*]]
; CHECK: for.body.lr.ph.i.i1702:
; CHECK-NEXT: unreachable
; CHECK: if.else1609:
@@ -117,31 +117,31 @@ return: ; preds = %if.then1595
define void @_Z8dBoxBox2RK9btVector3PKfS1_S1_S3_S1_RS_PfPiiP12dContactGeomiRN36btDiscreteCollisionDetectorInterface6ResultE(i1 %arg) {
; CHECK-LABEL: @_Z8dBoxBox2RK9btVector3PKfS1_S1_S3_S1_RS_PfPiiP12dContactGeomiRN36btDiscreteCollisionDetectorInterface6ResultE(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 %arg, label [[RETURN:%.*]], label [[IF_END:%.*]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[RETURN:%.*]], label [[IF_END:%.*]]
; CHECK: if.end:
-; CHECK-NEXT: br i1 %arg, label [[RETURN]], label [[IF_END111:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[RETURN]], label [[IF_END111:%.*]]
; CHECK: if.end111:
-; CHECK-NEXT: br i1 %arg, label [[RETURN]], label [[IF_END136:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[RETURN]], label [[IF_END136:%.*]]
; CHECK: if.end136:
-; CHECK-NEXT: br i1 %arg, label [[RETURN]], label [[IF_END162:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[RETURN]], label [[IF_END162:%.*]]
; CHECK: if.end162:
-; CHECK-NEXT: br i1 %arg, label [[RETURN]], label [[IF_END189:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[RETURN]], label [[IF_END189:%.*]]
; CHECK: if.end189:
-; CHECK-NEXT: br i1 %arg, label [[RETURN]], label [[IF_END216:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[RETURN]], label [[IF_END216:%.*]]
; CHECK: if.end216:
-; CHECK-NEXT: br i1 %arg, label [[IF_THEN218:%.*]], label [[IF_END225:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[IF_THEN218:%.*]], label [[IF_END225:%.*]]
; CHECK: if.then218:
; CHECK-NEXT: br label [[IF_END225]]
; CHECK: if.end225:
-; CHECK-NEXT: br i1 %arg, label [[RETURN]], label [[IF_END248:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[RETURN]], label [[IF_END248:%.*]]
; CHECK: if.end248:
-; CHECK-NEXT: br i1 %arg, label [[RETURN]], label [[IF_END304:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[RETURN]], label [[IF_END304:%.*]]
; CHECK: if.end304:
-; CHECK-NEXT: br i1 %arg, label [[RETURN]], label [[IF_END361:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[RETURN]], label [[IF_END361:%.*]]
; CHECK: if.end361:
-; CHECK-NEXT: br i1 %arg, label [[IF_THEN370:%.*]], label [[IF_END395:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[IF_THEN370:%.*]], label [[IF_END395:%.*]]
; CHECK: if.then370:
-; CHECK-NEXT: br i1 %arg, label [[IF_THEN374:%.*]], label [[IF_END395]]
+; CHECK-NEXT: br i1 [[ARG]], label [[IF_THEN374:%.*]], label [[IF_END395]]
; CHECK: if.then374:
; CHECK-NEXT: br label [[IF_END395]]
; CHECK: if.end395:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
index b5478ef3fb622..703c861521756 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_clear_undefs.ll
@@ -18,7 +18,7 @@ define i1 @foo() {
; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr null, align 4
; CHECK-NEXT: br i1 false, label [[TMP11:%.*]], label [[TMP2:%.*]]
; CHECK: 2:
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> <float undef, float 0.000000e+00>, float [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> <float undef, float 0.000000e+00>, float [[TMP1]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x float> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_cmpop.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_cmpop.ll
index 3b98a3f689025..216e01d8f6631 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_cmpop.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_cmpop.ll
@@ -19,7 +19,7 @@ define void @testfunc(ptr nocapture %dest, ptr nocapture readonly %src) {
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[DEST:%.*]], i64 [[INDVARS_IV]]
; CHECK-NEXT: store float [[ACC1_056]], ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x float> [[TMP0]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x float> [[TMP0]], [[SHUFFLE]]
; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
@@ -29,11 +29,11 @@ define void @testfunc(ptr nocapture %dest, ptr nocapture readonly %src) {
; CHECK-NEXT: [[TMP15:%.*]] = fcmp olt <2 x float> [[TMP7]], splat (float -1.000000e+00)
; CHECK-NEXT: [[TMP9:%.*]] = fmul <2 x float> [[TMP7]], zeroinitializer
; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[TMP15]], <2 x float> splat (float -0.000000e+00), <2 x float> [[TMP9]]
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x float> [[TMP10]], i32 0
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x float> [[TMP10]], i32 1
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x float> [[TMP10]], i64 0
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x float> [[TMP10]], i64 1
; CHECK-NEXT: [[ADD13]] = fadd float [[TMP12]], [[TMP11]]
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x float> [[TMP10]], <2 x float> poison, <2 x i32> <i32 poison, i32 0>
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x float> [[TMP16]], float [[ADD13]], i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x float> [[TMP16]], float [[ADD13]], i64 0
; CHECK-NEXT: [[TMP17:%.*]] = fcmp olt <2 x float> [[TMP14]], splat (float 1.000000e+00)
; CHECK-NEXT: [[TMP20:%.*]] = select <2 x i1> [[TMP17]], <2 x float> [[TMP14]], <2 x float> splat (float 1.000000e+00)
; CHECK-NEXT: [[TMP19:%.*]] = fcmp olt <2 x float> [[TMP20]], splat (float -1.000000e+00)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll
index faf4496ce2722..2138116f23104 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll
@@ -11,18 +11,18 @@ define void @_ZSt6uniqueISt15_Deque_iteratorIdRdPdEET_S4_S4_(ptr %__first, ptr n
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__FIRST:%.*]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x ptr>, ptr [[__LAST:%.*]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[TMP0]], i32 0
-; CHECK-NEXT: br i1 %arg, label [[_ZST13ADJACENT_FINDIST15_DEQUE_ITERATORIDRDPDEET_S4_S4__EXIT:%.*]], label [[WHILE_COND_I_PREHEADER:%.*]]
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[TMP0]], i64 0
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[_ZST13ADJACENT_FINDIST15_DEQUE_ITERATORIDRDPDEET_S4_S4__EXIT:%.*]], label [[WHILE_COND_I_PREHEADER:%.*]]
; CHECK: while.cond.i.preheader:
; CHECK-NEXT: br label [[WHILE_COND_I:%.*]]
; CHECK: while.cond.i:
-; CHECK-NEXT: br i1 %arg, label [[_ZST13ADJACENT_FINDIST15_DEQUE_ITERATORIDRDPDEET_S4_S4__EXIT]], label [[WHILE_BODY_I:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[_ZST13ADJACENT_FINDIST15_DEQUE_ITERATORIDRDPDEET_S4_S4__EXIT]], label [[WHILE_BODY_I:%.*]]
; CHECK: while.body.i:
-; CHECK-NEXT: br i1 %arg, label [[_ZST13ADJACENT_FINDIST15_DEQUE_ITERATORIDRDPDEET_S4_S4__EXIT]], label [[WHILE_COND_I]]
+; CHECK-NEXT: br i1 [[ARG]], label [[_ZST13ADJACENT_FINDIST15_DEQUE_ITERATORIDRDPDEET_S4_S4__EXIT]], label [[WHILE_COND_I]]
; CHECK: _ZSt13adjacent_findISt15_Deque_iteratorIdRdPdEET_S4_S4_.exit:
; CHECK-NEXT: [[TMP3:%.*]] = phi <2 x ptr> [ [[TMP2]], [[ENTRY:%.*]] ], [ [[TMP1]], [[WHILE_COND_I]] ], [ undef, [[WHILE_BODY_I]] ]
; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[__FIRST]], align 8
-; CHECK-NEXT: br i1 %arg, label [[IF_THEN_I55:%.*]], label [[WHILE_COND:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[IF_THEN_I55:%.*]], label [[WHILE_COND:%.*]]
; CHECK: if.then.i55:
; CHECK-NEXT: br label [[WHILE_COND]]
; CHECK: while.cond:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll
index 403a610da8d55..48a8591c900a8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll
@@ -27,17 +27,17 @@ define void @main(i1 %arg) {
; CHECK-NEXT: [[ADD19]] = fadd double undef, [[MUL18]]
; CHECK-NEXT: [[SUB:%.*]] = fsub double [[MUL13]], [[MUL14]]
; CHECK-NEXT: [[ADD20]] = fadd double undef, [[SUB]]
-; CHECK-NEXT: br i1 %arg, label [[FOR_BODY12]], label [[FOR_INC21]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_BODY12]], label [[FOR_INC21]]
; CHECK: for.inc21:
-; CHECK-NEXT: br i1 %arg, label [[FOR_END23:%.*]], label [[FOR_BODY6]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_END23:%.*]], label [[FOR_BODY6]]
; CHECK: for.end23:
-; CHECK-NEXT: br i1 %arg, label [[IF_THEN25:%.*]], label [[IF_THEN26:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[IF_THEN25:%.*]], label [[IF_THEN26:%.*]]
; CHECK: if.then25:
-; CHECK-NEXT: br i1 %arg, label [[FOR_END44:%.*]], label [[FOR_COND4_PREHEADER]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_END44:%.*]], label [[FOR_COND4_PREHEADER]]
; CHECK: if.then26:
; CHECK-NEXT: unreachable
; CHECK: for.end44:
-; CHECK-NEXT: br i1 %arg, label [[FOR_END48:%.*]], label [[FOR_BODY]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_END48:%.*]], label [[FOR_BODY]]
; CHECK: for.end48:
; CHECK-NEXT: ret void
;
@@ -96,13 +96,13 @@ define void @zot(ptr %arg, i1 %arg2) {
; CHECK-NEXT: [[TMP:%.*]] = load double, ptr undef, align 8
; CHECK-NEXT: [[TMP2:%.*]] = load double, ptr undef, align 8
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_HOGE:%.*]], ptr [[ARG:%.*]], i64 0, i32 1
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[TMP]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[TMP]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> [[TMP1]], undef
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP2]], undef
; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP3]], undef
; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[TMP7]], align 8
-; CHECK-NEXT: br i1 %arg2, label [[BB11:%.*]], label [[BB12:%.*]]
+; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB11:%.*]], label [[BB12:%.*]]
; CHECK: bb11:
; CHECK-NEXT: br label [[BB14:%.*]]
; CHECK: bb12:
@@ -144,11 +144,11 @@ define void @rc4_crypt(ptr nocapture %s, i1 %arg) {
; CHECK-LABEL: @rc4_crypt(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[Y2:%.*]] = getelementptr inbounds [[STRUCT_RC4_STATE_0_24:%.*]], ptr [[S:%.*]], i64 0, i32 1
-; CHECK-NEXT: br i1 %arg, label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[CONV4:%.*]] = and i32 undef, 255
; CHECK-NEXT: [[CONV7:%.*]] = and i32 undef, 255
-; CHECK-NEXT: br i1 %arg, label [[FOR_END]], label [[FOR_BODY]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_END]], label [[FOR_BODY]]
; CHECK: for.end:
; CHECK-NEXT: [[X_0_LCSSA:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[CONV4]], [[FOR_BODY]] ]
; CHECK-NEXT: [[Y_0_LCSSA:%.*]] = phi i32 [ undef, [[ENTRY]] ], [ [[CONV7]], [[FOR_BODY]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltpoison.ll
index 6f0521066f0d8..c51d90fa5308f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltpoison.ll
@@ -14,10 +14,10 @@ define void @_foo(double %p1, double %p2, double %p3) #0 {
; CHECK: [[BB1]]:
; CHECK-NEXT: [[MUL20:%.*]] = fmul double [[P3]], 1.638400e+04
; CHECK-NEXT: [[ADD:%.*]] = fadd double [[MUL20]], 8.192000e+03
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[P2]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[P1]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[P2]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[P1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP1]], splat (double 1.638400e+04)
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[ADD]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[ADD]], i64 0
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
; CHECK-NEXT: [[INDVARS_IV266:%.*]] = phi i64 [ 0, %[[BB1]] ], [ [[INDVARS_IV_NEXT267:%.*]], %[[FOR_BODY]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll
index 2d9e1f79e827c..d9dcf65b4e737 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling.ll
@@ -14,10 +14,10 @@ define void @_foo(double %p1, double %p2, double %p3) #0 {
; CHECK: [[BB1]]:
; CHECK-NEXT: [[MUL20:%.*]] = fmul double [[P3]], 1.638400e+04
; CHECK-NEXT: [[ADD:%.*]] = fadd double [[MUL20]], 8.192000e+03
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[P2]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[P1]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[P2]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[P1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP1]], splat (double 1.638400e+04)
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[ADD]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[ADD]], i64 0
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
; CHECK-NEXT: [[INDVARS_IV266:%.*]] = phi i64 [ 0, %[[BB1]] ], [ [[INDVARS_IV_NEXT267:%.*]], %[[FOR_BODY]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
index d434035051f5e..56e138f3dfbc6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
@@ -9,39 +9,39 @@ target triple = "x86_64-apple-macosx10.8.0"
define void @SIM4(i1 %arg) {
; CHECK-LABEL: @SIM4(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br i1 %arg, label [[RETURN:%.*]], label [[LOR_LHS_FALSE:%.*]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[RETURN:%.*]], label [[LOR_LHS_FALSE:%.*]]
; CHECK: lor.lhs.false:
-; CHECK-NEXT: br i1 %arg, label [[RETURN]], label [[IF_END:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[RETURN]], label [[IF_END:%.*]]
; CHECK: if.end:
-; CHECK-NEXT: br i1 %arg, label [[FOR_END605:%.*]], label [[FOR_BODY_LR_PH:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_END605:%.*]], label [[FOR_BODY_LR_PH:%.*]]
; CHECK: for.body.lr.ph:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: br i1 %arg, label [[FOR_INC603:%.*]], label [[IF_END12:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_INC603:%.*]], label [[IF_END12:%.*]]
; CHECK: if.end12:
-; CHECK-NEXT: br i1 %arg, label [[LAND_LHS_TRUE:%.*]], label [[LAND_LHS_TRUE167:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[LAND_LHS_TRUE:%.*]], label [[LAND_LHS_TRUE167:%.*]]
; CHECK: land.lhs.true:
-; CHECK-NEXT: br i1 %arg, label [[IF_THEN17:%.*]], label [[LAND_LHS_TRUE167]]
+; CHECK-NEXT: br i1 [[ARG]], label [[IF_THEN17:%.*]], label [[LAND_LHS_TRUE167]]
; CHECK: if.then17:
-; CHECK-NEXT: br i1 %arg, label [[IF_END98:%.*]], label [[LAND_RHS_LR_PH:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[IF_END98:%.*]], label [[LAND_RHS_LR_PH:%.*]]
; CHECK: land.rhs.lr.ph:
; CHECK-NEXT: unreachable
; CHECK: if.end98:
-; CHECK-NEXT: br i1 %arg, label [[LAND_LHS_TRUE167]], label [[IF_THEN103:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[LAND_LHS_TRUE167]], label [[IF_THEN103:%.*]]
; CHECK: if.then103:
; CHECK-NEXT: [[DOTSUB100:%.*]] = select i1 undef, i32 250, i32 undef
; CHECK-NEXT: [[MUL114:%.*]] = shl nsw i32 [[DOTSUB100]], 2
; CHECK-NEXT: [[COND125:%.*]] = select i1 undef, i32 undef, i32 [[MUL114]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[COND125]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[DOTSUB100]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[COND125]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[DOTSUB100]], i64 1
; CHECK-NEXT: br label [[FOR_COND_I:%.*]]
; CHECK: for.cond.i:
; CHECK-NEXT: [[TMP2:%.*]] = phi <2 x i32> [ undef, [[LAND_RHS_I874:%.*]] ], [ [[TMP1]], [[IF_THEN103]] ]
-; CHECK-NEXT: br i1 %arg, label [[LAND_RHS_I874]], label [[FOR_END_I:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[LAND_RHS_I874]], label [[FOR_END_I:%.*]]
; CHECK: land.rhs.i874:
-; CHECK-NEXT: br i1 %arg, label [[FOR_COND_I]], label [[FOR_END_I]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_COND_I]], label [[FOR_END_I]]
; CHECK: for.end.i:
-; CHECK-NEXT: br i1 %arg, label [[IF_THEN_I:%.*]], label [[IF_END_I:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[IF_THEN_I:%.*]], label [[IF_END_I:%.*]]
; CHECK: if.then.i:
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i32> [[TMP2]], undef
; CHECK-NEXT: br label [[EXTEND_BW_EXIT:%.*]]
@@ -52,15 +52,15 @@ define void @SIM4(i1 %arg) {
; CHECK: for.body28.lr.ph.i:
; CHECK-NEXT: br label [[FOR_END33_I]]
; CHECK: for.end33.i:
-; CHECK-NEXT: br i1 %arg, label [[FOR_END58_I:%.*]], label [[FOR_BODY52_LR_PH_I:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_END58_I:%.*]], label [[FOR_BODY52_LR_PH_I:%.*]]
; CHECK: for.body52.lr.ph.i:
; CHECK-NEXT: br label [[FOR_END58_I]]
; CHECK: for.end58.i:
; CHECK-NEXT: br label [[WHILE_COND260_I:%.*]]
; CHECK: while.cond260.i:
-; CHECK-NEXT: br i1 %arg, label [[LAND_RHS263_I:%.*]], label [[WHILE_END275_I:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[LAND_RHS263_I:%.*]], label [[WHILE_END275_I:%.*]]
; CHECK: land.rhs263.i:
-; CHECK-NEXT: br i1 %arg, label [[WHILE_COND260_I]], label [[WHILE_END275_I]]
+; CHECK-NEXT: br i1 [[ARG]], label [[WHILE_COND260_I]], label [[WHILE_END275_I]]
; CHECK: while.end275.i:
; CHECK-NEXT: br label [[EXTEND_BW_EXIT]]
; CHECK: extend_bw.exit:
@@ -73,7 +73,7 @@ define void @SIM4(i1 %arg) {
; CHECK: land.lhs.true167:
; CHECK-NEXT: unreachable
; CHECK: for.inc603:
-; CHECK-NEXT: br i1 %arg, label [[FOR_BODY]], label [[FOR_END605]]
+; CHECK-NEXT: br i1 [[ARG]], label [[FOR_BODY]], label [[FOR_END605]]
; CHECK: for.end605:
; CHECK-NEXT: unreachable
; CHECK: return:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll
index c7c4b06be2d19..24d781dccc55c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll
@@ -32,26 +32,26 @@ define void @bar(i1 %arg) {
; CHECK-NEXT: store double [[I7]], ptr [[I1]], align 8
; CHECK-NEXT: [[I10]] = load double, ptr [[I3]], align 8
; CHECK-NEXT: [[TMP0]] = load <2 x double>, ptr [[I2]], align 8
-; CHECK-NEXT: br i1 %arg, label [[BB11:%.*]], label [[BB12:%.*]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[BB11:%.*]], label [[BB12:%.*]]
; CHECK: bb11:
; CHECK-NEXT: ret void
; CHECK: bb12:
; CHECK-NEXT: store <2 x double> [[TMP0]], ptr [[I4]], align 8
-; CHECK-NEXT: br i1 %arg, label [[BB13:%.*]], label [[BB14:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[BB13:%.*]], label [[BB14:%.*]]
; CHECK: bb13:
; CHECK-NEXT: br label [[BB14]]
; CHECK: bb14:
-; CHECK-NEXT: br i1 %arg, label [[BB15:%.*]], label [[BB16]]
+; CHECK-NEXT: br i1 [[ARG]], label [[BB15:%.*]], label [[BB16]]
; CHECK: bb15:
; CHECK-NEXT: unreachable
; CHECK: bb16:
-; CHECK-NEXT: [[TMP1]] = extractelement <2 x double> [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1]] = extractelement <2 x double> [[TMP0]], i64 0
; CHECK-NEXT: switch i32 undef, label [[BB17]] [
; CHECK-NEXT: i32 32, label [[BB6]]
; CHECK-NEXT: i32 103, label [[BB6]]
; CHECK-NEXT: ]
; CHECK: bb17:
-; CHECK-NEXT: br i1 %arg, label [[BB6]], label [[BB18:%.*]]
+; CHECK-NEXT: br i1 [[ARG]], label [[BB6]], label [[BB18:%.*]]
; CHECK: bb18:
; CHECK-NEXT: unreachable
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cse.ll b/llvm/test/Transforms/SLPVectorizer/X86/cse.ll
index 26ef502b81f05..888066aea8408 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/cse.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/cse.ll
@@ -57,7 +57,7 @@ define i32 @foo(ptr nocapture %A, i32 %n) {
; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[N:%.*]] to double
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x double>, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = fmul <4 x double> [[TMP0]], <double 7.900000e+00, double 7.700000e+00, double 7.600000e+00, double 7.400000e+00>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> poison, double [[CONV]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> poison, double [[CONV]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fmul <4 x double> [[TMP3]], [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x double> [[TMP4]], <double 6.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00>
@@ -115,8 +115,8 @@ define i32 @test2(ptr nocapture %G, i32 %k) {
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds double, ptr [[G]], i64 6
; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = fmul double [[TMP7]], 3.000000e+00
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x double> poison, double [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x double> [[TMP9]], double [[TMP8]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x double> poison, double [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x double> [[TMP9]], double [[TMP8]], i64 1
; CHECK-NEXT: [[TMP11:%.*]] = fadd <2 x double> [[TMP10]], <double 1.000000e+00, double 6.000000e+00>
; CHECK-NEXT: store <2 x double> [[TMP11]], ptr [[G]], align 8
; CHECK-NEXT: br label [[TMP20:%.*]]
@@ -125,8 +125,8 @@ define i32 @test2(ptr nocapture %G, i32 %k) {
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds double, ptr [[G]], i64 6
; CHECK-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 8
; CHECK-NEXT: [[TMP16:%.*]] = fmul double [[TMP15]], 3.000000e+00
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <2 x double> poison, double [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x double> [[TMP17]], double [[TMP16]], i32 1
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <2 x double> poison, double [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x double> [[TMP17]], double [[TMP16]], i64 1
; CHECK-NEXT: [[TMP19:%.*]] = fadd <2 x double> [[TMP18]], <double 7.000000e+00, double 8.000000e+00>
; CHECK-NEXT: store <2 x double> [[TMP19]], ptr [[TMP13]], align 8
; CHECK-NEXT: br label [[TMP20]]
@@ -180,7 +180,7 @@ define i32 @foo4(ptr nocapture %A, i32 %n) {
; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[N:%.*]] to double
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x double>, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = fmul <4 x double> [[TMP0]], splat (double 7.900000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> poison, double [[CONV]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> poison, double [[CONV]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fmul <4 x double> [[TMP3]], [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x double> [[TMP4]], splat (double 6.000000e+00)
@@ -228,7 +228,7 @@ define i32 @partial_mrg(ptr nocapture %A, i32 %n) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[N:%.*]] to double
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[CONV]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[CONV]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP2]], [[TMP0]]
; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[A]], align 8
@@ -239,7 +239,7 @@ define i32 @partial_mrg(ptr nocapture %A, i32 %n) {
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[N]], 4
; CHECK-NEXT: [[CONV12:%.*]] = sitofp i32 [[ADD]] to double
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr [[ARRAYIDX7]], align 8
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> [[TMP1]], double [[CONV12]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> [[TMP1]], double [[CONV12]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x double> [[TMP5]], [[TMP4]]
; CHECK-NEXT: store <2 x double> [[TMP6]], ptr [[ARRAYIDX7]], align 8
; CHECK-NEXT: br label [[RETURN]]
@@ -331,7 +331,7 @@ if.end13: ; preds = %if.then12, %sw.epil
define void @cse_for_hoisted_instructions_in_preheader(ptr %dst, i32 %a, i1 %c) {
; CHECK-LABEL: @cse_for_hoisted_instructions_in_preheader(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[A:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[A:%.*]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/debug-counter.ll b/llvm/test/Transforms/SLPVectorizer/X86/debug-counter.ll
index 48f7ce2d58c42..bb4da977d63bf 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/debug-counter.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/debug-counter.ll
@@ -10,10 +10,10 @@ define void @blam(ptr %arg, double %load2, i1 %fcmp3) {
; COUNT0-NEXT: bb:
; COUNT0-NEXT: [[GETELEMENTPTR13:%.*]] = getelementptr double, ptr [[ARG]], i64 3
; COUNT0-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[ARG]], align 8
-; COUNT0-NEXT: [[TMP1:%.*]] = insertelement <2 x i1> poison, i1 [[FCMP3]], i32 0
+; COUNT0-NEXT: [[TMP1:%.*]] = insertelement <2 x i1> poison, i1 [[FCMP3]], i64 0
; COUNT0-NEXT: [[TMP2:%.*]] = shufflevector <2 x i1> [[TMP1]], <2 x i1> poison, <2 x i32> zeroinitializer
; COUNT0-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x double> zeroinitializer, <2 x double> [[TMP0]]
-; COUNT0-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP0]], double [[LOAD2]], i32 0
+; COUNT0-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP0]], double [[LOAD2]], i64 0
; COUNT0-NEXT: [[TMP5:%.*]] = fcmp olt <2 x double> [[TMP4]], zeroinitializer
; COUNT0-NEXT: [[TMP6:%.*]] = select <2 x i1> [[TMP5]], <2 x double> zeroinitializer, <2 x double> [[TMP0]]
; COUNT0-NEXT: [[TMP7:%.*]] = fcmp olt <2 x double> [[TMP3]], zeroinitializer
@@ -47,15 +47,15 @@ define void @blam(ptr %arg, double %load2, i1 %fcmp3) {
; COUNT1-NEXT: [[GETELEMENTPTR21:%.*]] = getelementptr double, ptr [[ARG]], i64 4
; COUNT1-NEXT: [[FCMP23:%.*]] = fcmp olt double [[SELECT10]], 0.000000e+00
; COUNT1-NEXT: [[SELECT24:%.*]] = select i1 [[FCMP23]], double 0.000000e+00, double 1.000000e+00
-; COUNT1-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[LOAD2]], i32 1
-; COUNT1-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[SELECT4]], i32 0
+; COUNT1-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[LOAD2]], i64 1
+; COUNT1-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[SELECT4]], i64 0
; COUNT1-NEXT: [[TMP2:%.*]] = fcmp olt <2 x double> [[TMP1]], zeroinitializer
-; COUNT1-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[LOAD7]], i32 1
+; COUNT1-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[LOAD7]], i64 1
; COUNT1-NEXT: [[TMP4:%.*]] = select <2 x i1> [[TMP2]], <2 x double> <double 1.000000e+00, double 0.000000e+00>, <2 x double> [[TMP3]]
; COUNT1-NEXT: [[FCMP33:%.*]] = fcmp olt double [[SELECT24]], [[SELECT3]]
; COUNT1-NEXT: [[SELECT34:%.*]] = select i1 [[FCMP33]], double 0.000000e+00, double [[LOAD2]]
-; COUNT1-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
-; COUNT1-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
+; COUNT1-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
+; COUNT1-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i64 1
; COUNT1-NEXT: [[FCMP39:%.*]] = fcmp olt double [[TMP5]], [[TMP6]]
; COUNT1-NEXT: [[SELECT40:%.*]] = select i1 [[FCMP39]], double [[LOAD2]], double 0.000000e+00
; COUNT1-NEXT: [[FCMP62:%.*]] = fcmp olt double [[SELECT34]], 0.000000e+00
@@ -86,15 +86,15 @@ define void @blam(ptr %arg, double %load2, i1 %fcmp3) {
; COUNT2-NEXT: [[SELECT128:%.*]] = select i1 [[FCMP11]], double 0.000000e+00, double [[LOAD7]]
; COUNT2-NEXT: [[GETELEMENTPTR13:%.*]] = getelementptr double, ptr [[ARG]], i64 3
; COUNT2-NEXT: [[GETELEMENTPTR21:%.*]] = getelementptr double, ptr [[ARG]], i64 4
-; COUNT2-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[SELECT10]], i32 0
-; COUNT2-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[LOAD]], i32 1
+; COUNT2-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[SELECT10]], i64 0
+; COUNT2-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[LOAD]], i64 1
; COUNT2-NEXT: [[TMP2:%.*]] = fcmp olt <2 x double> [[TMP1]], zeroinitializer
; COUNT2-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> <double 1.000000e+00, double poison>, <2 x i32> <i32 2, i32 1>
; COUNT2-NEXT: [[TMP4:%.*]] = select <2 x i1> [[TMP2]], <2 x double> zeroinitializer, <2 x double> [[TMP3]]
; COUNT2-NEXT: [[FCMP29:%.*]] = fcmp olt double [[SELECT4]], 0.000000e+00
; COUNT2-NEXT: [[SELECT30:%.*]] = select i1 [[FCMP29]], double 1.000000e+00, double 0.000000e+00
-; COUNT2-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
-; COUNT2-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
+; COUNT2-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
+; COUNT2-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i64 1
; COUNT2-NEXT: [[FCMP33:%.*]] = fcmp olt double [[TMP5]], [[TMP6]]
; COUNT2-NEXT: [[SELECT34:%.*]] = select i1 [[FCMP33]], double 0.000000e+00, double [[LOAD2]]
; COUNT2-NEXT: [[FCMP39:%.*]] = fcmp olt double [[SELECT30]], [[SELECT128]]
@@ -120,10 +120,10 @@ define void @blam(ptr %arg, double %load2, i1 %fcmp3) {
; COUNT-1-NEXT: bb:
; COUNT-1-NEXT: [[GETELEMENTPTR13:%.*]] = getelementptr double, ptr [[ARG]], i64 3
; COUNT-1-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[ARG]], align 8
-; COUNT-1-NEXT: [[TMP1:%.*]] = insertelement <2 x i1> poison, i1 [[FCMP3]], i32 0
+; COUNT-1-NEXT: [[TMP1:%.*]] = insertelement <2 x i1> poison, i1 [[FCMP3]], i64 0
; COUNT-1-NEXT: [[TMP2:%.*]] = shufflevector <2 x i1> [[TMP1]], <2 x i1> poison, <2 x i32> zeroinitializer
; COUNT-1-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x double> zeroinitializer, <2 x double> [[TMP0]]
-; COUNT-1-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP0]], double [[LOAD2]], i32 0
+; COUNT-1-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP0]], double [[LOAD2]], i64 0
; COUNT-1-NEXT: [[TMP5:%.*]] = fcmp olt <2 x double> [[TMP4]], zeroinitializer
; COUNT-1-NEXT: [[TMP6:%.*]] = select <2 x i1> [[TMP5]], <2 x double> zeroinitializer, <2 x double> [[TMP0]]
; COUNT-1-NEXT: [[TMP7:%.*]] = fcmp olt <2 x double> [[TMP3]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll b/llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
index 0a573de35edeb..4a36ddf06fdb3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/debug-info-salvage.ll
@@ -6,38 +6,38 @@ define void @test(i8 %a, i8 %b, ptr %p) {
; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]], ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[ARRAYIDX51_1_I:%.*]] = getelementptr i8, ptr [[P]], i64 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[B]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[A]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[B]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[A]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i16>
; CHECK-NEXT: br label %[[COND_END_I:.*]]
; CHECK: [[COND_END_I]]:
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i16> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i16> [[TMP2]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP3]] to i32
; CHECK-NEXT: [[ADD46_I30:%.*]] = or i32 0, [[TMP4]]
; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i16> zeroinitializer, [[TMP2]]
; CHECK-NEXT: #dbg_value(!DIArgList(i32 0, i8 [[A]]), [[META3:![0-9]+]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_convert, 8, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_or, DW_OP_stack_value), [[META7:![0-9]+]])
; CHECK-NEXT: [[TMP6:%.*]] = tail call i32 @llvm.umin.i32(i32 [[ADD46_I30]], i32 0)
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[TMP6]], i32 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i16> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[TMP6]], i64 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i16> [[TMP2]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = zext i16 [[TMP8]] to i32
; CHECK-NEXT: [[ADD49_1_I:%.*]] = or i32 0, [[TMP9]]
; CHECK-NEXT: [[TMP10:%.*]] = icmp slt <2 x i16> [[TMP5]], zeroinitializer
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <2 x i1> <i1 poison, i1 false>, <2 x i1> [[TMP10]], <2 x i32> <i32 3, i32 1>
; CHECK-NEXT: [[TMP12:%.*]] = select <2 x i1> [[TMP11]], <2 x i32> zeroinitializer, <2 x i32> [[TMP7]]
; CHECK-NEXT: [[TMP13:%.*]] = shl <2 x i32> [[TMP12]], <i32 16, i32 0>
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i32> [[TMP13]], i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i32> [[TMP13]], i64 0
; CHECK-NEXT: [[OP_RDX:%.*]] = or i32 0, [[TMP14]]
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i32> [[TMP13]], i32 1
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i32> [[TMP13]], i64 1
; CHECK-NEXT: [[OP_RDX1:%.*]] = or i32 [[OP_RDX]], [[TMP15]]
; CHECK-NEXT: store i32 [[OP_RDX1]], ptr null, align 4
; CHECK-NEXT: [[TMP16:%.*]] = tail call i32 @llvm.umin.i32(i32 [[ADD49_1_I]], i32 0)
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <2 x i1> <i1 false, i1 poison>, <2 x i1> [[TMP10]], <2 x i32> <i32 0, i32 2>
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[TMP16]], i32 0
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[TMP16]], i64 0
; CHECK-NEXT: [[TMP19:%.*]] = select <2 x i1> [[TMP17]], <2 x i32> zeroinitializer, <2 x i32> [[TMP18]]
; CHECK-NEXT: [[TMP20:%.*]] = shl <2 x i32> [[TMP19]], <i32 16, i32 0>
-; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i32> [[TMP20]], i32 0
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i32> [[TMP20]], i64 0
; CHECK-NEXT: [[OP_RDX2:%.*]] = or i32 0, [[TMP21]]
-; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i32> [[TMP20]], i32 1
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <2 x i32> [[TMP20]], i64 1
; CHECK-NEXT: [[OP_RDX3:%.*]] = or i32 [[OP_RDX2]], [[TMP22]]
; CHECK-NEXT: store i32 [[OP_RDX3]], ptr [[ARRAYIDX51_1_I]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll b/llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll
index 421257d611062..2e61ebdf6752a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/delayed-gather-emission.ll
@@ -21,13 +21,13 @@ define void @test() {
; CHECK-NEXT: [[I:%.*]] = phi float [ [[DOTPRE]], [[BB1]] ], [ [[I2]], [[BB2]] ]
; CHECK-NEXT: [[GULF_0]] = phi float [ [[FOXTROT_0]], [[BB1]] ], [ [[TMP6:%.*]], [[BB2]] ]
; CHECK-NEXT: [[I1:%.*]] = load float, ptr poison, align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[I]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[GULF_0]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[GULF_0]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[I1]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[I]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[GULF_0]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[GULF_0]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[I1]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = fdiv <2 x float> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP6]] = extractelement <2 x float> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x float> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP6]] = extractelement <2 x float> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x float> [[TMP4]], i64 1
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP6]], [[TMP7]]
; CHECK-NEXT: tail call void @foo(float [[MUL]])
; CHECK-NEXT: [[I2]] = load float, ptr poison, align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/deleted-inst-reduction-attempt.ll b/llvm/test/Transforms/SLPVectorizer/X86/deleted-inst-reduction-attempt.ll
index 5c2e22eace0d2..4d8233844404c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/deleted-inst-reduction-attempt.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/deleted-inst-reduction-attempt.ll
@@ -4,14 +4,14 @@
define double @test(ptr %0, double %1) {
; CHECK-LABEL: define double @test(
; CHECK-SAME: ptr [[TMP0:%.*]], double [[TMP1:%.*]]) {
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[TMP1]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = tail call double @llvm.exp.f64(double +qnan)
; CHECK-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr [[TMP0]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP7]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 poison>
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x double> poison, double [[TMP6]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x double> poison, double [[TMP6]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP10]], <4 x double> poison, <4 x i32> <i32 poison, i32 poison, i32 poison, i32 0>
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x double> [[TMP12]], <4 x double> [[TMP11]], <4 x i32> <i32 poison, i32 poison, i32 0, i32 7>
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x double> [[TMP8]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
@@ -22,11 +22,11 @@ define double @test(ptr %0, double %1) {
; CHECK-NEXT: [[TMP19:%.*]] = fadd <4 x double> [[TMP16]], [[TMP18]]
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <4 x double> [[TMP15]], <4 x double> <double 0.000000e+00, double poison, double 0.000000e+00, double 1.000000e+00>, <4 x i32> <i32 4, i32 3, i32 6, i32 7>
; CHECK-NEXT: [[TMP21:%.*]] = fmul <4 x double> [[TMP20]], [[TMP19]]
-; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x double> [[TMP21]], i32 0
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x double> [[TMP16]], i32 0
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x double> [[TMP21]], i64 0
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x double> [[TMP16]], i64 0
; CHECK-NEXT: [[TMP24:%.*]] = fadd double [[TMP23]], [[TMP22]]
-; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x double> [[TMP21]], i32 1
-; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x double> [[TMP21]], i32 2
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <4 x double> [[TMP21]], i64 1
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x double> [[TMP21]], i64 2
; CHECK-NEXT: [[TMP27:%.*]] = fadd double [[TMP25]], [[TMP26]]
; CHECK-NEXT: [[TMP28:%.*]] = fadd double [[TMP27]], [[TMP6]]
; CHECK-NEXT: [[TMP29:%.*]] = fadd double [[TMP24]], [[TMP28]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll b/llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
index a978a35cfd2d8..ae6da0913cc24 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
@@ -5,8 +5,8 @@ define void @test(i32 %arg, i32 %arg1, i64 %arg2) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]], i64 [[ARG2:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[BB:.*]]:
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 poison>, i32 [[ARG]], i32 3
-; CHECK-NEXT: [[TMP27:%.*]] = insertelement <2 x i32> poison, i32 [[ARG1]], i32 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 poison>, i32 [[ARG]], i64 3
+; CHECK-NEXT: [[TMP27:%.*]] = insertelement <2 x i32> poison, i32 [[ARG1]], i64 0
; CHECK-NEXT: [[TMP28:%.*]] = shufflevector <2 x i32> [[TMP27]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label %[[BB3:.*]]
; CHECK: [[BB3]]:
@@ -16,31 +16,31 @@ define void @test(i32 %arg, i32 %arg1, i64 %arg2) {
; CHECK-NEXT: [[TRUNC19:%.*]] = trunc i64 [[ADD18]] to i32
; CHECK-NEXT: [[TRUNC28:%.*]] = trunc i64 [[ARG2]] to i32
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[TMP3]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 poison, i32 0>, i32 [[TRUNC]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 poison, i32 0>, i32 [[TRUNC]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i32> zeroinitializer, [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP5]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP5]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP4]] to i64
; CHECK-NEXT: [[TRUNC10:%.*]] = trunc i64 [[TMP10]] to i32
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP5]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP5]], i64 2
; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
; CHECK-NEXT: [[TRUNC27:%.*]] = trunc i64 [[TMP7]] to i32
; CHECK-NEXT: [[OR11:%.*]] = or i32 [[TRUNC27]], 0
; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i32> zeroinitializer, [[TMP2]]
; CHECK-NEXT: [[TMP9:%.*]] = mul <4 x i32> [[TMP5]], [[TMP8]]
; CHECK-NEXT: [[XOR38:%.*]] = xor i32 [[ARG]], [[TRUNC28]]
-; CHECK-NEXT: [[TMP29:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[TRUNC19]], i32 0
+; CHECK-NEXT: [[TMP29:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[TRUNC19]], i64 0
; CHECK-NEXT: [[TMP14:%.*]] = xor <2 x i32> [[TMP28]], [[TMP29]]
; CHECK-NEXT: [[SHL:%.*]] = shl i32 0, 1
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i32> poison, i32 [[SHL]], i32 0
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP23]], i32 [[TRUNC10]], i32 1
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TRUNC27]], i32 3
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i32> poison, i32 [[SHL]], i64 0
+; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i32> [[TMP23]], i32 [[TRUNC10]], i64 1
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP31]], i32 [[TRUNC27]], i64 3
; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i32> [[TMP13]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
; CHECK-NEXT: [[TMP26:%.*]] = xor <4 x i32> [[TMP11]], [[TMP25]]
; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <4 x i32> [[TMP26]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP30:%.*]] = shufflevector <2 x i32> [[TMP14]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <8 x i32> [[TMP24]], <8 x i32> [[TMP30]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 9, i32 7>
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x i32> [[TMP15]], i32 [[XOR38]], i32 7
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x i32> [[TMP15]], i32 [[XOR38]], i64 7
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <8 x i32> [[TMP16]], <8 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <8 x i32> [[TMP17]], <8 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <4 x i32> [[TMP9]], <4 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/deleted-node-with-copyable-operands.ll b/llvm/test/Transforms/SLPVectorizer/X86/deleted-node-with-copyable-operands.ll
index c18f2a3e7da1a..8fd7d2f61a8d0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/deleted-node-with-copyable-operands.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/deleted-node-with-copyable-operands.ll
@@ -5,7 +5,7 @@ define void @test(ptr %0, ptr %1, i1 %cond, double %2) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]], i1 [[COND:%.*]], double [[TMP2:%.*]]) {
; CHECK-NEXT: [[ITER_CHECK:.*]]:
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double poison>, double [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double poison>, double [[TMP2]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 0>
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> <double 0.000000e+00, double 0.000000e+00, double poison, double 0.000000e+00>, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
; CHECK-NEXT: br [[DOTLR_PH383_US_US_US_US:label %.*]]
@@ -20,9 +20,9 @@ define void @test(ptr %0, ptr %1, i1 %cond, double %2) {
; CHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP0]], align 8
; CHECK-NEXT: [[TMP10:%.*]] = load double, ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP11:%.*]] = fmul double [[TMP9]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x double> poison, double [[TMP9]], i32 0
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x double> [[TMP12]], double [[TMP10]], i32 2
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x double> [[TMP13]], double [[TMP11]], i32 3
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x double> poison, double [[TMP9]], i64 0
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x double> [[TMP12]], double [[TMP10]], i64 2
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x double> [[TMP13]], double [[TMP11]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[TMP14]], <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
; CHECK-NEXT: [[TMP21:%.*]] = fadd <4 x double> [[TMP20]], [[TMP5]]
; CHECK-NEXT: br label %[[BB16]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/diamond.ll b/llvm/test/Transforms/SLPVectorizer/X86/diamond.ll
index 1b34d31eb623d..1199e838bf853 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/diamond.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/diamond.ll
@@ -17,7 +17,7 @@ define i32 @foo(ptr noalias nocapture %B, ptr noalias nocapture %A, i32 %n, i32
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MUL238:%.*]] = add i32 [[M:%.*]], [[N:%.*]]
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[A:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[MUL238]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[MUL238]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> [[TMP0]], [[TMP2]]
; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr [[B:%.*]], align 4
@@ -61,7 +61,7 @@ define i32 @extr_user(ptr noalias nocapture %B, ptr noalias nocapture %A, i32 %n
; CHECK-NEXT: [[MUL238:%.*]] = add i32 [[M:%.*]], [[N:%.*]]
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[A:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[MUL238]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[MUL238]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = mul <4 x i32> [[TMP0]], [[TMP3]]
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[B:%.*]], align 4
@@ -98,7 +98,7 @@ define i32 @extr_user1(ptr noalias nocapture %B, ptr noalias nocapture %A, i32 %
; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 1
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[A]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[MUL238]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[MUL238]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = mul <4 x i32> [[TMP0]], [[TMP3]]
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[B:%.*]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/diamond_broadcast_extra_shuffle.ll b/llvm/test/Transforms/SLPVectorizer/X86/diamond_broadcast_extra_shuffle.ll
index f1c5c7596d97c..6dcb62822b559 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/diamond_broadcast_extra_shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/diamond_broadcast_extra_shuffle.ll
@@ -5,7 +5,7 @@ define i32 @diamond_broadcast(ptr noalias nocapture %B, ptr noalias nocapture %A
; CHECK-LABEL: @diamond_broadcast(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[A:%.*]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LD]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[SHUFFLE]], [[SHUFFLE]]
; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[B:%.*]], align 4
@@ -31,7 +31,7 @@ define i32 @diamond_broadcast2(ptr noalias nocapture %B, ptr noalias nocapture %
; CHECK-LABEL: @diamond_broadcast2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[A:%.*]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LD]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[SHUFFLE]], [[SHUFFLE]]
; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[B:%.*]], align 4
@@ -57,7 +57,7 @@ define i32 @diamond_broadcast3(ptr noalias nocapture %B, ptr noalias nocapture %
; CHECK-LABEL: @diamond_broadcast3(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[A:%.*]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LD]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[SHUFFLE]], [[SHUFFLE]]
; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[B:%.*]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll b/llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll
index ac83da048182e..1ce21a280b602 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll
@@ -12,14 +12,14 @@ define i8 @test(ptr %g_127, i32 %0, i16 %1) {
; CHECK-NEXT: [[TMP2:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ 60, %[[FOR_COND166_PREHEADER_I]] ]
; CHECK-NEXT: [[CONV8_I_I:%.*]] = zext nneg i32 [[TMP0]] to i64
; CHECK-NEXT: [[DIV_I_I_1:%.*]] = udiv i64 [[CONV8_I_I]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> poison, i64 [[CONV8_I_I]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> poison, i64 [[CONV8_I_I]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i64> [[TMP3]], <4 x i64> poison, <4 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i64> poison, i64 [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i64> poison, i64 [[TMP2]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = udiv <4 x i64> [[TMP4]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = trunc <4 x i64> [[TMP7]] to <4 x i16>
; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[DIV_I_I_1]] to i16
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i16> poison, i16 [[TMP9]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i16> poison, i16 [[TMP9]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i16> [[TMP8]], <4 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <8 x i16> [[TMP10]], <8 x i16> [[TMP11]], <8 x i32> <i32 0, i32 8, i32 9, i32 10, i32 11, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i16> [[TMP12]], <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 2, i32 3, i32 3, i32 4, i32 4>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll b/llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
index 68ffc15b063ba..c499aea3819c7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/dot-product.ll
@@ -13,12 +13,12 @@ define double @dot4f64(ptr dereferenceable(32) %ptrx, ptr dereferenceable(32) %p
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr [[PTRX:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr [[PTRY:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x double> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP3]], i64 1
; CHECK-NEXT: [[DOT01:%.*]] = fadd double [[TMP4]], [[TMP5]]
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP3]], i64 2
; CHECK-NEXT: [[DOT012:%.*]] = fadd double [[DOT01]], [[TMP6]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP3]], i64 3
; CHECK-NEXT: [[DOT0123:%.*]] = fadd double [[DOT012]], [[TMP7]]
; CHECK-NEXT: ret double [[DOT0123]]
;
@@ -51,12 +51,12 @@ define float @dot4f32(ptr dereferenceable(16) %ptrx, ptr dereferenceable(16) %pt
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[PTRX:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[PTRY:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x float> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[TMP3]], i64 1
; CHECK-NEXT: [[DOT01:%.*]] = fadd float [[TMP7]], [[TMP8]]
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x float> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x float> [[TMP3]], i64 2
; CHECK-NEXT: [[DOT012:%.*]] = fadd float [[DOT01]], [[TMP9]]
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x float> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
; CHECK-NEXT: [[DOT0123:%.*]] = fadd float [[DOT012]], [[TMP10]]
; CHECK-NEXT: ret float [[DOT0123]]
;
@@ -162,9 +162,9 @@ define double @dot3f64(ptr dereferenceable(32) %ptrx, ptr dereferenceable(32) %p
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[PTRX1]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[PTRY1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i64 0
; CHECK-NEXT: [[DOT01:%.*]] = fadd double [[MUL0]], [[TMP4]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i64 1
; CHECK-NEXT: [[DOT012:%.*]] = fadd double [[DOT01]], [[TMP5]]
; CHECK-NEXT: ret double [[DOT012]]
;
@@ -196,9 +196,9 @@ define float @dot3f32(ptr dereferenceable(16) %ptrx, ptr dereferenceable(16) %pt
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[PTRX1]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[PTRY1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i64 0
; CHECK-NEXT: [[DOT01:%.*]] = fadd float [[MUL0]], [[TMP4]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i64 1
; CHECK-NEXT: [[DOT012:%.*]] = fadd float [[DOT01]], [[TMP5]]
; CHECK-NEXT: ret float [[DOT012]]
;
@@ -230,9 +230,9 @@ define double @dot3f64_fast(ptr dereferenceable(32) %ptrx, ptr dereferenceable(3
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[PTRX1]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[PTRY1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i64 0
; CHECK-NEXT: [[DOT01:%.*]] = fadd fast double [[MUL0]], [[TMP4]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i64 1
; CHECK-NEXT: [[DOT012:%.*]] = fadd fast double [[DOT01]], [[TMP5]]
; CHECK-NEXT: ret double [[DOT012]]
;
@@ -264,9 +264,9 @@ define float @dot3f32_fast(ptr dereferenceable(16) %ptrx, ptr dereferenceable(16
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[PTRX1]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[PTRY1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i64 0
; CHECK-NEXT: [[DOT01:%.*]] = fadd fast float [[MUL0]], [[TMP4]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i64 1
; CHECK-NEXT: [[DOT012:%.*]] = fadd fast float [[DOT01]], [[TMP5]]
; CHECK-NEXT: ret float [[DOT012]]
;
@@ -297,8 +297,8 @@ define double @dot2f64(ptr dereferenceable(16) %ptrx, ptr dereferenceable(16) %p
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[PTRX:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[PTRY:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i64 1
; CHECK-NEXT: [[DOT01:%.*]] = fadd double [[TMP4]], [[TMP5]]
; CHECK-NEXT: ret double [[DOT01]]
;
@@ -319,8 +319,8 @@ define float @dot2f32(ptr dereferenceable(16) %ptrx, ptr dereferenceable(16) %pt
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[PTRX:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[PTRY:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i64 1
; CHECK-NEXT: [[DOT01:%.*]] = fadd float [[TMP4]], [[TMP5]]
; CHECK-NEXT: ret float [[DOT01]]
;
@@ -348,8 +348,8 @@ define double @dot2f64_fast(ptr dereferenceable(16) %ptrx, ptr dereferenceable(1
; SSE4-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[PTRX:%.*]], align 4
; SSE4-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[PTRY:%.*]], align 4
; SSE4-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP1]], [[TMP2]]
-; SSE4-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
-; SSE4-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
+; SSE4-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i64 0
+; SSE4-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i64 1
; SSE4-NEXT: [[DOT01:%.*]] = fadd fast double [[TMP4]], [[TMP5]]
; SSE4-NEXT: ret double [[DOT01]]
;
@@ -357,8 +357,8 @@ define double @dot2f64_fast(ptr dereferenceable(16) %ptrx, ptr dereferenceable(1
; AVX-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[PTRX:%.*]], align 4
; AVX-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[PTRY:%.*]], align 4
; AVX-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP1]], [[TMP2]]
-; AVX-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
-; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
+; AVX-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i64 0
+; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i64 1
; AVX-NEXT: [[DOT01:%.*]] = fadd fast double [[TMP4]], [[TMP5]]
; AVX-NEXT: ret double [[DOT01]]
;
@@ -398,8 +398,8 @@ define float @dot2f32_fast(ptr dereferenceable(16) %ptrx, ptr dereferenceable(16
; SSE4-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[PTRX:%.*]], align 4
; SSE4-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[PTRY:%.*]], align 4
; SSE4-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP1]], [[TMP2]]
-; SSE4-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
-; SSE4-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; SSE4-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i64 0
+; SSE4-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i64 1
; SSE4-NEXT: [[DOT01:%.*]] = fadd fast float [[TMP4]], [[TMP5]]
; SSE4-NEXT: ret float [[DOT01]]
;
@@ -407,8 +407,8 @@ define float @dot2f32_fast(ptr dereferenceable(16) %ptrx, ptr dereferenceable(16
; AVX-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[PTRX:%.*]], align 4
; AVX-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[PTRY:%.*]], align 4
; AVX-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP1]], [[TMP2]]
-; AVX-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
-; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
+; AVX-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i64 0
+; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i64 1
; AVX-NEXT: [[DOT01:%.*]] = fadd fast float [[TMP4]], [[TMP5]]
; AVX-NEXT: ret float [[DOT01]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll b/llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
index 38dddb064b751..a46467563bb24 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
@@ -6,12 +6,12 @@ define i1 @test(i64 %v) {
; CHECK-SAME: (i64 [[V:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[V]], 3
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> <i64 poison, i64 poison, i64 0, i64 0>, i64 [[V]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> <i64 poison, i64 poison, i64 0, i64 0>, i64 [[V]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> <i64 7, i64 undef, i64 0, i64 0>, i64 [[V]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> <i64 7, i64 undef, i64 0, i64 0>, i64 [[V]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i64> [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 0, i32 3, i32 1>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i64> <i64 poison, i64 poison, i64 poison, i64 poison, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i64> <i64 poison, i64 poison, i64 poison, i64 poison, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i64> [[TMP6]], <8 x i64> poison, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i64> [[TMP7]], [[TMP5]]
; CHECK-NEXT: [[TMP9:%.*]] = sub <8 x i64> [[TMP7]], [[TMP5]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/entries-shuffled-diff-sizes.ll b/llvm/test/Transforms/SLPVectorizer/X86/entries-shuffled-diff-sizes.ll
index b99a1c2d83394..7d00120bf38d8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/entries-shuffled-diff-sizes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/entries-shuffled-diff-sizes.ll
@@ -10,8 +10,8 @@ define void @test() {
; CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr getelementptr ([16000 x i8], ptr @GLOB, i64 0, i64 1208), align 4
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr getelementptr ([16000 x i8], ptr @GLOB, i64 0, i64 1612), align 4
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
-; CHECK-NEXT: [[GEPLOAD1612:%.*]] = extractelement <16 x float> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <16 x float> [[TMP0]], i32 0
+; CHECK-NEXT: [[GEPLOAD1612:%.*]] = extractelement <16 x float> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <16 x float> [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = fmul reassoc ninf nsz arcp contract afn float [[GEPLOAD1612]], [[TMP1]]
; CHECK-NEXT: [[TMP6:%.*]] = fmul reassoc ninf nsz arcp contract afn <16 x float> [[TMP4]], [[TMP0]]
; CHECK-NEXT: store <16 x float> [[TMP6]], ptr getelementptr ([16000 x i8], ptr @GLOB, i64 0, i64 2928), align 16
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/entry-no-bundle-but-extra-use-on-vec.ll b/llvm/test/Transforms/SLPVectorizer/X86/entry-no-bundle-but-extra-use-on-vec.ll
index c945dc7f2c043..747a3df561544 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/entry-no-bundle-but-extra-use-on-vec.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/entry-no-bundle-but-extra-use-on-vec.ll
@@ -8,15 +8,15 @@ define void @test(ptr %nExp, float %0, i1 %cmp, float %1) {
; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
; CHECK: [[IF_THEN]]:
; CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[NEXP]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> [[TMP3]], float [[TMP11]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> [[TMP3]], float [[TMP11]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x float> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP9:%.*]] = fmul <2 x float> [[TMP8]], zeroinitializer
; CHECK-NEXT: br label %[[IF_END]]
; CHECK: [[IF_END]]:
-; CHECK-NEXT: [[TMP6:%.*]] = phi float [ [[TMP1]], %[[IF_THEN]] ], [ [[TMP0]], %[[ENTRY]] ]
-; CHECK-NEXT: [[TMP7:%.*]] = phi float [ 0.000000e+00, %[[IF_THEN]] ], [ [[TMP1]], %[[ENTRY]] ]
+; CHECK-NEXT: [[TMP16:%.*]] = phi float [ [[TMP1]], %[[IF_THEN]] ], [ [[TMP0]], %[[ENTRY]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = phi float [ 0.000000e+00, %[[IF_THEN]] ], [ [[TMP1]], %[[ENTRY]] ]
; CHECK-NEXT: [[TMP10:%.*]] = phi <2 x float> [ [[TMP9]], %[[IF_THEN]] ], [ zeroinitializer, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x float> [ zeroinitializer, %[[IF_THEN]] ], [ <float +qnan, float 1.000000e+00>, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP15:%.*]] = phi <2 x float> [ [[TMP5]], %[[IF_THEN]] ], [ zeroinitializer, %[[ENTRY]] ]
@@ -24,8 +24,8 @@ define void @test(ptr %nExp, float %0, i1 %cmp, float %1) {
; CHECK-NEXT: [[TMP18:%.*]] = fmul <2 x float> [[TMP15]], [[TMP13]]
; CHECK-NEXT: [[TMP17:%.*]] = fmul <2 x float> [[TMP10]], [[TMP14]]
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x float> [[TMP10]], <2 x float> [[TMP14]], <4 x i32> <i32 0, i32 2, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x float> [[TMP12]], float [[TMP7]], i32 2
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <4 x float> [[TMP21]], float [[TMP6]], i32 3
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x float> [[TMP12]], float [[TMP20]], i64 2
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <4 x float> [[TMP21]], float [[TMP16]], i64 3
; CHECK-NEXT: [[TMP19:%.*]] = fmul <4 x float> [[TMP28]], zeroinitializer
; CHECK-NEXT: [[TMP29:%.*]] = fadd <2 x float> [[TMP17]], [[TMP18]]
; CHECK-NEXT: [[CALL25:%.*]] = load volatile ptr, ptr null, align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/expanded-binop-doesnotneedschedule-user.ll b/llvm/test/Transforms/SLPVectorizer/X86/expanded-binop-doesnotneedschedule-user.ll
index fa0f927e36395..b7fde739e3ec6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/expanded-binop-doesnotneedschedule-user.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/expanded-binop-doesnotneedschedule-user.ll
@@ -14,7 +14,7 @@ define void @test() {
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> <i32 1, i32 poison>, <2 x i32> <i32 2, i32 1>
; CHECK-NEXT: [[TMP5]] = add <2 x i32> [[TMP4]], [[TMP3]]
; CHECK-NEXT: [[ADD6:%.*]] = add i32 0, 1
-; CHECK-NEXT: [[TMP6]] = insertelement <2 x i32> [[TMP5]], i32 [[ADD6]], i32 0
+; CHECK-NEXT: [[TMP6]] = insertelement <2 x i32> [[TMP5]], i32 [[ADD6]], i64 0
; CHECK-NEXT: br label %[[BB1]]
;
bb:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/expanded-operand-already-scheduled.ll b/llvm/test/Transforms/SLPVectorizer/X86/expanded-operand-already-scheduled.ll
index 2079aac55de9c..2ee5fb354fedd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/expanded-operand-already-scheduled.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/expanded-operand-already-scheduled.ll
@@ -13,9 +13,9 @@ define i32 @test() {
; CHECK-NEXT: [[TMP5:%.*]] = lshr <2 x i1> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i1> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i1> [[TMP5]], <2 x i1> [[TMP6]], <2 x i32> <i32 0, i32 3>
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP7]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP7]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = zext i1 [[TMP8]] to i32
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP7]], i64 1
; CHECK-NEXT: [[TMP11:%.*]] = zext i1 [[TMP10]] to i32
; CHECK-NEXT: [[TMP12:%.*]] = or i32 [[TMP9]], [[TMP11]]
; CHECK-NEXT: ret i32 [[TMP12]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/expected-prof-consecutive-access.ll b/llvm/test/Transforms/SLPVectorizer/X86/expected-prof-consecutive-access.ll
index c2ffba67afaa3..1d7f0e94ff770 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/expected-prof-consecutive-access.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/expected-prof-consecutive-access.ll
@@ -20,8 +20,8 @@ define double @test(ptr %a, i32 %n) {
; CHECK-NEXT: br i1 [[CMP15]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY:%.*]]
; CHECK: for.cond.cleanup:
; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x double> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[TMP5:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x double> [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x double> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP0]], i64 1
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret double [[MUL]]
; CHECK: for.body:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-different-bitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-different-bitwidth.ll
index 87f2ccaf76497..3cd441d0ae10b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-different-bitwidth.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-different-bitwidth.ll
@@ -8,7 +8,7 @@ define i32 @test() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: store i32 152, ptr @f, align 4
; CHECK-NEXT: [[AGG_TMP_SROA_0_0_COPYLOAD_I:%.*]] = load i32, ptr @f, align 4
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> <i32 poison, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080>, i32 [[AGG_TMP_SROA_0_0_COPYLOAD_I]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> <i32 poison, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080, i32 83886080>, i32 [[AGG_TMP_SROA_0_0_COPYLOAD_I]], i64 0
; CHECK-NEXT: [[TMP0:%.*]] = shl <8 x i32> [[TMP3]], <i32 24, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
; CHECK-NEXT: [[TMP1:%.*]] = add <8 x i32> <i32 83886080, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, [[TMP0]]
; CHECK-NEXT: [[TMP2:%.*]] = ashr <8 x i32> [[TMP1]], splat (i32 24)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll b/llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
index deb6e52e69596..2efb12a969a81 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
@@ -5,7 +5,7 @@ define void @test(ptr %0, ptr %1, double %2) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]], double [[TMP2:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ITER_CHECK:.*]]:
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> <double poison, double -0.000000e+00>, double [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> <double poison, double -0.000000e+00>, double [[TMP2]], i64 0
; CHECK-NEXT: br label %[[DOTLR_PH383_US_US_US_US:.*]]
; CHECK: [[_LR_PH383_US_US_US_US:.*:]]
; CHECK-NEXT: [[TMP3:%.*]] = phi <4 x double> [ [[TMP26:%.*]], %[[DOT_CRIT_EDGE384_US_US_US_US:.*]] ], [ zeroinitializer, %[[ITER_CHECK]] ]
@@ -18,17 +18,17 @@ define void @test(ptr %0, ptr %1, double %2) {
; CHECK-NEXT: [[TMP6:%.*]] = fmul double [[TMP5]], 0.000000e+00
; CHECK-NEXT: [[TMP10:%.*]] = fadd double [[TMP7]], [[TMP6]]
; CHECK-NEXT: [[TMP11:%.*]] = fadd double [[TMP7]], [[TMP6]]
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x double> poison, double [[TMP13]], i32 0
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <2 x double> [[TMP14]], double [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x double> poison, double [[TMP13]], i64 0
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <2 x double> [[TMP14]], double [[TMP5]], i64 1
; CHECK-NEXT: [[TMP18:%.*]] = fadd <2 x double> [[TMP15]], [[TMP17]]
; CHECK-NEXT: br label %[[BB19:.*]]
; CHECK: [[BB19]]:
; CHECK-NEXT: br label %[[BB20:.*]]
; CHECK: [[BB20]]:
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x double> poison, double [[TMP11]], i32 0
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x double> poison, double [[TMP11]], i64 0
; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <2 x double> [[TMP18]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <4 x double> [[TMP19]], <4 x double> [[TMP21]], <4 x i32> <i32 0, i32 4, i32 5, i32 poison>
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x double> [[TMP20]], double [[TMP10]], i32 3
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x double> [[TMP20]], double [[TMP10]], i64 3
; CHECK-NEXT: [[TMP24:%.*]] = fmul <4 x double> [[TMP23]], <double 0.000000e+00, double 1.000000e+00, double 1.000000e+00, double 0.000000e+00>
; CHECK-NEXT: [[TMP25:%.*]] = fadd <4 x double> [[TMP24]], [[TMP3]]
; CHECK-NEXT: br label %[[DOT_CRIT_EDGE384_US_US_US_US]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/external-reduced-value-vectorized.ll b/llvm/test/Transforms/SLPVectorizer/X86/external-reduced-value-vectorized.ll
index 3bf73034a1718..b5ff1ed24f352 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/external-reduced-value-vectorized.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/external-reduced-value-vectorized.ll
@@ -5,18 +5,18 @@ define i32 @test(ptr %c, i16 %a, i16 %0) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: ptr [[C:%.*]], i16 [[A:%.*]], i16 [[TMP0:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i16> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP16:%.*]] = zext <4 x i1> [[TMP3]] to <4 x i8>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> poison, <2 x i32> <i32 poison, i32 0>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i16> [[TMP5]], i16 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i16> [[TMP5]], i16 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i16> [[TMP6]], <2 x i16> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i8> [[TMP16]] to <4 x i16>
; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt <4 x i16> [[TMP7]], [[TMP4]]
; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i16 [[A]], -2
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i1> [[TMP3]], <4 x i1> poison, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 poison>
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i1> [[TMP10]], i1 [[TMP9]], i32 7
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i1> [[TMP10]], i1 [[TMP9]], i64 7
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <4 x i1> [[TMP8]], <4 x i1> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <8 x i1> [[TMP11]], <8 x i1> [[TMP17]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP13:%.*]] = freeze <8 x i1> [[TMP12]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/external_user.ll b/llvm/test/Transforms/SLPVectorizer/X86/external_user.ll
index 92157b24c6bb0..00b6d1eb112d6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/external_user.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/external_user.ll
@@ -39,7 +39,7 @@ define double @ext_user(ptr noalias nocapture %B, ptr noalias nocapture %A, i32
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
; CHECK: for.end:
; CHECK-NEXT: store <2 x double> [[TMP5]], ptr [[B:%.*]], align 8
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
; CHECK-NEXT: ret double [[TMP7]]
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll b/llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
index bb177196904fc..06e77d50c513d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
@@ -4,7 +4,7 @@
define i64 @foo(i32 %tmp7) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 poison, i32 poison, i32 0, i32 poison, i32 poison, i32 poison>, i32 [[TMP8:%.*]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 poison, i32 poison, i32 0, i32 poison, i32 poison, i32 poison>, i32 [[TMP8:%.*]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = sub <8 x i32> [[TMP0]], <i32 0, i32 0, i32 poison, i32 0, i32 0, i32 poison, i32 0, i32 poison>
; CHECK-NEXT: [[TMP5:%.*]] = sub nsw <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 poison, i32 0>, [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = add nsw <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 poison, i32 0>, [[TMP4]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extract-subvector-long-input.ll b/llvm/test/Transforms/SLPVectorizer/X86/extract-subvector-long-input.ll
index f90456297d7cb..300ce27e70bf7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extract-subvector-long-input.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extract-subvector-long-input.ll
@@ -8,7 +8,7 @@ define void @test() {
; CHECK: bb1:
; CHECK-NEXT: [[PHI7:%.*]] = phi i32 [ 0, [[BB10:%.*]] ], [ 0, [[BB:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = phi <8 x i32> [ poison, [[BB10]] ], [ zeroinitializer, [[BB]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[PHI7]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[PHI7]], i64 0
; CHECK-NEXT: switch i32 0, label [[BB16:%.*]] [
; CHECK-NEXT: i32 0, label [[BB14:%.*]]
; CHECK-NEXT: i32 1, label [[BB11:%.*]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extract-used-in-many-nodes.ll b/llvm/test/Transforms/SLPVectorizer/X86/extract-used-in-many-nodes.ll
index 7e37ae0c3e047..ebb15095b7a93 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extract-used-in-many-nodes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extract-used-in-many-nodes.ll
@@ -7,12 +7,12 @@ define i1 @test() {
; CHECK-NEXT: [[C2:%.*]] = fpext float 0.000000e+00 to double
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <8 x double> <double 0.000000e+00, double 5.000000e+00, double undef, double undef, double undef, double undef, double undef, double undef>, <8 x double> <double 4.000000e+00, double 3.000000e+00, double undef, double undef, double undef, double undef, double undef, double undef>, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x double> [[TMP0]], <8 x double> <double 2.000000e+00, double 1.000000e+00, double undef, double undef, double undef, double undef, double undef, double undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x double> [[TMP1]], double [[C2]], i32 6
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x double> [[TMP1]], double [[C2]], i64 6
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 0>
; CHECK-NEXT: [[TMP6:%.*]] = fmul <8 x double> zeroinitializer, [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> zeroinitializer, <8 x double> [[TMP6]], <8 x double> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = fcmp olt <8 x double> [[TMP7]], zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i1> [[TMP8]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i1> [[TMP8]], i64 0
; CHECK-NEXT: ret i1 [[TMP9]]
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll b/llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
index fa82ccbf2fb16..315cfe0b659cb 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll
@@ -10,7 +10,7 @@ define void @fn1() {
; CHECK-LABEL: @fn1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr @a, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x ptr> [[TMP1]], <2 x ptr> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, <2 x ptr> [[TMP2]], <2 x i64> <i64 11, i64 56>
; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 11
@@ -37,7 +37,7 @@ define void @fn2(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[A:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP2]] to <4 x float>
; CHECK-NEXT: [[TMP5:%.*]] = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> [[TMP4]], i32 [[TMP3]])
; CHECK-NEXT: store <4 x float> [[TMP5]], ptr [[C:%.*]], align 4
@@ -90,7 +90,7 @@ define void @externally_used_ptrs() {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr @a, align 8
; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 11
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x ptr> [[TMP1]], <2 x ptr> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, <2 x ptr> [[TMP2]], <2 x i64> <i64 56, i64 11>
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint <2 x ptr> [[TMP3]] to <2 x i64>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
index c6f5308cf54aa..0ebb73a59eaf7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
@@ -7,12 +7,12 @@ target triple = "x86_64-apple-macosx10.8.0"
define i32 @foo(ptr nocapture %A, i32 %n, i32 %m) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> [[SHUFFLE]], <i32 5, i32 9, i32 8, i32 10>
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], splat (i32 9)
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[A:%.*]], align 4
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i64 0
; CHECK-NEXT: [[EXTERNALUSE1:%.*]] = add nsw i32 [[TMP6]], [[M:%.*]]
; CHECK-NEXT: [[EXTERNALUSE2:%.*]] = mul nsw i32 [[TMP6]], [[M]]
; CHECK-NEXT: [[ADD10:%.*]] = add nsw i32 [[EXTERNALUSE1]], [[EXTERNALUSE2]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multi-register-use.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multi-register-use.ll
index c945799b38122..3a66f79121163 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multi-register-use.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multi-register-use.ll
@@ -6,16 +6,16 @@ define void @test(double %i) {
; CHECK-SAME: double [[I:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[I74:%.*]] = fsub double 0.000000e+00, poison
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[I]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[I]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fsub <2 x double> zeroinitializer, [[TMP2]]
; CHECK-NEXT: [[I96:%.*]] = fsub double poison, 0.000000e+00
; CHECK-NEXT: [[I75:%.*]] = fsub double 0.000000e+00, [[I]]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[I]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[I]], i64 0
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> <double 0.000000e+00, double poison>, <2 x i32> <i32 2, i32 0>
; CHECK-NEXT: [[TMP15:%.*]] = fsub <2 x double> [[TMP4]], [[TMP8]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP15]], <2 x double> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x double> <double 0.000000e+00, double 0.000000e+00, double poison, double poison, double 0.000000e+00, double poison, double poison, double poison>, <8 x double> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x double> [[TMP6]], double [[I75]], i32 5
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x double> [[TMP6]], double [[I75]], i64 5
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x double> [[TMP7]], <8 x double> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP11:%.*]] = fmul <8 x double> zeroinitializer, [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = fadd <8 x double> zeroinitializer, [[TMP11]]
@@ -23,7 +23,7 @@ define void @test(double %i) {
; CHECK-NEXT: [[TMP14:%.*]] = fcmp ult <8 x double> [[TMP13]], zeroinitializer
; CHECK-NEXT: br label [[BB116:%.*]]
; CHECK: bb116:
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x double> [[TMP15]], i32 0
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x double> [[TMP15]], i64 0
; CHECK-NEXT: [[I117:%.*]] = fmul double 0.000000e+00, [[TMP16]]
; CHECK-NEXT: [[I119:%.*]] = fmul double 0.000000e+00, [[I96]]
; CHECK-NEXT: [[I120:%.*]] = fadd double [[I117]], [[I119]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multiple-uses.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multiple-uses.ll
index 35f521fbe8113..efd1910068c0d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multiple-uses.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-multiple-uses.ll
@@ -16,8 +16,8 @@ define float @multi_uses(<2 x float> %x, <2 x float> %y) {
; CHECK-LABEL: @multi_uses(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x float> [[Y:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x float> [[X:%.*]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP4]]
; CHECK-NEXT: ret float [[ADD]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
index 31e4feabd3582..9464b12308034 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-single-use-many-nodes.ll
@@ -5,13 +5,13 @@ define void @foo(double %i) {
; CHECK-LABEL: define void @foo(
; CHECK-SAME: double [[I:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x double> <double 0.000000e+00, double 0.000000e+00, double poison, double 0.000000e+00>, double [[I]], i32 2
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x double> <double 0.000000e+00, double 0.000000e+00, double poison, double 0.000000e+00>, double [[I]], i64 2
; CHECK-NEXT: [[TMP1:%.*]] = fsub <4 x double> zeroinitializer, [[TMP0]]
; CHECK-NEXT: [[I82:%.*]] = fsub double 0.000000e+00, poison
; CHECK-NEXT: [[I103:%.*]] = fsub double 0.000000e+00, [[I]]
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> poison, <8 x i32> <i32 poison, i32 0, i32 poison, i32 1, i32 poison, i32 0, i32 poison, i32 1>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x double> [[TMP8]], <8 x double> <double 0.000000e+00, double poison, double poison, double poison, double 0.000000e+00, double poison, double poison, double poison>, <8 x i32> <i32 8, i32 1, i32 poison, i32 3, i32 12, i32 5, i32 poison, i32 7>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x double> [[TMP5]], double [[I82]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x double> [[TMP5]], double [[I82]], i64 2
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x double> [[TMP6]], <8 x double> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 2, i32 7>
; CHECK-NEXT: [[TMP12:%.*]] = fmul <8 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, [[TMP7]]
; CHECK-NEXT: [[TMP13:%.*]] = fadd <8 x double> zeroinitializer, [[TMP12]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractelement.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractelement.ll
index f5718e04df9ad..cdf41cfa79053 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extractelement.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extractelement.ll
@@ -8,22 +8,22 @@
define float @f(<2 x float> %x) {
; CHECK-LABEL: @f(
; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x float> [[X:%.*]], [[X]]
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP1]], i64 1
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP2]], [[TMP3]]
; CHECK-NEXT: ret float [[ADD]]
;
; THRESH1-LABEL: @f(
; THRESH1-NEXT: [[TMP1:%.*]] = fmul <2 x float> [[X:%.*]], [[X]]
-; THRESH1-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[TMP1]], i32 0
-; THRESH1-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP1]], i32 1
+; THRESH1-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[TMP1]], i64 0
+; THRESH1-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP1]], i64 1
; THRESH1-NEXT: [[ADD:%.*]] = fadd float [[TMP2]], [[TMP3]]
; THRESH1-NEXT: ret float [[ADD]]
;
; THRESH2-LABEL: @f(
; THRESH2-NEXT: [[TMP1:%.*]] = fmul <2 x float> [[X:%.*]], [[X]]
-; THRESH2-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[TMP1]], i32 0
-; THRESH2-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP1]], i32 1
+; THRESH2-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[TMP1]], i64 0
+; THRESH2-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP1]], i64 1
; THRESH2-NEXT: [[ADD:%.*]] = fadd float [[TMP2]], [[TMP3]]
; THRESH2-NEXT: ret float [[ADD]]
;
@@ -39,8 +39,8 @@ define float @f_used_out_of_tree(<2 x float> %x) {
; CHECK-LABEL: @f_used_out_of_tree(
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[X:%.*]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x float> [[X]], [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP4]]
; CHECK-NEXT: store float [[ADD]], ptr @a, align 4
; CHECK-NEXT: ret float [[TMP1]]
@@ -48,8 +48,8 @@ define float @f_used_out_of_tree(<2 x float> %x) {
; THRESH1-LABEL: @f_used_out_of_tree(
; THRESH1-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[X:%.*]], i32 0
; THRESH1-NEXT: [[TMP2:%.*]] = fmul <2 x float> [[X]], [[X]]
-; THRESH1-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; THRESH1-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; THRESH1-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; THRESH1-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; THRESH1-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP4]]
; THRESH1-NEXT: store float [[ADD]], ptr @a, align 4
; THRESH1-NEXT: ret float [[TMP1]]
@@ -57,8 +57,8 @@ define float @f_used_out_of_tree(<2 x float> %x) {
; THRESH2-LABEL: @f_used_out_of_tree(
; THRESH2-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[X:%.*]], i32 0
; THRESH2-NEXT: [[TMP2:%.*]] = fmul <2 x float> [[X]], [[X]]
-; THRESH2-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; THRESH2-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; THRESH2-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; THRESH2-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; THRESH2-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP4]]
; THRESH2-NEXT: store float [[ADD]], ptr @a, align 4
; THRESH2-NEXT: ret float [[TMP1]]
@@ -84,16 +84,16 @@ define float @f_used_twice_in_tree(<2 x float> %x) {
; THRESH1-LABEL: @f_used_twice_in_tree(
; THRESH1-NEXT: [[TMP1:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 1>
; THRESH1-NEXT: [[TMP2:%.*]] = fmul <2 x float> [[TMP1]], [[X]]
-; THRESH1-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; THRESH1-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; THRESH1-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; THRESH1-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; THRESH1-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP4]]
; THRESH1-NEXT: ret float [[ADD]]
;
; THRESH2-LABEL: @f_used_twice_in_tree(
; THRESH2-NEXT: [[TMP1:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 1>
; THRESH2-NEXT: [[TMP2:%.*]] = fmul <2 x float> [[TMP1]], [[X]]
-; THRESH2-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; THRESH2-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; THRESH2-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; THRESH2-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; THRESH2-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP4]]
; THRESH2-NEXT: ret float [[ADD]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractelements-subnodes-same-index.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractelements-subnodes-same-index.ll
index f77d7065e8a8f..a2586ac447a1e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extractelements-subnodes-same-index.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extractelements-subnodes-same-index.ll
@@ -25,16 +25,16 @@ define i32 @test() {
; CHECK-NEXT: store i32 [[LOAD32]], ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) null, i64 16), align 4
; CHECK-NEXT: [[LOAD33:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) null, i64 12), align 4
; CHECK-NEXT: store i32 [[LOAD33]], ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) null, i64 12), align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <24 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 [[LOAD]], i32 6
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <24 x i32> [[TMP0]], i32 [[LOAD9]], i32 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <24 x i32> [[TMP1]], i32 [[LOAD14]], i32 9
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <24 x i32> [[TMP2]], i32 [[LOAD15]], i32 10
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <24 x i32> [[TMP3]], i32 [[LOAD20]], i32 11
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <24 x i32> [[TMP4]], i32 [[LOAD21]], i32 12
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <24 x i32> [[TMP5]], i32 [[LOAD26]], i32 13
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <24 x i32> [[TMP6]], i32 [[LOAD27]], i32 14
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <24 x i32> [[TMP7]], i32 [[LOAD32]], i32 15
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <24 x i32> [[TMP8]], i32 [[LOAD33]], i32 16
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <24 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 [[LOAD]], i64 6
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <24 x i32> [[TMP0]], i32 [[LOAD9]], i64 8
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <24 x i32> [[TMP1]], i32 [[LOAD14]], i64 9
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <24 x i32> [[TMP2]], i32 [[LOAD15]], i64 10
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <24 x i32> [[TMP3]], i32 [[LOAD20]], i64 11
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <24 x i32> [[TMP4]], i32 [[LOAD21]], i64 12
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <24 x i32> [[TMP5]], i32 [[LOAD26]], i64 13
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <24 x i32> [[TMP6]], i32 [[LOAD27]], i64 14
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <24 x i32> [[TMP7]], i32 [[LOAD32]], i64 15
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <24 x i32> [[TMP8]], i32 [[LOAD33]], i64 16
; CHECK-NEXT: [[TMP10:%.*]] = call <24 x i32> @llvm.ctpop.v24i32(<24 x i32> [[TMP9]])
; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.or.v24i32(<24 x i32> [[TMP10]])
; CHECK-NEXT: ret i32 [[TMP11]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractelements-with-undef-vector.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractelements-with-undef-vector.ll
index e3461aa452577..5c4d27418eec5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extractelements-with-undef-vector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extractelements-with-undef-vector.ll
@@ -5,11 +5,11 @@ define i32 @test() {
; CHECK-LABEL: define i32 @test() {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[D:%.*]] = extractelement <2 x i32> undef, i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 undef>, i32 [[D]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 undef>, i32 [[D]], i64 3
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[TMP0:%.*]] = phi <4 x i32> [ [[TMP2]], %[[ENTRY]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x i32> [ [[TMP0]], %[[ENTRY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3
; CHECK-NEXT: ret i32 [[TMP1]]
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractelemets-extended-by-poison.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractelemets-extended-by-poison.ll
index 132865da252c9..a5962bc787e9e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extractelemets-extended-by-poison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extractelemets-extended-by-poison.ll
@@ -5,7 +5,7 @@ define i32 @test() {
; CHECK-LABEL: define i32 @test() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr null, align 16
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i64> [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i64> [[TMP0]], i64 1
; CHECK-NEXT: [[TMP13:%.*]] = or i64 [[TMP12]], 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP0]], <4 x i64> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 1>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <6 x i64> [[TMP3]], <6 x i64> <i64 poison, i64 poison, i64 poison, i64 poison, i64 0, i64 poison>, <6 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 10, i32 5>
@@ -17,7 +17,7 @@ define i32 @test() {
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <6 x i32> [[TMP11]], <6 x i32> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 2, i32 2, i32 5, i32 4, i32 3>
; CHECK-NEXT: [[TMP15:%.*]] = add <8 x i32> [[TMP14]], zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = add <16 x i32> [[TMP7]], zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i64> [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i64> [[TMP0]], i64 0
; CHECK-NEXT: [[INC_3_3_I_1:%.*]] = or i64 [[TMP9]], 0
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <16 x i32> [[TMP8]], <16 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[RDX_OP:%.*]] = or <8 x i32> [[TMP16]], [[TMP15]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll b/llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll
index 0875b8dd2f9ee..98a2bd359322d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll
@@ -5,7 +5,7 @@ define void @test(i64 %v) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i64 [[V:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[BB:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> <i64 0, i64 poison>, i64 [[V]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> <i64 0, i64 poison>, i64 [[V]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i64> zeroinitializer, [[TMP0]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TMP2]], <8 x i64> <i64 poison, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0>, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 4, i32 13, i32 14, i32 15>
@@ -17,7 +17,7 @@ define void @test(i64 %v) {
; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[TMP8]], i1 false, i1 false
; CHECK-NEXT: br i1 [[OP_RDX1]], label %[[BB_I107_PREHEADER:.*]], label %[[BB_I27_I_PREHEADER:.*]]
; CHECK: [[BB_I107_PREHEADER]]:
-; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
; CHECK-NEXT: [[DOTSROA_1278_10_EXTRACT_SHIFT83_I1622_1:%.*]] = xor i64 0, [[TMP21]]
; CHECK-NEXT: [[TMP22:%.*]] = xor <2 x i64> zeroinitializer, [[TMP1]]
; CHECK-NEXT: [[TMP23:%.*]] = or <2 x i64> [[TMP22]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll b/llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
index ef0a7fa6a3812..fdb43f683f644 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
@@ -11,12 +11,12 @@ target triple = "i686-unknown-linux-gnu"
define void @vectorize_fp128(fp128 %c, fp128 %d) #0 {
; CHECK-LABEL: @vectorize_fp128(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x fp128> poison, fp128 [[C:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x fp128> [[TMP0]], fp128 [[D:%.*]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x fp128> poison, fp128 [[C:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x fp128> [[TMP0]], fp128 [[D:%.*]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x fp128> @llvm.fabs.v2f128(<2 x fp128> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = fcmp oeq <2 x fp128> [[TMP2]], splat (fp128 +inf)
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP3]], i64 1
; CHECK-NEXT: [[OR_COND39:%.*]] = or i1 [[TMP4]], [[TMP5]]
; CHECK-NEXT: br i1 [[OR_COND39]], label [[IF_THEN13:%.*]], label [[IF_END24:%.*]]
; CHECK: if.then13:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
index 9223a77bc5263..af36ad10729f0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
@@ -445,10 +445,10 @@ define void @fptosi_8f32_8i8() #0 {
define <4 x i32> @fptosi_4xf64_4i32(double %a0, double %a1, double %a2, double %a3) #0 {
; CHECK-LABEL: @fptosi_4xf64_4i32(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[A2:%.*]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[A2:%.*]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = fptosi <4 x double> [[TMP4]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[TMP5]]
;
@@ -465,10 +465,10 @@ define <4 x i32> @fptosi_4xf64_4i32(double %a0, double %a1, double %a2, double %
define <4 x i32> @fptosi_4xf32_4i32(float %a0, float %a1, float %a2, float %a3) #0 {
; CHECK-LABEL: @fptosi_4xf32_4i32(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[A2:%.*]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[A2:%.*]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = fptosi <4 x float> [[TMP4]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[TMP5]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
index 7959e64e5e141..0f55b57851ee5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
@@ -445,10 +445,10 @@ define void @fptosi_8f32_8i8() #0 {
define <4 x i32> @fptosi_4xf64_4i32(double %a0, double %a1, double %a2, double %a3) #0 {
; CHECK-LABEL: @fptosi_4xf64_4i32(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[A2:%.*]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[A2:%.*]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = fptosi <4 x double> [[TMP4]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[TMP5]]
;
@@ -465,10 +465,10 @@ define <4 x i32> @fptosi_4xf64_4i32(double %a0, double %a1, double %a2, double %
define <4 x i32> @fptosi_4xf32_4i32(float %a0, float %a1, float %a2, float %a3) #0 {
; CHECK-LABEL: @fptosi_4xf32_4i32(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[A2:%.*]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[A2:%.*]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = fptosi <4 x float> [[TMP4]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[TMP5]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll b/llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
index 7455fedf0762c..77b2d6dca17ec 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/full-match-with-poison-scalar.ll
@@ -7,7 +7,7 @@ define i32 @test() {
; CHECK-NEXT: br label %[[FUNC_135_EXIT_I:.*]]
; CHECK: [[FUNC_135_EXIT_I]]:
; CHECK-NEXT: [[G_228_PROMOTED166_I1105_I:%.*]] = phi i32 [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <5 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 0>, i32 [[G_228_PROMOTED166_I1105_I]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <5 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 0>, i32 [[G_228_PROMOTED166_I1105_I]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <5 x i32> [[TMP0]], <5 x i32> poison, <5 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4>
; CHECK-NEXT: [[TMP2:%.*]] = add <5 x i32> zeroinitializer, [[TMP1]]
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <5 x i32> [[TMP2]], <5 x i32> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3, i32 4>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll b/llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll
index e1868a26b4127..016ccdbfa53e8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/full-matched-bv-with-subvectors.ll
@@ -6,8 +6,8 @@ define i32 @test(i64 %l.549) {
; CHECK-SAME: i64 [[L_549:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[CONV3:%.*]] = sext i32 0 to i64
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[CONV3]], i32 2
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i64> poison, i64 [[L_549]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[CONV3]], i64 2
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i64> poison, i64 [[L_549]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i64> [[TMP8]], <4 x i64> poison, <4 x i32> <i32 poison, i32 0, i32 poison, i32 poison>
; CHECK-NEXT: br label %[[IF_THEN19:.*]]
; CHECK: [[P:.*]]:
@@ -16,7 +16,7 @@ define i32 @test(i64 %l.549) {
; CHECK: [[Q]]:
; CHECK-NEXT: [[XOR39:%.*]] = phi i64 [ 0, %[[P]] ], [ 0, %[[LAND_LHS_TRUE:.*]] ]
; CHECK-NEXT: [[TMP16:%.*]] = phi <2 x i64> [ zeroinitializer, %[[P]] ], [ zeroinitializer, %[[LAND_LHS_TRUE]] ]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[XOR39]], i32 3
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[XOR39]], i64 3
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <2 x i64> [[TMP16]], <2 x i64> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> [[TMP18]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: br i1 false, label %[[LOR_LHS_FALSE:.*]], label %[[R:.*]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/full-non-schedulable-overlap.ll b/llvm/test/Transforms/SLPVectorizer/X86/full-non-schedulable-overlap.ll
index 231a9512c9ee9..b704aeb1ffcae 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/full-non-schedulable-overlap.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/full-non-schedulable-overlap.ll
@@ -5,7 +5,7 @@ define void @test(double %v) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: double [[V:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[V]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[V]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x double> zeroinitializer, [[TMP0]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: br label %[[LOOP:.*]]
@@ -13,8 +13,8 @@ define void @test(double %v) {
; CHECK-NEXT: [[T50_02:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP8:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[TMP3:%.*]] = phi <2 x double> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP10:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP3]], [[TMP2]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = fadd double [[TMP6]], [[TMP5]]
; CHECK-NEXT: [[TMP8]] = fadd double [[TMP7]], [[V]]
; CHECK-NEXT: [[TMP9:%.*]] = fmul <2 x double> zeroinitializer, [[TMP1]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gather-move-out-of-loop.ll b/llvm/test/Transforms/SLPVectorizer/X86/gather-move-out-of-loop.ll
index 78fc3a60f0514..2ef2ec606e771 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/gather-move-out-of-loop.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/gather-move-out-of-loop.ll
@@ -4,7 +4,7 @@
define void @test(i16 %0) {
; CHECK-LABEL: @test(
; CHECK-NEXT: for.body92.preheader:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> <i16 0, i16 poison>, i16 [[TMP0:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> <i16 0, i16 poison>, i16 [[TMP0:%.*]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> <i32 0, i32 3>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll b/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
index 4f62a8d24387f..fa13e9d4b40c5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll
@@ -7,8 +7,8 @@ define void @foo(ptr %i7, i32 %0, i1 %tobool62.not) {
; CHECK-LABEL: define void @foo(
; CHECK-SAME: ptr [[I7:%.*]], i32 [[TMP0:%.*]], i1 [[TOBOOL62_NOT:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RC21:%.*]] = alloca [0 x [0 x %struct.rect]], i32 0, align 4
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[RC21:%.*]] = alloca [0 x [0 x [[STRUCT_RECT:%.*]]]], i32 0, align 4
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x float>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 1, i32 0, i32 1, i32 0>
@@ -16,8 +16,8 @@ define void @foo(ptr %i7, i32 %0, i1 %tobool62.not) {
; CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[Y0]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[I7]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = load <2 x float>, ptr [[RC21]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> poison, float [[TMP6]], i32 2
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x float> [[TMP10]], float [[TMP7]], i32 3
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> poison, float [[TMP6]], i64 2
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x float> [[TMP10]], float [[TMP7]], i64 3
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <2 x float> [[TMP8]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x float> [[TMP9]], <4 x float> [[TMP11]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP12:%.*]] = fcmp olt <4 x float> [[TMP13]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gather-with-cmp-user.ll b/llvm/test/Transforms/SLPVectorizer/X86/gather-with-cmp-user.ll
index c9aeafc5a0b19..05450dc4432c0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/gather-with-cmp-user.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/gather-with-cmp-user.ll
@@ -6,7 +6,7 @@ define i1 @test(i32 %g, i16 %d) {
; CHECK-SAME: i32 [[G:%.*]], i16 [[D:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = and i16 [[D]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[G]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[G]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i32> [[TMP2]], <i32 0, i32 1>
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll b/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll
index 7ce45b872fae4..467511f7f0392 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll
@@ -13,11 +13,11 @@ define i64 @foo() {
; CHECK-NEXT: [[PHI4:%.*]] = phi i64 [ 0, [[BB:%.*]] ], [ 0, [[BB3]] ]
; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i64> [ zeroinitializer, [[BB]] ], [ [[TMP3:%.*]], [[BB3]] ]
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> <i64 poison, i64 0>, <2 x i32> <i32 0, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> <i64 poison, i64 0>, i64 [[PHI4]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> <i64 poison, i64 0>, i64 [[PHI4]], i64 0
; CHECK-NEXT: [[TMP3]] = add <2 x i64> [[TMP4]], [[TMP2]]
; CHECK-NEXT: [[TMP5]] = add <2 x i64> [[TMP0]], [[TMP2]]
; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr i64, ptr addrspace(1) null, i64 [[ADD7]]
-; CHECK-NEXT: [[OR:%.*]] = extractelement <2 x i64> [[TMP5]], i32 1
+; CHECK-NEXT: [[OR:%.*]] = extractelement <2 x i64> [[TMP5]], i64 1
; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i64 [[OR]], 0
; CHECK-NEXT: br i1 false, label [[BB3]], label [[BB1:%.*]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll b/llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
index 113dc804090db..648b21ebb53df 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
@@ -46,24 +46,24 @@ define void @test(ptr noalias %0) {
; CHECK-NEXT: [[TMP37:%.*]] = fmul double [[TMP32]], [[TMP23]]
; CHECK-NEXT: [[TMP41:%.*]] = fmul double [[TMP36]], [[TMP31]]
; CHECK-NEXT: [[TMP42:%.*]] = fsub double 0.000000e+00, [[TMP25]]
-; CHECK-NEXT: [[TMP49:%.*]] = insertelement <2 x double> poison, double [[TMP42]], i32 0
-; CHECK-NEXT: [[TMP44:%.*]] = insertelement <2 x double> [[TMP49]], double [[TMP41]], i32 1
+; CHECK-NEXT: [[TMP49:%.*]] = insertelement <2 x double> poison, double [[TMP42]], i64 0
+; CHECK-NEXT: [[TMP44:%.*]] = insertelement <2 x double> [[TMP49]], double [[TMP41]], i64 1
; CHECK-NEXT: [[TMP50:%.*]] = fmul <2 x double> [[TMP44]], zeroinitializer
; CHECK-NEXT: [[TMP43:%.*]] = shufflevector <2 x double> [[TMP50]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP51:%.*]] = insertelement <4 x double> [[TMP43]], double [[TMP37]], i32 2
-; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x double> [[TMP51]], double [[TMP47]], i32 3
+; CHECK-NEXT: [[TMP51:%.*]] = insertelement <4 x double> [[TMP43]], double [[TMP37]], i64 2
+; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x double> [[TMP51]], double [[TMP47]], i64 3
; CHECK-NEXT: [[TMP46:%.*]] = fadd <4 x double> [[TMP52]], <double 0.000000e+00, double 0.000000e+00, double -0.000000e+00, double 0.000000e+00>
; CHECK-NEXT: [[TMP53:%.*]] = fmul <4 x double> [[TMP46]], <double 0.000000e+00, double 1.000000e+00, double 0.000000e+00, double 1.000000e+00>
-; CHECK-NEXT: [[TMP59:%.*]] = insertelement <4 x double> <double 0.000000e+00, double poison, double poison, double 1.000000e+00>, double [[TMP33]], i32 1
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <4 x double> <double 0.000000e+00, double poison, double poison, double 1.000000e+00>, double [[TMP33]], i64 1
; CHECK-NEXT: [[TMP60:%.*]] = shufflevector <4 x double> [[TMP59]], <4 x double> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 3>
; CHECK-NEXT: [[TMP61:%.*]] = fmul <4 x double> [[TMP60]], [[TMP53]]
; CHECK-NEXT: store <4 x double> [[TMP61]], ptr getelementptr inbounds (i8, ptr @solid_, i64 384), align 8
; CHECK-NEXT: [[TMP56:%.*]] = shufflevector <4 x double> [[TMP61]], <4 x double> poison, <2 x i32> <i32 1, i32 2>
-; CHECK-NEXT: [[TMP45:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[TMP17]], i32 0
+; CHECK-NEXT: [[TMP45:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[TMP17]], i64 0
; CHECK-NEXT: [[TMP48:%.*]] = fmul <2 x double> [[TMP56]], [[TMP45]]
; CHECK-NEXT: [[TMP54:%.*]] = fadd <2 x double> [[TMP48]], zeroinitializer
-; CHECK-NEXT: [[TMP55:%.*]] = insertelement <2 x double> poison, double [[TMP38]], i32 0
-; CHECK-NEXT: [[TMP62:%.*]] = insertelement <2 x double> [[TMP55]], double [[TMP33]], i32 1
+; CHECK-NEXT: [[TMP55:%.*]] = insertelement <2 x double> poison, double [[TMP38]], i64 0
+; CHECK-NEXT: [[TMP62:%.*]] = insertelement <2 x double> [[TMP55]], double [[TMP33]], i64 1
; CHECK-NEXT: [[TMP57:%.*]] = fadd <2 x double> [[TMP62]], [[TMP54]]
; CHECK-NEXT: [[TMP58:%.*]] = fsub <2 x double> zeroinitializer, [[TMP57]]
; CHECK-NEXT: store <2 x double> [[TMP58]], ptr getelementptr inbounds (i8, ptr @solid_, i64 296), align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gathered-node-with-in-order-parent.ll b/llvm/test/Transforms/SLPVectorizer/X86/gathered-node-with-in-order-parent.ll
index 222697ea03757..4ded1a475e796 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/gathered-node-with-in-order-parent.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/gathered-node-with-in-order-parent.ll
@@ -12,7 +12,7 @@ define double @test() {
; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[TMP0]], <i32 0, i32 0, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
; CHECK-NEXT: [[TMP3]] = or <4 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP6]], 0
; CHECK-NEXT: br i1 false, label %[[BB7:.*]], label %[[BB1]]
; CHECK: [[BB7]]:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/hoist.ll b/llvm/test/Transforms/SLPVectorizer/X86/hoist.ll
index 65ede4baf6519..ab76cb2d41893 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/hoist.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/hoist.ll
@@ -16,8 +16,8 @@ target triple = "i386-apple-macosx10.9.0"
define i32 @foo(ptr nocapture %A, i32 %n, i32 %k) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[K:%.*]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[N:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[K:%.*]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
index 4e434a61e1f1c..2c0787e9bc65c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
@@ -250,8 +250,8 @@ define float @bar() {
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr @arr, align 16
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr @arr1, align 16
; CHECK-NEXT: [[TMP2:%.*]] = fmul fast <2 x float> [[TMP1]], [[TMP0]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; CHECK-NEXT: [[CMP4:%.*]] = fcmp fast ogt float [[TMP3]], [[TMP4]]
; CHECK-NEXT: [[MAX_0_MUL3:%.*]] = select i1 [[CMP4]], float [[TMP3]], float [[TMP4]]
; CHECK-NEXT: [[TMP5:%.*]] = load float, ptr getelementptr inbounds ([20 x float], ptr @arr, i64 0, i64 2), align 8
@@ -272,8 +272,8 @@ define float @bar() {
; THRESHOLD-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr @arr, align 16
; THRESHOLD-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr @arr1, align 16
; THRESHOLD-NEXT: [[TMP2:%.*]] = fmul fast <2 x float> [[TMP1]], [[TMP0]]
-; THRESHOLD-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; THRESHOLD-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; THRESHOLD-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; THRESHOLD-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; THRESHOLD-NEXT: [[CMP4:%.*]] = fcmp fast ogt float [[TMP3]], [[TMP4]]
; THRESHOLD-NEXT: [[MAX_0_MUL3:%.*]] = select i1 [[CMP4]], float [[TMP3]], float [[TMP4]]
; THRESHOLD-NEXT: [[TMP5:%.*]] = load float, ptr getelementptr inbounds ([20 x float], ptr @arr, i64 0, i64 2), align 8
@@ -915,13 +915,13 @@ define float @extra_args_no_fast(ptr %x, float %a, float %b) {
; THRESHOLD-NEXT: [[ADDC:%.*]] = fadd fast float [[B:%.*]], 3.000000e+00
; THRESHOLD-NEXT: [[ADD:%.*]] = fadd fast float [[A:%.*]], [[ADDC]]
; THRESHOLD-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[X:%.*]], align 4
-; THRESHOLD-NEXT: [[T0:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; THRESHOLD-NEXT: [[T0:%.*]] = extractelement <4 x float> [[TMP1]], i64 0
; THRESHOLD-NEXT: [[ADD1:%.*]] = fadd fast float [[T0]], [[ADD]]
-; THRESHOLD-NEXT: [[T1:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; THRESHOLD-NEXT: [[T1:%.*]] = extractelement <4 x float> [[TMP1]], i64 1
; THRESHOLD-NEXT: [[ADD4:%.*]] = fadd fast float [[T1]], [[ADD1]]
-; THRESHOLD-NEXT: [[T2:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; THRESHOLD-NEXT: [[T2:%.*]] = extractelement <4 x float> [[TMP1]], i64 2
; THRESHOLD-NEXT: [[ADD4_1:%.*]] = fadd float [[T2]], [[ADD4]]
-; THRESHOLD-NEXT: [[T3:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; THRESHOLD-NEXT: [[T3:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; THRESHOLD-NEXT: [[ADD4_2:%.*]] = fadd fast float [[T3]], [[ADD4_1]]
; THRESHOLD-NEXT: [[ADD5:%.*]] = fadd fast float [[ADD4_2]], [[A]]
; THRESHOLD-NEXT: ret float [[ADD5]]
@@ -946,9 +946,9 @@ define float @extra_args_no_fast(ptr %x, float %a, float %b) {
define i32 @wobble(i32 %arg, i32 %bar) {
; CHECK-LABEL: @wobble(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG:%.*]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[BAR:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[BAR:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = xor <4 x i32> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[X4:%.*]] = xor i32 [[ARG]], [[BAR]]
@@ -961,9 +961,9 @@ define i32 @wobble(i32 %arg, i32 %bar) {
;
; THRESHOLD-LABEL: @wobble(
; THRESHOLD-NEXT: bb:
-; THRESHOLD-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG:%.*]], i32 0
+; THRESHOLD-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG:%.*]], i64 0
; THRESHOLD-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
-; THRESHOLD-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[BAR:%.*]], i32 0
+; THRESHOLD-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[BAR:%.*]], i64 0
; THRESHOLD-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; THRESHOLD-NEXT: [[TMP4:%.*]] = xor <4 x i32> [[TMP1]], [[TMP3]]
; THRESHOLD-NEXT: [[X4:%.*]] = xor i32 [[ARG]], [[BAR]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
index 5b8ef03947412..90528f949a0d5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
@@ -209,8 +209,8 @@ define float @maxf8(float) {
;
; THRESH-LABEL: @maxf8(
; THRESH-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr @arr1, align 16
-; THRESH-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; THRESH-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; THRESH-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; THRESH-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; THRESH-NEXT: [[TMP5:%.*]] = fcmp fast ogt float [[TMP3]], [[TMP4]]
; THRESH-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
; THRESH-NEXT: [[TMP7:%.*]] = load float, ptr getelementptr inbounds ([32 x float], ptr @arr1, i64 0, i64 2), align 8
@@ -312,8 +312,8 @@ define float @maxf16(float) {
;
; THRESH-LABEL: @maxf16(
; THRESH-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr @arr1, align 16
-; THRESH-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; THRESH-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; THRESH-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; THRESH-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; THRESH-NEXT: [[TMP5:%.*]] = fcmp fast ogt float [[TMP3]], [[TMP4]]
; THRESH-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
; THRESH-NEXT: [[TMP7:%.*]] = load float, ptr getelementptr inbounds ([32 x float], ptr @arr1, i64 0, i64 2), align 8
@@ -511,8 +511,8 @@ define float @maxf32(float) {
;
; THRESH-LABEL: @maxf32(
; THRESH-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr @arr1, align 16
-; THRESH-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; THRESH-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; THRESH-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; THRESH-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; THRESH-NEXT: [[TMP5:%.*]] = fcmp fast ogt float [[TMP3]], [[TMP4]]
; THRESH-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP4]]
; THRESH-NEXT: [[TMP7:%.*]] = load float, ptr getelementptr inbounds ([32 x float], ptr @arr1, i64 0, i64 2), align 8
@@ -707,8 +707,8 @@ define float @maxf32(float) {
define i32 @maxi8_mutiple_uses(i32 %0) {
; CHECK-LABEL: @maxi8_mutiple_uses(
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr @arr, align 16
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i32> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i32> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP2]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[TMP3]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP2]])
; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP5]], i32 3, i32 4
@@ -837,8 +837,8 @@ define ptr @maxp8(i32) {
;
; THRESH-LABEL: @maxp8(
; THRESH-NEXT: [[TMP2:%.*]] = load <2 x ptr>, ptr @arrp, align 16
-; THRESH-NEXT: [[TMP3:%.*]] = extractelement <2 x ptr> [[TMP2]], i32 0
-; THRESH-NEXT: [[TMP4:%.*]] = extractelement <2 x ptr> [[TMP2]], i32 1
+; THRESH-NEXT: [[TMP3:%.*]] = extractelement <2 x ptr> [[TMP2]], i64 0
+; THRESH-NEXT: [[TMP4:%.*]] = extractelement <2 x ptr> [[TMP2]], i64 1
; THRESH-NEXT: [[TMP5:%.*]] = icmp ugt ptr [[TMP3]], [[TMP4]]
; THRESH-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], ptr [[TMP3]], ptr [[TMP4]]
; THRESH-NEXT: [[TMP7:%.*]] = load ptr, ptr getelementptr inbounds ([32 x ptr], ptr @arrp, i64 0, i64 2), align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
index ce11457bfecde..9cbe1fbcf4dd0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
@@ -578,8 +578,8 @@ define void @store_red_double(ptr noalias %A, ptr noalias %B, ptr noalias %C, i3
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i64 [[MUL]]
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[ARRAYIDX2]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x double> [[TMP0]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i64 1
; CHECK-NEXT: [[ADD8:%.*]] = fadd fast double [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds double, ptr [[C:%.*]], i64 [[I_018]]
; CHECK-NEXT: store double [[ADD8]], ptr [[ARRAYIDX9]], align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/icmp-altopcode-after-reordering.ll b/llvm/test/Transforms/SLPVectorizer/X86/icmp-altopcode-after-reordering.ll
index 278e55c67f23f..e5756fb964519 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/icmp-altopcode-after-reordering.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/icmp-altopcode-after-reordering.ll
@@ -8,7 +8,7 @@ define i32 @test(ptr %sptr, i64 %0) {
; CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP0]] to i32
; CHECK-NEXT: [[IV2:%.*]] = getelementptr i8, ptr [[SPTR]], i64 4
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[IV2]], align 4
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[CONV_I]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[CONV_I]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 poison, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP3]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 1, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/identity-match-splat-less-defined.ll b/llvm/test/Transforms/SLPVectorizer/X86/identity-match-splat-less-defined.ll
index 68c0a7df33830..d800de4c5c643 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/identity-match-splat-less-defined.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/identity-match-splat-less-defined.ll
@@ -3,7 +3,7 @@
define i32 @test() {
; CHECK-LABEL: define i32 @test() {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i32> poison, i32 0, i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i32> poison, i32 0, i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <3 x i32> [[TMP1]], <3 x i32> poison, <3 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = or <3 x i32> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <3 x i32> [[TMP3]], <3 x i32> poison, <16 x i32> <i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll b/llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
index e4143a7b91168..5ff741de5d412 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
@@ -11,7 +11,7 @@ define void @in_tree_user(ptr nocapture %A, i32 %n) {
; CHECK-LABEL: @in_tree_user(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[N:%.*]] to double
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
@@ -22,9 +22,9 @@ define void @in_tree_user(ptr nocapture %A, i32 %n) {
; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], <double 7.000000e+00, double 4.000000e+00>
; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[TMP5]], <double 5.000000e+00, double 9.000000e+00>
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i64 0
; CHECK-NEXT: [[INTREEUSER:%.*]] = fadd double [[TMP7]], [[TMP7]]
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP6]], i64 1
; CHECK-NEXT: [[CMP11:%.*]] = fcmp ogt double [[TMP7]], [[TMP8]]
; CHECK-NEXT: br i1 [[CMP11]], label [[IF_THEN:%.*]], label [[FOR_INC]]
; CHECK: if.then:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/insert-after-bundle.ll b/llvm/test/Transforms/SLPVectorizer/X86/insert-after-bundle.ll
index f0a1836e6c273..0d4e37437d23c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/insert-after-bundle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/insert-after-bundle.ll
@@ -24,7 +24,7 @@ entry:
define void @bar(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, ptr noalias nocapture readonly %c, ptr noalias nocapture readonly %d, ptr noalias nocapture %e, i32 %w) local_unnamed_addr #1 {
; CHECK-LABEL: @bar(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i32> poison, i32 [[W:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i32> poison, i32 [[W:%.*]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <16 x i32> zeroinitializer
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/insert-subvector.ll b/llvm/test/Transforms/SLPVectorizer/X86/insert-subvector.ll
index 989da443dd7fd..d26d264e15e08 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/insert-subvector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/insert-subvector.ll
@@ -9,9 +9,9 @@ define <16 x double> @test(ptr %x, double %v, double %a) {
; CHECK-NEXT: [[TMP1:%.*]] = load <6 x double>, ptr [[X]], align 4
; CHECK-NEXT: [[TMP6:%.*]] = load <2 x double>, ptr [[GEP6]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr [[GEP8]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x double> poison, double [[A]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x double> poison, double [[A]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <16 x double> [[TMP4]], <16 x double> poison, <16 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <6 x double> poison, double [[V]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <6 x double> poison, double [[V]], i64 0
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <6 x double> [[TMP9]], <6 x double> poison, <6 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <6 x double> [[TMP16]], <6 x double> poison, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <2 x double> [[TMP7]], <2 x double> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/insertelement-with-copyable-args.ll b/llvm/test/Transforms/SLPVectorizer/X86/insertelement-with-copyable-args.ll
index 67fb9ddf983c9..a583d7bee1c8c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/insertelement-with-copyable-args.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/insertelement-with-copyable-args.ll
@@ -11,10 +11,12 @@ define i64 @test(i32 %arg) {
; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(1) null, align 4
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 poison>, i32 [[ARG]], i32 3
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[FREEZE]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[FREEZE]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[FREEZE]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x i32> poison, i32 [[FREEZE]], i32 0
+; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <2 x i32> [[TMP14]], <2 x i32> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i32> [[TMP15]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[ARG]], i32 0
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP5]], i32 [[LOAD]], i32 1
; CHECK-NEXT: [[TMP7:%.*]] = icmp ult <2 x i32> [[TMP4]], [[TMP6]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll b/llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
index 7609d2b3d4a40..3621a0f1c7ae0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
@@ -9,9 +9,9 @@ define void @julia_2xdouble(ptr sret([2 x double]), ptr, ptr, ptr) {
; CHECK-NEXT: [[TMP8:%.*]] = fmul <2 x double> [[TMP5]], [[TMP7]]
; CHECK-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr [[TMP1:%.*]], align 4
; CHECK-NEXT: [[TMP11:%.*]] = fadd <2 x double> [[TMP8]], [[TMP10]]
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x double> [[TMP11]], i32 0
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x double> [[TMP11]], i64 0
; CHECK-NEXT: [[I0:%.*]] = insertvalue [2 x double] undef, double [[TMP12]], 0
-; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x double> [[TMP11]], i32 1
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x double> [[TMP11]], i64 1
; CHECK-NEXT: [[I1:%.*]] = insertvalue [2 x double] [[I0]], double [[TMP13]], 1
; CHECK-NEXT: store [2 x double] [[I1]], ptr [[TMP0:%.*]], align 4
; CHECK-NEXT: ret void
@@ -44,13 +44,13 @@ define void @julia_4xfloat(ptr sret([4 x float]), ptr, ptr, ptr) {
; CHECK-NEXT: [[TMP8:%.*]] = fmul <4 x float> [[TMP5]], [[TMP7]]
; CHECK-NEXT: [[TMP10:%.*]] = load <4 x float>, ptr [[TMP1:%.*]], align 4
; CHECK-NEXT: [[TMP11:%.*]] = fadd <4 x float> [[TMP8]], [[TMP10]]
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x float> [[TMP11]], i32 0
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x float> [[TMP11]], i64 0
; CHECK-NEXT: [[I0:%.*]] = insertvalue [4 x float] undef, float [[TMP12]], 0
-; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP11]], i32 1
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP11]], i64 1
; CHECK-NEXT: [[I1:%.*]] = insertvalue [4 x float] [[I0]], float [[TMP13]], 1
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x float> [[TMP11]], i32 2
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x float> [[TMP11]], i64 2
; CHECK-NEXT: [[I2:%.*]] = insertvalue [4 x float] [[I1]], float [[TMP14]], 2
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x float> [[TMP11]], i32 3
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x float> [[TMP11]], i64 3
; CHECK-NEXT: [[I3:%.*]] = insertvalue [4 x float] [[I2]], float [[TMP15]], 3
; CHECK-NEXT: store [4 x float] [[I3]], ptr [[TMP0:%.*]], align 4
; CHECK-NEXT: ret void
@@ -99,13 +99,13 @@ define void @julia_load_array_of_float(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[A:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[B:%.*]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = fsub <4 x float> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP4]], i64 0
; CHECK-NEXT: [[C_ARR0:%.*]] = insertvalue [4 x float] undef, float [[TMP5]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP4]], i64 1
; CHECK-NEXT: [[C_ARR1:%.*]] = insertvalue [4 x float] [[C_ARR0]], float [[TMP6]], 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP4]], i32 2
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP4]], i64 2
; CHECK-NEXT: [[C_ARR2:%.*]] = insertvalue [4 x float] [[C_ARR1]], float [[TMP7]], 2
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[TMP4]], i32 3
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[TMP4]], i64 3
; CHECK-NEXT: [[C_ARR3:%.*]] = insertvalue [4 x float] [[C_ARR2]], float [[TMP8]], 3
; CHECK-NEXT: store [4 x float] [[C_ARR3]], ptr [[C:%.*]], align 4
; CHECK-NEXT: ret void
@@ -139,13 +139,13 @@ define void @julia_load_array_of_i32(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[B:%.*]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP4]], i64 0
; CHECK-NEXT: [[C_ARR0:%.*]] = insertvalue [4 x i32] undef, i32 [[TMP5]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i64 1
; CHECK-NEXT: [[C_ARR1:%.*]] = insertvalue [4 x i32] [[C_ARR0]], i32 [[TMP6]], 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP4]], i32 2
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP4]], i64 2
; CHECK-NEXT: [[C_ARR2:%.*]] = insertvalue [4 x i32] [[C_ARR1]], i32 [[TMP7]], 2
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP4]], i32 3
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP4]], i64 3
; CHECK-NEXT: [[C_ARR3:%.*]] = insertvalue [4 x i32] [[C_ARR2]], i32 [[TMP8]], 3
; CHECK-NEXT: store [4 x i32] [[C_ARR3]], ptr [[C:%.*]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/inst_size_bug.ll b/llvm/test/Transforms/SLPVectorizer/X86/inst_size_bug.ll
index 48b657e8bf6e5..7cf912c89678c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/inst_size_bug.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/inst_size_bug.ll
@@ -10,7 +10,7 @@ define void @inst_size(ptr %a, <2 x i64> %b) {
; CHECK-NEXT: [[PTR4:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 3
; CHECK-NEXT: [[TMPL4:%.*]] = load i64, ptr [[PTR4]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[B:%.*]], <2 x i64> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[TMPL1]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[TMPL1]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt <4 x i64> zeroinitializer, [[TMP3]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/inversed-icmp-to-gather.ll b/llvm/test/Transforms/SLPVectorizer/X86/inversed-icmp-to-gather.ll
index 452770182debe..f334cc31fedae 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/inversed-icmp-to-gather.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/inversed-icmp-to-gather.ll
@@ -5,7 +5,7 @@ define i16 @test(i64 %0) {
; CHECK-LABEL: define i16 @test(
; CHECK-SAME: i64 [[TMP0:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i64> poison, i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i64> poison, i64 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> [[TMP1]], <8 x i64> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i64> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <8 x i64> [[TMP2]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/landing-pad-for-split-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/landing-pad-for-split-node.ll
index 6c729d17c1a9b..81506d32aba13 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/landing-pad-for-split-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/landing-pad-for-split-node.ll
@@ -20,14 +20,14 @@ define void @test(i32 %arg) personality ptr null {
; CHECK-NEXT: [[PHI8:%.*]] = phi i32 [ 0, %[[BB]] ]
; CHECK-NEXT: [[LANDINGPAD:%.*]] = landingpad { ptr, i32 }
; CHECK-NEXT: cleanup
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LOAD]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[LOAD1]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[LOAD3]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[LOAD2]], i32 3
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> poison, i32 [[PHI]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[PHI8]], i32 1
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[PHI6]], i32 2
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[PHI7]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LOAD]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[LOAD1]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[LOAD3]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[LOAD2]], i64 3
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> poison, i32 [[PHI]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[PHI8]], i64 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[PHI6]], i64 2
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[PHI7]], i64 3
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/landing_pad.ll b/llvm/test/Transforms/SLPVectorizer/X86/landing_pad.ll
index 4282ae2ab88ec..a23088e252e0d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/landing_pad.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/landing_pad.ll
@@ -14,8 +14,8 @@ define void @foo() personality ptr @bar {
; CHECK-NEXT: ret void
; CHECK: bb3:
; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x i32> [ [[TMP3:%.*]], [[BB6:%.*]] ], [ poison, [[BB1:%.*]] ]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = invoke i32 poison(ptr addrspace(1) nonnull poison, i32 0, i32 0, i32 poison) [ "deopt"() ]
; CHECK-NEXT: to label [[BB4:%.*]] unwind label [[BB10:%.*]]
; CHECK: bb4:
@@ -40,8 +40,8 @@ define void @foo() personality ptr @bar {
; CHECK-NEXT: [[LOCAL_5_33118_LCSSA:%.*]] = phi i32 [ [[TMP4]], [[BB3]] ]
; CHECK-NEXT: [[LANDING_PAD68:%.*]] = landingpad { ptr, i32 }
; CHECK-NEXT: cleanup
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> poison, i32 [[LOCAL_10_38123_LCSSA]], i32 2
-; CHECK-NEXT: [[TMP9]] = insertelement <4 x i32> [[TMP8]], i32 [[LOCAL_5_33118_LCSSA]], i32 3
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> poison, i32 [[LOCAL_10_38123_LCSSA]], i64 2
+; CHECK-NEXT: [[TMP9]] = insertelement <4 x i32> [[TMP8]], i32 [[LOCAL_5_33118_LCSSA]], i64 3
; CHECK-NEXT: br label [[BB9]]
; CHECK: bb11:
; CHECK-NEXT: ret void
@@ -50,8 +50,8 @@ define void @foo() personality ptr @bar {
; CHECK-NEXT: [[LOCAL_5_84111_LCSSA:%.*]] = phi i32 [ [[LOCAL_5_84111]], [[BB7]] ]
; CHECK-NEXT: [[LANDING_PAD149:%.*]] = landingpad { ptr, i32 }
; CHECK-NEXT: cleanup
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> poison, i32 [[LOCAL_10_89113_LCSSA]], i32 2
-; CHECK-NEXT: [[TMP11]] = insertelement <4 x i32> [[TMP12]], i32 [[LOCAL_5_84111_LCSSA]], i32 3
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> poison, i32 [[LOCAL_10_89113_LCSSA]], i64 2
+; CHECK-NEXT: [[TMP11]] = insertelement <4 x i32> [[TMP12]], i32 [[LOCAL_5_84111_LCSSA]], i64 3
; CHECK-NEXT: br label [[BB9]]
;
bb1:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
index 9c045a57e665c..daf93190cab6d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
@@ -107,13 +107,13 @@ define void @PR43578_prefer128(ptr %r, ptr %p, ptr %q) #0 {
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[P2]], align 2
; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr [[Q2]], align 2
; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <2 x i64> [[TMP4]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0
; CHECK-NEXT: [[G0:%.*]] = getelementptr inbounds i32, ptr [[R:%.*]], i64 [[TMP7]]
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP3]], i64 1
; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP8]]
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP6]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP6]], i64 0
; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP9]]
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP6]], i64 1
; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP10]]
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll b/llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll
index 954b920418075..b407a83333502 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll
@@ -107,13 +107,13 @@ define void @PR43578_prefer128(ptr %r, ptr %p, ptr %q) #0 {
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[P2]], align 2
; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr [[Q2]], align 2
; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <2 x i64> [[TMP4]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0
; CHECK-NEXT: [[G0:%.*]] = getelementptr inbounds i32, ptr [[R:%.*]], i64 [[TMP7]]
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP3]], i64 1
; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP8]]
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP6]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP6]], i64 0
; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP9]]
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP6]], i64 1
; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP10]]
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll b/llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
index cd6a610cd79fd..c926ef716b2a3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
@@ -361,8 +361,8 @@ define void @lookahead_crash(ptr %A, ptr %S, ptr %Arg0) {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[C0:%.*]] = call double @_ZN1i2ayEv(ptr [[ARG0:%.*]])
; CHECK-NEXT: [[C1:%.*]] = call double @_ZN1i2axEv()
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[C0]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[C1]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[C0]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[C1]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = fadd fast <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[S:%.*]], align 8
; CHECK-NEXT: ret void
@@ -392,10 +392,10 @@ define void @ChecksExtractScores(ptr %storeArray, ptr %array, ptr %vecPtr1, ptr
; CHECK-NEXT: [[LOADA1:%.*]] = load double, ptr [[IDX1]], align 4
; CHECK-NEXT: [[LOADVEC:%.*]] = load <2 x double>, ptr [[VECPTR1:%.*]], align 4
; CHECK-NEXT: [[LOADVEC2:%.*]] = load <2 x double>, ptr [[VECPTR2:%.*]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[LOADA0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[LOADA0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[LOADVEC]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[LOADA1]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[LOADA1]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x double> [[LOADVEC2]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = fadd <2 x double> [[TMP3]], [[TMP6]]
@@ -543,11 +543,11 @@ define void @ChecksExtractScores_different_vectors(ptr %storeArray, ptr %array,
; AVX-NEXT: [[LOADVEC3:%.*]] = load <2 x double>, ptr [[VECPTR3:%.*]], align 4
; AVX-NEXT: [[LOADVEC4:%.*]] = load <2 x double>, ptr [[VECPTR4:%.*]], align 4
; AVX-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[LOADVEC]], <2 x double> [[LOADVEC2]], <2 x i32> <i32 0, i32 3>
-; AVX-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[LOADA0]], i32 0
+; AVX-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[LOADA0]], i64 0
; AVX-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; AVX-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP1]], [[TMP3]]
; AVX-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[LOADVEC3]], <2 x double> [[LOADVEC4]], <2 x i32> <i32 0, i32 3>
-; AVX-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[LOADA1]], i32 0
+; AVX-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[LOADA1]], i64 0
; AVX-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> poison, <2 x i32> zeroinitializer
; AVX-NEXT: [[TMP8:%.*]] = fmul <2 x double> [[TMP5]], [[TMP7]]
; AVX-NEXT: [[TMP9:%.*]] = fadd <2 x double> [[TMP4]], [[TMP8]]
@@ -590,11 +590,11 @@ define double @splat_loads(ptr %array1, ptr %array2, ptr %ptrA, ptr %ptrB) {
; SSE-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAY2:%.*]], align 8
; SSE-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; SSE-NEXT: [[TMP4:%.*]] = fmul <4 x double> [[TMP2]], [[TMP3]]
-; SSE-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP4]], i32 0
-; SSE-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP4]], i32 2
+; SSE-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP4]], i64 0
+; SSE-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP4]], i64 2
; SSE-NEXT: [[ADD3:%.*]] = fadd double [[TMP6]], [[TMP7]]
-; SSE-NEXT: [[TMP9:%.*]] = extractelement <4 x double> [[TMP4]], i32 1
-; SSE-NEXT: [[TMP8:%.*]] = extractelement <4 x double> [[TMP4]], i32 3
+; SSE-NEXT: [[TMP9:%.*]] = extractelement <4 x double> [[TMP4]], i64 1
+; SSE-NEXT: [[TMP8:%.*]] = extractelement <4 x double> [[TMP4]], i64 3
; SSE-NEXT: [[ADD2:%.*]] = fadd double [[TMP9]], [[TMP8]]
; SSE-NEXT: [[ADD4:%.*]] = fadd double [[ADD3]], [[ADD2]]
; SSE-NEXT: ret double [[ADD4]]
@@ -651,8 +651,8 @@ define double @splat_loads_with_internal_uses(ptr %array1, ptr %array2, ptr %ptr
; SSE-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP3]], [[TMP4]]
; SSE-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer
; SSE-NEXT: [[TMP7:%.*]] = fsub <2 x double> [[TMP5]], [[TMP6]]
-; SSE-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i32 0
-; SSE-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i32 1
+; SSE-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i64 0
+; SSE-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i64 1
; SSE-NEXT: [[RES:%.*]] = fadd double [[TMP8]], [[TMP9]]
; SSE-NEXT: ret double [[RES]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll b/llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
index 20b0885b22537..e6d6bef177db5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
@@ -13,7 +13,7 @@ define i32 @foo(ptr nocapture %A, i32 %n) {
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVARS_IV]]
; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr [[ARRAYIDX]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[N]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[N]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <8 x i32> [[TMP0]], [[TMP2]]
; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr [[ARRAYIDX]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll b/llvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
index 311a08f4180cc..42c5b4d0eae68 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/malformed_phis.ll
@@ -12,7 +12,7 @@ define void @test() #0 {
; CHECK: bb1:
; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ 1, [[BB1]] ], [ 2, [[BB:%.*]] ]
; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ [[TMP18:%.*]], [[BB1]] ], [ 3, [[BB]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i32> poison, i32 [[TMP]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i32> poison, i32 [[TMP]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <16 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> [[TMP1]])
; CHECK-NEXT: [[TMP18]] = mul i32 [[TMP2]], 4
@@ -93,8 +93,8 @@ define i64 @test_3() #0 {
; CHECK: bb3:
; CHECK-NEXT: [[TMP2:%.*]] = phi <2 x i32> [ splat (i32 3), [[BB1]] ], [ poison, [[BB2:%.*]] ]
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <28 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1>
-; CHECK-NEXT: [[VAL4:%.*]] = extractelement <28 x i32> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <32 x i32> poison, i32 [[VAL4]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <28 x i32> [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <32 x i32> poison, i32 [[TMP4]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> [[TMP0]], <32 x i32> poison, <32 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <32 x i32> [[TMP1]], <32 x i32> poison, <28 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
; CHECK-NEXT: [[RDX_OP:%.*]] = mul <28 x i32> [[TMP5]], [[TMP3]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/many-uses-parent-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/many-uses-parent-node.ll
index 75713615fbbf7..d958dcb51dfd8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/many-uses-parent-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/many-uses-parent-node.ll
@@ -7,7 +7,7 @@ define i32 @test(ptr addrspace(1) %arg) {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr addrspace(1)> poison, ptr addrspace(1) [[ARG]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr addrspace(1)> poison, ptr addrspace(1) [[ARG]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x ptr addrspace(1)> [[TMP0]], <2 x ptr addrspace(1)> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, <2 x ptr addrspace(1)> [[TMP1]], <2 x i64> <i64 21, i64 22>
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr addrspace(1)> [[TMP1]], <2 x i64> <i64 20, i64 21>
@@ -127,7 +127,7 @@ define i32 @test(ptr addrspace(1) %arg) {
; CHECK: [[BB72:.*]]:
; CHECK-NEXT: br i1 false, label %[[BB142:.*]], label %[[BB79:.*]]
; CHECK: [[BB73]]:
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x ptr addrspace(1)> <ptr addrspace(1) poison, ptr addrspace(1) null>, ptr addrspace(1) [[GETELEMENTPTR3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x ptr addrspace(1)> <ptr addrspace(1) poison, ptr addrspace(1) null>, ptr addrspace(1) [[GETELEMENTPTR3]], i64 0
; CHECK-NEXT: br i1 false, label %[[BB146:.*]], label %[[BB74:.*]]
; CHECK: [[BB74]]:
; CHECK-NEXT: br i1 false, label %[[BB75:.*]], label %[[BB76:.*]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/matched-bv-schedulable.ll b/llvm/test/Transforms/SLPVectorizer/X86/matched-bv-schedulable.ll
index 6fa33671a7b53..77b1dea020fab 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/matched-bv-schedulable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/matched-bv-schedulable.ll
@@ -7,12 +7,12 @@ define void @test() {
; CHECK-NEXT: br i1 false, label %[[BB1:.*]], label %[[BB5:.*]]
; CHECK: [[BB1]]:
; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ [[TMP3:%.*]], %[[BB1]] ], [ zeroinitializer, %[[BB]] ]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 0, i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 0, i64 0
; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i32> [[TMP0]], [[TMP4]]
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> <i32 poison, i32 0>, <2 x i32> <i32 0, i32 3>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> <i32 poison, i32 1>, i32 0, i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> <i32 poison, i32 1>, i32 0, i64 0
; CHECK-NEXT: [[TMP3]] = or <2 x i32> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP5]], i64 1
; CHECK-NEXT: [[OR3:%.*]] = or i32 [[TMP6]], 0
; CHECK-NEXT: br i1 false, label %[[BB1]], label %[[BB5]]
; CHECK: [[BB5]]:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/matched-gather-part-of-combined.ll b/llvm/test/Transforms/SLPVectorizer/X86/matched-gather-part-of-combined.ll
index ebc163d983044..d20dc5c39bbd2 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/matched-gather-part-of-combined.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/matched-gather-part-of-combined.ll
@@ -7,7 +7,7 @@ define void @test(ptr %0, i32 %.sroa.31.0.copyload4033) {
; CHECK-NEXT: [[_PREHEADER1937_PREHEADER:.*:]]
; CHECK-NEXT: br [[DOTPREHEADER1927_PREHEADER:label %.*]]
; CHECK: [[_PREHEADER1927_PREHEADER:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[DOTSROA_31_0_COPYLOAD4033]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[DOTSROA_31_0_COPYLOAD4033]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: br [[DOTPREHEADER1927:label %.*]]
; CHECK: [[_LOOPEXIT1924:.*:]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll b/llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
index b1864b43512d8..1d0b439be33c0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/matched-nodes-updated.ll
@@ -5,11 +5,11 @@ define i32 @test(i32 %s.0) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[S_0:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 0>, i32 [[S_0]], i32 2
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 0>, i32 [[S_0]], i64 2
; CHECK-NEXT: br label %[[K:.*]]
; CHECK: [[K]]:
-; CHECK-NEXT: [[DOTPRE:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[TMP17:%.*]], %[[T:.*]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[DOTPRE]], i32 1
+; CHECK-NEXT: [[DOTPRE:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[TMP14:%.*]], %[[T:.*]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[DOTPRE]], i64 1
; CHECK-NEXT: br label %[[O:.*]]
; CHECK: [[IF_END3:.*]]:
; CHECK-NEXT: br label %[[IF_END6:.*]]
@@ -18,7 +18,7 @@ define i32 @test(i32 %s.0) {
; CHECK-NEXT: [[TMP3:%.*]] = phi <4 x i32> [ poison, %[[IF_END3]] ], [ zeroinitializer, %[[O]] ]
; CHECK-NEXT: [[TMP4:%.*]] = phi <2 x i32> [ poison, %[[IF_END3]] ], [ [[TMP29:%.*]], %[[O]] ]
; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i32> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 [[TMP22:%.*]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 [[TMP22:%.*]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> [[TMP7]], <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 10, i32 11, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP30:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <8 x i32> <i32 1, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -32,7 +32,7 @@ define i32 @test(i32 %s.0) {
; CHECK-NEXT: br label %[[T]]
; CHECK: [[T]]:
; CHECK-NEXT: [[TMP13:%.*]] = phi <8 x i32> [ [[TMP33:%.*]], %[[O]] ], [ poison, %[[IF_THEN18]] ]
-; CHECK-NEXT: [[TMP17]] = extractelement <4 x i32> [[TMP23:%.*]], i32 0
+; CHECK-NEXT: [[TMP14]] = extractelement <4 x i32> [[TMP23:%.*]], i64 0
; CHECK-NEXT: br i1 false, label %[[IF_END24]], label %[[K]]
; CHECK: [[IF_END24]]:
; CHECK-NEXT: [[TMP18:%.*]] = phi <8 x i32> [ [[TMP12]], %[[IF_THEN11]] ], [ [[TMP31]], %[[IF_END6]] ], [ [[TMP13]], %[[T]] ]
@@ -44,7 +44,7 @@ define i32 @test(i32 %s.0) {
; CHECK-NEXT: [[TMP23]] = phi <4 x i32> [ [[TMP1]], %[[K]] ], [ [[TMP20]], %[[IF_END24]] ]
; CHECK-NEXT: [[TMP24]] = phi <2 x i32> [ zeroinitializer, %[[K]] ], [ [[TMP19]], %[[IF_END24]] ]
; CHECK-NEXT: [[TMP21:%.*]] = phi <4 x i32> [ zeroinitializer, %[[K]] ], [ [[TMP34]], %[[IF_END24]] ]
-; CHECK-NEXT: [[TMP22]] = extractelement <2 x i32> [[TMP24]], i32 1
+; CHECK-NEXT: [[TMP22]] = extractelement <2 x i32> [[TMP24]], i64 1
; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i32> [[TMP23]], <4 x i32> poison, <8 x i32> <i32 0, i32 poison, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP26:%.*]] = shufflevector <8 x i32> [[TMP25]], <8 x i32> <i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, <8 x i32> <i32 0, i32 9, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP32:%.*]] = shufflevector <4 x i32> [[TMP23]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/matched-shuffled-entries.ll b/llvm/test/Transforms/SLPVectorizer/X86/matched-shuffled-entries.ll
index 29b525d137f7f..7f417e48c918c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/matched-shuffled-entries.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/matched-shuffled-entries.ll
@@ -10,12 +10,12 @@ define i32 @bar() local_unnamed_addr {
; CHECK-NEXT: [[ADD78_2:%.*]] = add nsw i32 undef, undef
; CHECK-NEXT: [[SUB102_3:%.*]] = sub nsw i32 undef, undef
; CHECK-NEXT: [[SUB102_4:%.*]] = sub nsw i32 undef, undef
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> <i32 undef, i32 undef, i32 poison, i32 poison, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[SUB102_3]], i32 2
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> [[TMP0]], i32 [[ADD78_2]], i32 3
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> <i32 undef, i32 undef, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 undef>, i32 [[SUB102_1]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[ADD78_1]], i32 3
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[ADD94_1]], i32 5
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[SUB102_4]], i32 6
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> <i32 undef, i32 undef, i32 poison, i32 poison, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[SUB102_3]], i64 2
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> [[TMP0]], i32 [[ADD78_2]], i64 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> <i32 undef, i32 undef, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 undef>, i32 [[SUB102_1]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[ADD78_1]], i64 3
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[ADD94_1]], i64 5
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[SUB102_4]], i64 6
; CHECK-NEXT: [[TMP6:%.*]] = add nsw <8 x i32> [[TMP1]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP5]], <8 x i32> <i32 undef, i32 undef, i32 poison, i32 poison, i32 poison, i32 undef, i32 undef, i32 undef>, <8 x i32> <i32 8, i32 9, i32 3, i32 2, i32 5, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP5]], <8 x i32> <i32 poison, i32 poison, i32 3, i32 2, i32 poison, i32 poison, i32 poison, i32 14>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/matching-gather-nodes-phi-users.ll b/llvm/test/Transforms/SLPVectorizer/X86/matching-gather-nodes-phi-users.ll
index d0b0441315d57..fd2813de9f529 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/matching-gather-nodes-phi-users.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/matching-gather-nodes-phi-users.ll
@@ -34,10 +34,10 @@ define void @test(ptr %dst, float %a, float %b, float %c, float %d) {
; CHECK-NEXT: [[CALL1:%.*]] = call fast float @foo(float [[B]])
; CHECK-NEXT: [[CALL2:%.*]] = call fast float @foo(float [[C]])
; CHECK-NEXT: [[CALL3:%.*]] = call fast float @foo(float [[D]])
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> poison, float [[CALL0]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[CALL1]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[CALL2]], i32 2
-; CHECK-NEXT: [[TMP5]] = insertelement <4 x float> [[TMP4]], float [[CALL3]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> poison, float [[CALL0]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[CALL1]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[CALL2]], i64 2
+; CHECK-NEXT: [[TMP5]] = insertelement <4 x float> [[TMP4]], float [[CALL3]], i64 3
; CHECK-NEXT: br i1 poison, label [[USERBLOCK0]], label [[USERBLOCK1]]
; CHECK: UserBlock1:
; CHECK-NEXT: [[TMP6:%.*]] = phi <4 x float> [ [[TMP5]], [[BLKX]] ], [ [[TMP9:%.*]], [[LOOP_INNER]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/matching-insert-point-for-nodes.ll b/llvm/test/Transforms/SLPVectorizer/X86/matching-insert-point-for-nodes.ll
index d7797ec26bb45..d7176bbede356 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/matching-insert-point-for-nodes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/matching-insert-point-for-nodes.ll
@@ -16,9 +16,9 @@ define i32 @test() {
; CHECK: [[BB11]]:
; CHECK-NEXT: br i1 false, label %[[BB12:.*]], label %[[BB16:.*]]
; CHECK: [[BB12]]:
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
; CHECK-NEXT: [[OR:%.*]] = or i32 0, [[TMP4]]
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[OR]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[OR]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> [[TMP1]], <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: br label %[[BB13:.*]]
; CHECK: [[BB13]]:
@@ -26,8 +26,8 @@ define i32 @test() {
; CHECK-NEXT: br label %[[BB16]]
; CHECK: [[BB16]]:
; CHECK-NEXT: [[TMP8:%.*]] = phi <2 x i32> [ zeroinitializer, %[[BB11]] ], [ [[TMP7]], %[[BB13]] ]
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i32> [[TMP8]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i32> [[TMP8]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i32> [[TMP8]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i32> [[TMP8]], i64 1
; CHECK-NEXT: br label %[[BB19]]
; CHECK: [[BB19]]:
; CHECK-NEXT: [[PHI20:%.*]] = phi i32 [ 0, %[[BB4]] ], [ [[TMP10]], %[[BB16]] ]
@@ -38,12 +38,12 @@ define i32 @test() {
; CHECK: [[BB24]]:
; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[PHI20]], 0
; CHECK-NEXT: [[AND:%.*]] = and i32 [[LSHR]], 0
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[LSHR25:%.*]] = lshr i32 [[TMP11]], [[AND]]
; CHECK-NEXT: [[OR26:%.*]] = or i32 0, [[OR23]]
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> poison, i32 [[OR26]], i32 2
-; CHECK-NEXT: [[TMP13]] = insertelement <4 x i32> [[TMP12]], i32 [[LSHR25]], i32 3
-; CHECK-NEXT: [[TMP14]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[LSHR25]], i32 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> poison, i32 [[OR26]], i64 2
+; CHECK-NEXT: [[TMP13]] = insertelement <4 x i32> [[TMP12]], i32 [[LSHR25]], i64 3
+; CHECK-NEXT: [[TMP14]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[LSHR25]], i64 1
; CHECK-NEXT: br label %[[BB1]]
;
bb:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll b/llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll
index 281019e8befa6..2d19a8c22cac1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/memory-runtime-checks.ll
@@ -189,7 +189,7 @@ define void @gather_sequence_crash(<2 x float> %arg, ptr %arg1, float %arg2, ptr
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, ptr [[ARG1:%.*]], i32 3
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <2 x float> [[ARG:%.*]], <2 x float> poison, <4 x i32> <i32 poison, i32 0, i32 1, i32 poison>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> <float poison, float poison, float poison, float 0.000000e+00>, <4 x i32> <i32 poison, i32 1, i32 2, i32 7>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> poison, float [[ARG2:%.*]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> poison, float [[ARG2:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP6]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x float> [[TMP2]], zeroinitializer
; CHECK-NEXT: store <4 x float> [[TMP3]], ptr [[TMP8]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-cast.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-cast.ll
index 6d4ef87db2dd3..630cf0cd01e4e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-cast.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-cast.ll
@@ -6,13 +6,13 @@ define ptr @test(i8 %0) {
; CHECK-SAME: i8 [[TMP0:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CONV12_I:%.*]] = zext i8 [[TMP0]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[CONV12_I]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[CONV12_I]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i32> [[TMP2]] to <2 x i8>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i8> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i8> [[TMP3]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP4]] to i64
; CHECK-NEXT: [[ARRAYIDX50_I:%.*]] = getelementptr i8, ptr null, i64 [[TMP5]]
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[TMP3]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = zext i8 [[TMP6]] to i64
; CHECK-NEXT: [[ARRAYIDX16_I:%.*]] = getelementptr i8, ptr null, i64 [[TMP7]]
; CHECK-NEXT: ret ptr null
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
index 285397fefb68a..efa6337d9f365 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
@@ -6,7 +6,7 @@ define i32 @test() {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_PROMOTED:%.*]] = load i8, ptr null, align 1
; CHECK-NEXT: [[TMP10:%.*]] = or i8 [[A_PROMOTED]], 0
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[A_PROMOTED]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[A_PROMOTED]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i8> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll
index 60c067e6555ef..56d0c75cd171b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll
@@ -13,8 +13,8 @@ define i1 @test(ptr noalias %0, i64 %1, ptr noalias %p, ptr %p1) {
; CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 16
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 16
; CHECK-NEXT: [[BF_LOAD_I1345:%.*]] = load i24, ptr [[TMP5]], align 16
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i24> poison, i24 [[BF_LOAD_I1336]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i24> [[TMP6]], i24 [[BF_LOAD_I1345]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i24> poison, i24 [[BF_LOAD_I1336]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i24> [[TMP6]], i24 [[BF_LOAD_I1345]], i64 1
; CHECK-NEXT: [[TMP8:%.*]] = and <2 x i24> [[TMP7]], splat (i24 255)
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq <2 x i24> [[TMP8]], splat (i24 24)
; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[TMP9]], <2 x i24> splat (i24 23), <2 x i24> [[TMP8]]
@@ -26,9 +26,9 @@ define i1 @test(ptr noalias %0, i64 %1, ptr noalias %p, ptr %p1) {
; CHECK-NEXT: [[TMP16:%.*]] = select <2 x i1> [[TMP17]], <2 x i32> splat (i32 31), <2 x i32> [[TMP14]]
; CHECK-NEXT: [[TMP27:%.*]] = icmp eq <2 x i32> [[TMP16]], splat (i32 54)
; CHECK-NEXT: [[TMP18:%.*]] = select <2 x i1> [[TMP27]], <2 x i32> splat (i32 53), <2 x i32> [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP18]], i32 0
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP18]], i64 0
; CHECK-NEXT: store i32 [[TMP19]], ptr [[P1]], align 4
-; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i32> [[TMP18]], i32 1
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i32> [[TMP18]], i64 1
; CHECK-NEXT: [[CMP210_NOT:%.*]] = icmp eq i32 [[TMP19]], [[TMP20]]
; CHECK-NEXT: ret i1 [[CMP210_NOT]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll
index 6da0ecef5cd96..616426467d02e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll
@@ -5,7 +5,7 @@ define void @test(i64 %d.promoted.i) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i64 [[D_PROMOTED_I:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> <i64 poison, i64 0>, i64 [[D_PROMOTED_I]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> <i64 poison, i64 0>, i64 [[D_PROMOTED_I]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> zeroinitializer, [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP2]] to <2 x i1>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i1> [[TMP3]], <2 x i1> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minbw-bitcast-to-fp.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbw-bitcast-to-fp.ll
index 29c58621ad0af..d2cf49a312f93 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/minbw-bitcast-to-fp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/minbw-bitcast-to-fp.ll
@@ -5,7 +5,7 @@ define i16 @test(i16 %conv11) {
; CHECK-LABEL: define i16 @test(
; CHECK-SAME: i16 [[CONV11:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 0, i16 0, i16 0, i16 poison>, i16 [[CONV11]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 0, i16 0, i16 0, i16 poison>, i16 [[CONV11]], i64 3
; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i16> [[TMP0]], zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i64>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP2]] to <4 x double>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll b/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
index 3b085ee821001..cb826e27b55be 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/minimum-sizes.ll
@@ -30,13 +30,13 @@ define i8 @PR31243_zext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {
;
; AVX-LABEL: @PR31243_zext(
; AVX-NEXT: entry:
-; AVX-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[V0:%.*]], i32 0
-; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[V1:%.*]], i32 1
+; AVX-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[V0:%.*]], i64 0
+; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[V1:%.*]], i64 1
; AVX-NEXT: [[TMP2:%.*]] = or <2 x i8> [[TMP1]], splat (i8 1)
-; AVX-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i32 0
+; AVX-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i64 0
; AVX-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
; AVX-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i32 [[TMP4]]
-; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i32 1
+; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i64 1
; AVX-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32
; AVX-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 [[TMP6]]
; AVX-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1
@@ -86,13 +86,13 @@ define i8 @PR31243_sext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %ptr) {
;
; AVX-LABEL: @PR31243_sext(
; AVX-NEXT: entry:
-; AVX-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[V0:%.*]], i32 0
-; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[V1:%.*]], i32 1
+; AVX-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> poison, i8 [[V0:%.*]], i64 0
+; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[V1:%.*]], i64 1
; AVX-NEXT: [[TMP2:%.*]] = or <2 x i8> [[TMP1]], splat (i8 1)
-; AVX-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i32 0
+; AVX-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i64 0
; AVX-NEXT: [[TMP4:%.*]] = sext i8 [[TMP3]] to i32
; AVX-NEXT: [[T4:%.*]] = getelementptr inbounds i8, ptr [[PTR:%.*]], i32 [[TMP4]]
-; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i32 1
+; AVX-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i64 1
; AVX-NEXT: [[TMP6:%.*]] = sext i8 [[TMP5]] to i32
; AVX-NEXT: [[T5:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 [[TMP6]]
; AVX-NEXT: [[T6:%.*]] = load i8, ptr [[T4]], align 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll b/llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
index d0af6a8811c31..ade4507710150 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/mul-shl-nsw-intmin.ll
@@ -6,8 +6,8 @@
; nsw and the vector op must not be nsw.
define void @mul_intmin_converted_to_shl(ptr %p, i32 %x, i32 %y) {
; CHECK-LABEL: @mul_intmin_converted_to_shl(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i32> [[TMP2]], <i32 1, i32 31>
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr [[P:%.*]], align 4
; CHECK-NEXT: ret void
@@ -23,8 +23,8 @@ define void @mul_intmin_converted_to_shl(ptr %p, i32 %x, i32 %y) {
; The mul lane keeps its own opcode (no conversion), so nsw stays valid.
define void @keep_nsw_same_opcode(ptr %p, i32 %x, i32 %y) {
; CHECK-LABEL: @keep_nsw_same_opcode(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = mul nsw <2 x i32> [[TMP2]], <i32 2, i32 -2147483648>
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr [[P:%.*]], align 4
; CHECK-NEXT: ret void
@@ -40,8 +40,8 @@ define void @keep_nsw_same_opcode(ptr %p, i32 %x, i32 %y) {
; Non-INT_MIN power-of-2 mul converted to shl preserves nsw.
define void @keep_nsw_non_intmin(ptr %p, i32 %x, i32 %y) {
; CHECK-LABEL: @keep_nsw_non_intmin(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[Y:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = shl nsw <2 x i32> [[TMP2]], <i32 1, i32 2>
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr [[P:%.*]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
index 4f9ffb77718d0..f7897b4e8441e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
@@ -6,7 +6,7 @@ define i32 @foo() {
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[D:%.*]] = load i32, ptr null, align 4
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> poison, i32 [[D]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> poison, i32 [[D]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> [[TMP3]], <8 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x i32> <i32 0, i32 undef, i32 1, i32 0>, <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
index af1a32320d567..cfb02a9ad5c32 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi-node-for-copyable-parent.ll
@@ -6,8 +6,8 @@ define i1 @test(double %circ_radius, ptr %x) {
; CHECK-SAME: double [[CIRC_RADIUS:%.*]], ptr [[X:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[X]], align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[CIRC_RADIUS]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[CIRC_RADIUS]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[TMP0]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT: [[TMP4:%.*]] = fadd <4 x double> [[TMP3]], <double -0.000000e+00, double -0.000000e+00, double 0.000000e+00, double -0.000000e+00>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> <double 0.000000e+00, double poison, double 0.000000e+00, double 0.000000e+00>, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi-node-reuse-in-bv.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi-node-reuse-in-bv.ll
index a9f2ed61d9ee4..b77d5c0aba5b8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi-node-reuse-in-bv.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi-node-reuse-in-bv.ll
@@ -17,7 +17,7 @@ define i64 @test() {
; CHECK-LABEL: define i64 @test(
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 0, i32 1, i32 0>, i32 0, i32 6
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 0, i32 1, i32 0>, i32 0, i64 6
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <32 x i32> [[TMP0]], <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <32 x i32> [[TMP1]], <32 x i32> <i32 0, i32 0, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 32, i32 33, i32 34, i32 35, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: [[TMP3:%.*]] = sub <32 x i32> zeroinitializer, [[TMP2]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi-node-user-with-copyable-ops.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi-node-user-with-copyable-ops.ll
index 9bf1c85bfd4a5..1753c9e29dbfb 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi-node-user-with-copyable-ops.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi-node-user-with-copyable-ops.ll
@@ -6,14 +6,14 @@ define i1 @test(double %circ_radius, ptr %x, double %0) {
; CHECK-SAME: double [[CIRC_RADIUS:%.*]], ptr [[X:%.*]], double [[TMP0:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[X]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> poison, double [[TMP0]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> poison, double [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[TMP1]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x double> [[TMP4]], <double -0.000000e+00, double -0.000000e+00, double 0.000000e+00, double -0.000000e+00>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> <double 0.000000e+00, double poison, double 0.000000e+00, double 0.000000e+00>, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
; CHECK-NEXT: [[TMP7:%.*]] = fmul <4 x double> [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x double> [[TMP7]], <4 x double> poison, <4 x i32> <i32 1, i32 2, i32 poison, i32 0>
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x double> poison, double [[CIRC_RADIUS]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x double> poison, double [[CIRC_RADIUS]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x double> [[TMP9]], <4 x double> poison, <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP8]], <4 x double> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
; CHECK-NEXT: [[TMP12:%.*]] = fadd <4 x double> [[TMP7]], [[TMP11]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi-nodes-to-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi-nodes-to-shuffle.ll
index a48076adc8090..9d73d2a7d89d0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi-nodes-to-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi-nodes-to-shuffle.ll
@@ -5,10 +5,10 @@
define void @test(i64 %p0, i64 %p1, i64 %p2, i64 %p3) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[P0:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[P1:%.*]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[P2:%.*]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[P3:%.*]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[P0:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[P1:%.*]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[P2:%.*]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[P3:%.*]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i64> [[TMP3]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = mul <4 x i64> [[TMP3]], [[TMP3]]
; CHECK-NEXT: [[TMP6:%.*]] = sdiv <4 x i64> [[TMP3]], [[TMP3]]
@@ -30,10 +30,10 @@ define void @test(i64 %p0, i64 %p1, i64 %p2, i64 %p3) {
;
; AVX2-LABEL: @test(
; AVX2-NEXT: entry:
-; AVX2-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[P0:%.*]], i32 0
-; AVX2-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[P1:%.*]], i32 1
-; AVX2-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[P2:%.*]], i32 2
-; AVX2-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[P3:%.*]], i32 3
+; AVX2-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[P0:%.*]], i64 0
+; AVX2-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[P1:%.*]], i64 1
+; AVX2-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> [[TMP1]], i64 [[P2:%.*]], i64 2
+; AVX2-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[P3:%.*]], i64 3
; AVX2-NEXT: [[TMP4:%.*]] = add <4 x i64> [[TMP3]], [[TMP3]]
; AVX2-NEXT: [[TMP5:%.*]] = mul <4 x i64> [[TMP3]], [[TMP3]]
; AVX2-NEXT: [[TMP6:%.*]] = sdiv <4 x i64> [[TMP3]], [[TMP3]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi-parent-instr-copyable-regular.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi-parent-instr-copyable-regular.ll
index bd9d3813b9068..d7ba46ff439a6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi-parent-instr-copyable-regular.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi-parent-instr-copyable-regular.ll
@@ -11,19 +11,19 @@ define void @test(ptr %0, ptr %1, ptr %2, ptr %3, double %4, double %5) {
; CHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP2]], align 8
; CHECK-NEXT: [[TMP15:%.*]] = fmul double [[TMP9]], 0.000000e+00
; CHECK-NEXT: [[TMP16:%.*]] = fmul double [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x double> poison, double [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x double> [[TMP10]], double [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x double> poison, double [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x double> [[TMP19]], double [[TMP5]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x double> [[TMP11]], <4 x double> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x double> <double 0.000000e+00, double 0.000000e+00, double 1.000000e+00, double poison>, double [[TMP4]], i32 3
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x double> <double 0.000000e+00, double 0.000000e+00, double 1.000000e+00, double poison>, double [[TMP4]], i64 3
; CHECK-NEXT: [[TMP14:%.*]] = fmul <4 x double> [[TMP12]], [[TMP13]]
; CHECK-NEXT: [[TMP17:%.*]] = fmul double [[TMP15]], [[TMP8]]
; CHECK-NEXT: [[TMP18:%.*]] = fmul double [[TMP9]], [[TMP16]]
; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <4 x double> [[TMP12]], <4 x double> <double 1.000000e+00, double 1.000000e+00, double poison, double poison>, <4 x i32> <i32 4, i32 5, i32 0, i32 0>
; CHECK-NEXT: [[TMP22:%.*]] = fmul <4 x double> [[TMP12]], [[TMP21]]
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x double> <double 0.000000e+00, double poison, double 1.000000e+00, double 0.000000e+00>, double [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x double> <double 0.000000e+00, double poison, double 1.000000e+00, double 0.000000e+00>, double [[TMP7]], i64 1
; CHECK-NEXT: [[TMP24:%.*]] = fmul <4 x double> [[TMP23]], [[TMP14]]
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x double> [[TMP24]], double [[TMP18]], i32 0
-; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x double> [[TMP25]], double [[TMP17]], i32 2
+; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x double> [[TMP24]], double [[TMP18]], i64 0
+; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x double> [[TMP25]], double [[TMP17]], i64 2
; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <4 x double> [[TMP26]], <4 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
; CHECK-NEXT: [[TMP28:%.*]] = fmul <4 x double> [[TMP27]], zeroinitializer
; CHECK-NEXT: [[TMP29:%.*]] = fmul <4 x double> [[TMP22]], <double 1.000000e+00, double 1.000000e+00, double 0.000000e+00, double 0.000000e+00>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi-use-bitcasted-reduction.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi-use-bitcasted-reduction.ll
index b112953581297..9f24074dd0f00 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi-use-bitcasted-reduction.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi-use-bitcasted-reduction.ll
@@ -5,8 +5,8 @@ define i32 @test(i32 %arg, i32 %arg1, i1 %arg4, i1 %arg5) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]], i1 [[ARG4:%.*]], i1 [[ARG5:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[BB:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[ARG1]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[ARG1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
; CHECK-NEXT: [[TMP3:%.*]] = sdiv <4 x i32> [[TMP2]], splat (i32 64)
; CHECK-NEXT: [[TMP4:%.*]] = shl <4 x i32> [[TMP3]], <i32 1, i32 0, i32 0, i32 0>
@@ -23,14 +23,14 @@ define i32 @test(i32 %arg, i32 %arg1, i1 %arg4, i1 %arg5) {
; CHECK: [[BB16]]:
; CHECK-NEXT: br i1 [[ARG5]], label %[[BB17]], label %[[BB20]]
; CHECK: [[BB17]]:
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[TMP7]], i64 1
; CHECK-NEXT: [[OR18:%.*]] = or i32 [[TMP10]], [[TMP9]]
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> [[TMP7]], i32 2
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> [[TMP7]], i64 2
; CHECK-NEXT: [[OR19]] = or i32 [[OR18]], [[TMP11]]
; CHECK-NEXT: br label %[[COMMON_RET]]
; CHECK: [[BB20]]:
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP7]], i32 3
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP7]], i64 3
; CHECK-NEXT: store volatile i32 [[TMP12]], ptr null, align 4294967296
; CHECK-NEXT: br label %[[COMMON_RET]]
;
@@ -76,8 +76,8 @@ define i32 @test_multi_cond_use(i32 %arg, i32 %arg1, i1 %arg4, i1 %arg5) {
; CHECK-LABEL: define i32 @test_multi_cond_use(
; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]], i1 [[ARG4:%.*]], i1 [[ARG5:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[BB:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[ARG1]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[ARG1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = sdiv <4 x i32> [[TMP2]], splat (i32 64)
; CHECK-NEXT: [[TMP4:%.*]] = shl <4 x i32> [[TMP3]], <i32 0, i32 0, i32 1, i32 0>
@@ -85,13 +85,13 @@ define i32 @test_multi_cond_use(i32 %arg, i32 %arg1, i1 %arg4, i1 %arg5) {
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <4 x i32> [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = icmp ne <4 x i32> [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i1> [[TMP6]], <4 x i1> [[TMP7]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP10]], i32 2
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP10]], i64 2
; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP8]] to i32
-; CHECK-NEXT: [[ICMP7:%.*]] = extractelement <4 x i1> [[TMP10]], i32 3
+; CHECK-NEXT: [[ICMP7:%.*]] = extractelement <4 x i1> [[TMP10]], i64 3
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[ICMP7]], i32 0, i32 2
-; CHECK-NEXT: [[ICMP9:%.*]] = extractelement <4 x i1> [[TMP10]], i32 1
+; CHECK-NEXT: [[ICMP9:%.*]] = extractelement <4 x i1> [[TMP10]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[ICMP9]], i32 0, i32 4
-; CHECK-NEXT: [[ICMP11:%.*]] = extractelement <4 x i1> [[TMP10]], i32 0
+; CHECK-NEXT: [[ICMP11:%.*]] = extractelement <4 x i1> [[TMP10]], i64 0
; CHECK-NEXT: [[TMP13:%.*]] = select i1 [[ICMP11]], i32 0, i32 8
; CHECK-NEXT: [[EXT1:%.*]] = zext i1 [[ICMP11]] to i32
; CHECK-NEXT: br i1 [[ARG4]], label %[[BB13:.*]], label %[[BB16:.*]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/multi_user.ll b/llvm/test/Transforms/SLPVectorizer/X86/multi_user.ll
index c9e821f023266..fb83a4bd66a35 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/multi_user.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/multi_user.ll
@@ -15,7 +15,7 @@ target triple = "x86_64-apple-macosx10.7.0"
define i32 @foo(ptr nocapture %A, i32 %n) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: [[TMP1:%.*]] = mul nsw i32 [[N:%.*]], 5
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[SHUFFLE]], <i32 7, i32 8, i32 9, i32 10>
; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr [[A:%.*]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll b/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
index bac05129dd9ad..7f914fb4497ad 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
@@ -5,11 +5,11 @@ define void @test_add_sdiv(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i32
; CHECK-LABEL: @test_add_sdiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i32 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i64 2
; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[TMP5]], <i32 1, i32 1, i32 42, i32 1>
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> <i32 1146, i32 146, i32 0, i32 0>, [[TMP3]]
; CHECK-NEXT: [[TMP8:%.*]] = sdiv <4 x i32> [[TMP0]], [[TMP6]]
; CHECK-NEXT: [[TMP9:%.*]] = add nsw <4 x i32> [[TMP8]], [[TMP4]]
@@ -52,11 +52,11 @@ define void @test_add_udiv(ptr %arr1, ptr %arr2, i32 %a0, i32 %a1, i32 %a2, i32
; CHECK-LABEL: @test_add_udiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[ARR1:%.*]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i32 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[A2:%.*]], i64 2
; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[TMP5]], <i32 1, i32 1, i32 42, i32 1>
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> <i32 1146, i32 146, i32 0, i32 0>, [[TMP3]]
; CHECK-NEXT: [[TMP8:%.*]] = udiv <4 x i32> [[TMP0]], [[TMP6]]
; CHECK-NEXT: [[TMP9:%.*]] = add nsw <4 x i32> [[TMP8]], [[TMP4]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
index b71dbc49e7478..c87b313072986 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-commutative-op-in-commutative-inst.ll
@@ -8,8 +8,8 @@ define void @test(ptr %quat, float %call13) {
; CHECK-SAME: ptr [[QUAT:%.*]], float [[CALL13:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[CALL121:%.*]] = load volatile float, ptr null, align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[CALL13]], i32 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[CALL121]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[CALL13]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[CALL121]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[TMP1]], <2 x float> zeroinitializer, <2 x float> zeroinitializer)
; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x float> [[TMP2]], <float 0.000000e+00, float -0.000000e+00>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> <i32 1, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
index f1bd3384f0488..466ffd8b2d0ee 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-power-2-num-elems-reused.ll
@@ -5,7 +5,7 @@ define i64 @test() {
; CHECK-LABEL: define i64 @test() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[OR54_I_I_6:%.*]] = or i32 0, 0
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i32> poison, i32 [[OR54_I_I_6]], i32 8
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i32> poison, i32 [[OR54_I_I_6]], i64 8
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[TMP1]], <16 x i32> poison, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 7, i32 7, i32 8>
; CHECK-NEXT: [[TMP3:%.*]] = zext <16 x i32> [[TMP2]] to <16 x i64>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-bswap.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-bswap.ll
index 11ffa3d7ea3f7..6bd2c60f6be51 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-bswap.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-bswap.ll
@@ -4,7 +4,7 @@
define i32 @test(i8 %0) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i8 [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i8> poison, i8 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i8> poison, i8 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <3 x i8> [[TMP2]], <3 x i8> poison, <3 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = and <3 x i8> [[TMP3]], splat (i8 1)
; CHECK-NEXT: [[TMP5:%.*]] = zext <3 x i8> [[TMP4]] to <3 x i32>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
index 9f3a45b7a15b4..a63f3840225e6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-power-of-2-order-detection.ll
@@ -12,17 +12,17 @@ define void @e(ptr %c, i64 %0) {
; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8
; CHECK-NEXT: [[TMP18:%.*]] = load <2 x ptr>, ptr [[ARRAYIDX5]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x ptr> [[TMP18]], <2 x ptr> poison, <2 x i32> <i32 1, i32 0>
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x ptr> poison, ptr [[TMP3]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x ptr> [[TMP5]], <2 x ptr> poison, <2 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <6 x ptr> poison, ptr [[TMP2]], i32 2
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <6 x ptr> [[TMP7]], ptr [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <6 x ptr> poison, ptr [[TMP2]], i64 2
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <6 x ptr> [[TMP9]], ptr [[TMP1]], i64 3
; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <2 x ptr> [[TMP6]], <2 x ptr> poison, <6 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <6 x ptr> [[TMP8]], <6 x ptr> [[TMP21]], <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 6, i32 7>
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <2 x ptr> [[TMP4]], <2 x ptr> poison, <6 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <6 x ptr> [[TMP19]], <6 x ptr> [[TMP20]], <6 x i32> <i32 6, i32 7, i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint <6 x ptr> [[TMP10]] to <6 x i64>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <6 x i64> [[TMP11]], <6 x i64> poison, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3, i32 3, i32 4, i32 4, i32 4, i32 4, i32 5, i32 5, i32 5>
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <32 x i64> poison, i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <32 x i64> poison, i64 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <32 x i64> [[TMP13]], <32 x i64> poison, <32 x i32> zeroinitializer
; CHECK-NEXT: [[TMP15:%.*]] = or <32 x i64> [[TMP14]], [[TMP12]]
; CHECK-NEXT: [[TMP16:%.*]] = icmp ult <32 x i64> [[TMP15]], splat (i64 16)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-reduced-select-of-bits.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-reduced-select-of-bits.ll
index 0d0f7fe1b071d..c32ac9d171e6a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-reduced-select-of-bits.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-reduced-select-of-bits.ll
@@ -6,11 +6,11 @@ define i8 @test(ptr %c, i1 %cmp3, i8 %c.promoted) {
; CHECK-SAME: ptr [[C:%.*]], i1 [[CMP3:%.*]], i8 [[C_PROMOTED:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[C]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i1> poison, i1 [[CMP3]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i1> poison, i1 [[CMP3]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i8> <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128>, <8 x i8> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP0]] to i8
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i8> poison, i8 [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i8> poison, i8 [[TMP4]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x i8> [[TMP5]], <8 x i8> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i8> [[TMP6]], [[TMP3]]
; CHECK-NEXT: [[TMP8:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP7]])
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-before-main.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-before-main.ll
index ab563de8ff800..72b0acce0cb94 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-before-main.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-before-main.ll
@@ -11,7 +11,7 @@ define void @test() {
; CHECK-NEXT: [[ADD3:%.*]] = add i32 0, 1
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ADD3]] to i64
; CHECK-NEXT: [[ADD4:%.*]] = add i32 0, 1
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 poison, i32 1>, i32 [[ADD4]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 poison, i32 1>, i32 [[ADD4]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> <i32 1, i32 0, i32 undef, i32 undef>, <4 x i32> <i32 0, i32 4, i32 5, i32 3>
; CHECK-NEXT: br i1 false, label %[[BB5]], label %[[BB5]]
; CHECK: [[BB5]]:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-instructions-become-schedulable.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-instructions-become-schedulable.ll
index 6bb52e0fc43b3..5c347e3ff6be4 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-instructions-become-schedulable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-instructions-become-schedulable.ll
@@ -10,7 +10,7 @@ define void @test() {
; CHECK-NEXT: br label %[[BB3:.*]]
; CHECK: [[BB1]]:
; CHECK-NEXT: [[TMP0:%.*]] = zext i1 false to i64
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> <i64 0, i64 0, i64 poison, i64 0>, i64 [[TMP0]], i32 2
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> <i64 0, i64 0, i64 poison, i64 0>, i64 [[TMP0]], i64 2
; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i64> zeroinitializer, [[TMP1]]
; CHECK-NEXT: br i1 false, label %[[BB3]], label %[[BB2:.*]]
; CHECK: [[BB3]]:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll
index 9aa0b13096299..44958729d1542 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-parent-multi-copyables.ll
@@ -6,13 +6,13 @@ define void @test() {
; CHECK-NEXT: [[BB:.*]]:
; CHECK-NEXT: br i1 false, label %[[BB1:.*]], label %[[BB6:.*]]
; CHECK: [[BB1]]:
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> poison, i32 0, i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> poison, i32 0, i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP9]], <4 x i32> <i32 0, i32 -1, i32 undef, i32 undef>, <4 x i32> <i32 0, i32 4, i32 5, i32 poison>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
; CHECK-NEXT: br label %[[BB6]]
; CHECK: [[BB6]]:
-; CHECK-NEXT: [[TMP0:%.*]] = phi <4 x i32> [ <i32 0, i32 0, i32 poison, i32 0>, %[[BB]] ], [ [[TMP4]], %[[BB1]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = phi <4 x i32> [ <i32 0, i32 0, i32 poison, i32 0>, %[[BB]] ], [ [[TMP4]], %[[BB1]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP5]], i64 3
; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 0
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-split-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-split-node.ll
index 98ea4db6f6492..a76d05878c110 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-split-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-split-node.ll
@@ -7,14 +7,14 @@ define i64 @test(i256 %0, { i32, i1 } %1) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP1]], 0
; CHECK-NEXT: [[TMP3:%.*]] = trunc i256 [[TMP0]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[TMP3]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i1 } [[TMP1]], 0
; CHECK-NEXT: [[TMP8:%.*]] = extractvalue { i32, i1 } [[TMP1]], 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[TMP8]], i32 1
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP7]], i32 2
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[TMP8]], i64 1
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP7]], i64 2
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x i32> [[TMP11]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 1>
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <4 x i32> [[TMP12]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-user-different-bb.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-user-different-bb.ll
index 9d6e4596d0113..6c4a988c220e7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-user-different-bb.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-user-different-bb.ll
@@ -13,8 +13,8 @@ define i1 @test() {
; CHECK-NEXT: [[MUL1920:%.*]] = mul i32 poison, 0
; CHECK-NEXT: [[REM1878:%.*]] = urem i32 [[MUL1877]], 0
; CHECK-NEXT: [[REM1921:%.*]] = urem i32 [[MUL1920]], 0
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[REM1921]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[REM1878]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[REM1921]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> [[TMP0]], i32 [[REM1878]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> <i32 poison, i32 poison, i32 0, i32 0>, <4 x i32> [[TMP2]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> poison, [[TMP3]]
@@ -22,7 +22,7 @@ define i1 @test() {
; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> zeroinitializer, <4 x i32> [[TMP5]], <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = urem <4 x i32> [[TMP6]], splat (i32 46337)
; CHECK-NEXT: [[TMP8:%.*]] = icmp ult <4 x i32> [[TMP7]], zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP8]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP8]], i64 0
; CHECK-NEXT: ret i1 [[TMP9]]
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-extern-use.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-extern-use.ll
index d2ea15a374211..5a3012bc5e394 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-extern-use.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-extern-use.ll
@@ -8,7 +8,7 @@ define void @test(i32 %arg) {
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[ARG]]
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, i32 [[SUB]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, i32 [[SUB]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i32> zeroinitializer, [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> zeroinitializer, [[TMP2]]
; CHECK-NEXT: br i1 false, label %[[BB8:.*]], label %[[BB4:.*]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll
index 6e656ba942a6b..d6d8c18b5697f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll
@@ -10,7 +10,7 @@ define void @foo() {
; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP1]], <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP6]] = or <2 x i32> [[TMP5]], zeroinitializer
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP6]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP6]], i64 0
; CHECK-NEXT: [[CALL:%.*]] = call i64 null(i32 [[TMP7]])
; CHECK-NEXT: br label [[BB4]]
; CHECK: bb4:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-vectorizable-inst-operand.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-vectorizable-inst-operand.ll
index 4e489a2ac87db..262ab83f2698d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/non-vectorizable-inst-operand.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/non-vectorizable-inst-operand.ll
@@ -16,9 +16,9 @@ define void @test_two_calls_with_vectorizable_operands(ptr %p, ptr %out0, ptr %o
; CHECK-SAME: ptr [[P:%.*]], ptr [[OUT0:%.*]], ptr [[OUT1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[P]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP1]], <double 2.000000e+00, double 3.000000e+00>
-; CHECK-NEXT: [[M0:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
+; CHECK-NEXT: [[M0:%.*]] = extractelement <2 x double> [[TMP2]], i64 0
; CHECK-NEXT: [[R0:%.*]] = call double @user_func(double [[M0]])
-; CHECK-NEXT: [[M1:%.*]] = extractelement <2 x double> [[TMP2]], i32 1
+; CHECK-NEXT: [[M1:%.*]] = extractelement <2 x double> [[TMP2]], i64 1
; CHECK-NEXT: [[R1:%.*]] = call double @user_func(double [[M1]])
; CHECK-NEXT: store double [[R0]], ptr [[OUT0]], align 8
; CHECK-NEXT: store double [[R1]], ptr [[OUT1]], align 8
@@ -45,11 +45,11 @@ define void @test_two_calls_paired_operands(ptr %p, ptr %q, ptr %out0, ptr %out1
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP1]], <double 2.000000e+00, double 3.000000e+00>
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[Q]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP3]], <double 4.000000e+00, double 5.000000e+00>
-; CHECK-NEXT: [[M0:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
-; CHECK-NEXT: [[N0:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
+; CHECK-NEXT: [[M0:%.*]] = extractelement <2 x double> [[TMP2]], i64 0
+; CHECK-NEXT: [[N0:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
; CHECK-NEXT: [[R0:%.*]] = call double @another_user_func(double [[M0]], double [[N0]])
-; CHECK-NEXT: [[M1:%.*]] = extractelement <2 x double> [[TMP2]], i32 1
-; CHECK-NEXT: [[N1:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
+; CHECK-NEXT: [[M1:%.*]] = extractelement <2 x double> [[TMP2]], i64 1
+; CHECK-NEXT: [[N1:%.*]] = extractelement <2 x double> [[TMP4]], i64 1
; CHECK-NEXT: [[R1:%.*]] = call double @another_user_func(double [[M1]], double [[N1]])
; CHECK-NEXT: store double [[R0]], ptr [[OUT0]], align 8
; CHECK-NEXT: store double [[R1]], ptr [[OUT1]], align 8
@@ -150,13 +150,13 @@ define void @test_atomicrmw_value_chain(ptr %p1, ptr %p2, ptr %p3, ptr %p4, ptr
; CHECK-SAME: ptr [[P1:%.*]], ptr [[P2:%.*]], ptr [[P3:%.*]], ptr [[P4:%.*]], ptr [[SRC:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[SRC]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], splat (i32 7)
-; CHECK-NEXT: [[V0:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
+; CHECK-NEXT: [[V0:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0
; CHECK-NEXT: [[OLD0:%.*]] = atomicrmw add ptr [[P1]], i32 [[V0]] seq_cst, align 4
-; CHECK-NEXT: [[V1:%.*]] = extractelement <4 x i32> [[TMP2]], i32 1
+; CHECK-NEXT: [[V1:%.*]] = extractelement <4 x i32> [[TMP2]], i64 1
; CHECK-NEXT: [[OLD1:%.*]] = atomicrmw add ptr [[P2]], i32 [[V1]] seq_cst, align 4
-; CHECK-NEXT: [[V2:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2
+; CHECK-NEXT: [[V2:%.*]] = extractelement <4 x i32> [[TMP2]], i64 2
; CHECK-NEXT: [[OLD2:%.*]] = atomicrmw add ptr [[P3]], i32 [[V2]] seq_cst, align 4
-; CHECK-NEXT: [[V3:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3
+; CHECK-NEXT: [[V3:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3
; CHECK-NEXT: [[OLD3:%.*]] = atomicrmw add ptr [[P4]], i32 [[V3]] seq_cst, align 4
; CHECK-NEXT: ret void
;
@@ -187,11 +187,11 @@ define void @test_cmpxchg_value_chain(ptr %p1, ptr %p2, ptr %src_a, ptr %src_b)
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP6:%.*]] = mul <4 x i32> [[TMP5]], <i32 11, i32 11, i32 13, i32 13>
-; CHECK-NEXT: [[CMP0:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0
-; CHECK-NEXT: [[NEW0:%.*]] = extractelement <4 x i32> [[TMP6]], i32 2
+; CHECK-NEXT: [[CMP0:%.*]] = extractelement <4 x i32> [[TMP6]], i64 0
+; CHECK-NEXT: [[NEW0:%.*]] = extractelement <4 x i32> [[TMP6]], i64 2
; CHECK-NEXT: [[R0:%.*]] = cmpxchg ptr [[P1]], i32 [[CMP0]], i32 [[NEW0]] seq_cst seq_cst, align 4
-; CHECK-NEXT: [[CMP1:%.*]] = extractelement <4 x i32> [[TMP6]], i32 1
-; CHECK-NEXT: [[NEW1:%.*]] = extractelement <4 x i32> [[TMP6]], i32 3
+; CHECK-NEXT: [[CMP1:%.*]] = extractelement <4 x i32> [[TMP6]], i64 1
+; CHECK-NEXT: [[NEW1:%.*]] = extractelement <4 x i32> [[TMP6]], i64 3
; CHECK-NEXT: [[R1:%.*]] = cmpxchg ptr [[P2]], i32 [[CMP1]], i32 [[NEW1]] seq_cst seq_cst, align 4
; CHECK-NEXT: ret void
;
@@ -237,13 +237,13 @@ define void @test_scattered_stores(ptr %p1, ptr %p2, ptr %p3, ptr %p4, ptr %src)
; CHECK-SAME: ptr [[P1:%.*]], ptr [[P2:%.*]], ptr [[P3:%.*]], ptr [[P4:%.*]], ptr [[SRC:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr [[SRC]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x double> [[TMP1]], <double 2.000000e+00, double 3.000000e+00, double 5.000000e+00, double 7.000000e+00>
-; CHECK-NEXT: [[V0:%.*]] = extractelement <4 x double> [[TMP2]], i32 0
+; CHECK-NEXT: [[V0:%.*]] = extractelement <4 x double> [[TMP2]], i64 0
; CHECK-NEXT: store double [[V0]], ptr [[P1]], align 8
-; CHECK-NEXT: [[V1:%.*]] = extractelement <4 x double> [[TMP2]], i32 1
+; CHECK-NEXT: [[V1:%.*]] = extractelement <4 x double> [[TMP2]], i64 1
; CHECK-NEXT: store double [[V1]], ptr [[P2]], align 8
-; CHECK-NEXT: [[V2:%.*]] = extractelement <4 x double> [[TMP2]], i32 2
+; CHECK-NEXT: [[V2:%.*]] = extractelement <4 x double> [[TMP2]], i64 2
; CHECK-NEXT: store double [[V2]], ptr [[P3]], align 8
-; CHECK-NEXT: [[V3:%.*]] = extractelement <4 x double> [[TMP2]], i32 3
+; CHECK-NEXT: [[V3:%.*]] = extractelement <4 x double> [[TMP2]], i64 3
; CHECK-NEXT: store double [[V3]], ptr [[P4]], align 8
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/odd_store.ll b/llvm/test/Transforms/SLPVectorizer/X86/odd_store.ll
index 8af013b65db1b..c9be115ff7035 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/odd_store.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/odd_store.ll
@@ -20,16 +20,16 @@ define void @foo(ptr noalias nocapture %A, ptr noalias nocapture %B, float %T) {
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[B]], i64 11
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = load <2 x float>, ptr [[TMP7]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x float> poison, float [[T]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x float> poison, float [[T]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <2 x float> [[TMP10]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP16:%.*]] = fmul <2 x float> [[TMP9]], [[TMP11]]
; CHECK-NEXT: [[TMP17:%.*]] = fpext <2 x float> [[TMP16]] to <2 x double>
; CHECK-NEXT: [[TMP14:%.*]] = fadd <2 x double> [[TMP17]], <double 5.000000e+00, double 6.000000e+00>
; CHECK-NEXT: [[TMP15:%.*]] = fptosi <2 x double> [[TMP14]] to <2 x i8>
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i8> [[TMP15]], i32 0
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i8> [[TMP15]], i64 0
; CHECK-NEXT: store i8 [[TMP12]], ptr [[TMP13]], align 1
; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 2
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i8> [[TMP15]], i32 1
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i8> [[TMP15]], i64 1
; CHECK-NEXT: store i8 [[TMP19]], ptr [[TMP20]], align 1
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/opaque-ptr.ll b/llvm/test/Transforms/SLPVectorizer/X86/opaque-ptr.ll
index d7f46f50a3543..4348b411616f0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/opaque-ptr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/opaque-ptr.ll
@@ -8,13 +8,13 @@ define void @test(ptr %r, ptr %p, ptr %q) #0 {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr [[P0]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr [[Q0]], align 2
; CHECK-NEXT: [[TMP3:%.*]] = sub nsw <4 x i64> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i64 0
; CHECK-NEXT: [[G0:%.*]] = getelementptr inbounds i32, ptr [[R:%.*]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i64 1
; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP5]]
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i64 2
; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP6]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i64 3
; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i32, ptr [[R]], i64 [[TMP7]]
; CHECK-NEXT: ret void
;
@@ -52,8 +52,8 @@ define void @test(ptr %r, ptr %p, ptr %q) #0 {
define void @test2(ptr %a, ptr %b) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[A:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[B:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[A:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[B:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, <2 x ptr> [[TMP2]], <2 x i64> <i64 1, i64 3>
; CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint <2 x ptr> [[TMP3]] to <2 x i64>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/operand-reorder-with-copyables.ll b/llvm/test/Transforms/SLPVectorizer/X86/operand-reorder-with-copyables.ll
index 22bca2072636a..bcdd498154ce1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/operand-reorder-with-copyables.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/operand-reorder-with-copyables.ll
@@ -17,17 +17,17 @@ define void @test(ptr %p0, ptr %p1, ptr %dst, i32 %a0, i32 %a1, i32 %a2, i32 %a3
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[P0]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[P1]], align 4
; CHECK-NEXT: [[RES2:%.*]] = udiv i32 [[C2]], [[A2]]
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[RES2]], i32 2
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[RES2]], i64 2
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3]], i64 3
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> [[TMP8]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[Y3]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[Y3]], i64 3
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP13]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP15:%.*]] = sub <4 x i32> [[TMP9]], [[TMP14]]
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP16]], i32 [[A1]], i32 1
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[A3]], i32 3
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP16]], i32 [[A1]], i64 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[A3]], i64 3
; CHECK-NEXT: [[TMP10:%.*]] = add <4 x i32> [[TMP15]], [[TMP12]]
; CHECK-NEXT: store <4 x i32> [[TMP10]], ptr [[DST]], align 4
; CHECK-NEXT: ret void
@@ -87,17 +87,17 @@ define void @test_baseline(ptr %p0, ptr %p1, ptr %dst, i32 %a0, i32 %a1, i32 %a2
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[P0]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[P1]], align 4
; CHECK-NEXT: [[RES2:%.*]] = udiv i32 [[C2]], [[A2]]
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[RES2]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[RES2]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[X3]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[Y3]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[Y3]], i64 3
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP9:%.*]] = sub <4 x i32> [[TMP5]], [[TMP8]]
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[A1]], i32 1
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[A3]], i32 3
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 poison>, i32 [[A0]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[A1]], i64 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[A3]], i64 3
; CHECK-NEXT: [[TMP13:%.*]] = add <4 x i32> [[TMP9]], [[TMP12]]
; CHECK-NEXT: store <4 x i32> [[TMP13]], ptr [[DST]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll b/llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
index de72521345435..93ffc2985dd1f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
@@ -10,16 +10,16 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
define void @shuffle_operands1(ptr noalias %from, ptr noalias %to, double %v1, double %v2) {
; CHECK-LABEL: @shuffle_operands1(
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[V1:%.*]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[V2:%.*]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[V1:%.*]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[V2:%.*]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[TO:%.*]], align 4
; CHECK-NEXT: ret void
;
; SSE2-LABEL: @shuffle_operands1(
; SSE2-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
-; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[V1:%.*]], i32 0
-; SSE2-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[V2:%.*]], i32 1
+; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[V1:%.*]], i64 0
+; SSE2-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[V2:%.*]], i64 1
; SSE2-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]]
; SSE2-NEXT: store <2 x double> [[TMP4]], ptr [[TO:%.*]], align 4
; SSE2-NEXT: ret void
@@ -43,7 +43,7 @@ define void @vecload_vs_broadcast(ptr noalias %from, ptr noalias %to, double %v1
; CHECK-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> <i32 poison, i32 0>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP0]], [[TMP2]]
; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[TO:%.*]], align 4
; CHECK-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -57,7 +57,7 @@ define void @vecload_vs_broadcast(ptr noalias %from, ptr noalias %to, double %v1
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
; SSE2-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> <i32 poison, i32 0>
-; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i32 0
+; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 0
; SSE2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP0]], [[TMP2]]
; SSE2-NEXT: store <2 x double> [[TMP3]], ptr [[TO:%.*]], align 4
; SSE2-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -91,7 +91,7 @@ define void @vecload_vs_broadcast2(ptr noalias %from, ptr noalias %to, double %v
; CHECK-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> <i32 poison, i32 0>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[TMP0]]
; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[TO:%.*]], align 4
; CHECK-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -105,7 +105,7 @@ define void @vecload_vs_broadcast2(ptr noalias %from, ptr noalias %to, double %v
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
; SSE2-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> <i32 poison, i32 0>
-; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i32 0
+; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 0
; SSE2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[TMP0]]
; SSE2-NEXT: store <2 x double> [[TMP3]], ptr [[TO:%.*]], align 4
; SSE2-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -139,7 +139,7 @@ define void @vecload_vs_broadcast3(ptr noalias %from, ptr noalias %to, double %v
; CHECK-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> <i32 poison, i32 0>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[TMP0]]
; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[TO:%.*]], align 4
; CHECK-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -153,7 +153,7 @@ define void @vecload_vs_broadcast3(ptr noalias %from, ptr noalias %to, double %v
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
; SSE2-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> <i32 poison, i32 0>
-; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i32 0
+; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[P]], i64 0
; SSE2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[TMP0]]
; SSE2-NEXT: store <2 x double> [[TMP3]], ptr [[TO:%.*]], align 4
; SSE2-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -188,9 +188,9 @@ define void @shuffle_nodes_match1(ptr noalias %from, ptr noalias %to, double %v1
; CHECK-NEXT: [[FROM_1:%.*]] = getelementptr double, ptr [[FROM:%.*]], i64 1
; CHECK-NEXT: [[V0_1:%.*]] = load double, ptr [[FROM]], align 4
; CHECK-NEXT: [[V0_2:%.*]] = load double, ptr [[FROM_1]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[V0_2]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[P]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[V0_1]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[V0_2]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[P]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[V0_1]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[TO:%.*]], align 4
@@ -205,7 +205,7 @@ define void @shuffle_nodes_match1(ptr noalias %from, ptr noalias %to, double %v1
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
; SSE2-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
-; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP0]], double [[P]], i32 1
+; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP0]], double [[P]], i64 1
; SSE2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[TMP1]]
; SSE2-NEXT: store <2 x double> [[TMP3]], ptr [[TO:%.*]], align 4
; SSE2-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -239,7 +239,7 @@ define void @vecload_vs_broadcast4(ptr noalias %from, ptr noalias %to, double %v
; CHECK-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP0]], double [[P]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP0]], double [[P]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[TMP1]]
; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[TO:%.*]], align 4
; CHECK-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -253,7 +253,7 @@ define void @vecload_vs_broadcast4(ptr noalias %from, ptr noalias %to, double %v
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
; SSE2-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
-; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP0]], double [[P]], i32 1
+; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP0]], double [[P]], i64 1
; SSE2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], [[TMP1]]
; SSE2-NEXT: store <2 x double> [[TMP3]], ptr [[TO:%.*]], align 4
; SSE2-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -289,10 +289,10 @@ define void @shuffle_nodes_match2(ptr noalias %from, ptr noalias %to, double %v1
; CHECK-NEXT: [[FROM_1:%.*]] = getelementptr double, ptr [[FROM:%.*]], i64 1
; CHECK-NEXT: [[V0_1:%.*]] = load double, ptr [[FROM]], align 4
; CHECK-NEXT: [[V0_2:%.*]] = load double, ptr [[FROM_1]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[V0_1]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[V0_1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[V0_2]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[P]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[V0_2]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[P]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <2 x double> [[TMP4]], ptr [[TO:%.*]], align 4
; CHECK-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -306,7 +306,7 @@ define void @shuffle_nodes_match2(ptr noalias %from, ptr noalias %to, double %v1
; SSE2-NEXT: [[P:%.*]] = phi double [ 1.000000e+00, [[LP]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; SSE2-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[FROM:%.*]], align 4
; SSE2-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
-; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP0]], double [[P]], i32 1
+; SSE2-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP0]], double [[P]], i64 1
; SSE2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]]
; SSE2-NEXT: store <2 x double> [[TMP3]], ptr [[TO:%.*]], align 4
; SSE2-NEXT: br i1 [[C:%.*]], label [[LP]], label [[EXT:%.*]]
@@ -355,7 +355,7 @@ define void @good_load_order() {
; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX31]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x float> [[TMP8]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 1, i32 2>
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x float> [[TMP9]], <4 x float> [[TMP12]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP11:%.*]] = fmul <4 x float> [[TMP8]], [[TMP10]]
; CHECK-NEXT: store <4 x float> [[TMP11]], ptr [[ARRAYIDX5]], align 4
@@ -387,7 +387,7 @@ define void @good_load_order() {
; SSE2-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX31]], align 4
; SSE2-NEXT: [[TMP8:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 4
; SSE2-NEXT: [[TMP9:%.*]] = shufflevector <4 x float> [[TMP8]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 1, i32 2>
-; SSE2-NEXT: [[TMP12:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; SSE2-NEXT: [[TMP12:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i64 0
; SSE2-NEXT: [[TMP10:%.*]] = shufflevector <4 x float> [[TMP9]], <4 x float> [[TMP12]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>
; SSE2-NEXT: [[TMP11:%.*]] = fmul <4 x float> [[TMP8]], [[TMP10]]
; SSE2-NEXT: store <4 x float> [[TMP11]], ptr [[ARRAYIDX5]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/ordered-reduction-root-deleted.ll b/llvm/test/Transforms/SLPVectorizer/X86/ordered-reduction-root-deleted.ll
index 0b618f1d41d5c..2234a2e608c14 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/ordered-reduction-root-deleted.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/ordered-reduction-root-deleted.ll
@@ -14,11 +14,11 @@ define void @test(ptr %arg3, double %load.2.i, double %load.i, double %fadd10.i.
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[GETELEMENTPTR_7_I:%.*]] = getelementptr i8, ptr [[ARG3]], i64 56
; CHECK-NEXT: [[LOAD_7_I:%.*]] = load double, ptr [[GETELEMENTPTR_7_I]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[LOAD_4_I]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[LOAD_7_I]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[LOAD_I]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[LOAD_2_I]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x double> [[TMP6]], double [[FADD10_I_I]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[LOAD_4_I]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[LOAD_7_I]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[LOAD_I]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[LOAD_2_I]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x double> [[TMP6]], double [[FADD10_I_I]], i64 1
; CHECK-NEXT: br label %[[BB7:.*]]
; CHECK: [[BB7]]:
; CHECK-NEXT: [[TMP8:%.*]] = phi <2 x double> [ [[TMP4]], %[[BB]] ], [ [[TMP17:%.*]], %[[BB7]] ]
@@ -30,7 +30,7 @@ define void @test(ptr %arg3, double %load.2.i, double %load.i, double %fadd10.i.
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <4 x double> [[TMP13]], <4 x double> poison, <4 x i32> <i32 3, i32 0, i32 2, i32 1>
; CHECK-NEXT: [[TMP14:%.*]] = call double @llvm.vector.reduce.fadd.v4f64(double -0.000000e+00, <4 x double> [[TMP18]])
; CHECK-NEXT: [[TMP15]] = fadd <2 x double> [[TMP7]], <double 0.000000e+00, double -0.000000e+00>
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <2 x double> [[TMP5]], double [[TMP14]], i32 1
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <2 x double> [[TMP5]], double [[TMP14]], i64 1
; CHECK-NEXT: [[TMP17]] = fadd <2 x double> [[TMP16]], zeroinitializer
; CHECK-NEXT: br label %[[BB7]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/ordered-reductions.ll b/llvm/test/Transforms/SLPVectorizer/X86/ordered-reductions.ll
index 19c704a570f66..ac9a8e63f3e16 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/ordered-reductions.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/ordered-reductions.ll
@@ -7,7 +7,7 @@ define float @test1(<2 x float> %retval.i69.sroa.0.0.copyload.i.i) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <2 x float> [[RETVAL_I69_SROA_0_0_COPYLOAD_I_I]], <2 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[TMP0]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float [[TMP2]], <4 x float> [[TMP1]])
; CHECK-NEXT: ret float [[TMP3]]
;
@@ -35,7 +35,7 @@ define float @test2(<2 x float> %retval.i69.sroa.0.0.copyload.i.i) {
; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[TMP0]], <float -0.000000e+00, float 0.000000e+00, float 0.000000e+00, float -0.000000e+00>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> <float 0.000000e+00, float poison, float poison, float 0.000000e+00>, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
; CHECK-NEXT: [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i64 0
; CHECK-NEXT: [[OP_RDX:%.*]] = fadd float 1.000000e+00, [[TMP4]]
; CHECK-NEXT: [[TMP5:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float [[OP_RDX]], <4 x float> [[TMP3]])
; CHECK-NEXT: ret float [[TMP5]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/ordering-bug.ll b/llvm/test/Transforms/SLPVectorizer/X86/ordering-bug.ll
index e1c794a6fd279..3b5937de8b271 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/ordering-bug.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/ordering-bug.ll
@@ -16,19 +16,19 @@ define void @f(i1 %x) #0 {
; CHECK: while.body.lr.ph:
; CHECK-NEXT: [[ICMP_A1:%.*]] = icmp eq i64 [[A1]], 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @b, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i1> poison, i1 [[ICMP_A1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i1> poison, i1 [[ICMP_A1]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i1> [[TMP2]], <2 x i1> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = select <2 x i1> [[TMP3]], <2 x i64> [[TMP1]], <2 x i64> [[TMP0]]
; CHECK-NEXT: br label [[WHILE_END]]
; CHECK: while.end:
; CHECK-NEXT: [[TMP5:%.*]] = phi <2 x i64> [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP4]], [[WHILE_BODY_LR_PH]] ]
; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i64>, ptr @c, align 8
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP5]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i64> [[TMP5]], i64 0
; CHECK-NEXT: [[ICMP_D0:%.*]] = icmp eq i64 [[TMP7]], 0
; CHECK-NEXT: br i1 [[ICMP_D0]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then:
; CHECK-NEXT: [[AND0_TMP:%.*]] = and i64 [[TMP7]], 8
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> poison, i64 [[AND0_TMP]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> poison, i64 [[AND0_TMP]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i64> [[TMP8]], <2 x i64> [[TMP5]], <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP10:%.*]] = and <2 x i64> [[TMP9]], [[TMP6]]
; CHECK-NEXT: store <2 x i64> [[TMP10]], ptr @a, align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/original-inst-scheduled-after-copyable.ll b/llvm/test/Transforms/SLPVectorizer/X86/original-inst-scheduled-after-copyable.ll
index b05e41461a75b..befeafd486fb5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/original-inst-scheduled-after-copyable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/original-inst-scheduled-after-copyable.ll
@@ -13,12 +13,12 @@ define void @test(ptr %0, i32 %1, i32 %2) {
; CHECK-NEXT: [[TMP18:%.*]] = zext i32 [[ADD_NARROWED_I_I]] to i64
; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[TMP18]], -1
; CHECK-NEXT: [[TMP17:%.*]] = load <2 x i32>, ptr [[TMP5]], align 8
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <2 x i32> <i32 1, i32 poison>, i32 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP32:%.*]] = insertelement <2 x i32> <i32 1, i32 poison>, i32 [[TMP1]], i64 1
; CHECK-NEXT: [[TMP33:%.*]] = and <2 x i32> [[TMP17]], [[TMP32]]
; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr null)
; CHECK-NEXT: [[TMP23:%.*]] = zext <2 x i32> [[TMP33]] to <2 x i64>
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <2 x i32> [[TMP33]], <2 x i32> poison, <2 x i32> <i32 poison, i32 0>
-; CHECK-NEXT: [[TMP34:%.*]] = insertelement <2 x i32> [[TMP20]], i32 [[TMP10]], i32 0
+; CHECK-NEXT: [[TMP34:%.*]] = insertelement <2 x i32> [[TMP20]], i32 [[TMP10]], i64 0
; CHECK-NEXT: [[TMP22:%.*]] = zext <2 x i32> [[TMP34]] to <2 x i64>
; CHECK-NEXT: [[TMP35:%.*]] = shl <2 x i64> [[TMP23]], splat (i64 1)
; CHECK-NEXT: [[TMP25:%.*]] = or <2 x i64> [[TMP35]], [[TMP22]]
@@ -29,10 +29,10 @@ define void @test(ptr %0, i32 %1, i32 %2) {
; CHECK-NEXT: [[TMP30:%.*]] = and <2 x i32> [[TMP29]], [[TMP26]]
; CHECK-NEXT: [[TMP31:%.*]] = or <2 x i32> [[TMP30]], [[TMP27]]
; CHECK-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP19]] to i32
-; CHECK-NEXT: [[TMP37:%.*]] = insertelement <2 x i32> poison, i32 [[TMP36]], i32 0
+; CHECK-NEXT: [[TMP37:%.*]] = insertelement <2 x i32> poison, i32 [[TMP36]], i64 0
; CHECK-NEXT: [[TMP38:%.*]] = shufflevector <2 x i32> [[TMP37]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP39:%.*]] = and <2 x i32> [[TMP38]], splat (i32 -2)
-; CHECK-NEXT: [[TMP28:%.*]] = insertelement <2 x i32> <i32 poison, i32 -2>, i32 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <2 x i32> <i32 poison, i32 -2>, i32 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP40:%.*]] = or <2 x i32> [[TMP28]], [[TMP39]]
; CHECK-NEXT: [[TMP41:%.*]] = xor <2 x i32> [[TMP28]], [[TMP39]]
; CHECK-NEXT: [[TMP42:%.*]] = shufflevector <2 x i32> [[TMP40]], <2 x i32> [[TMP41]], <2 x i32> <i32 0, i32 3>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/parent-node-schedulable-with-multi-copyables.ll b/llvm/test/Transforms/SLPVectorizer/X86/parent-node-schedulable-with-multi-copyables.ll
index 05611ba0151e6..a4c46c5176c15 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/parent-node-schedulable-with-multi-copyables.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/parent-node-schedulable-with-multi-copyables.ll
@@ -5,9 +5,9 @@ define i64 @test(ptr %arg1, i64 %alloca.promoted344, i8 %load.311.i, i1 %load1.i
; CHECK-LABEL: define i64 @test(
; CHECK-SAME: ptr [[ARG1:%.*]], i64 [[ALLOCA_PROMOTED344:%.*]], i8 [[LOAD_311_I:%.*]], i1 [[LOAD1_I:%.*]]) {
; CHECK-NEXT: [[BB:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> <i8 0, i8 0, i8 0, i8 poison>, i8 [[LOAD_311_I]], i32 3
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> <i8 poison, i8 poison, i8 0, i8 0>, i8 [[LOAD_311_I]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[ALLOCA_PROMOTED344]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> <i8 0, i8 0, i8 0, i8 poison>, i8 [[LOAD_311_I]], i64 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> <i8 poison, i8 poison, i8 0, i8 0>, i8 [[LOAD_311_I]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[ALLOCA_PROMOTED344]], i64 0
; CHECK-NEXT: br label %[[BB2:.*]]
; CHECK: [[BB2]]:
; CHECK-NEXT: [[TMP3:%.*]] = phi <2 x i64> [ zeroinitializer, %[[BB]] ], [ [[TMP28:%.*]], %[[BB12_8_I:.*]] ]
@@ -20,7 +20,7 @@ define i64 @test(ptr %arg1, i64 %alloca.promoted344, i8 %load.311.i, i1 %load1.i
; CHECK-NEXT: [[LOAD4_I_I_PEEL:%.*]] = load i64, ptr [[ARG1]], align 8
; CHECK-NEXT: [[SHL_I_I_PEEL:%.*]] = shl i64 [[LOAD4_I_I_PEEL]], 1
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> poison, <2 x i32> <i32 poison, i32 0>
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i64> [[TMP6]], i64 [[SHL_I_I_PEEL]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i64> [[TMP6]], i64 [[SHL_I_I_PEEL]], i64 0
; CHECK-NEXT: [[TMP22:%.*]] = or <2 x i64> [[TMP5]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = xor <2 x i64> [[TMP5]], [[TMP7]]
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP22]], <2 x i64> [[TMP9]], <2 x i32> <i32 0, i32 3>
@@ -29,7 +29,7 @@ define i64 @test(ptr %arg1, i64 %alloca.promoted344, i8 %load.311.i, i1 %load1.i
; CHECK-NEXT: [[TMP11:%.*]] = phi <2 x i64> [ [[TMP10]], %[[BB3_I_I_PEEL]] ], [ zeroinitializer, %[[BB4_LR_PH_I]] ]
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x i64> [[TMP11]], <2 x i64> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 0>
; CHECK-NEXT: [[TMP13:%.*]] = trunc <4 x i64> [[TMP12]] to <4 x i8>
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i64> [[TMP12]], i32 1
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i64> [[TMP12]], i64 1
; CHECK-NEXT: br label %[[SPAM_EXIT]]
; CHECK: [[SPAM_EXIT]]:
; CHECK-NEXT: [[GETELEMENTPTR_I_I_PROMOTED346:%.*]] = phi i64 [ [[TMP14]], %[[EGGS_EXIT_I_PEEL]] ], [ 0, %[[BB2]] ]
@@ -38,43 +38,43 @@ define i64 @test(ptr %arg1, i64 %alloca.promoted344, i8 %load.311.i, i1 %load1.i
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <4 x i8> [[TMP15]], <4 x i8> poison, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
; CHECK-NEXT: br i1 [[LOAD1_I]], label %[[BB12_8_I]], label %[[BB12_1_THREAD_I:.*]]
; CHECK: [[BB12_1_THREAD_I]]:
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <8 x i8> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <8 x i8> [[TMP4]], i64 0
; CHECK-NEXT: [[ICMP5_3_I:%.*]] = icmp eq i8 [[TMP17]], 0
; CHECK-NEXT: br i1 [[ICMP5_3_I]], label %[[BB12_3_I:.*]], label %[[BB8_3_I:.*]]
; CHECK: [[BB8_3_I]]:
; CHECK-NEXT: br label %[[BB12_3_I]]
; CHECK: [[BB12_3_I]]:
-; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i8> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i8> [[TMP4]], i64 1
; CHECK-NEXT: [[ICMP5_7_I:%.*]] = icmp eq i8 [[TMP20]], 0
; CHECK-NEXT: br i1 [[ICMP5_7_I]], label %[[BB12_4_I:.*]], label %[[BB8_4_I:.*]]
; CHECK: [[BB8_4_I]]:
; CHECK-NEXT: br label %[[BB12_4_I]]
; CHECK: [[BB12_4_I]]:
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i8> [[TMP4]], i32 2
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i8> [[TMP4]], i64 2
; CHECK-NEXT: [[ICMP5_5_I:%.*]] = icmp eq i8 [[TMP19]], 0
; CHECK-NEXT: br i1 [[ICMP5_5_I]], label %[[BB12_5_I:.*]], label %[[BB8_5_I:.*]]
; CHECK: [[BB8_5_I]]:
; CHECK-NEXT: br label %[[BB12_5_I]]
; CHECK: [[BB12_5_I]]:
-; CHECK-NEXT: [[TMP21:%.*]] = extractelement <8 x i8> [[TMP4]], i32 3
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <8 x i8> [[TMP4]], i64 3
; CHECK-NEXT: [[ICMP5_8_I:%.*]] = icmp eq i8 [[TMP21]], 0
; CHECK-NEXT: br i1 [[ICMP5_8_I]], label %[[BB12_7_I:.*]], label %[[BB8_7_I:.*]]
; CHECK: [[BB8_7_I]]:
; CHECK-NEXT: br label %[[BB12_7_I]]
; CHECK: [[BB12_7_I]]:
-; CHECK-NEXT: [[TMP30:%.*]] = extractelement <8 x i8> [[TMP4]], i32 4
+; CHECK-NEXT: [[TMP30:%.*]] = extractelement <8 x i8> [[TMP4]], i64 4
; CHECK-NEXT: [[ICMP5_8_I1:%.*]] = icmp eq i8 [[TMP30]], 0
; CHECK-NEXT: br i1 [[ICMP5_8_I1]], label %[[BB12_8_I]], label %[[BB8_8_I:.*]]
; CHECK: [[BB8_8_I]]:
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[LOAD_8_I]], i32 1
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i8> poison, i8 [[LOAD_8_I]], i32 0
+; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[LOAD_8_I]], i64 1
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i8> poison, i8 [[LOAD_8_I]], i64 0
; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <8 x i8> [[TMP4]], <8 x i8> poison, <4 x i32> <i32 poison, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <4 x i8> [[TMP23]], <4 x i8> [[TMP24]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
; CHECK-NEXT: br label %[[BB12_8_I]]
; CHECK: [[BB12_8_I]]:
; CHECK-NEXT: [[TMP26:%.*]] = phi <4 x i8> [ [[TMP0]], %[[BB12_7_I]] ], [ [[TMP31]], %[[BB8_8_I]] ], [ [[TMP15]], %[[SPAM_EXIT]] ]
; CHECK-NEXT: [[TMP27:%.*]] = phi <4 x i8> [ zeroinitializer, %[[BB12_7_I]] ], [ [[TMP25]], %[[BB8_8_I]] ], [ [[TMP16]], %[[SPAM_EXIT]] ]
-; CHECK-NEXT: [[TMP28]] = insertelement <2 x i64> [[TMP2]], i64 [[GETELEMENTPTR_I_I_PROMOTED346]], i32 1
+; CHECK-NEXT: [[TMP28]] = insertelement <2 x i64> [[TMP2]], i64 [[GETELEMENTPTR_I_I_PROMOTED346]], i64 1
; CHECK-NEXT: [[TMP29]] = shufflevector <4 x i8> [[TMP26]], <4 x i8> [[TMP27]], <8 x i32> <i32 2, i32 7, i32 5, i32 0, i32 1, i32 3, i32 4, i32 6>
; CHECK-NEXT: br label %[[BB2]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/parent-node-split-non-schedulable.ll b/llvm/test/Transforms/SLPVectorizer/X86/parent-node-split-non-schedulable.ll
index bb912bc7c9713..fcd009961a754 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/parent-node-split-non-schedulable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/parent-node-split-non-schedulable.ll
@@ -5,16 +5,16 @@ define i32 @main(ptr %c, i32 %0, i1 %tobool4.not, i16 %1) {
; CHECK-LABEL: define i32 @main(
; CHECK-SAME: ptr [[C:%.*]], i32 [[TMP0:%.*]], i1 [[TOBOOL4_NOT:%.*]], i16 [[TMP1:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 1, i32 0>, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 1, i32 0>, i32 [[TMP0]], i64 0
; CHECK-NEXT: br label %[[IF_END:.*]]
; CHECK: [[IF_END]]:
; CHECK-NEXT: [[B_0_PH:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[TMP32:%.*]], %[[WHILE_COND_PREHEADER:.*]] ]
; CHECK-NEXT: [[TMP3:%.*]] = phi <2 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP33:%.*]], %[[WHILE_COND_PREHEADER]] ]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[B_0_PH]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[B_0_PH]], i64 1
; CHECK-NEXT: br i1 [[TOBOOL4_NOT]], label %[[R:.*]], label %[[IF_END9:.*]]
; CHECK: [[IF_END9]]:
; CHECK-NEXT: [[CONV11:%.*]] = sext i16 [[TMP1]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 1>, i32 [[CONV11]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 1>, i32 [[CONV11]], i64 1
; CHECK-NEXT: br label %[[R]]
; CHECK: [[R]]:
; CHECK-NEXT: [[TMP6:%.*]] = phi <4 x i32> [ [[TMP5]], %[[IF_END9]] ], [ [[TMP4]], %[[IF_END]] ]
@@ -24,40 +24,40 @@ define i32 @main(ptr %c, i32 %0, i1 %tobool4.not, i16 %1) {
; CHECK-NEXT: br label %[[IF_END14]]
; CHECK: [[IF_END14]]:
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[C]], align 4
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i32> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i32> [[TMP3]], i64 1
; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP8]], 1
; CHECK-NEXT: [[AND25:%.*]] = and i32 [[TMP0]], 1
; CHECK-NEXT: [[NOT:%.*]] = xor i32 [[AND]], 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i32> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i32> [[TMP3]], i64 0
; CHECK-NEXT: [[AND17:%.*]] = and i32 [[TMP9]], 1
; CHECK-NEXT: [[DIV20:%.*]] = sdiv i32 [[AND17]], [[TMP0]]
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[AND17]], i32 1
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP10]], i32 2
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[AND25]], i32 3
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> <i32 0, i32 1, i32 poison, i32 1>, i32 [[DIV20]], i32 2
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[AND17]], i64 1
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP10]], i64 2
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[AND25]], i64 3
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> <i32 0, i32 1, i32 poison, i32 1>, i32 [[DIV20]], i64 2
; CHECK-NEXT: [[TMP16:%.*]] = xor <4 x i32> [[TMP14]], [[TMP15]]
; CHECK-NEXT: [[TMP22:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <4 x i32> [[TMP16]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <8 x i32> [[TMP22]], <8 x i32> [[TMP23]], <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 9, i32 10, i32 11, i32 poison>
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <8 x i32> [[TMP17]], i32 [[NOT]], i32 7
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <8 x i32> <i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison>, i32 [[B_0_PH]], i32 0
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <8 x i32> [[TMP19]], i32 [[TMP0]], i32 7
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <8 x i32> [[TMP17]], i32 [[NOT]], i64 7
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <8 x i32> <i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison>, i32 [[B_0_PH]], i64 0
+; CHECK-NEXT: [[TMP20:%.*]] = insertelement <8 x i32> [[TMP19]], i32 [[TMP0]], i64 7
; CHECK-NEXT: br label %[[AH:.*]]
; CHECK: [[AH]]:
; CHECK-NEXT: [[TMP21:%.*]] = phi <8 x i32> [ [[TMP20]], %[[AH]] ], [ [[TMP18]], %[[IF_END14]] ]
-; CHECK-NEXT: [[TMP25:%.*]] = extractelement <8 x i32> [[TMP21]], i32 5
-; CHECK-NEXT: [[TMP26:%.*]] = extractelement <8 x i32> [[TMP21]], i32 7
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <8 x i32> [[TMP21]], i64 5
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <8 x i32> [[TMP21]], i64 7
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP25]], [[TMP26]]
-; CHECK-NEXT: [[TMP28:%.*]] = extractelement <8 x i32> [[TMP21]], i32 4
+; CHECK-NEXT: [[TMP28:%.*]] = extractelement <8 x i32> [[TMP21]], i64 4
; CHECK-NEXT: [[TMP29:%.*]] = or i32 [[ADD]], [[TMP28]]
-; CHECK-NEXT: [[TMP30:%.*]] = extractelement <8 x i32> [[TMP21]], i32 6
+; CHECK-NEXT: [[TMP30:%.*]] = extractelement <8 x i32> [[TMP21]], i64 6
; CHECK-NEXT: [[OR27:%.*]] = or i32 [[TMP29]], [[TMP30]]
; CHECK-NEXT: store i32 [[OR27]], ptr [[C]], align 4
; CHECK-NEXT: br i1 [[TOBOOL4_NOT]], label %[[WHILE_COND_PREHEADER]], label %[[AH]]
; CHECK: [[WHILE_COND_PREHEADER]]:
-; CHECK-NEXT: [[TMP31:%.*]] = extractelement <8 x i32> [[TMP21]], i32 1
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <8 x i32> [[TMP21]], i64 1
; CHECK-NEXT: [[CALL69:%.*]] = tail call i32 @s(i32 [[TMP31]])
-; CHECK-NEXT: [[TMP32]] = extractelement <8 x i32> [[TMP21]], i32 0
+; CHECK-NEXT: [[TMP32]] = extractelement <8 x i32> [[TMP21]], i64 0
; CHECK-NEXT: [[TMP33]] = shufflevector <8 x i32> [[TMP21]], <8 x i32> poison, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: br label %[[IF_END]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/parent-phi-node-reordered.ll b/llvm/test/Transforms/SLPVectorizer/X86/parent-phi-node-reordered.ll
index d01c35f6bc090..72c66a80ded05 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/parent-phi-node-reordered.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/parent-phi-node-reordered.ll
@@ -5,8 +5,8 @@ define void @test(i32 %arg, i32 %arg1) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]]) {
; CHECK-NEXT: [[BB:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG1]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[ARG]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[ARG1]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[ARG]], i64 0
; CHECK-NEXT: br label %[[BB6:.*]]
; CHECK: [[BB2:.*]]:
; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x i32> [ [[TMP14:%.*]], %[[BB19:.*]] ]
@@ -20,8 +20,8 @@ define void @test(i32 %arg, i32 %arg1) {
; CHECK-NEXT: [[PHI12:%.*]] = phi i32 [ 0, %[[BB28]] ], [ 0, %[[BB6]] ]
; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i32> [ [[TMP3]], %[[BB28]] ], [ zeroinitializer, %[[BB6]] ]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> <i32 poison, i32 0, i32 poison, i32 poison>, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[ARG]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[PHI12]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[ARG]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[PHI12]], i64 3
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> <i32 poison, i32 0, i32 poison, i32 0>, <4 x i32> <i32 poison, i32 5, i32 2, i32 7>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> [[TMP1]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>
; CHECK-NEXT: switch i8 0, label %[[BB19]] [
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/phi-node-bitwidt-op-not.ll b/llvm/test/Transforms/SLPVectorizer/X86/phi-node-bitwidt-op-not.ll
index 0dac02b0bcc09..2d3c433660f33 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/phi-node-bitwidt-op-not.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/phi-node-bitwidt-op-not.ll
@@ -7,18 +7,18 @@ define i32 @test(ptr %b, ptr %c, i32 %0, ptr %a, i1 %tobool3.not) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[TOBOOL3_NOT]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[TMP2]], splat (i32 16)
; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <4 x i32> [[TMP3]], [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i1> [[TMP4]] to <4 x i16>
; CHECK-NEXT: br label [[BB3:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i32> [[TMP7]], zeroinitializer
; CHECK-NEXT: [[TMP9:%.*]] = zext <4 x i1> [[TMP8]] to <4 x i32>
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i1> poison, i1 [[TOBOOL3_NOT]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i1> poison, i1 [[TOBOOL3_NOT]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i1> [[TMP10]], <4 x i1> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP7]], <4 x i32> [[TMP9]]
; CHECK-NEXT: [[TMP13:%.*]] = shl <4 x i32> [[TMP12]], splat (i32 16)
@@ -27,16 +27,16 @@ define i32 @test(ptr %b, ptr %c, i32 %0, ptr %a, i1 %tobool3.not) {
; CHECK-NEXT: br i1 true, label [[BB3]], label [[BB2]]
; CHECK: bb3:
; CHECK-NEXT: [[TMP16:%.*]] = phi <4 x i16> [ [[TMP5]], [[BB1]] ], [ [[TMP15]], [[BB2]] ]
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i16> [[TMP16]], i32 0
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i16> [[TMP16]], i64 0
; CHECK-NEXT: [[TMP18:%.*]] = sext i16 [[TMP17]] to i32
; CHECK-NEXT: store i32 [[TMP18]], ptr [[B]], align 16
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i16> [[TMP16]], i32 1
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i16> [[TMP16]], i64 1
; CHECK-NEXT: [[TMP20:%.*]] = sext i16 [[TMP19]] to i32
; CHECK-NEXT: store i32 [[TMP20]], ptr [[A]], align 8
-; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i16> [[TMP16]], i32 2
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i16> [[TMP16]], i64 2
; CHECK-NEXT: [[TMP22:%.*]] = sext i16 [[TMP21]] to i32
; CHECK-NEXT: store i32 [[TMP22]], ptr [[C]], align 16
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i16> [[TMP16]], i32 3
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i16> [[TMP16]], i64 3
; CHECK-NEXT: [[TMP24:%.*]] = sext i16 [[TMP23]] to i32
; CHECK-NEXT: store i32 [[TMP24]], ptr [[B]], align 8
; CHECK-NEXT: ret i32 0
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/phi-node-with-cycle.ll b/llvm/test/Transforms/SLPVectorizer/X86/phi-node-with-cycle.ll
index af165de293005..143cf143e940f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/phi-node-with-cycle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/phi-node-with-cycle.ll
@@ -4,7 +4,7 @@
define void @test(float %0) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[TMP0]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> <float 0.000000e+00, float poison>, <2 x i32> <i32 2, i32 0>
; CHECK-NEXT: [[TMP5:%.*]] = fdiv <2 x float> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fdiv <2 x float> [[TMP6]], zeroinitializer
@@ -21,8 +21,8 @@ define void @test(float %0) {
; CHECK: [[BB12]]:
; CHECK-NEXT: [[TMP13:%.*]] = fmul <2 x float> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP14:%.*]] = fsub <2 x float> [[TMP11]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x float> [[TMP14]], i32 0
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[TMP14]], i32 1
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x float> [[TMP14]], i64 0
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[TMP14]], i64 1
; CHECK-NEXT: [[TMP17:%.*]] = fadd float [[TMP15]], [[TMP16]]
; CHECK-NEXT: [[TMP18:%.*]] = call float @llvm.fabs.f32(float [[TMP17]])
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/phi.ll b/llvm/test/Transforms/SLPVectorizer/X86/phi.ll
index 2c88e9ab40e50..14c631204cf10 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/phi.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/phi.ll
@@ -155,7 +155,7 @@ define float @foo3(ptr nocapture readonly %A) #0 {
; CHECK-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds float, ptr [[ARRAYIDX1]], i64 [[TMP7]]
; CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX24]], align 4
; CHECK-NEXT: [[TMP24]] = load <2 x float>, ptr [[ARRAYIDX19]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> poison, float [[TMP9]], i32 2
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> poison, float [[TMP9]], i64 2
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <2 x float> [[TMP24]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x float> [[TMP10]], <4 x float> [[TMP11]], <4 x i32> <i32 poison, i32 poison, i32 2, i32 4>
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <2 x float> [[TMP8]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/phi3.ll b/llvm/test/Transforms/SLPVectorizer/X86/phi3.ll
index 038409c56789b..d120d5976281d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/phi3.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/phi3.ll
@@ -14,15 +14,15 @@ define void @Rf_GReset() {
; CHECK-LABEL: @Rf_GReset(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr @d, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[TMP1]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq ptr inttoptr (i64 115 to ptr), @Rf_gpptr
; CHECK-NEXT: br i1 [[CMP2]], label [[IF_THEN:%.*]], label [[IF_END7:%.*]]
; CHECK: if.then:
; CHECK-NEXT: [[TMP3:%.*]] = fsub <2 x double> [[TMP2]], undef
; CHECK-NEXT: [[TMP4:%.*]] = fdiv <2 x double> [[TMP3]], undef
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i64 1
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP6]], [[TMP5]]
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN6:%.*]], label [[IF_END7]]
; CHECK: if.then6:
@@ -57,15 +57,15 @@ define void @Rf_GReset_unary_fneg() {
; CHECK-LABEL: @Rf_GReset_unary_fneg(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr @d, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = fneg <2 x double> [[TMP1]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq ptr inttoptr (i64 115 to ptr), @Rf_gpptr
; CHECK-NEXT: br i1 [[CMP2]], label [[IF_THEN:%.*]], label [[IF_END7:%.*]]
; CHECK: if.then:
; CHECK-NEXT: [[TMP3:%.*]] = fsub <2 x double> [[TMP2]], undef
; CHECK-NEXT: [[TMP4:%.*]] = fdiv <2 x double> [[TMP3]], undef
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i64 1
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[TMP6]], [[TMP5]]
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN6:%.*]], label [[IF_END7]]
; CHECK: if.then6:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/phi_landingpad.ll b/llvm/test/Transforms/SLPVectorizer/X86/phi_landingpad.ll
index 3f765d5a51e88..2da553436f3dc 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/phi_landingpad.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/phi_landingpad.ll
@@ -16,8 +16,8 @@ define void @test_phi_in_landingpad() personality ptr
; CHECK-NEXT: [[Y1:%.*]] = phi double [ undef, [[ENTRY]] ], [ undef, [[INNER]] ]
; CHECK-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 }
; CHECK-NEXT: catch ptr null
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[X1]], i32 0
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> [[TMP3]], double [[Y1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[X1]], i64 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> [[TMP3]], double [[Y1]], i64 1
; CHECK-NEXT: br label [[DONE]]
; CHECK: done:
; CHECK-NEXT: [[TMP2:%.*]] = phi <2 x double> [ undef, [[INNER]] ], [ [[TMP0]], [[LPAD]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/phi_overalignedtype.ll b/llvm/test/Transforms/SLPVectorizer/X86/phi_overalignedtype.ll
index ddbe943e32446..302cefe621220 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/phi_overalignedtype.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/phi_overalignedtype.ll
@@ -12,22 +12,22 @@ define void @test(ptr %i1, ptr %i2, ptr %o, i1 %arg) {
; CHECK-NEXT: [[I1_0:%.*]] = load double, ptr [[I1:%.*]], align 16
; CHECK-NEXT: [[I1_GEP1:%.*]] = getelementptr double, ptr [[I1]], i64 1
; CHECK-NEXT: [[I1_1:%.*]] = load double, ptr [[I1_GEP1]], align 16
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[I1_0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[I1_1]], i32 1
-; CHECK-NEXT: br i1 %arg, label [[THEN:%.*]], label [[END:%.*]]
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[I1_0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[I1_1]], i64 1
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[THEN:%.*]], label [[END:%.*]]
; CHECK: then:
; CHECK-NEXT: [[I2_0:%.*]] = load double, ptr [[I2:%.*]], align 16
; CHECK-NEXT: [[I2_GEP1:%.*]] = getelementptr inbounds double, ptr [[I2]], i64 1
; CHECK-NEXT: [[I2_1:%.*]] = load double, ptr [[I2_GEP1]], align 16
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[I2_0]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[I2_1]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[I2_0]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[I2_1]], i64 1
; CHECK-NEXT: br label [[END]]
; CHECK: end:
; CHECK-NEXT: [[TMP4:%.*]] = phi <2 x double> [ [[TMP1]], [[ENTRY:%.*]] ], [ [[TMP3]], [[THEN]] ]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
; CHECK-NEXT: store double [[TMP5]], ptr [[O:%.*]], align 16
; CHECK-NEXT: [[O_GEP1:%.*]] = getelementptr inbounds double, ptr [[O]], i64 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i64 1
; CHECK-NEXT: store double [[TMP6]], ptr [[O_GEP1]], align 16
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/phis-different-order.ll b/llvm/test/Transforms/SLPVectorizer/X86/phis-different-order.ll
index 2a0d4804026fd..2a744bb6b225e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/phis-different-order.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/phis-different-order.ll
@@ -10,7 +10,7 @@ define ptr @test() {
; CHECK-NEXT: [[PC:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ 0, [[BB:%.*]] ]
; CHECK-NEXT: br i1 false, label [[FOR_INC:%.*]], label [[BB2:%.*]]
; CHECK: for.inc:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> <i64 0, i64 poison>, i64 [[PC]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> <i64 0, i64 poison>, i64 [[PC]], i64 1
; CHECK-NEXT: br i1 false, label [[BB2]], label [[BB]]
; CHECK: bb:
; CHECK-NEXT: br i1 false, label [[BB2]], label [[FOR_BODY]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll b/llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
index ac898a8e9a6f7..d982ce4524438 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/poor-throughput-seeds.ll
@@ -8,17 +8,17 @@ define void @prim(double %x, double %y, double %z, double %w, ptr %p0, ptr %p1)
; CHECK-LABEL: define void @prim(
; CHECK-SAME: double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]], double [[W:%.*]], ptr [[P0:%.*]], ptr [[P1:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[X]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[Y]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[Z]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[W]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[X]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[Y]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[Z]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[W]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> [[TMP5]], <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP7:%.*]] = fdiv <2 x double> [[TMP6]], [[TMP3]]
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i64 0
; CHECK-NEXT: [[X3:%.*]] = fsub double [[TMP8]], [[Z]]
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i64 1
; CHECK-NEXT: [[Y3:%.*]] = fadd double [[TMP9]], [[W]]
; CHECK-NEXT: store double [[X3]], ptr [[P0]], align 8
; CHECK-NEXT: store double [[Y3]], ptr [[P1]], align 8
@@ -53,17 +53,17 @@ define void @prim_sqrt(double %x, double %y, double %z, double %w, ptr %p0, ptr
; CHECK-LABEL: define void @prim_sqrt(
; CHECK-SAME: double [[X:%.*]], double [[Y:%.*]], double [[Z:%.*]], double [[W:%.*]], ptr [[P0:%.*]], ptr [[P1:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[X]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[Y]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[Z]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[W]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[X]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[Y]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[Z]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[W]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> [[TMP5]], <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP7:%.*]] = call <2 x double> @llvm.sqrt.v2f64(<2 x double> [[TMP6]])
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i64 0
; CHECK-NEXT: [[X3:%.*]] = fsub double [[TMP8]], [[Z]]
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i64 1
; CHECK-NEXT: [[Y3:%.*]] = fadd double [[TMP9]], [[W]]
; CHECK-NEXT: store double [[X3]], ptr [[P0]], align 8
; CHECK-NEXT: store double [[Y3]], ptr [[P1]], align 8
@@ -98,27 +98,27 @@ define void @prim_v4(double %x0, double %x1, double %x2, double %x3, double %d0,
; CHECK-LABEL: define void @prim_v4(
; CHECK-SAME: double [[X0:%.*]], double [[X1:%.*]], double [[X2:%.*]], double [[X3:%.*]], double [[D0:%.*]], double [[D1:%.*]], double [[D2:%.*]], double [[D3:%.*]], ptr [[P0:%.*]], ptr [[P1:%.*]], ptr [[P2:%.*]], ptr [[P3:%.*]]) #[[ATTR1]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[X0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[X2]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[D0]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[D2]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[X0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[X2]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[D0]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[D2]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[X1]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> [[TMP5]], double [[X3]], i32 1
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x double> poison, double [[D1]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x double> [[TMP7]], double [[D3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[X1]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> [[TMP5]], double [[X3]], i64 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x double> poison, double [[D1]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x double> [[TMP7]], double [[D3]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = fadd <2 x double> [[TMP6]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = fdiv <2 x double> [[TMP4]], [[TMP3]]
; CHECK-NEXT: [[TMP11:%.*]] = fsub <2 x double> [[TMP10]], [[TMP3]]
; CHECK-NEXT: [[TMP12:%.*]] = fdiv <2 x double> [[TMP9]], [[TMP8]]
; CHECK-NEXT: [[TMP13:%.*]] = fadd <2 x double> [[TMP12]], [[TMP8]]
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x double> [[TMP11]], i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x double> [[TMP11]], i64 0
; CHECK-NEXT: store double [[TMP14]], ptr [[P0]], align 8
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x double> [[TMP13]], i32 0
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x double> [[TMP13]], i64 0
; CHECK-NEXT: store double [[TMP15]], ptr [[P1]], align 8
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x double> [[TMP11]], i32 1
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x double> [[TMP11]], i64 1
; CHECK-NEXT: store double [[TMP16]], ptr [[P2]], align 8
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x double> [[TMP13]], i32 1
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x double> [[TMP13]], i64 1
; CHECK-NEXT: store double [[TMP17]], ptr [[P3]], align 8
; CHECK-NEXT: ret void
;
@@ -129,25 +129,25 @@ define void @prim_v4(double %x0, double %x1, double %x2, double %x3, double %d0,
; DISABLED-NEXT: [[A1:%.*]] = fadd double [[X1]], [[D1]]
; DISABLED-NEXT: [[A2:%.*]] = fsub double [[X2]], [[D2]]
; DISABLED-NEXT: [[A3:%.*]] = fadd double [[X3]], [[D3]]
-; DISABLED-NEXT: [[TMP0:%.*]] = insertelement <4 x double> poison, double [[A1]], i32 0
-; DISABLED-NEXT: [[TMP1:%.*]] = insertelement <4 x double> [[TMP0]], double [[A3]], i32 1
-; DISABLED-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[A0]], i32 2
-; DISABLED-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[A2]], i32 3
-; DISABLED-NEXT: [[TMP4:%.*]] = insertelement <4 x double> poison, double [[D1]], i32 0
-; DISABLED-NEXT: [[TMP5:%.*]] = insertelement <4 x double> [[TMP4]], double [[D3]], i32 1
-; DISABLED-NEXT: [[TMP6:%.*]] = insertelement <4 x double> [[TMP5]], double [[D0]], i32 2
-; DISABLED-NEXT: [[TMP7:%.*]] = insertelement <4 x double> [[TMP6]], double [[D2]], i32 3
+; DISABLED-NEXT: [[TMP0:%.*]] = insertelement <4 x double> poison, double [[A1]], i64 0
+; DISABLED-NEXT: [[TMP1:%.*]] = insertelement <4 x double> [[TMP0]], double [[A3]], i64 1
+; DISABLED-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[A0]], i64 2
+; DISABLED-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[A2]], i64 3
+; DISABLED-NEXT: [[TMP4:%.*]] = insertelement <4 x double> poison, double [[D1]], i64 0
+; DISABLED-NEXT: [[TMP5:%.*]] = insertelement <4 x double> [[TMP4]], double [[D3]], i64 1
+; DISABLED-NEXT: [[TMP6:%.*]] = insertelement <4 x double> [[TMP5]], double [[D0]], i64 2
+; DISABLED-NEXT: [[TMP7:%.*]] = insertelement <4 x double> [[TMP6]], double [[D2]], i64 3
; DISABLED-NEXT: [[TMP8:%.*]] = fdiv <4 x double> [[TMP3]], [[TMP7]]
; DISABLED-NEXT: [[TMP9:%.*]] = fadd <4 x double> [[TMP8]], [[TMP7]]
; DISABLED-NEXT: [[TMP10:%.*]] = fsub <4 x double> [[TMP8]], [[TMP7]]
; DISABLED-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP9]], <4 x double> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
-; DISABLED-NEXT: [[TMP12:%.*]] = extractelement <4 x double> [[TMP11]], i32 2
+; DISABLED-NEXT: [[TMP12:%.*]] = extractelement <4 x double> [[TMP11]], i64 2
; DISABLED-NEXT: store double [[TMP12]], ptr [[P0]], align 8
-; DISABLED-NEXT: [[TMP13:%.*]] = extractelement <4 x double> [[TMP11]], i32 0
+; DISABLED-NEXT: [[TMP13:%.*]] = extractelement <4 x double> [[TMP11]], i64 0
; DISABLED-NEXT: store double [[TMP13]], ptr [[P1]], align 8
-; DISABLED-NEXT: [[TMP14:%.*]] = extractelement <4 x double> [[TMP11]], i32 3
+; DISABLED-NEXT: [[TMP14:%.*]] = extractelement <4 x double> [[TMP11]], i64 3
; DISABLED-NEXT: store double [[TMP14]], ptr [[P2]], align 8
-; DISABLED-NEXT: [[TMP15:%.*]] = extractelement <4 x double> [[TMP11]], i32 1
+; DISABLED-NEXT: [[TMP15:%.*]] = extractelement <4 x double> [[TMP11]], i64 1
; DISABLED-NEXT: store double [[TMP15]], ptr [[P3]], align 8
; DISABLED-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr27163.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr27163.ll
index eed772b0dd104..ac51c85d43b6a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr27163.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr27163.ll
@@ -9,18 +9,18 @@ define void @test1(ptr %p) personality ptr @__CxxFrameHandler3 {
; CHECK-LABEL: @test1(
; CHECK-NEXT: invoke.cont:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[P:%.*]], align 8
-; CHECK-NEXT: [[LOAD1:%.*]] = extractelement <2 x i64> [[TMP0]], i32 0
+; CHECK-NEXT: [[LOAD1:%.*]] = extractelement <2 x i64> [[TMP0]], i64 0
; CHECK-NEXT: store <2 x i64> [[TMP0]], ptr [[P]], align 8
; CHECK-NEXT: invoke void @throw()
; CHECK-NEXT: to label [[UNREACHABLE:%.*]] unwind label [[CATCH_DISPATCH:%.*]]
; CHECK: catch.dispatch:
-; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label %invoke.cont1] unwind label [[EHCLEANUP:%.*]]
+; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label [[INVOKE_CONT1:%.*]]] unwind label [[EHCLEANUP:%.*]]
; CHECK: invoke.cont1:
; CHECK-NEXT: [[CATCH:%.*]] = catchpad within [[CS]] [ptr null, i32 64, ptr null]
; CHECK-NEXT: invoke void @throw() [ "funclet"(token [[CATCH]]) ]
; CHECK-NEXT: to label [[UNREACHABLE]] unwind label [[EHCLEANUP]]
; CHECK: ehcleanup:
-; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[LOAD1]], [[CATCH_DISPATCH]] ], [ 9, [[INVOKE_CONT1:%.*]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[LOAD1]], [[CATCH_DISPATCH]] ], [ 9, [[INVOKE_CONT1]] ]
; CHECK-NEXT: [[CLEANUP:%.*]] = cleanuppad within none []
; CHECK-NEXT: call void @release(i64 [[PHI]]) [ "funclet"(token [[CLEANUP]]) ]
; CHECK-NEXT: cleanupret from [[CLEANUP]] unwind to caller
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr35497.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr35497.ll
index ae9537aa252a6..5cb050ef836cb 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr35497.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr35497.ll
@@ -31,8 +31,8 @@ define void @_ZN1C10SwitchModeEv(ptr %p, i64 %c) {
; AVX-NEXT: store i64 [[OR_1]], ptr [[P:%.*]], align 8
; AVX-NEXT: [[BAR5:%.*]] = load i64, ptr [[P]], align 8
; AVX-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[P]], align 8
-; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[OR_1]], i32 0
-; AVX-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[BAR5]], i32 1
+; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[OR_1]], i64 0
+; AVX-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[BAR5]], i64 1
; AVX-NEXT: [[TMP3:%.*]] = and <2 x i64> [[TMP2]], [[TMP0]]
; AVX-NEXT: store <2 x i64> [[TMP3]], ptr [[P]], align 8
; AVX-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr40522.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr40522.ll
index 618c316c6f2fa..2234d458b5037 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr40522.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr40522.ll
@@ -5,10 +5,10 @@ define void @test1(float %a, float %b, float %c, float %d, ptr nocapture %p) {
; CHECK-LABEL: define void @test1(
; CHECK-SAME: float [[A:%.*]], float [[B:%.*]], float [[C:%.*]], float [[D:%.*]], ptr captures(none) [[P:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[A]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[B]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[C]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[D]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[A]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[B]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[C]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[D]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i32>
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[P]], align 4, !tbaa [[INT_TBAA0:![0-9]+]]
; CHECK-NEXT: ret void
@@ -32,10 +32,10 @@ define void @test1_vec(float %a, float %b, float %c, float %d, ptr nocapture %p)
; CHECK-LABEL: define void @test1_vec(
; CHECK-SAME: float [[A:%.*]], float [[B:%.*]], float [[C:%.*]], float [[D:%.*]], ptr captures(none) [[P:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[A]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[B]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[C]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[D]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[A]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[B]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[C]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[D]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i32>
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[P]], align 16, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: ret void
@@ -57,10 +57,10 @@ define void @test2(i32 %a, i32 %b, i32 %c, i32 %d, ptr nocapture %p) {
; CHECK-LABEL: define void @test2(
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], ptr captures(none) [[P:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[B]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[C]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[D]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[B]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[C]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[D]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], splat (i32 1)
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[P]], align 4, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: ret void
@@ -83,10 +83,10 @@ entry:
define void @test2_vec(i32 %0, i32 %1, i32 %2, i32 %3, ptr nocapture %4) {
; CHECK-LABEL: define void @test2_vec(
; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]], i32 [[TMP3:%.*]], ptr captures(none) [[TMP4:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[TMP2]], i32 2
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[TMP2]], i64 2
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[TMP3]], i64 3
; CHECK-NEXT: [[TMP10:%.*]] = add nsw <4 x i32> [[TMP9]], splat (i32 1)
; CHECK-NEXT: store <4 x i32> [[TMP10]], ptr [[TMP4]], align 16, !tbaa [[INT_TBAA0]]
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll
index 62c59be3fce02..b5cfb846e3d49 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll
@@ -44,17 +44,17 @@ define [2 x %StructTy] @ArrayOfStruct(ptr %Ptr) {
; CHECK-LABEL: @ArrayOfStruct(
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fadd fast <4 x float> [[TMP2]], <float 1.100000e+01, float 1.200000e+01, float 1.300000e+01, float 1.400000e+01>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i64 0
; CHECK-NEXT: [[STRUCTIN0:%.*]] = insertvalue [[STRUCTTY:%.*]] undef, float [[TMP4]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i64 1
; CHECK-NEXT: [[STRUCTIN1:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN0]], float [[TMP5]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i64 2
; CHECK-NEXT: [[STRUCTIN2:%.*]] = insertvalue [[STRUCTTY]] undef, float [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
; CHECK-NEXT: [[STRUCTIN3:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN2]], float [[TMP7]], 1
-; CHECK-NEXT: [[RET0:%.*]] = insertvalue [2 x %StructTy] undef, [[STRUCTTY]] [[STRUCTIN1]], 0
-; CHECK-NEXT: [[RET1:%.*]] = insertvalue [2 x %StructTy] [[RET0]], [[STRUCTTY]] [[STRUCTIN3]], 1
-; CHECK-NEXT: ret [2 x %StructTy] [[RET1]]
+; CHECK-NEXT: [[RET0:%.*]] = insertvalue [2 x [[STRUCTTY]]] undef, [[STRUCTTY]] [[STRUCTIN1]], 0
+; CHECK-NEXT: [[RET1:%.*]] = insertvalue [2 x [[STRUCTTY]]] [[RET0]], [[STRUCTTY]] [[STRUCTIN3]], 1
+; CHECK-NEXT: ret [2 x [[STRUCTTY]]] [[RET1]]
;
%L0 = load float, ptr %Ptr
%GEP1 = getelementptr inbounds float, ptr %Ptr, i64 1
@@ -84,13 +84,13 @@ define {%StructTy, %StructTy} @StructOfStruct(ptr %Ptr) {
; CHECK-LABEL: @StructOfStruct(
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fadd fast <4 x float> [[TMP2]], <float 1.100000e+01, float 1.200000e+01, float 1.300000e+01, float 1.400000e+01>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i64 0
; CHECK-NEXT: [[STRUCTIN0:%.*]] = insertvalue [[STRUCTTY:%.*]] undef, float [[TMP4]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i64 1
; CHECK-NEXT: [[STRUCTIN1:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN0]], float [[TMP5]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i64 2
; CHECK-NEXT: [[STRUCTIN2:%.*]] = insertvalue [[STRUCTTY]] undef, float [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
; CHECK-NEXT: [[STRUCTIN3:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN2]], float [[TMP7]], 1
; CHECK-NEXT: [[RET0:%.*]] = insertvalue { [[STRUCTTY]], [[STRUCTTY]] } undef, [[STRUCTTY]] [[STRUCTIN1]], 0
; CHECK-NEXT: [[RET1:%.*]] = insertvalue { [[STRUCTTY]], [[STRUCTTY]] } [[RET0]], [[STRUCTTY]] [[STRUCTIN3]], 1
@@ -169,21 +169,21 @@ define {%Struct2Ty, %Struct2Ty} @StructOfStructOfStruct(ptr %Ptr) {
; CHECK-LABEL: @StructOfStructOfStruct(
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[PTR:%.*]], align 2
; CHECK-NEXT: [[TMP3:%.*]] = add <8 x i16> [[TMP2]], <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i64 0
; CHECK-NEXT: [[STRUCTIN0:%.*]] = insertvalue [[STRUCT1TY:%.*]] undef, i16 [[TMP4]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i64 1
; CHECK-NEXT: [[STRUCTIN1:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN0]], i16 [[TMP5]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i64 2
; CHECK-NEXT: [[STRUCTIN2:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i64 3
; CHECK-NEXT: [[STRUCTIN3:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN2]], i16 [[TMP7]], 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i64 4
; CHECK-NEXT: [[STRUCTIN4:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP8]], 0
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i64 5
; CHECK-NEXT: [[STRUCTIN5:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN4]], i16 [[TMP9]], 1
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 6
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i64 6
; CHECK-NEXT: [[STRUCTIN6:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP10]], 0
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i64 7
; CHECK-NEXT: [[STRUCTIN7:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN6]], i16 [[TMP11]], 1
; CHECK-NEXT: [[STRUCT2IN0:%.*]] = insertvalue [[STRUCT2TY:%.*]] undef, [[STRUCT1TY]] [[STRUCTIN1]], 0
; CHECK-NEXT: [[STRUCT2IN1:%.*]] = insertvalue [[STRUCT2TY]] [[STRUCT2IN0]], [[STRUCT1TY]] [[STRUCTIN3]], 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr42022.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr42022.ll
index ad6bad31bf4f0..6bd1b64b88a57 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr42022.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr42022.ll
@@ -44,17 +44,17 @@ define [2 x %StructTy] @ArrayOfStruct(ptr %Ptr) {
; CHECK-LABEL: @ArrayOfStruct(
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fadd fast <4 x float> [[TMP2]], <float 1.100000e+01, float 1.200000e+01, float 1.300000e+01, float 1.400000e+01>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i64 0
; CHECK-NEXT: [[STRUCTIN0:%.*]] = insertvalue [[STRUCTTY:%.*]] undef, float [[TMP4]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i64 1
; CHECK-NEXT: [[STRUCTIN1:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN0]], float [[TMP5]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i64 2
; CHECK-NEXT: [[STRUCTIN2:%.*]] = insertvalue [[STRUCTTY]] undef, float [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
; CHECK-NEXT: [[STRUCTIN3:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN2]], float [[TMP7]], 1
-; CHECK-NEXT: [[RET0:%.*]] = insertvalue [2 x %StructTy] undef, [[STRUCTTY]] [[STRUCTIN1]], 0
-; CHECK-NEXT: [[RET1:%.*]] = insertvalue [2 x %StructTy] [[RET0]], [[STRUCTTY]] [[STRUCTIN3]], 1
-; CHECK-NEXT: ret [2 x %StructTy] [[RET1]]
+; CHECK-NEXT: [[RET0:%.*]] = insertvalue [2 x [[STRUCTTY]]] undef, [[STRUCTTY]] [[STRUCTIN1]], 0
+; CHECK-NEXT: [[RET1:%.*]] = insertvalue [2 x [[STRUCTTY]]] [[RET0]], [[STRUCTTY]] [[STRUCTIN3]], 1
+; CHECK-NEXT: ret [2 x [[STRUCTTY]]] [[RET1]]
;
%L0 = load float, ptr %Ptr
%GEP1 = getelementptr inbounds float, ptr %Ptr, i64 1
@@ -84,13 +84,13 @@ define {%StructTy, %StructTy} @StructOfStruct(ptr %Ptr) {
; CHECK-LABEL: @StructOfStruct(
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = fadd fast <4 x float> [[TMP2]], <float 1.100000e+01, float 1.200000e+01, float 1.300000e+01, float 1.400000e+01>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i64 0
; CHECK-NEXT: [[STRUCTIN0:%.*]] = insertvalue [[STRUCTTY:%.*]] undef, float [[TMP4]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i64 1
; CHECK-NEXT: [[STRUCTIN1:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN0]], float [[TMP5]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i64 2
; CHECK-NEXT: [[STRUCTIN2:%.*]] = insertvalue [[STRUCTTY]] undef, float [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
; CHECK-NEXT: [[STRUCTIN3:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN2]], float [[TMP7]], 1
; CHECK-NEXT: [[RET0:%.*]] = insertvalue { [[STRUCTTY]], [[STRUCTTY]] } undef, [[STRUCTTY]] [[STRUCTIN1]], 0
; CHECK-NEXT: [[RET1:%.*]] = insertvalue { [[STRUCTTY]], [[STRUCTTY]] } [[RET0]], [[STRUCTTY]] [[STRUCTIN3]], 1
@@ -169,21 +169,21 @@ define {%Struct2Ty, %Struct2Ty} @StructOfStructOfStruct(ptr %Ptr) {
; CHECK-LABEL: @StructOfStructOfStruct(
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[PTR:%.*]], align 2
; CHECK-NEXT: [[TMP3:%.*]] = add <8 x i16> [[TMP2]], <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i64 0
; CHECK-NEXT: [[STRUCTIN0:%.*]] = insertvalue [[STRUCT1TY:%.*]] undef, i16 [[TMP4]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i64 1
; CHECK-NEXT: [[STRUCTIN1:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN0]], i16 [[TMP5]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i64 2
; CHECK-NEXT: [[STRUCTIN2:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i64 3
; CHECK-NEXT: [[STRUCTIN3:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN2]], i16 [[TMP7]], 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i64 4
; CHECK-NEXT: [[STRUCTIN4:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP8]], 0
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i64 5
; CHECK-NEXT: [[STRUCTIN5:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN4]], i16 [[TMP9]], 1
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 6
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i64 6
; CHECK-NEXT: [[STRUCTIN6:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP10]], 0
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i64 7
; CHECK-NEXT: [[STRUCTIN7:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN6]], i16 [[TMP11]], 1
; CHECK-NEXT: [[STRUCT2IN0:%.*]] = insertvalue [[STRUCT2TY:%.*]] undef, [[STRUCT1TY]] [[STRUCTIN1]], 0
; CHECK-NEXT: [[STRUCT2IN1:%.*]] = insertvalue [[STRUCT2TY]] [[STRUCT2IN0]], [[STRUCT1TY]] [[STRUCTIN3]], 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll
index e8703f2081c66..f9099ef557d2b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll
@@ -29,21 +29,21 @@ define {%Struct2Ty, %Struct2Ty} @StructOfStructOfStruct(ptr %Ptr) {
; CHECK-LABEL: @StructOfStructOfStruct(
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[PTR:%.*]], align 2
; CHECK-NEXT: [[TMP3:%.*]] = add <8 x i16> [[TMP2]], <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i64 1
; CHECK-NEXT: [[STRUCTIN0:%.*]] = insertvalue [[STRUCT1TY:%.*]] undef, i16 [[TMP4]], 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i64 0
; CHECK-NEXT: [[STRUCTIN1:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN0]], i16 [[TMP5]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i64 2
; CHECK-NEXT: [[STRUCTIN2:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i64 3
; CHECK-NEXT: [[STRUCTIN3:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN2]], i16 [[TMP7]], 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i64 4
; CHECK-NEXT: [[STRUCTIN4:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP8]], 0
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i64 5
; CHECK-NEXT: [[STRUCTIN5:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN4]], i16 [[TMP9]], 1
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i64 7
; CHECK-NEXT: [[STRUCTIN6:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP10]], 1
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i32 6
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i64 6
; CHECK-NEXT: [[STRUCTIN7:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN6]], i16 [[TMP11]], 0
; CHECK-NEXT: [[STRUCT2IN0:%.*]] = insertvalue [[STRUCT2TY:%.*]] undef, [[STRUCT1TY]] [[STRUCTIN1]], 0
; CHECK-NEXT: [[STRUCT2IN1:%.*]] = insertvalue [[STRUCT2TY]] [[STRUCT2IN0]], [[STRUCT1TY]] [[STRUCTIN3]], 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr44067.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr44067.ll
index a77f2788200da..5cc44cd0956a2 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr44067.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr44067.ll
@@ -29,21 +29,21 @@ define {%Struct2Ty, %Struct2Ty} @StructOfStructOfStruct(ptr %Ptr) {
; CHECK-LABEL: @StructOfStructOfStruct(
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[PTR:%.*]], align 2
; CHECK-NEXT: [[TMP3:%.*]] = add <8 x i16> [[TMP2]], <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i64 1
; CHECK-NEXT: [[STRUCTIN0:%.*]] = insertvalue [[STRUCT1TY:%.*]] undef, i16 [[TMP4]], 1
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i64 0
; CHECK-NEXT: [[STRUCTIN1:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN0]], i16 [[TMP5]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i64 2
; CHECK-NEXT: [[STRUCTIN2:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i64 3
; CHECK-NEXT: [[STRUCTIN3:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN2]], i16 [[TMP7]], 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i64 4
; CHECK-NEXT: [[STRUCTIN4:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP8]], 0
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i64 5
; CHECK-NEXT: [[STRUCTIN5:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN4]], i16 [[TMP9]], 1
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i64 7
; CHECK-NEXT: [[STRUCTIN6:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP10]], 1
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i32 6
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i64 6
; CHECK-NEXT: [[STRUCTIN7:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN6]], i16 [[TMP11]], 0
; CHECK-NEXT: [[STRUCT2IN0:%.*]] = insertvalue [[STRUCT2TY:%.*]] undef, [[STRUCT1TY]] [[STRUCTIN1]], 0
; CHECK-NEXT: [[STRUCT2IN1:%.*]] = insertvalue [[STRUCT2TY]] [[STRUCT2IN0]], [[STRUCT1TY]] [[STRUCTIN3]], 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
index d3919f6883950..d0a6f1236fa56 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
@@ -9,7 +9,7 @@ define void @store_i32(ptr nocapture %0, i32 %1, i32 %2) {
; CHECK-LABEL: define void @store_i32(
; CHECK-SAME: ptr captures(none) [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4, !tbaa [[INT_TBAA0:![0-9]+]]
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = mul <4 x i32> [[TMP4]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = lshr <4 x i32> [[TMP7]], splat (i32 15)
@@ -53,7 +53,7 @@ define void @store_i8(ptr nocapture %0, i32 %1, i32 %2) {
; CHECK-SAME: ptr captures(none) [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i8>, ptr [[TMP0]], align 1, !tbaa [[CHAR_TBAA4:![0-9]+]]
; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = mul <4 x i32> [[TMP5]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = lshr <4 x i32> [[TMP8]], splat (i32 15)
@@ -106,7 +106,7 @@ define void @store_i64(ptr nocapture %0, i32 %1, i32 %2) {
; CHECK-SSE2-SAME: ptr captures(none) [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR0]] {
; CHECK-SSE2-NEXT: [[TMP4:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-SSE2-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr [[TMP0]], align 8, !tbaa [[LONG_TBAA5:![0-9]+]]
-; CHECK-SSE2-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; CHECK-SSE2-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i64 0
; CHECK-SSE2-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-SSE2-NEXT: [[TMP8:%.*]] = mul <4 x i64> [[TMP5]], [[TMP7]]
; CHECK-SSE2-NEXT: [[TMP9:%.*]] = lshr <4 x i64> [[TMP8]], splat (i64 15)
@@ -121,7 +121,7 @@ define void @store_i64(ptr nocapture %0, i32 %1, i32 %2) {
; CHECK-SSE42-SAME: ptr captures(none) [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR0]] {
; CHECK-SSE42-NEXT: [[TMP4:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-SSE42-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr [[TMP0]], align 8, !tbaa [[LONG_TBAA5:![0-9]+]]
-; CHECK-SSE42-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; CHECK-SSE42-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i64 0
; CHECK-SSE42-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-SSE42-NEXT: [[TMP8:%.*]] = mul <4 x i64> [[TMP5]], [[TMP7]]
; CHECK-SSE42-NEXT: [[TMP9:%.*]] = lshr <4 x i64> [[TMP8]], splat (i64 15)
@@ -150,17 +150,17 @@ define void @store_i64(ptr nocapture %0, i32 %1, i32 %2) {
; CHECK-AVX-NEXT: [[TMP17:%.*]] = load i64, ptr [[TMP0]], align 8, !tbaa [[LONG_TBAA5]]
; CHECK-AVX-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP4]]
; CHECK-AVX-NEXT: [[TMP19:%.*]] = mul i64 [[TMP17]], [[TMP4]]
-; CHECK-AVX-NEXT: [[TMP20:%.*]] = insertelement <2 x i64> poison, i64 [[TMP19]], i32 0
-; CHECK-AVX-NEXT: [[TMP21:%.*]] = insertelement <2 x i64> [[TMP20]], i64 [[TMP18]], i32 1
+; CHECK-AVX-NEXT: [[TMP20:%.*]] = insertelement <2 x i64> poison, i64 [[TMP19]], i64 0
+; CHECK-AVX-NEXT: [[TMP21:%.*]] = insertelement <2 x i64> [[TMP20]], i64 [[TMP18]], i64 1
; CHECK-AVX-NEXT: [[TMP22:%.*]] = lshr <2 x i64> [[TMP21]], splat (i64 15)
; CHECK-AVX-NEXT: [[TMP23:%.*]] = trunc <2 x i64> [[TMP22]] to <2 x i32>
; CHECK-AVX-NEXT: [[TMP24:%.*]] = shufflevector <2 x i32> [[TMP23]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
-; CHECK-AVX-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[TMP15]], i32 2
-; CHECK-AVX-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP14]], i32 3
+; CHECK-AVX-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[TMP15]], i64 2
+; CHECK-AVX-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP14]], i64 3
; CHECK-AVX-NEXT: [[TMP27:%.*]] = icmp ult <4 x i32> [[TMP26]], splat (i32 255)
; CHECK-AVX-NEXT: [[TMP28:%.*]] = shufflevector <2 x i64> [[TMP22]], <2 x i64> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
-; CHECK-AVX-NEXT: [[TMP29:%.*]] = insertelement <4 x i64> [[TMP28]], i64 [[TMP13]], i32 2
-; CHECK-AVX-NEXT: [[TMP30:%.*]] = insertelement <4 x i64> [[TMP29]], i64 [[TMP12]], i32 3
+; CHECK-AVX-NEXT: [[TMP29:%.*]] = insertelement <4 x i64> [[TMP28]], i64 [[TMP13]], i64 2
+; CHECK-AVX-NEXT: [[TMP30:%.*]] = insertelement <4 x i64> [[TMP29]], i64 [[TMP12]], i64 3
; CHECK-AVX-NEXT: [[TMP31:%.*]] = and <4 x i64> [[TMP30]], splat (i64 4294967295)
; CHECK-AVX-NEXT: [[TMP32:%.*]] = select <4 x i1> [[TMP27]], <4 x i64> [[TMP31]], <4 x i64> splat (i64 255)
; CHECK-AVX-NEXT: store <4 x i64> [[TMP32]], ptr [[TMP0]], align 8, !tbaa [[LONG_TBAA5]]
@@ -170,7 +170,7 @@ define void @store_i64(ptr nocapture %0, i32 %1, i32 %2) {
; CHECK-AVX2-SAME: ptr captures(none) [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR0]] {
; CHECK-AVX2-NEXT: [[TMP4:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-AVX2-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr [[TMP0]], align 8, !tbaa [[LONG_TBAA5:![0-9]+]]
-; CHECK-AVX2-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; CHECK-AVX2-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i64 0
; CHECK-AVX2-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-AVX2-NEXT: [[TMP8:%.*]] = mul <4 x i64> [[TMP5]], [[TMP7]]
; CHECK-AVX2-NEXT: [[TMP9:%.*]] = lshr <4 x i64> [[TMP8]], splat (i64 15)
@@ -185,7 +185,7 @@ define void @store_i64(ptr nocapture %0, i32 %1, i32 %2) {
; CHECK-AVX512-SAME: ptr captures(none) [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR0]] {
; CHECK-AVX512-NEXT: [[TMP4:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-AVX512-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr [[TMP0]], align 8, !tbaa [[LONG_TBAA5:![0-9]+]]
-; CHECK-AVX512-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; CHECK-AVX512-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i64 0
; CHECK-AVX512-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <4 x i32> zeroinitializer
; CHECK-AVX512-NEXT: [[TMP8:%.*]] = mul <4 x i64> [[TMP5]], [[TMP7]]
; CHECK-AVX512-NEXT: [[TMP9:%.*]] = lshr <4 x i64> [[TMP8]], splat (i64 15)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
index 026678edf06ea..02d7698fc040e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
@@ -143,10 +143,10 @@ define void @gather_load_2(ptr noalias nocapture %0, ptr noalias nocapture reado
; AVX-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 5
; AVX-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
-; AVX-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP6]], i32 1
-; AVX-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP8]], i32 2
-; AVX-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP10]], i32 3
+; AVX-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 0
+; AVX-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP6]], i64 1
+; AVX-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP8]], i64 2
+; AVX-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP10]], i64 3
; AVX-NEXT: [[TMP15:%.*]] = add nsw <4 x i32> [[TMP14]], <i32 1, i32 2, i32 3, i32 4>
; AVX-NEXT: store <4 x i32> [[TMP15]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: ret void
@@ -161,10 +161,10 @@ define void @gather_load_2(ptr noalias nocapture %0, ptr noalias nocapture reado
; AVX2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 5
; AVX2-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX2-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
-; AVX2-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP6]], i32 1
-; AVX2-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP8]], i32 2
-; AVX2-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP10]], i32 3
+; AVX2-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 0
+; AVX2-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP6]], i64 1
+; AVX2-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP8]], i64 2
+; AVX2-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP10]], i64 3
; AVX2-NEXT: [[TMP15:%.*]] = add nsw <4 x i32> [[TMP14]], <i32 1, i32 2, i32 3, i32 4>
; AVX2-NEXT: store <4 x i32> [[TMP15]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX2-NEXT: ret void
@@ -272,14 +272,14 @@ define void @gather_load_3(ptr noalias nocapture %0, ptr noalias nocapture reado
; AVX-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 21
; AVX-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX-NEXT: [[TMP18:%.*]] = insertelement <8 x i32> poison, i32 [[TMP3]], i32 0
-; AVX-NEXT: [[TMP19:%.*]] = insertelement <8 x i32> [[TMP18]], i32 [[TMP5]], i32 1
-; AVX-NEXT: [[TMP20:%.*]] = insertelement <8 x i32> [[TMP19]], i32 [[TMP7]], i32 2
-; AVX-NEXT: [[TMP21:%.*]] = insertelement <8 x i32> [[TMP20]], i32 [[TMP9]], i32 3
-; AVX-NEXT: [[TMP22:%.*]] = insertelement <8 x i32> [[TMP21]], i32 [[TMP11]], i32 4
-; AVX-NEXT: [[TMP23:%.*]] = insertelement <8 x i32> [[TMP22]], i32 [[TMP13]], i32 5
-; AVX-NEXT: [[TMP24:%.*]] = insertelement <8 x i32> [[TMP23]], i32 [[TMP15]], i32 6
-; AVX-NEXT: [[TMP25:%.*]] = insertelement <8 x i32> [[TMP24]], i32 [[TMP17]], i32 7
+; AVX-NEXT: [[TMP18:%.*]] = insertelement <8 x i32> poison, i32 [[TMP3]], i64 0
+; AVX-NEXT: [[TMP19:%.*]] = insertelement <8 x i32> [[TMP18]], i32 [[TMP5]], i64 1
+; AVX-NEXT: [[TMP20:%.*]] = insertelement <8 x i32> [[TMP19]], i32 [[TMP7]], i64 2
+; AVX-NEXT: [[TMP21:%.*]] = insertelement <8 x i32> [[TMP20]], i32 [[TMP9]], i64 3
+; AVX-NEXT: [[TMP22:%.*]] = insertelement <8 x i32> [[TMP21]], i32 [[TMP11]], i64 4
+; AVX-NEXT: [[TMP23:%.*]] = insertelement <8 x i32> [[TMP22]], i32 [[TMP13]], i64 5
+; AVX-NEXT: [[TMP24:%.*]] = insertelement <8 x i32> [[TMP23]], i32 [[TMP15]], i64 6
+; AVX-NEXT: [[TMP25:%.*]] = insertelement <8 x i32> [[TMP24]], i32 [[TMP17]], i64 7
; AVX-NEXT: [[TMP26:%.*]] = add <8 x i32> [[TMP25]], <i32 1, i32 2, i32 3, i32 4, i32 1, i32 2, i32 3, i32 4>
; AVX-NEXT: store <8 x i32> [[TMP26]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: ret void
@@ -412,14 +412,14 @@ define void @gather_load_4(ptr noalias nocapture %t0, ptr noalias nocapture read
; AVX-NEXT: [[T23:%.*]] = load i32, ptr [[T22]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[T27:%.*]] = load i32, ptr [[T26]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[T31:%.*]] = load i32, ptr [[T30]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[T3]], i32 0
-; AVX-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> [[TMP1]], i32 [[T7]], i32 1
-; AVX-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[T11]], i32 2
-; AVX-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[T15]], i32 3
-; AVX-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[T19]], i32 4
-; AVX-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[T23]], i32 5
-; AVX-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[T27]], i32 6
-; AVX-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[T31]], i32 7
+; AVX-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[T3]], i64 0
+; AVX-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> [[TMP1]], i32 [[T7]], i64 1
+; AVX-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[T11]], i64 2
+; AVX-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[T15]], i64 3
+; AVX-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[T19]], i64 4
+; AVX-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[T23]], i64 5
+; AVX-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[T27]], i64 6
+; AVX-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[T31]], i64 7
; AVX-NEXT: [[TMP9:%.*]] = add <8 x i32> [[TMP8]], <i32 1, i32 2, i32 3, i32 4, i32 1, i32 2, i32 3, i32 4>
; AVX-NEXT: store <8 x i32> [[TMP9]], ptr [[T0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: ret void
@@ -510,7 +510,7 @@ define void @gather_load_div(ptr noalias nocapture %0, ptr noalias nocapture rea
; SSE-NEXT: [[TMP10:%.*]] = load <2 x float>, ptr [[TMP6]], align 4, !tbaa [[SHORT_TBAA0]]
; SSE-NEXT: [[TMP11:%.*]] = load <2 x float>, ptr [[TMP4]], align 4, !tbaa [[SHORT_TBAA0]]
; SSE-NEXT: [[TMP12:%.*]] = load <2 x float>, ptr [[TMP5]], align 4, !tbaa [[SHORT_TBAA0]]
-; SSE-NEXT: [[TMP13:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i32 0
+; SSE-NEXT: [[TMP13:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i64 0
; SSE-NEXT: [[TMP14:%.*]] = shufflevector <2 x float> [[TMP11]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; SSE-NEXT: [[TMP15:%.*]] = shufflevector <4 x float> [[TMP13]], <4 x float> [[TMP14]], <4 x i32> <i32 0, i32 4, i32 poison, i32 poison>
; SSE-NEXT: [[TMP16:%.*]] = shufflevector <2 x float> [[TMP10]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
@@ -519,7 +519,7 @@ define void @gather_load_div(ptr noalias nocapture %0, ptr noalias nocapture rea
; SSE-NEXT: [[TMP19:%.*]] = shufflevector <4 x float> [[TMP17]], <4 x float> [[TMP18]], <4 x i32> <i32 0, i32 1, i32 2, i32 5>
; SSE-NEXT: [[TMP20:%.*]] = shufflevector <2 x float> [[TMP10]], <2 x float> [[TMP12]], <4 x i32> <i32 1, i32 2, i32 poison, i32 poison>
; SSE-NEXT: [[TMP21:%.*]] = shufflevector <4 x float> [[TMP20]], <4 x float> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 5, i32 poison>
-; SSE-NEXT: [[TMP22:%.*]] = insertelement <4 x float> [[TMP21]], float [[TMP8]], i32 3
+; SSE-NEXT: [[TMP22:%.*]] = insertelement <4 x float> [[TMP21]], float [[TMP8]], i64 3
; SSE-NEXT: [[TMP23:%.*]] = fdiv <4 x float> [[TMP19]], [[TMP22]]
; SSE-NEXT: store <4 x float> [[TMP23]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; SSE-NEXT: [[TMP24:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 17
@@ -538,14 +538,14 @@ define void @gather_load_div(ptr noalias nocapture %0, ptr noalias nocapture rea
; SSE-NEXT: [[TMP37:%.*]] = load float, ptr [[TMP36]], align 4, !tbaa [[SHORT_TBAA0]]
; SSE-NEXT: [[TMP38:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 23
; SSE-NEXT: [[TMP39:%.*]] = load float, ptr [[TMP38]], align 4, !tbaa [[SHORT_TBAA0]]
-; SSE-NEXT: [[TMP40:%.*]] = insertelement <4 x float> poison, float [[TMP25]], i32 0
-; SSE-NEXT: [[TMP41:%.*]] = insertelement <4 x float> [[TMP40]], float [[TMP29]], i32 1
-; SSE-NEXT: [[TMP42:%.*]] = insertelement <4 x float> [[TMP41]], float [[TMP33]], i32 2
-; SSE-NEXT: [[TMP43:%.*]] = insertelement <4 x float> [[TMP42]], float [[TMP37]], i32 3
-; SSE-NEXT: [[TMP44:%.*]] = insertelement <4 x float> poison, float [[TMP27]], i32 0
-; SSE-NEXT: [[TMP45:%.*]] = insertelement <4 x float> [[TMP44]], float [[TMP31]], i32 1
-; SSE-NEXT: [[TMP46:%.*]] = insertelement <4 x float> [[TMP45]], float [[TMP35]], i32 2
-; SSE-NEXT: [[TMP47:%.*]] = insertelement <4 x float> [[TMP46]], float [[TMP39]], i32 3
+; SSE-NEXT: [[TMP40:%.*]] = insertelement <4 x float> poison, float [[TMP25]], i64 0
+; SSE-NEXT: [[TMP41:%.*]] = insertelement <4 x float> [[TMP40]], float [[TMP29]], i64 1
+; SSE-NEXT: [[TMP42:%.*]] = insertelement <4 x float> [[TMP41]], float [[TMP33]], i64 2
+; SSE-NEXT: [[TMP43:%.*]] = insertelement <4 x float> [[TMP42]], float [[TMP37]], i64 3
+; SSE-NEXT: [[TMP44:%.*]] = insertelement <4 x float> poison, float [[TMP27]], i64 0
+; SSE-NEXT: [[TMP45:%.*]] = insertelement <4 x float> [[TMP44]], float [[TMP31]], i64 1
+; SSE-NEXT: [[TMP46:%.*]] = insertelement <4 x float> [[TMP45]], float [[TMP35]], i64 2
+; SSE-NEXT: [[TMP47:%.*]] = insertelement <4 x float> [[TMP46]], float [[TMP39]], i64 3
; SSE-NEXT: [[TMP48:%.*]] = fdiv <4 x float> [[TMP43]], [[TMP47]]
; SSE-NEXT: store <4 x float> [[TMP48]], ptr [[TMP9]], align 4, !tbaa [[SHORT_TBAA0]]
; SSE-NEXT: ret void
@@ -577,24 +577,24 @@ define void @gather_load_div(ptr noalias nocapture %0, ptr noalias nocapture rea
; AVX-NEXT: [[TMP25:%.*]] = load <2 x float>, ptr [[TMP6]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[TMP26:%.*]] = load <2 x float>, ptr [[TMP4]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[TMP27:%.*]] = load <2 x float>, ptr [[TMP5]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX-NEXT: [[TMP28:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i32 0
+; AVX-NEXT: [[TMP28:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i64 0
; AVX-NEXT: [[TMP29:%.*]] = shufflevector <2 x float> [[TMP26]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP30:%.*]] = shufflevector <8 x float> [[TMP28]], <8 x float> [[TMP29]], <8 x i32> <i32 0, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP31:%.*]] = shufflevector <2 x float> [[TMP25]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP32:%.*]] = shufflevector <8 x float> [[TMP30]], <8 x float> [[TMP31]], <8 x i32> <i32 0, i32 1, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP33:%.*]] = shufflevector <2 x float> [[TMP27]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP34:%.*]] = shufflevector <8 x float> [[TMP32]], <8 x float> [[TMP33]], <8 x i32> <i32 0, i32 1, i32 2, i32 9, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP35:%.*]] = insertelement <8 x float> [[TMP34]], float [[TMP10]], i32 4
-; AVX-NEXT: [[TMP36:%.*]] = insertelement <8 x float> [[TMP35]], float [[TMP14]], i32 5
-; AVX-NEXT: [[TMP37:%.*]] = insertelement <8 x float> [[TMP36]], float [[TMP18]], i32 6
-; AVX-NEXT: [[TMP38:%.*]] = insertelement <8 x float> [[TMP37]], float [[TMP22]], i32 7
+; AVX-NEXT: [[TMP35:%.*]] = insertelement <8 x float> [[TMP34]], float [[TMP10]], i64 4
+; AVX-NEXT: [[TMP36:%.*]] = insertelement <8 x float> [[TMP35]], float [[TMP14]], i64 5
+; AVX-NEXT: [[TMP37:%.*]] = insertelement <8 x float> [[TMP36]], float [[TMP18]], i64 6
+; AVX-NEXT: [[TMP38:%.*]] = insertelement <8 x float> [[TMP37]], float [[TMP22]], i64 7
; AVX-NEXT: [[TMP39:%.*]] = shufflevector <2 x float> [[TMP25]], <2 x float> [[TMP27]], <8 x i32> <i32 1, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP40:%.*]] = shufflevector <8 x float> [[TMP39]], <8 x float> [[TMP29]], <8 x i32> <i32 0, i32 1, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP41:%.*]] = insertelement <8 x float> [[TMP40]], float [[TMP8]], i32 3
-; AVX-NEXT: [[TMP42:%.*]] = insertelement <8 x float> [[TMP41]], float [[TMP12]], i32 4
-; AVX-NEXT: [[TMP43:%.*]] = insertelement <8 x float> [[TMP42]], float [[TMP16]], i32 5
-; AVX-NEXT: [[TMP44:%.*]] = insertelement <8 x float> [[TMP43]], float [[TMP20]], i32 6
-; AVX-NEXT: [[TMP45:%.*]] = insertelement <8 x float> [[TMP44]], float [[TMP24]], i32 7
+; AVX-NEXT: [[TMP41:%.*]] = insertelement <8 x float> [[TMP40]], float [[TMP8]], i64 3
+; AVX-NEXT: [[TMP42:%.*]] = insertelement <8 x float> [[TMP41]], float [[TMP12]], i64 4
+; AVX-NEXT: [[TMP43:%.*]] = insertelement <8 x float> [[TMP42]], float [[TMP16]], i64 5
+; AVX-NEXT: [[TMP44:%.*]] = insertelement <8 x float> [[TMP43]], float [[TMP20]], i64 6
+; AVX-NEXT: [[TMP45:%.*]] = insertelement <8 x float> [[TMP44]], float [[TMP24]], i64 7
; AVX-NEXT: [[TMP46:%.*]] = fdiv <8 x float> [[TMP38]], [[TMP45]]
; AVX-NEXT: store <8 x float> [[TMP46]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: ret void
@@ -626,24 +626,24 @@ define void @gather_load_div(ptr noalias nocapture %0, ptr noalias nocapture rea
; AVX2-NEXT: [[TMP25:%.*]] = load <2 x float>, ptr [[TMP6]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX2-NEXT: [[TMP26:%.*]] = load <2 x float>, ptr [[TMP4]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX2-NEXT: [[TMP27:%.*]] = load <2 x float>, ptr [[TMP5]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX2-NEXT: [[TMP28:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i32 0
+; AVX2-NEXT: [[TMP28:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i64 0
; AVX2-NEXT: [[TMP29:%.*]] = shufflevector <2 x float> [[TMP26]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP30:%.*]] = shufflevector <8 x float> [[TMP28]], <8 x float> [[TMP29]], <8 x i32> <i32 0, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP31:%.*]] = shufflevector <2 x float> [[TMP25]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP32:%.*]] = shufflevector <8 x float> [[TMP30]], <8 x float> [[TMP31]], <8 x i32> <i32 0, i32 1, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP33:%.*]] = shufflevector <2 x float> [[TMP27]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP34:%.*]] = shufflevector <8 x float> [[TMP32]], <8 x float> [[TMP33]], <8 x i32> <i32 0, i32 1, i32 2, i32 9, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX2-NEXT: [[TMP35:%.*]] = insertelement <8 x float> [[TMP34]], float [[TMP10]], i32 4
-; AVX2-NEXT: [[TMP36:%.*]] = insertelement <8 x float> [[TMP35]], float [[TMP14]], i32 5
-; AVX2-NEXT: [[TMP37:%.*]] = insertelement <8 x float> [[TMP36]], float [[TMP18]], i32 6
-; AVX2-NEXT: [[TMP38:%.*]] = insertelement <8 x float> [[TMP37]], float [[TMP22]], i32 7
+; AVX2-NEXT: [[TMP35:%.*]] = insertelement <8 x float> [[TMP34]], float [[TMP10]], i64 4
+; AVX2-NEXT: [[TMP36:%.*]] = insertelement <8 x float> [[TMP35]], float [[TMP14]], i64 5
+; AVX2-NEXT: [[TMP37:%.*]] = insertelement <8 x float> [[TMP36]], float [[TMP18]], i64 6
+; AVX2-NEXT: [[TMP38:%.*]] = insertelement <8 x float> [[TMP37]], float [[TMP22]], i64 7
; AVX2-NEXT: [[TMP39:%.*]] = shufflevector <2 x float> [[TMP25]], <2 x float> [[TMP27]], <8 x i32> <i32 1, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP40:%.*]] = shufflevector <8 x float> [[TMP39]], <8 x float> [[TMP29]], <8 x i32> <i32 0, i32 1, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX2-NEXT: [[TMP41:%.*]] = insertelement <8 x float> [[TMP40]], float [[TMP8]], i32 3
-; AVX2-NEXT: [[TMP42:%.*]] = insertelement <8 x float> [[TMP41]], float [[TMP12]], i32 4
-; AVX2-NEXT: [[TMP43:%.*]] = insertelement <8 x float> [[TMP42]], float [[TMP16]], i32 5
-; AVX2-NEXT: [[TMP44:%.*]] = insertelement <8 x float> [[TMP43]], float [[TMP20]], i32 6
-; AVX2-NEXT: [[TMP45:%.*]] = insertelement <8 x float> [[TMP44]], float [[TMP24]], i32 7
+; AVX2-NEXT: [[TMP41:%.*]] = insertelement <8 x float> [[TMP40]], float [[TMP8]], i64 3
+; AVX2-NEXT: [[TMP42:%.*]] = insertelement <8 x float> [[TMP41]], float [[TMP12]], i64 4
+; AVX2-NEXT: [[TMP43:%.*]] = insertelement <8 x float> [[TMP42]], float [[TMP16]], i64 5
+; AVX2-NEXT: [[TMP44:%.*]] = insertelement <8 x float> [[TMP43]], float [[TMP20]], i64 6
+; AVX2-NEXT: [[TMP45:%.*]] = insertelement <8 x float> [[TMP44]], float [[TMP24]], i64 7
; AVX2-NEXT: [[TMP46:%.*]] = fdiv <8 x float> [[TMP38]], [[TMP45]]
; AVX2-NEXT: store <8 x float> [[TMP46]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX2-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
index 01309be30f51e..d22e056b4bba4 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
@@ -143,10 +143,10 @@ define void @gather_load_2(ptr noalias nocapture %0, ptr noalias nocapture reado
; AVX-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 5
; AVX-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
-; AVX-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP6]], i32 1
-; AVX-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP8]], i32 2
-; AVX-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP10]], i32 3
+; AVX-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 0
+; AVX-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP6]], i64 1
+; AVX-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP8]], i64 2
+; AVX-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP10]], i64 3
; AVX-NEXT: [[TMP15:%.*]] = add nsw <4 x i32> [[TMP14]], <i32 1, i32 2, i32 3, i32 4>
; AVX-NEXT: store <4 x i32> [[TMP15]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: ret void
@@ -161,10 +161,10 @@ define void @gather_load_2(ptr noalias nocapture %0, ptr noalias nocapture reado
; AVX2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 5
; AVX2-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX2-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
-; AVX2-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP6]], i32 1
-; AVX2-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP8]], i32 2
-; AVX2-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP10]], i32 3
+; AVX2-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 0
+; AVX2-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP6]], i64 1
+; AVX2-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP8]], i64 2
+; AVX2-NEXT: [[TMP14:%.*]] = insertelement <4 x i32> [[TMP13]], i32 [[TMP10]], i64 3
; AVX2-NEXT: [[TMP15:%.*]] = add nsw <4 x i32> [[TMP14]], <i32 1, i32 2, i32 3, i32 4>
; AVX2-NEXT: store <4 x i32> [[TMP15]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX2-NEXT: ret void
@@ -272,14 +272,14 @@ define void @gather_load_3(ptr noalias nocapture %0, ptr noalias nocapture reado
; AVX-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 21
; AVX-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX-NEXT: [[TMP18:%.*]] = insertelement <8 x i32> poison, i32 [[TMP3]], i32 0
-; AVX-NEXT: [[TMP19:%.*]] = insertelement <8 x i32> [[TMP18]], i32 [[TMP5]], i32 1
-; AVX-NEXT: [[TMP20:%.*]] = insertelement <8 x i32> [[TMP19]], i32 [[TMP7]], i32 2
-; AVX-NEXT: [[TMP21:%.*]] = insertelement <8 x i32> [[TMP20]], i32 [[TMP9]], i32 3
-; AVX-NEXT: [[TMP22:%.*]] = insertelement <8 x i32> [[TMP21]], i32 [[TMP11]], i32 4
-; AVX-NEXT: [[TMP23:%.*]] = insertelement <8 x i32> [[TMP22]], i32 [[TMP13]], i32 5
-; AVX-NEXT: [[TMP24:%.*]] = insertelement <8 x i32> [[TMP23]], i32 [[TMP15]], i32 6
-; AVX-NEXT: [[TMP25:%.*]] = insertelement <8 x i32> [[TMP24]], i32 [[TMP17]], i32 7
+; AVX-NEXT: [[TMP18:%.*]] = insertelement <8 x i32> poison, i32 [[TMP3]], i64 0
+; AVX-NEXT: [[TMP19:%.*]] = insertelement <8 x i32> [[TMP18]], i32 [[TMP5]], i64 1
+; AVX-NEXT: [[TMP20:%.*]] = insertelement <8 x i32> [[TMP19]], i32 [[TMP7]], i64 2
+; AVX-NEXT: [[TMP21:%.*]] = insertelement <8 x i32> [[TMP20]], i32 [[TMP9]], i64 3
+; AVX-NEXT: [[TMP22:%.*]] = insertelement <8 x i32> [[TMP21]], i32 [[TMP11]], i64 4
+; AVX-NEXT: [[TMP23:%.*]] = insertelement <8 x i32> [[TMP22]], i32 [[TMP13]], i64 5
+; AVX-NEXT: [[TMP24:%.*]] = insertelement <8 x i32> [[TMP23]], i32 [[TMP15]], i64 6
+; AVX-NEXT: [[TMP25:%.*]] = insertelement <8 x i32> [[TMP24]], i32 [[TMP17]], i64 7
; AVX-NEXT: [[TMP26:%.*]] = add <8 x i32> [[TMP25]], <i32 1, i32 2, i32 3, i32 4, i32 1, i32 2, i32 3, i32 4>
; AVX-NEXT: store <8 x i32> [[TMP26]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: ret void
@@ -412,14 +412,14 @@ define void @gather_load_4(ptr noalias nocapture %t0, ptr noalias nocapture read
; AVX-NEXT: [[T23:%.*]] = load i32, ptr [[T22]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[T27:%.*]] = load i32, ptr [[T26]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[T31:%.*]] = load i32, ptr [[T30]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[T3]], i32 0
-; AVX-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> [[TMP1]], i32 [[T7]], i32 1
-; AVX-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[T11]], i32 2
-; AVX-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[T15]], i32 3
-; AVX-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[T19]], i32 4
-; AVX-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[T23]], i32 5
-; AVX-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[T27]], i32 6
-; AVX-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[T31]], i32 7
+; AVX-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> poison, i32 [[T3]], i64 0
+; AVX-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> [[TMP1]], i32 [[T7]], i64 1
+; AVX-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[T11]], i64 2
+; AVX-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[T15]], i64 3
+; AVX-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[T19]], i64 4
+; AVX-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[T23]], i64 5
+; AVX-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[T27]], i64 6
+; AVX-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[T31]], i64 7
; AVX-NEXT: [[TMP9:%.*]] = add <8 x i32> [[TMP8]], <i32 1, i32 2, i32 3, i32 4, i32 1, i32 2, i32 3, i32 4>
; AVX-NEXT: store <8 x i32> [[TMP9]], ptr [[T0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: ret void
@@ -510,7 +510,7 @@ define void @gather_load_div(ptr noalias nocapture %0, ptr noalias nocapture rea
; SSE-NEXT: [[TMP10:%.*]] = load <2 x float>, ptr [[TMP6]], align 4, !tbaa [[SHORT_TBAA0]]
; SSE-NEXT: [[TMP11:%.*]] = load <2 x float>, ptr [[TMP4]], align 4, !tbaa [[SHORT_TBAA0]]
; SSE-NEXT: [[TMP12:%.*]] = load <2 x float>, ptr [[TMP5]], align 4, !tbaa [[SHORT_TBAA0]]
-; SSE-NEXT: [[TMP13:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i32 0
+; SSE-NEXT: [[TMP13:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i64 0
; SSE-NEXT: [[TMP14:%.*]] = shufflevector <2 x float> [[TMP11]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; SSE-NEXT: [[TMP15:%.*]] = shufflevector <4 x float> [[TMP13]], <4 x float> [[TMP14]], <4 x i32> <i32 0, i32 4, i32 poison, i32 poison>
; SSE-NEXT: [[TMP16:%.*]] = shufflevector <2 x float> [[TMP10]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
@@ -519,7 +519,7 @@ define void @gather_load_div(ptr noalias nocapture %0, ptr noalias nocapture rea
; SSE-NEXT: [[TMP19:%.*]] = shufflevector <4 x float> [[TMP17]], <4 x float> [[TMP18]], <4 x i32> <i32 0, i32 1, i32 2, i32 5>
; SSE-NEXT: [[TMP20:%.*]] = shufflevector <2 x float> [[TMP10]], <2 x float> [[TMP12]], <4 x i32> <i32 1, i32 2, i32 poison, i32 poison>
; SSE-NEXT: [[TMP21:%.*]] = shufflevector <4 x float> [[TMP20]], <4 x float> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 5, i32 poison>
-; SSE-NEXT: [[TMP22:%.*]] = insertelement <4 x float> [[TMP21]], float [[TMP8]], i32 3
+; SSE-NEXT: [[TMP22:%.*]] = insertelement <4 x float> [[TMP21]], float [[TMP8]], i64 3
; SSE-NEXT: [[TMP23:%.*]] = fdiv <4 x float> [[TMP19]], [[TMP22]]
; SSE-NEXT: store <4 x float> [[TMP23]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; SSE-NEXT: [[TMP24:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 17
@@ -538,14 +538,14 @@ define void @gather_load_div(ptr noalias nocapture %0, ptr noalias nocapture rea
; SSE-NEXT: [[TMP37:%.*]] = load float, ptr [[TMP36]], align 4, !tbaa [[SHORT_TBAA0]]
; SSE-NEXT: [[TMP38:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 23
; SSE-NEXT: [[TMP39:%.*]] = load float, ptr [[TMP38]], align 4, !tbaa [[SHORT_TBAA0]]
-; SSE-NEXT: [[TMP40:%.*]] = insertelement <4 x float> poison, float [[TMP25]], i32 0
-; SSE-NEXT: [[TMP41:%.*]] = insertelement <4 x float> [[TMP40]], float [[TMP29]], i32 1
-; SSE-NEXT: [[TMP42:%.*]] = insertelement <4 x float> [[TMP41]], float [[TMP33]], i32 2
-; SSE-NEXT: [[TMP43:%.*]] = insertelement <4 x float> [[TMP42]], float [[TMP37]], i32 3
-; SSE-NEXT: [[TMP44:%.*]] = insertelement <4 x float> poison, float [[TMP27]], i32 0
-; SSE-NEXT: [[TMP45:%.*]] = insertelement <4 x float> [[TMP44]], float [[TMP31]], i32 1
-; SSE-NEXT: [[TMP46:%.*]] = insertelement <4 x float> [[TMP45]], float [[TMP35]], i32 2
-; SSE-NEXT: [[TMP47:%.*]] = insertelement <4 x float> [[TMP46]], float [[TMP39]], i32 3
+; SSE-NEXT: [[TMP40:%.*]] = insertelement <4 x float> poison, float [[TMP25]], i64 0
+; SSE-NEXT: [[TMP41:%.*]] = insertelement <4 x float> [[TMP40]], float [[TMP29]], i64 1
+; SSE-NEXT: [[TMP42:%.*]] = insertelement <4 x float> [[TMP41]], float [[TMP33]], i64 2
+; SSE-NEXT: [[TMP43:%.*]] = insertelement <4 x float> [[TMP42]], float [[TMP37]], i64 3
+; SSE-NEXT: [[TMP44:%.*]] = insertelement <4 x float> poison, float [[TMP27]], i64 0
+; SSE-NEXT: [[TMP45:%.*]] = insertelement <4 x float> [[TMP44]], float [[TMP31]], i64 1
+; SSE-NEXT: [[TMP46:%.*]] = insertelement <4 x float> [[TMP45]], float [[TMP35]], i64 2
+; SSE-NEXT: [[TMP47:%.*]] = insertelement <4 x float> [[TMP46]], float [[TMP39]], i64 3
; SSE-NEXT: [[TMP48:%.*]] = fdiv <4 x float> [[TMP43]], [[TMP47]]
; SSE-NEXT: store <4 x float> [[TMP48]], ptr [[TMP9]], align 4, !tbaa [[SHORT_TBAA0]]
; SSE-NEXT: ret void
@@ -577,24 +577,24 @@ define void @gather_load_div(ptr noalias nocapture %0, ptr noalias nocapture rea
; AVX-NEXT: [[TMP25:%.*]] = load <2 x float>, ptr [[TMP6]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[TMP26:%.*]] = load <2 x float>, ptr [[TMP4]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: [[TMP27:%.*]] = load <2 x float>, ptr [[TMP5]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX-NEXT: [[TMP28:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i32 0
+; AVX-NEXT: [[TMP28:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i64 0
; AVX-NEXT: [[TMP29:%.*]] = shufflevector <2 x float> [[TMP26]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP30:%.*]] = shufflevector <8 x float> [[TMP28]], <8 x float> [[TMP29]], <8 x i32> <i32 0, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP31:%.*]] = shufflevector <2 x float> [[TMP25]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP32:%.*]] = shufflevector <8 x float> [[TMP30]], <8 x float> [[TMP31]], <8 x i32> <i32 0, i32 1, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP33:%.*]] = shufflevector <2 x float> [[TMP27]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP34:%.*]] = shufflevector <8 x float> [[TMP32]], <8 x float> [[TMP33]], <8 x i32> <i32 0, i32 1, i32 2, i32 9, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP35:%.*]] = insertelement <8 x float> [[TMP34]], float [[TMP10]], i32 4
-; AVX-NEXT: [[TMP36:%.*]] = insertelement <8 x float> [[TMP35]], float [[TMP14]], i32 5
-; AVX-NEXT: [[TMP37:%.*]] = insertelement <8 x float> [[TMP36]], float [[TMP18]], i32 6
-; AVX-NEXT: [[TMP38:%.*]] = insertelement <8 x float> [[TMP37]], float [[TMP22]], i32 7
+; AVX-NEXT: [[TMP35:%.*]] = insertelement <8 x float> [[TMP34]], float [[TMP10]], i64 4
+; AVX-NEXT: [[TMP36:%.*]] = insertelement <8 x float> [[TMP35]], float [[TMP14]], i64 5
+; AVX-NEXT: [[TMP37:%.*]] = insertelement <8 x float> [[TMP36]], float [[TMP18]], i64 6
+; AVX-NEXT: [[TMP38:%.*]] = insertelement <8 x float> [[TMP37]], float [[TMP22]], i64 7
; AVX-NEXT: [[TMP39:%.*]] = shufflevector <2 x float> [[TMP25]], <2 x float> [[TMP27]], <8 x i32> <i32 1, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[TMP40:%.*]] = shufflevector <8 x float> [[TMP39]], <8 x float> [[TMP29]], <8 x i32> <i32 0, i32 1, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX-NEXT: [[TMP41:%.*]] = insertelement <8 x float> [[TMP40]], float [[TMP8]], i32 3
-; AVX-NEXT: [[TMP42:%.*]] = insertelement <8 x float> [[TMP41]], float [[TMP12]], i32 4
-; AVX-NEXT: [[TMP43:%.*]] = insertelement <8 x float> [[TMP42]], float [[TMP16]], i32 5
-; AVX-NEXT: [[TMP44:%.*]] = insertelement <8 x float> [[TMP43]], float [[TMP20]], i32 6
-; AVX-NEXT: [[TMP45:%.*]] = insertelement <8 x float> [[TMP44]], float [[TMP24]], i32 7
+; AVX-NEXT: [[TMP41:%.*]] = insertelement <8 x float> [[TMP40]], float [[TMP8]], i64 3
+; AVX-NEXT: [[TMP42:%.*]] = insertelement <8 x float> [[TMP41]], float [[TMP12]], i64 4
+; AVX-NEXT: [[TMP43:%.*]] = insertelement <8 x float> [[TMP42]], float [[TMP16]], i64 5
+; AVX-NEXT: [[TMP44:%.*]] = insertelement <8 x float> [[TMP43]], float [[TMP20]], i64 6
+; AVX-NEXT: [[TMP45:%.*]] = insertelement <8 x float> [[TMP44]], float [[TMP24]], i64 7
; AVX-NEXT: [[TMP46:%.*]] = fdiv <8 x float> [[TMP38]], [[TMP45]]
; AVX-NEXT: store <8 x float> [[TMP46]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX-NEXT: ret void
@@ -626,24 +626,24 @@ define void @gather_load_div(ptr noalias nocapture %0, ptr noalias nocapture rea
; AVX2-NEXT: [[TMP25:%.*]] = load <2 x float>, ptr [[TMP6]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX2-NEXT: [[TMP26:%.*]] = load <2 x float>, ptr [[TMP4]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX2-NEXT: [[TMP27:%.*]] = load <2 x float>, ptr [[TMP5]], align 4, !tbaa [[SHORT_TBAA0]]
-; AVX2-NEXT: [[TMP28:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i32 0
+; AVX2-NEXT: [[TMP28:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i64 0
; AVX2-NEXT: [[TMP29:%.*]] = shufflevector <2 x float> [[TMP26]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP30:%.*]] = shufflevector <8 x float> [[TMP28]], <8 x float> [[TMP29]], <8 x i32> <i32 0, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP31:%.*]] = shufflevector <2 x float> [[TMP25]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP32:%.*]] = shufflevector <8 x float> [[TMP30]], <8 x float> [[TMP31]], <8 x i32> <i32 0, i32 1, i32 8, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP33:%.*]] = shufflevector <2 x float> [[TMP27]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP34:%.*]] = shufflevector <8 x float> [[TMP32]], <8 x float> [[TMP33]], <8 x i32> <i32 0, i32 1, i32 2, i32 9, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX2-NEXT: [[TMP35:%.*]] = insertelement <8 x float> [[TMP34]], float [[TMP10]], i32 4
-; AVX2-NEXT: [[TMP36:%.*]] = insertelement <8 x float> [[TMP35]], float [[TMP14]], i32 5
-; AVX2-NEXT: [[TMP37:%.*]] = insertelement <8 x float> [[TMP36]], float [[TMP18]], i32 6
-; AVX2-NEXT: [[TMP38:%.*]] = insertelement <8 x float> [[TMP37]], float [[TMP22]], i32 7
+; AVX2-NEXT: [[TMP35:%.*]] = insertelement <8 x float> [[TMP34]], float [[TMP10]], i64 4
+; AVX2-NEXT: [[TMP36:%.*]] = insertelement <8 x float> [[TMP35]], float [[TMP14]], i64 5
+; AVX2-NEXT: [[TMP37:%.*]] = insertelement <8 x float> [[TMP36]], float [[TMP18]], i64 6
+; AVX2-NEXT: [[TMP38:%.*]] = insertelement <8 x float> [[TMP37]], float [[TMP22]], i64 7
; AVX2-NEXT: [[TMP39:%.*]] = shufflevector <2 x float> [[TMP25]], <2 x float> [[TMP27]], <8 x i32> <i32 1, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[TMP40:%.*]] = shufflevector <8 x float> [[TMP39]], <8 x float> [[TMP29]], <8 x i32> <i32 0, i32 1, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AVX2-NEXT: [[TMP41:%.*]] = insertelement <8 x float> [[TMP40]], float [[TMP8]], i32 3
-; AVX2-NEXT: [[TMP42:%.*]] = insertelement <8 x float> [[TMP41]], float [[TMP12]], i32 4
-; AVX2-NEXT: [[TMP43:%.*]] = insertelement <8 x float> [[TMP42]], float [[TMP16]], i32 5
-; AVX2-NEXT: [[TMP44:%.*]] = insertelement <8 x float> [[TMP43]], float [[TMP20]], i32 6
-; AVX2-NEXT: [[TMP45:%.*]] = insertelement <8 x float> [[TMP44]], float [[TMP24]], i32 7
+; AVX2-NEXT: [[TMP41:%.*]] = insertelement <8 x float> [[TMP40]], float [[TMP8]], i64 3
+; AVX2-NEXT: [[TMP42:%.*]] = insertelement <8 x float> [[TMP41]], float [[TMP12]], i64 4
+; AVX2-NEXT: [[TMP43:%.*]] = insertelement <8 x float> [[TMP42]], float [[TMP16]], i64 5
+; AVX2-NEXT: [[TMP44:%.*]] = insertelement <8 x float> [[TMP43]], float [[TMP20]], i64 6
+; AVX2-NEXT: [[TMP45:%.*]] = insertelement <8 x float> [[TMP44]], float [[TMP24]], i64 7
; AVX2-NEXT: [[TMP46:%.*]] = fdiv <8 x float> [[TMP38]], [[TMP45]]
; AVX2-NEXT: store <8 x float> [[TMP46]], ptr [[TMP0]], align 4, !tbaa [[SHORT_TBAA0]]
; AVX2-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr47642.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr47642.ll
index e69e0a1b2c7ee..eec95a0687aa7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr47642.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr47642.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-unknown-linux-gnu"
define <4 x i32> @foo(<4 x i32> %x, i32 %f) {
; CHECK-LABEL: @foo(
-; CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x i32> poison, i32 [[F:%.*]], i32 0
+; CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x i32> poison, i32 [[F:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[VECINIT]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[VECINIT51:%.*]] = add nsw <4 x i32> [[TMP2]], <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: ret <4 x i32> [[VECINIT51]]
@@ -23,7 +23,7 @@ define <4 x i32> @foo(<4 x i32> %x, i32 %f) {
define <4 x i32> @bar(<4 x i32> %x, i32 %f) {
; CHECK-LABEL: @bar(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[F:%.*]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[F:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP2]], <i32 2, i32 2, i32 2, i32 3>
; CHECK-NEXT: ret <4 x i32> [[TMP4]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/propagate-mmra.ll b/llvm/test/Transforms/SLPVectorizer/X86/propagate-mmra.ll
index a84c6ae6b0980..02f23936a8ffa 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/propagate-mmra.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/propagate-mmra.ll
@@ -5,7 +5,7 @@ define void @foo() {
; CHECK-LABEL: define void @foo() {
; CHECK-NEXT: [[_PREHEADER16_PREHEADER:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr null, align 4, !mmra [[META0:![0-9]+]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP2]], <float 1.000000e+00, float 0.000000e+00>
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x float> [[TMP3]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-non-scheduled-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-non-scheduled-node.ll
index e187b2ad2114e..d615e55d95345 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-non-scheduled-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-non-scheduled-node.ll
@@ -7,8 +7,8 @@ define i32 @test() {
; CHECK-NEXT: [[ARRAYIDX565:%.*]] = getelementptr i8, ptr poison, i64 56
; CHECK-NEXT: [[MUL474:%.*]] = fmul double 0.000000e+00, 0.000000e+00
; CHECK-NEXT: [[MUL475:%.*]] = fmul double 0.000000e+00, [[MUL474]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double 0.000000e+00, i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[MUL475]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double 0.000000e+00, i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[MUL475]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> zeroinitializer, [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP3]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-shared-inst.ll b/llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-shared-inst.ll
index 32ab8d6356ed4..1c70e17005b0b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-shared-inst.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/recalc-copyable-operand-deps-shared-inst.ll
@@ -8,23 +8,23 @@ define i32 @test(ptr %r, i32 %0) {
; CHECK-NEXT: [[SHR_I:%.*]] = lshr i32 6, [[TMP0]]
; CHECK-NEXT: [[SUB8_I:%.*]] = sub i32 0, [[SHR_I]]
; CHECK-NEXT: [[XOR_I:%.*]] = xor i32 [[SUB8_I]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 -1, i32 poison>, i32 [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 -1, i32 poison>, i32 [[TMP0]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> <i32 8, i32 1>, [[TMP1]]
; CHECK-NEXT: [[MUL47_NEG_I:%.*]] = shl i32 [[SUB8_I]], 1
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> <i32 1, i32 poison>
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[SUB8_I]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[SUB8_I]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> <i32 1, i32 poison>, <2 x i32> <i32 2, i32 1>
; CHECK-NEXT: [[TMP14:%.*]] = add <2 x i32> [[TMP8]], [[TMP12]]
; CHECK-NEXT: store i32 [[MUL47_NEG_I]], ptr [[R]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[XOR_I]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[XOR_I]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = lshr <2 x i32> [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i32> [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> [[TMP4]], <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i32> [[TMP14]], [[TMP10]]
; CHECK-NEXT: [[TMP19:%.*]] = shl <2 x i32> [[TMP11]], splat (i32 1)
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP19]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP19]], i64 0
; CHECK-NEXT: [[NOT263_I:%.*]] = add i32 [[TMP5]], -805306497
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP19]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP19]], i64 1
; CHECK-NEXT: [[SUB265_I:%.*]] = or i32 [[NOT263_I]], [[TMP6]]
; CHECK-NEXT: ret i32 [[SUB265_I]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduced-bswap-with-larger-reduced-type.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduced-bswap-with-larger-reduced-type.ll
index 04976d1183ff3..6c222861610ab 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduced-bswap-with-larger-reduced-type.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduced-bswap-with-larger-reduced-type.ll
@@ -5,7 +5,7 @@ define i80 @test(i8 %0, i80 %.sroa.0.7.insert.ext) {
; CHECK-LABEL: define i80 @test(
; CHECK-SAME: i8 [[TMP0:%.*]], i80 [[DOTSROA_0_7_INSERT_EXT:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> poison, i8 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> poison, i8 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP3]])
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduced-val-extracted-and-externally-used.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduced-val-extracted-and-externally-used.ll
index 6adfc18fddad7..d6b37914397f1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduced-val-extracted-and-externally-used.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduced-val-extracted-and-externally-used.ll
@@ -5,7 +5,7 @@ define void @test(i32 %arg) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[ARG:%.*]]) {
; CHECK-NEXT: [[BB:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i64 0
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 0, %[[BB]] ], [ [[TMP5:%.*]], %[[BB1]] ]
@@ -19,8 +19,8 @@ define void @test(i32 %arg) {
; CHECK-NEXT: [[TMP3:%.*]] = add <8 x i32> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i32> [[TMP0]], <i32 0, i32 1>
; CHECK-NEXT: [[TMP8]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <8 x i32> <i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
-; CHECK-NEXT: [[TMP5]] = extractelement <8 x i32> [[TMP8]], i32 0
-; CHECK-NEXT: [[TMP6]] = extractelement <8 x i32> [[TMP8]], i32 2
+; CHECK-NEXT: [[TMP5]] = extractelement <8 x i32> [[TMP8]], i64 0
+; CHECK-NEXT: [[TMP6]] = extractelement <8 x i32> [[TMP8]], i64 2
; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> [[TMP3]])
; CHECK-NEXT: [[ADD23:%.*]] = xor i32 [[TMP7]], [[ADD14]]
; CHECK-NEXT: [[XOR23:%.*]] = xor i32 [[ADD20]], [[ADD21]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement-cost.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement-cost.ll
index 3089a72ef5f79..6c363e2be6954 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement-cost.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement-cost.ll
@@ -5,7 +5,7 @@ define i32 @test(i32 %arg) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[ARG:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 [[ARG]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 [[ARG]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = srem <4 x i32> [[TMP0]], splat (i32 46337)
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <4 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> zeroinitializer, <4 x i32> zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement.ll
index b4e5d0968346d..511724b6b7d43 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-replace-extractelement.ll
@@ -7,11 +7,11 @@ define void @test() {
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 0 to i32
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
-; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ zeroinitializer, %[[BB]] ], [ [[TMP4:%.*]], %[[BB1]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ zeroinitializer, %[[BB]] ], [ [[TMP2:%.*]], %[[BB1]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1
; CHECK-NEXT: [[OP_RDX:%.*]] = mul i32 0, [[TMP1]]
; CHECK-NEXT: [[OP_RDX1:%.*]] = mul i32 [[OP_RDX]], [[TRUNC]]
-; CHECK-NEXT: [[TMP4]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[OP_RDX1]], i32 1
+; CHECK-NEXT: [[TMP2]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[OP_RDX1]], i64 1
; CHECK-NEXT: br label %[[BB1]]
;
bb:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-stored.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-stored.ll
index 0380648192354..dda1a2cf84bba 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-stored.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduced-value-stored.ll
@@ -5,9 +5,9 @@ define i16 @test(i32 %call5, i32 %add36) {
; CHECK-LABEL: define i16 @test(
; CHECK-SAME: i32 [[CALL5:%.*]], i32 [[ADD36:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 poison>, i32 [[CALL5]], i32 2
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> [[TMP0]], i32 [[ADD36]], i32 7
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 1, i32 poison, i32 0, i32 0, i32 0, i32 0>, i32 [[CALL5]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 poison>, i32 [[CALL5]], i64 2
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> [[TMP0]], i32 [[ADD36]], i64 7
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 1, i32 poison, i32 0, i32 0, i32 0, i32 0>, i32 [[CALL5]], i64 3
; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <8 x i32> [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i1> [[TMP3]], <8 x i1> [[TMP4]], <8 x i32> <i32 0, i32 9, i32 2, i32 3, i32 4, i32 13, i32 14, i32 7>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-across-different-bb.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-across-different-bb.ll
index 27eaecdc43a18..96b223dd2803e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction-across-different-bb.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-across-different-bb.ll
@@ -24,20 +24,20 @@ define void @test(ptr %j, ptr %b) {
; CHECK-NEXT: [[BOUND050:%.*]] = icmp ugt ptr [[SCEVGEP5]], @f
; CHECK-NEXT: [[BOUND151:%.*]] = icmp ult ptr [[B]], getelementptr inbounds nuw (i8, ptr @f, i16 1)
; CHECK-NEXT: [[FOUND_CONFLICT52:%.*]] = and i1 [[BOUND050]], [[BOUND151]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x ptr> <ptr poison, ptr getelementptr inbounds nuw (i8, ptr @a, i64 1), ptr getelementptr inbounds nuw (i8, ptr @f, i64 1), ptr poison>, ptr [[SCEVGEP5]], i32 3
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x ptr> <ptr poison, ptr @a, ptr @f, ptr poison>, ptr [[B]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x ptr> <ptr poison, ptr getelementptr inbounds nuw (i8, ptr @a, i64 1), ptr getelementptr inbounds nuw (i8, ptr @f, i64 1), ptr poison>, ptr [[SCEVGEP5]], i64 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x ptr> <ptr poison, ptr @a, ptr @f, ptr poison>, ptr [[B]], i64 3
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr @c, align 1
; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr @e, align 1
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[TMP2]], i16 1
; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[TMP3]], i16 4
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP2]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x ptr> [[TMP4]], <4 x ptr> poison, <4 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x ptr> [[TMP0]], ptr [[SCEVGEP4]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x ptr> [[TMP0]], ptr [[SCEVGEP4]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = icmp ult <4 x ptr> [[TMP5]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x ptr> [[TMP1]], ptr [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x ptr> poison, ptr [[SCEVGEP]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x ptr> [[TMP1]], ptr [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x ptr> poison, ptr [[SCEVGEP]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x ptr> [[TMP9]], <4 x ptr> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP11:%.*]] = icmp ult <4 x ptr> [[TMP8]], [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = and <4 x i1> [[TMP7]], [[TMP11]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll
index 789ac9ef23b31..72ac916e114a1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll
@@ -20,10 +20,10 @@ define i1 @test(i32 %x) {
define i1 @test1(i32 %x, i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: define i1 @test1(
; CHECK-SAME: i32 [[X:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[B]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[C]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[B]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[C]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[TMP4]], splat (i32 1)
; CHECK-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[D]], 1
; CHECK-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP5]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-copyable-reused-scalars.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-copyable-reused-scalars.ll
index 574897e0467d8..1c5afe46837a4 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction-copyable-reused-scalars.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-copyable-reused-scalars.ll
@@ -34,13 +34,13 @@ define fastcc i32 @func_nno0tw_28(ptr %v1) {
; CHECK-NEXT: [[ADD2844:%.*]] = add i32 -16457, [[ADD2842]]
; CHECK-NEXT: [[REASS_SUB:%.*]] = sub i32 0, [[ADD2844]]
; CHECK-NEXT: [[REM2924:%.*]] = urem i32 [[ADD2923]], 46337
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 0, i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 0, i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = shl <4 x i32> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr [[ALIASCHECK_50_0_SROA_0]], align 16
; CHECK-NEXT: [[TMP6:%.*]] = shl <4 x i32> [[TMP3]], splat (i32 1)
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 389369760, i32 1339756373, i32 -588265445, i32 45324178, i32 79842678, i32 8113750, i32 64148112, i32 0, i32 poison, i32 poison, i32 poison, i32 poison>, i32 0, i32 12
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i32> [[TMP7]], i32 [[REM2924]], i32 15
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 389369760, i32 1339756373, i32 -588265445, i32 45324178, i32 79842678, i32 8113750, i32 64148112, i32 0, i32 poison, i32 poison, i32 poison, i32 poison>, i32 0, i64 12
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i32> [[TMP7]], i32 [[REM2924]], i64 15
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
index 5e0dea82bddac..c10caf1f9d5c3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
@@ -155,12 +155,12 @@ define i1 @logical_and_icmp_diff_const(<4 x i32> %x) {
define i1 @mixed_logical_icmp(<4 x i32> %x) {
; CHECK-LABEL: @mixed_logical_icmp(
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i1> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i1> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i1> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i1> [[TMP1]], i64 1
; CHECK-NEXT: [[S1:%.*]] = select i1 [[TMP2]], i1 [[TMP3]], i1 false
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP1]], i64 2
; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 true, i1 [[TMP4]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP1]], i64 3
; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[TMP5]], i1 false
; CHECK-NEXT: ret i1 [[S3]]
;
@@ -184,8 +184,8 @@ define i1 @logical_and_icmp_subvec(<4 x i32> %x) {
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[X2]], 0
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP2]], i64 1
; CHECK-NEXT: [[S1:%.*]] = select i1 [[TMP3]], i1 [[TMP4]], i1 false
; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false
; CHECK-NEXT: ret i1 [[S2]]
@@ -241,7 +241,7 @@ define i1 @logical_and_icmp_clamp(<4 x i32> %x) {
define i1 @logical_and_icmp_clamp_extra_use_cmp(<4 x i32> %x) {
; CHECK-LABEL: @logical_and_icmp_clamp_extra_use_cmp(
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i32> [[X:%.*]], splat (i32 42)
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP1]], i64 2
; CHECK-NEXT: call void @use1(i1 [[TMP5]])
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[X]], splat (i32 17)
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i1> [[TMP3]], <4 x i1> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -278,15 +278,15 @@ define i1 @logical_and_icmp_clamp_extra_use_select(<4 x i32> %x) {
; CHECK-LABEL: @logical_and_icmp_clamp_extra_use_select(
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <4 x i32> [[X:%.*]], splat (i32 42)
; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[X]], splat (i32 17)
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i1> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i1> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP1]], i64 1
; CHECK-NEXT: [[S1:%.*]] = select i1 [[TMP3]], i1 [[TMP4]], i1 false
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i1> [[TMP1]], i64 2
; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[TMP5]], i1 false
; CHECK-NEXT: call void @use1(i1 [[S2]])
; CHECK-NEXT: [[TMP6:%.*]] = freeze <4 x i1> [[TMP2]]
; CHECK-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP6]])
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP1]], i64 3
; CHECK-NEXT: [[OP_RDX:%.*]] = select i1 [[TMP7]], i1 [[TMP8]], i1 false
; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[S2]], i1 [[OP_RDX]], i1 false
; CHECK-NEXT: ret i1 [[OP_RDX1]]
@@ -353,16 +353,16 @@ define i1 @logical_and_icmp_clamp_v8i32(<8 x i32> %x, <8 x i32> %y) {
define i1 @logical_and_icmp_clamp_partial(<4 x i32> %x) {
; CHECK-LABEL: @logical_and_icmp_clamp_partial(
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 2
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 2
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <2 x i32> [[TMP2]], splat (i32 42)
; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[TMP1]], 42
; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt <4 x i32> [[X]], splat (i32 17)
; CHECK-NEXT: [[TMP5:%.*]] = freeze <4 x i1> [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP3]], i64 0
; CHECK-NEXT: [[OP_RDX:%.*]] = select i1 [[TMP6]], i1 [[TMP7]], i1 false
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP3]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = freeze i1 [[TMP8]]
; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[TMP9]], i1 [[C2]], i1 false
; CHECK-NEXT: [[TMP10:%.*]] = freeze i1 [[OP_RDX]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-same-vals.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-same-vals.ll
index 3daebe50d724f..d749e89dc1f95 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction-same-vals.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-same-vals.ll
@@ -10,7 +10,7 @@ define i64 @test() {
; CHECK: bb3:
; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ 0, [[BB2:%.*]] ], [ 0, [[BB1:%.*]] ]
; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ 0, [[BB2]] ], [ 0, [[BB1]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[TMP0]], <8 x i32> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> [[TMP1]])
; CHECK-NEXT: [[OP_RDX:%.*]] = mul i32 [[TMP2]], [[TMP4]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll
index 7d47ad5502be3..f23d2b5554052 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-shl1-add-merge.ll
@@ -13,13 +13,13 @@ define i32 @reduce_add_sub_shl(ptr %p, ptr %q, ptr %out) {
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> [[TMP7]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP9:%.*]] = add <8 x i32> [[TMP0]], [[TMP8]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i32> [[TMP9]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i32> [[TMP9]], i64 0
; CHECK-NEXT: store volatile i32 [[TMP3]], ptr [[OUT]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP9]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP9]], i64 1
; CHECK-NEXT: store volatile i32 [[TMP4]], ptr [[OUT]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP9]], i32 2
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP9]], i64 2
; CHECK-NEXT: store volatile i32 [[TMP5]], ptr [[OUT]], align 4
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i32> [[TMP9]], i32 3
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i32> [[TMP9]], i64 3
; CHECK-NEXT: store volatile i32 [[TMP6]], ptr [[OUT]], align 4
; CHECK-NEXT: [[OP_RDX3:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP9]])
; CHECK-NEXT: ret i32 [[OP_RDX3]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-with-removed-extracts.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-with-removed-extracts.ll
index a63c1a98605c5..2fb0061c8c518 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction-with-removed-extracts.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-with-removed-extracts.ll
@@ -5,7 +5,7 @@ define i32 @test(i32 %arg) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[BB:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 [[ARG]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 [[ARG]], i64 1
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 0, %[[BB]] ], [ [[OP_RDX5:%.*]], %[[BB1]] ]
@@ -15,7 +15,7 @@ define i32 @test(i32 %arg) {
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 3>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP10:%.*]] = mul <4 x i32> zeroinitializer, [[TMP8]]
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP10]], i32 3
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP10]], i64 3
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <8 x i32> [[TMP7]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[RDX_OP:%.*]] = mul <4 x i32> [[TMP11]], [[TMP10]]
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[RDX_OP]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
index 2e7829a22613e..0836c0d63ed8e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
@@ -23,8 +23,8 @@ define i32 @reduce(ptr nocapture %A, i32 %n, i32 %m) {
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i32 [[MUL]]
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x double> [[TMP0]], splat (double 7.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i64 1
; CHECK-NEXT: [[ADD5:%.*]] = fadd double [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[ADD6]] = fadd double [[SUM_014]], [[ADD5]]
; CHECK-NEXT: [[INC]] = add nsw i32 [[I_015]], 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
index a9599eae5882a..03cdc54eb779f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
@@ -15,8 +15,8 @@ define double @foo(ptr nocapture %D) {
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr [[TMP3]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x double> [[TMP5]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP6]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = fadd double [[TMP7]], [[TMP8]]
; CHECK-NEXT: [[TMP10]] = fadd double [[SUM_01]], [[TMP9]]
; CHECK-NEXT: [[TMP11]] = add nsw i32 [[I_02]], 1
@@ -89,21 +89,21 @@ define i1 @fcmp_lt_gt(double %a, double %b, double %c) {
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[A:%.*]], 2.000000e+00
; CHECK-NEXT: [[ADD:%.*]] = fsub double [[C:%.*]], [[B]]
; CHECK-NEXT: [[SUB:%.*]] = fsub double [[FNEG]], [[C]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[SUB]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[ADD]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[MUL]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[SUB]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[ADD]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[MUL]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fdiv <2 x double> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP4]], i64 1
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[TMP8]], f0x3EB0C6F7A0B5ED8D
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
; CHECK-NEXT: [[CMP4:%.*]] = fcmp olt double [[TMP9]], f0x3EB0C6F7A0B5ED8D
; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[CMP]], [[CMP4]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[CLEANUP:%.*]], label [[LOR_LHS_FALSE:%.*]]
; CHECK: lor.lhs.false:
; CHECK-NEXT: [[TMP7:%.*]] = fcmp ule <2 x double> [[TMP4]], splat (double 1.000000e+00)
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP7]], i64 1
; CHECK-NEXT: [[NOT_OR_COND9:%.*]] = or i1 [[TMP11]], [[TMP12]]
; CHECK-NEXT: ret i1 [[NOT_OR_COND9]]
; CHECK: cleanup:
@@ -137,14 +137,14 @@ define i1 @fcmp_lt(double %a, double %b, double %c) {
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[A:%.*]], 2.000000e+00
; CHECK-NEXT: [[ADD:%.*]] = fsub double [[C:%.*]], [[B]]
; CHECK-NEXT: [[SUB:%.*]] = fsub double [[FNEG]], [[C]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[SUB]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[ADD]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[MUL]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[SUB]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[ADD]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[MUL]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = fdiv <2 x double> [[TMP2]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = fcmp uge <2 x double> [[TMP5]], splat (double f0x3EB0C6F7A0B5ED8D)
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP6]], i64 1
; CHECK-NEXT: [[NOT_OR_COND:%.*]] = or i1 [[TMP10]], [[TMP11]]
; CHECK-NEXT: ret i1 [[NOT_OR_COND]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll b/llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
index cc7638431e03b..67054d202d5a2 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
@@ -10,7 +10,7 @@ declare void @llvm.masked.scatter.v2f64.v2p0(<2 x double>, <2 x ptr>, i32 immarg
define void @test(ptr nocapture readonly %arg, ptr nocapture readonly %arg1, ptr nocapture %arg2) {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr [[ARG:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x ptr> poison, ptr [[ARG:%.*]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x ptr> [[TMP0]], <8 x ptr> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds double, <8 x ptr> [[TMP1]], <8 x i64> <i64 1, i64 3, i64 5, i64 7, i64 9, i64 11, i64 13, i64 15>
; CHECK-NEXT: [[GEP2_0:%.*]] = getelementptr inbounds double, ptr [[ARG1:%.*]], i64 16
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/remark-partial-loads-vectorize.ll b/llvm/test/Transforms/SLPVectorizer/X86/remark-partial-loads-vectorize.ll
index c258c7d54df82..1b4cdb6353fa8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/remark-partial-loads-vectorize.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/remark-partial-loads-vectorize.ll
@@ -16,9 +16,9 @@ define <4 x float> @test(ptr %x, float %v, float %a) {
; CHECK-LABEL: define <4 x float> @test(
; CHECK-SAME: ptr [[X:%.*]], float [[V:%.*]], float [[A:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[X]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> poison, float [[A]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> poison, float [[A]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> poison, <4 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> poison, float [[V]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> poison, float [[V]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> poison, <4 x i32> <i32 0, i32 0, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/remark_gather-load-redux-cost.ll b/llvm/test/Transforms/SLPVectorizer/X86/remark_gather-load-redux-cost.ll
index 171298ad55d61..2e0f0ea67a0de 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/remark_gather-load-redux-cost.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/remark_gather-load-redux-cost.ll
@@ -8,7 +8,7 @@ define i32 @test(ptr noalias %p, ptr noalias %addr) {
; CHECK-NEXT: [[OFF0_1:%.*]] = getelementptr inbounds i32, ptr [[ADDR:%.*]], i32 1
; CHECK-NEXT: [[TMP0:%.*]] = call <15 x i32> @llvm.masked.load.v15i32.p0(ptr align 8 [[OFF0_1]], <15 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <15 x i32> poison)
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <15 x i32> [[TMP0]], <15 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x ptr> poison, ptr [[P:%.*]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x ptr> poison, ptr [[P:%.*]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x ptr> [[TMP4]], <8 x ptr> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, <8 x ptr> [[TMP5]], <8 x i32> [[TMP3]]
; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> align 4 [[TMP6]], <8 x i1> splat (i1 true), <8 x i32> poison)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll b/llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll
index 82fcde5319aa0..01016e329db8b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll
@@ -18,10 +18,10 @@ define i32 @foo(ptr nocapture readonly %diff) #0 {
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = add nsw <2 x i32> [[TMP3]], [[TMP2]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP4]], i64 0
; CHECK-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP5]], [[A_088]]
; CHECK-NEXT: store <2 x i32> [[TMP4]], ptr [[ARRAYIDX6]], align 16
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP4]], i64 1
; CHECK-NEXT: [[ADD24]] = add nsw i32 [[ADD10]], [[TMP6]]
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reorder-possible-strided-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/reorder-possible-strided-node.ll
index 723537befb9de..981b7b01162e3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reorder-possible-strided-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reorder-possible-strided-node.ll
@@ -13,8 +13,8 @@ define void @test() {
; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr align 4 null, <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> poison)
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <2 x i32> <i32 0, i32 7>
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[ARRAYIDX22]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i32 2
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP9]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i64 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP9]], i64 3
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x i32> [[TMP10]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP12]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> [[TMP1]], [[TMP7]]
@@ -74,8 +74,8 @@ define void @test1() {
; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr align 4 null, <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> poison)
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <2 x i32> <i32 0, i32 7>
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[ARRAYIDX22]], align 4
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i32 2
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP9]], i32 3
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i64 2
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP9]], i64 3
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[TMP10]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP12]], <4 x i32> [[TMP14]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> [[TMP1]], [[TMP7]]
@@ -137,8 +137,8 @@ define void @test_div() {
; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr align 4 null, <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> poison)
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <2 x i32> <i32 0, i32 7>
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[ARRAYIDX22]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i32 2
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP4]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i64 2
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP4]], i64 3
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP11]], <4 x i32> [[TMP12]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP9:%.*]] = mul <4 x i32> [[TMP1]], [[TMP7]]
@@ -198,8 +198,8 @@ define void @test_rem() {
; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr align 4 null, <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> poison)
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <2 x i32> <i32 0, i32 7>
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[ARRAYIDX22]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i32 2
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP4]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i64 2
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP4]], i64 3
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP11]], <4 x i32> [[TMP12]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP9:%.*]] = mul <4 x i32> [[TMP1]], [[TMP7]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-subvector.ll b/llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-subvector.ll
index 3f6ec8ccad4ee..6b4bcd833b1ad 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-subvector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reorder-reused-subvector.ll
@@ -5,9 +5,9 @@ define void @test(i32 %j.6, i32 %m.4, i8 %v.5, ptr %a, i1 %tobool14.not) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[J_6:%.*]], i32 [[M_4:%.*]], i8 [[V_5:%.*]], ptr [[A:%.*]], i1 [[TOBOOL14_NOT:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> <i8 0, i8 poison>, i8 [[V_5]], i32 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 1, i32 poison>, i32 [[M_4]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[J_6]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> <i8 0, i8 poison>, i8 [[V_5]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 1, i32 poison>, i32 [[M_4]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[J_6]], i64 3
; CHECK-NEXT: br label %[[N:.*]]
; CHECK: [[ENTRY_O_CRIT_EDGE:.*]]:
; CHECK-NEXT: br label %[[O:.*]]
@@ -24,20 +24,20 @@ define void @test(i32 %j.6, i32 %m.4, i8 %v.5, ptr %a, i1 %tobool14.not) {
; CHECK: [[P]]:
; CHECK-NEXT: [[TMP7:%.*]] = phi <2 x i8> [ <i8 1, i8 0>, %[[IF_END18]] ], [ [[TMP0]], %[[N]] ]
; CHECK-NEXT: [[TMP8:%.*]] = phi <8 x i32> [ [[TMP35:%.*]], %[[IF_END18]] ], [ [[TMP6]], %[[N]] ]
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i32> [[TMP8]], i32 7
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i32> [[TMP8]], i64 7
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <2 x i32> <i32 5, i32 6>
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <2 x i32> [[TMP10]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP11]], i32 0
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP11]], i64 0
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP12]], i32 [[TMP9]], i32 0
-; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i8> [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i8> [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i8> [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i8> [[TMP7]], i64 1
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <4 x i32> <i32 poison, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <8 x i32> <i32 1, i32 0, i32 poison, i32 poison, i32 undef, i32 undef, i32 undef, i32 undef>, <8 x i32> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 9, i32 poison>
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x i32> [[TMP17]], i32 [[SPEC_SELECT]], i32 3
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i32> [[TMP8]], i32 2
-; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP8]], i32 4
-; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i1> [[TMP11]], i32 1
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x i32> [[TMP17]], i32 [[SPEC_SELECT]], i64 3
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <8 x i32> [[TMP8]], i64 2
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <8 x i32> [[TMP8]], i64 4
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <2 x i1> [[TMP11]], i64 1
; CHECK-NEXT: br i1 [[TMP21]], label %[[O_SINK_SPLIT]], label %[[Q:.*]]
; CHECK: [[O_SINK_SPLIT]]:
; CHECK-NEXT: [[SPEC_SELECT_SINK:%.*]] = phi i32 [ [[J_0]], %[[N]] ], [ [[SPEC_SELECT]], %[[P]] ]
@@ -52,8 +52,8 @@ define void @test(i32 %j.6, i32 %m.4, i8 %v.5, ptr %a, i1 %tobool14.not) {
; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[J_6]]
; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], [[I_3_PH]]
; CHECK-NEXT: [[SUB13:%.*]] = sub i32 0, [[DIV]]
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> poison, i32 [[SUB]], i32 0
-; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[SUB13]], i32 1
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> poison, i32 [[SUB]], i64 0
+; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[SUB13]], i64 1
; CHECK-NEXT: [[TMP26:%.*]] = shufflevector <4 x i32> [[TMP25]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <4 x i32> [[TMP26]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP34:%.*]] = shufflevector <4 x i32> [[TMP23]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -68,7 +68,7 @@ define void @test(i32 %j.6, i32 %m.4, i8 %v.5, ptr %a, i1 %tobool14.not) {
; CHECK-NEXT: [[TMP32:%.*]] = shufflevector <2 x i32> [[TMP31]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[CONV17:%.*]] = sext i8 [[V_44]] to i32
; CHECK-NEXT: [[REM:%.*]] = mul i32 [[U_4]], [[CONV17]]
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 poison, i32 0, i32 0>, i32 [[REM]], i32 5
+; CHECK-NEXT: [[TMP33:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 poison, i32 0, i32 0>, i32 [[REM]], i64 5
; CHECK-NEXT: [[TMP38:%.*]] = shufflevector <4 x i32> [[TMP32]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP39:%.*]] = shufflevector <2 x i32> [[TMP31]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP40:%.*]] = shufflevector <8 x i32> [[TMP33]], <8 x i32> [[TMP39]], <8 x i32> <i32 8, i32 9, i32 8, i32 9, i32 4, i32 5, i32 6, i32 7>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reorder_diamond_match.ll b/llvm/test/Transforms/SLPVectorizer/X86/reorder_diamond_match.ll
index fd16a5200b868..e12c8623932ef 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reorder_diamond_match.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reorder_diamond_match.ll
@@ -32,10 +32,10 @@ define void @test() {
; CHECK-NEXT: [[TMP27:%.*]] = add nsw i32 [[TMP24]], [[TMP18]]
; CHECK-NEXT: [[TMP28:%.*]] = sub nsw i32 [[TMP18]], [[TMP24]]
; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [4 x [4 x i32]], ptr undef, i64 0, i64 1, i64 0
-; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 0>, i32 [[TMP25]], i32 0
-; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i32> [[TMP30]], i32 [[TMP26]], i32 1
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 poison>, i32 [[TMP27]], i32 2
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <4 x i32> [[TMP32]], i32 [[TMP28]], i32 3
+; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 0, i32 0>, i32 [[TMP25]], i64 0
+; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i32> [[TMP30]], i32 [[TMP26]], i64 1
+; CHECK-NEXT: [[TMP32:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 poison>, i32 [[TMP27]], i64 2
+; CHECK-NEXT: [[TMP33:%.*]] = insertelement <4 x i32> [[TMP32]], i32 [[TMP28]], i64 3
; CHECK-NEXT: [[TMP34:%.*]] = sub nsw <4 x i32> [[TMP31]], [[TMP33]]
; CHECK-NEXT: store <4 x i32> [[TMP34]], ptr [[TMP29]], align 16
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll b/llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
index f0e734d8c5aef..13e7bee0cdd5d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
@@ -17,10 +17,10 @@ define void @foo (ptr %A, ptr %B, ptr %Result) {
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_COMPLEX]], ptr [[B]], i64 [[TMP1]], i32 1
; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[TMP6]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = load <2 x float>, ptr [[TMP3]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x float> poison, float [[TMP5]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x float> poison, float [[TMP5]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x float> [[TMP9]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP11:%.*]] = fmul <2 x float> [[TMP8]], [[TMP10]]
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x float> poison, float [[TMP7]], i32 0
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x float> poison, float [[TMP7]], i64 0
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x float> [[TMP12]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP14:%.*]] = fmul <2 x float> [[TMP8]], [[TMP13]]
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <2 x float> [[TMP14]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll b/llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll
index 4820d2a21424a..04fa2a70fd64c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll
@@ -53,19 +53,19 @@ define void @non_consecutive_external_users(ptr %A, ptr %ptr) {
; CHECK-LABEL: @non_consecutive_external_users(
; CHECK-NEXT: bb1:
; CHECK-NEXT: [[LD:%.*]] = load double, ptr undef, align 8
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x double> poison, double [[LD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x double> poison, double [[LD]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x double> [[TMP0]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x double> [[SHUFFLE]], <double 1.100000e+00, double 2.200000e+00, double 3.300000e+00, double 4.400000e+00>
; CHECK-NEXT: [[TMP2:%.*]] = fadd <4 x double> [[TMP1]], <double 1.100000e+00, double 2.200000e+00, double 3.300000e+00, double 4.400000e+00>
; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x double> [[TMP2]], <double 1.100000e+00, double 2.200000e+00, double 3.300000e+00, double 4.400000e+00>
; CHECK-NEXT: [[PTRA4:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i64 3
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP3]], i32 3
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP3]], i64 3
; CHECK-NEXT: store double [[TMP4]], ptr [[A]], align 8
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP3]], i32 2
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP3]], i64 2
; CHECK-NEXT: store double [[TMP5]], ptr [[A]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP3]], i64 1
; CHECK-NEXT: store double [[TMP6]], ptr [[PTRA4]], align 8
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP3]], i64 0
; CHECK-NEXT: store double [[TMP7]], ptr [[PTRA4]], align 8
; CHECK-NEXT: br label [[SEED_LOOP:%.*]]
; CHECK: seed_loop:
@@ -112,7 +112,7 @@ define void @addsub_and_external_users(ptr %A, ptr %ptr) {
; CHECK-LABEL: @addsub_and_external_users(
; CHECK-NEXT: bb1:
; CHECK-NEXT: [[LD:%.*]] = load double, ptr undef, align 8
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[LD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[LD]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[TMP1]], <double 1.200000e+00, double -1.100000e+00>
; CHECK-NEXT: [[TMP3:%.*]] = fdiv <2 x double> [[TMP2]], <double 2.200000e+00, double 2.100000e+00>
@@ -121,8 +121,8 @@ define void @addsub_and_external_users(ptr %A, ptr %ptr) {
; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb2:
; CHECK-NEXT: [[TMP7:%.*]] = fadd <2 x double> [[SHUFFLE1]], <double 4.200000e+00, double 4.100000e+00>
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i64 1
; CHECK-NEXT: [[SEED:%.*]] = fcmp ogt double [[TMP9]], [[TMP8]]
; CHECK-NEXT: ret void
;
@@ -156,7 +156,7 @@ define void @subadd_and_external_users(ptr %A, ptr %ptr) {
; CHECK-LABEL: @subadd_and_external_users(
; CHECK-NEXT: bb1:
; CHECK-NEXT: [[LD:%.*]] = load double, ptr undef, align 8
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[LD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[LD]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fsub <2 x double> [[TMP1]], <double 1.200000e+00, double -1.100000e+00>
; CHECK-NEXT: [[TMP4:%.*]] = fdiv <2 x double> [[TMP3]], <double 2.200000e+00, double 2.100000e+00>
@@ -165,8 +165,8 @@ define void @subadd_and_external_users(ptr %A, ptr %ptr) {
; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb2:
; CHECK-NEXT: [[TMP7:%.*]] = fadd <2 x double> [[TMP5]], <double 4.200000e+00, double 4.100000e+00>
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP7]], i64 1
; CHECK-NEXT: [[SEED:%.*]] = fcmp ogt double [[TMP9]], [[TMP8]]
; CHECK-NEXT: ret void
;
@@ -199,7 +199,7 @@ define void @alt_but_not_addsub_and_external_users(ptr %A, ptr %ptr) {
; CHECK-LABEL: @alt_but_not_addsub_and_external_users(
; CHECK-NEXT: bb1:
; CHECK-NEXT: [[LD:%.*]] = load double, ptr undef, align 8
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x double> poison, double [[LD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x double> poison, double [[LD]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x double> [[TMP0]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fadd <4 x double> [[SHUFFLE]], <double -1.400000e+00, double 1.300000e+00, double 1.200000e+00, double -1.100000e+00>
; CHECK-NEXT: [[TMP4:%.*]] = fdiv <4 x double> [[TMP3]], <double 2.400000e+00, double 2.300000e+00, double 2.200000e+00, double 2.100000e+00>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/replaced-external-in-reduction.ll b/llvm/test/Transforms/SLPVectorizer/X86/replaced-external-in-reduction.ll
index 22734f56813bc..37bf890866f2e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/replaced-external-in-reduction.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/replaced-external-in-reduction.ll
@@ -5,14 +5,14 @@ define void @test(i32 %0, ptr %p) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[TMP0:%.*]], ptr [[P:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 0, i32 poison, i32 1, i32 1, i32 1, i32 poison>, i32 [[TMP0]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 0, i32 poison, i32 1, i32 1, i32 1, i32 poison>, i32 [[TMP0]], i64 3
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 3>
; CHECK-NEXT: [[TMP8:%.*]] = xor <8 x i32> [[TMP2]], <i32 1, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0>
-; CHECK-NEXT: [[OP_RDX:%.*]] = extractelement <8 x i32> [[TMP8]], i32 3
+; CHECK-NEXT: [[OP_RDX:%.*]] = extractelement <8 x i32> [[TMP8]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[PH:%.*]]
; CHECK: ph:
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0>, i32 [[TMP0]], i32 4
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0>, i32 [[TMP0]], i64 4
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: [[TMP9:%.*]] = phi <8 x i32> [ [[TMP8]], [[ENTRY:%.*]] ], [ [[TMP6]], [[PH]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/resched.ll b/llvm/test/Transforms/SLPVectorizer/X86/resched.ll
index 636234b448072..35e6b797245d6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/resched.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/resched.ll
@@ -10,8 +10,8 @@ define void @test(i1 %arg, i32 %a, ptr %p) {
; CHECK: if.then22.i:
; CHECK-NEXT: [[SUB_I:%.*]] = add nsw i32 [[A:%.*]], -1
; CHECK-NEXT: [[CONV31_I:%.*]] = and i32 [[A]], [[SUB_I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i32> poison, i32 [[SUB_I]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i32> [[TMP0]], i32 [[CONV31_I]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <16 x i32> poison, i32 [[SUB_I]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i32> [[TMP0]], i32 [[CONV31_I]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[TMP1]], <16 x i32> poison, <16 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = lshr <16 x i32> [[TMP2]], <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP4:%.*]] = trunc <16 x i32> [[TMP3]] to <16 x i8>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reschedule-only-scheduled.ll b/llvm/test/Transforms/SLPVectorizer/X86/reschedule-only-scheduled.ll
index ce308692fbb2e..863890322a902 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reschedule-only-scheduled.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reschedule-only-scheduled.ll
@@ -6,8 +6,8 @@ define i16 @test() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[CALL99_I:%.*]] = call i32 @llvm.bswap.i32(i32 0)
; CHECK-NEXT: [[CALL7_I45:%.*]] = tail call i32 null(i32 0)
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 0>, i32 [[CALL99_I]], i32 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[CALL7_I45]], i32 2
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 0>, i32 [[CALL99_I]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[CALL7_I45]], i64 2
; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <24 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <24 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/resized-bv-values-non-power-of2-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/resized-bv-values-non-power-of2-node.ll
index a0329c64b8cab..060a662659f65 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/resized-bv-values-non-power-of2-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/resized-bv-values-non-power-of2-node.ll
@@ -4,16 +4,16 @@
define <16 x half> @test(i32 %0, float %1, i32 %2) {
; CHECK-LABEL: define <16 x half> @test(
; CHECK-SAME: i32 [[TMP0:%.*]], float [[TMP1:%.*]], i32 [[TMP2:%.*]]) {
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison, float 0.000000e+00, float 0.000000e+00>, float [[TMP1]], i32 13
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison, float 0.000000e+00, float 0.000000e+00>, float [[TMP1]], i64 13
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x float> [[TMP4]] to <16 x i32>
; CHECK-NEXT: [[TMP6:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> zeroinitializer, <2 x float> zeroinitializer, <2 x float> zeroinitializer)
; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP2]], 0
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP0]], [[TMP0]]
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP6]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP6]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = fcmp ogt float [[TMP9]], 0.000000e+00
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP0]], 0
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x i32> [[TMP5]], i32 10
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x i32> [[TMP5]], i64 10
; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0
; CHECK-NEXT: [[TMP13:%.*]] = bitcast float 0.000000e+00 to i32
; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0
@@ -22,7 +22,7 @@ define <16 x half> @test(i32 %0, float %1, i32 %2) {
; CHECK-NEXT: [[TMP19:%.*]] = icmp ult i32 0, 0
; CHECK-NEXT: [[TMP20:%.*]] = icmp ult i32 0, 0
; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i32 0, 0
-; CHECK-NEXT: [[TMP22:%.*]] = extractelement <16 x i32> [[TMP5]], i32 4
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <16 x i32> [[TMP5]], i64 4
; CHECK-NEXT: [[TMP31:%.*]] = icmp eq i32 [[TMP22]], 0
; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i32 [[TMP0]], [[TMP0]]
; CHECK-NEXT: [[TMP23:%.*]] = bitcast float 0.000000e+00 to i32
@@ -32,8 +32,8 @@ define <16 x half> @test(i32 %0, float %1, i32 %2) {
; CHECK-NEXT: [[TMP29:%.*]] = sitofp <16 x i32> [[TMP28]] to <16 x float>
; CHECK-NEXT: [[TMP30:%.*]] = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> [[TMP29]], <16 x float> zeroinitializer, <16 x float> zeroinitializer)
; CHECK-NEXT: [[TMP41:%.*]] = fadd <16 x float> [[TMP30]], zeroinitializer
-; CHECK-NEXT: [[TMP42:%.*]] = insertelement <16 x i1> <i1 poison, i1 false, i1 poison, i1 poison, i1 false, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 poison, i1 false, i1 false, i1 poison>, i1 false, i32 0
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <16 x i1> [[TMP42]], i1 false, i32 5
+; CHECK-NEXT: [[TMP42:%.*]] = insertelement <16 x i1> <i1 poison, i1 false, i1 poison, i1 poison, i1 false, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 poison, i1 false, i1 false, i1 poison>, i1 false, i64 0
+; CHECK-NEXT: [[TMP33:%.*]] = insertelement <16 x i1> [[TMP42]], i1 false, i64 5
; CHECK-NEXT: [[TMP34:%.*]] = shufflevector <16 x i1> [[TMP33]], <16 x i1> poison, <16 x i32> <i32 0, i32 1, i32 0, i32 0, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 0, i32 13, i32 14, i32 0>
; CHECK-NEXT: [[TMP35:%.*]] = select <16 x i1> [[TMP34]], <16 x float> zeroinitializer, <16 x float> [[TMP41]]
; CHECK-NEXT: [[TMP36:%.*]] = bitcast <16 x float> [[TMP35]] to <16 x i32>
@@ -42,16 +42,16 @@ define <16 x half> @test(i32 %0, float %1, i32 %2) {
; CHECK-NEXT: [[TMP53:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP39:%.*]] = shufflevector <16 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison, float poison>, <16 x float> [[TMP53]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17>
; CHECK-NEXT: [[TMP40:%.*]] = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> zeroinitializer, <16 x float> [[TMP38]], <16 x float> [[TMP39]])
-; CHECK-NEXT: [[TMP43:%.*]] = extractelement <16 x float> [[TMP29]], i32 0
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <16 x float> [[TMP29]], i64 0
; CHECK-NEXT: [[TMP44:%.*]] = fcmp olt float [[TMP43]], 0.000000e+00
-; CHECK-NEXT: [[TMP45:%.*]] = extractelement <16 x float> [[TMP29]], i32 14
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <16 x float> [[TMP29]], i64 14
; CHECK-NEXT: [[TMP49:%.*]] = fcmp ogt float [[TMP45]], 0.000000e+00
; CHECK-NEXT: [[TMP46:%.*]] = fcmp olt float [[TMP45]], 0.000000e+00
-; CHECK-NEXT: [[TMP47:%.*]] = extractelement <16 x float> [[TMP29]], i32 13
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <16 x float> [[TMP29]], i64 13
; CHECK-NEXT: [[TMP50:%.*]] = fcmp ogt float [[TMP47]], 0.000000e+00
; CHECK-NEXT: [[TMP48:%.*]] = fcmp olt float [[TMP47]], 0.000000e+00
; CHECK-NEXT: [[TMP54:%.*]] = fcmp olt float [[TMP43]], 0.000000e+00
-; CHECK-NEXT: [[TMP51:%.*]] = extractelement <16 x float> [[TMP29]], i32 1
+; CHECK-NEXT: [[TMP51:%.*]] = extractelement <16 x float> [[TMP29]], i64 1
; CHECK-NEXT: [[TMP55:%.*]] = fcmp ogt float [[TMP51]], 0.000000e+00
; CHECK-NEXT: [[TMP52:%.*]] = fcmp oeq <16 x float> [[TMP40]], zeroinitializer
; CHECK-NEXT: ret <16 x half> zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reused-extract-scalar-lanes.ll b/llvm/test/Transforms/SLPVectorizer/X86/reused-extract-scalar-lanes.ll
index 10f4000546852..1a2db8f0d7361 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reused-extract-scalar-lanes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reused-extract-scalar-lanes.ll
@@ -6,11 +6,11 @@ define i32 @test(i32 %v4) {
; CHECK-SAME: i32 [[V4:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[REM23:%.*]] = select i1 false, i32 0, i32 0
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 1, i32 poison>, i32 [[V4]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 1, i32 poison>, i32 [[V4]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> zeroinitializer, <2 x i32> [[TMP0]], <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> <i32 1, i32 poison>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[REM23]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[REM23]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[TMP6:%.*]] = mul <4 x i32> [[TMP5]], zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = urem <4 x i32> [[TMP6]], splat (i32 46337)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reused-extracts.ll b/llvm/test/Transforms/SLPVectorizer/X86/reused-extracts.ll
index 1820407daf078..ebb2355a33274 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reused-extracts.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reused-extracts.ll
@@ -4,9 +4,9 @@
define void @test() {
; CHECK-LABEL: define void @test() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i1> poison, i1 false, i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i1> poison, i1 false, i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([17 x i64], ptr null, i64 0, i64 9), align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i1> [[TMP0]], i1 false, i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i1> [[TMP0]], i1 false, i64 1
; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i1> [[TMP2]] to <2 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP1]], [[TMP3]]
; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr getelementptr inbounds ([17 x i64], ptr null, i64 0, i64 9), align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reused-last-instruction-in-split-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/reused-last-instruction-in-split-node.ll
index 49164e59621fb..efac9f0695308 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reused-last-instruction-in-split-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reused-last-instruction-in-split-node.ll
@@ -4,9 +4,9 @@
define float @test() {
; CHECK-LABEL: define float @test() {
; CHECK-NEXT: [[LABEL:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <12 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef>, float 0.000000e+00, i32 5
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <12 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00, float undef>, float 0.000000e+00, i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <12 x float> [[TMP1]], float 0.000000e+00, i32 8
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <12 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef>, float 0.000000e+00, i64 5
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <12 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00, float undef>, float 0.000000e+00, i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <12 x float> [[TMP1]], float 0.000000e+00, i64 8
; CHECK-NEXT: [[TMP3:%.*]] = fmul <12 x float> [[TMP0]], [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = fadd <12 x float> [[TMP3]], <float 0.000000e+00, float 0.000000e+00, float -0.000000e+00, float 0.000000e+00, float -0.000000e+00, float 0.000000e+00, float -0.000000e+00, float 0.000000e+00, float 0.000000e+00, float -0.000000e+00, float 0.000000e+00, float poison>
; CHECK-NEXT: [[TMP5:%.*]] = fsub <8 x float> zeroinitializer, <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison>
@@ -17,7 +17,7 @@ define float @test() {
; CHECK-NEXT: br label %[[REGION_30:.*]]
; CHECK: [[REGION_30]]:
; CHECK-NEXT: [[TMP10:%.*]] = phi <20 x float> [ [[TMP9]], %[[LABEL]] ]
-; CHECK-NEXT: [[TMP27:%.*]] = extractelement <20 x float> [[TMP10]], i32 10
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <20 x float> [[TMP10]], i64 10
; CHECK-NEXT: ret float [[TMP27]]
;
label:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reused-mask-with-poison-index.ll b/llvm/test/Transforms/SLPVectorizer/X86/reused-mask-with-poison-index.ll
index efd44f5a85664..b36e6e649b687 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reused-mask-with-poison-index.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reused-mask-with-poison-index.ll
@@ -34,12 +34,12 @@ define fastcc i32 @test(ptr %0, <2 x float> %1, i1 %2, float %3, float %4) {
; CHECK-NEXT: [[TMP30:%.*]] = fcmp olt float [[TMP21]], 0.000000e+00
; CHECK-NEXT: br i1 [[TMP30]], label %[[BB57]], label %[[BB31:.*]]
; CHECK: [[BB31]]:
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP32:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i64 0
; CHECK-NEXT: [[TMP33:%.*]] = shufflevector <4 x float> [[TMP32]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP34:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP33]], <4 x float> zeroinitializer, <4 x float> zeroinitializer)
-; CHECK-NEXT: [[TMP37:%.*]] = extractelement <4 x float> [[TMP25]], i32 0
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <4 x float> [[TMP25]], i64 0
; CHECK-NEXT: [[TMP38:%.*]] = fsub float [[TMP15]], [[TMP37]]
-; CHECK-NEXT: [[TMP48:%.*]] = extractelement <4 x float> [[TMP25]], i32 1
+; CHECK-NEXT: [[TMP48:%.*]] = extractelement <4 x float> [[TMP25]], i64 1
; CHECK-NEXT: [[TMP49:%.*]] = fsub float [[TMP17]], [[TMP48]]
; CHECK-NEXT: [[TMP39:%.*]] = insertelement <2 x float> zeroinitializer, float [[TMP14]], i64 0
; CHECK-NEXT: [[TMP40:%.*]] = shufflevector <4 x float> [[TMP25]], <4 x float> poison, <2 x i32> <i32 poison, i32 2>
@@ -61,7 +61,7 @@ define fastcc i32 @test(ptr %0, <2 x float> %1, i1 %2, float %3, float %4) {
; CHECK-NEXT: br i1 [[TMP2]], label %[[BB57]], label %[[BB53:.*]]
; CHECK: [[BB53]]:
; CHECK-NEXT: [[TMP54:%.*]] = extractelement <2 x float> [[TMP1]], i64 0
-; CHECK-NEXT: [[TMP55:%.*]] = extractelement <4 x float> [[TMP25]], i32 3
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <4 x float> [[TMP25]], i64 3
; CHECK-NEXT: br label %[[BB57]]
; CHECK: [[TMP56]]:
; CHECK-NEXT: br label %[[BB8]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reused-reductions-with-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/reused-reductions-with-minbitwidth.ll
index 1d1fcec2a7aeb..b6a217163248c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reused-reductions-with-minbitwidth.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reused-reductions-with-minbitwidth.ll
@@ -5,7 +5,7 @@ define i1 @test(i1 %cmp5.not.31) {
; CHECK-LABEL: define i1 @test(
; CHECK-SAME: i1 [[CMP5_NOT_31:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i1> <i1 poison, i1 false, i1 false, i1 false>, i1 [[CMP5_NOT_31]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i1> <i1 poison, i1 false, i1 false, i1 false>, i1 [[CMP5_NOT_31]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> zeroinitializer, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], <i32 2, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP2]])
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reused-scalars-in-buildvector.ll b/llvm/test/Transforms/SLPVectorizer/X86/reused-scalars-in-buildvector.ll
index d1b177e2b6dea..874fa40230f6d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reused-scalars-in-buildvector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reused-scalars-in-buildvector.ll
@@ -3,14 +3,14 @@
define void @test(ptr %p, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) {
; CHECK-LABEL: @test(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[B:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[B:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = sub <2 x i32> [[TMP2]], splat (i32 1)
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[E:%.*]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[F:%.*]], i32 1
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[C:%.*]], i32 2
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[D:%.*]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[E:%.*]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[F:%.*]], i64 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[C:%.*]], i64 2
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[D:%.*]], i64 3
; CHECK-NEXT: [[TMP9:%.*]] = mul <4 x i32> [[TMP4]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reused-undefs.ll b/llvm/test/Transforms/SLPVectorizer/X86/reused-undefs.ll
index ce6a477f30a08..155fe20d466b5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reused-undefs.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reused-undefs.ll
@@ -6,11 +6,11 @@ define i32 @main(i32 %0) {
; CHECK-NEXT: for.cond.preheader:
; CHECK-NEXT: br i1 false, label [[FOR_END:%.*]], label [[FOR_INC_PREHEADER:%.*]]
; CHECK: for.inc.preheader:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison, i32 undef>, i32 [[TMP0:%.*]], i32 6
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison, i32 undef>, i32 [[TMP0:%.*]], i64 6
; CHECK-NEXT: br i1 false, label [[FOR_END]], label [[L1_PREHEADER:%.*]]
; CHECK: for.end:
; CHECK-NEXT: [[DOTPR:%.*]] = phi i32 [ 0, [[FOR_INC_PREHEADER]] ], [ 0, [[FOR_COND_PREHEADER:%.*]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[DOTPR]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[DOTPR]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: br label [[L1_PREHEADER]]
; CHECK: L1.preheader:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/revec-fma-vectorize.ll b/llvm/test/Transforms/SLPVectorizer/X86/revec-fma-vectorize.ll
index 63ad002e2214c..3c5f0a17c15d7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/revec-fma-vectorize.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/revec-fma-vectorize.ll
@@ -6,7 +6,7 @@ define dso_local <2 x float> @fma_f32(ptr %A, float %B) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[A:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nsz contract <2 x float> [[TMP0]], splat (float 2.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> <float poison, float -0.000000e+00>, float [[B:%.*]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> <float poison, float -0.000000e+00>, float [[B:%.*]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = fadd reassoc nsz contract <2 x float> [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret <2 x float> [[TMP3]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/revec-non-power-2-to-power-2-large-vect.ll b/llvm/test/Transforms/SLPVectorizer/X86/revec-non-power-2-to-power-2-large-vect.ll
index cf2a32a910fbd..d1e3df3244be2 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/revec-non-power-2-to-power-2-large-vect.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/revec-non-power-2-to-power-2-large-vect.ll
@@ -6,25 +6,25 @@ define float @test(ptr %0, double %1, double %2, double %3) {
; CHECK-SAME: ptr [[TMP0:%.*]], double [[TMP1:%.*]], double [[TMP2:%.*]], double [[TMP3:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP5:%.*]] = fmul double [[TMP1]], 0.000000e+00
; CHECK-NEXT: [[TMP6:%.*]] = fmul double [[TMP1]], 0.000000e+00
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <3 x double> poison, double [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <3 x double> [[TMP7]], double [[TMP2]], i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <3 x double> [[TMP8]], double [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <3 x double> poison, double [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <3 x double> [[TMP7]], double [[TMP2]], i64 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <3 x double> [[TMP8]], double [[TMP1]], i64 2
; CHECK-NEXT: [[TMP10:%.*]] = fmul <3 x double> [[TMP9]], zeroinitializer
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <3 x double> [[TMP9]], <3 x double> poison, <3 x i32> <i32 1, i32 0, i32 2>
; CHECK-NEXT: [[TMP14:%.*]] = fmul <3 x double> [[TMP13]], zeroinitializer
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[TMP0]], i64 1356
; CHECK-NEXT: [[TMP18:%.*]] = fmul double [[TMP1]], 0.000000e+00
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <3 x double> <double -0.000000e+00, double poison, double -0.000000e+00>, double [[TMP6]], i32 1
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <3 x double> <double poison, double poison, double -0.000000e+00>, double [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <3 x double> [[TMP16]], double [[TMP18]], i32 0
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <3 x double> <double -0.000000e+00, double poison, double -0.000000e+00>, double [[TMP6]], i64 1
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <3 x double> <double poison, double poison, double -0.000000e+00>, double [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <3 x double> [[TMP16]], double [[TMP18]], i64 0
; CHECK-NEXT: [[TMP20:%.*]] = fadd <3 x double> [[TMP17]], [[TMP19]]
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <3 x double> <double 0.000000e+00, double poison, double 0.000000e+00>, double [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <3 x double> <double 0.000000e+00, double poison, double 0.000000e+00>, double [[TMP5]], i64 1
; CHECK-NEXT: [[TMP22:%.*]] = fadd <3 x double> [[TMP21]], [[TMP20]]
; CHECK-NEXT: [[TMP23:%.*]] = fadd <3 x double> [[TMP14]], [[TMP22]]
; CHECK-NEXT: [[TMP24:%.*]] = fadd <3 x double> [[TMP10]], [[TMP23]]
; CHECK-NEXT: [[TMP25:%.*]] = fptrunc <3 x double> [[TMP24]] to <3 x float>
; CHECK-NEXT: store <3 x float> [[TMP25]], ptr [[TMP15]], align 4
-; CHECK-NEXT: [[TMP26:%.*]] = extractelement <3 x float> [[TMP25]], i32 0
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <3 x float> [[TMP25]], i64 0
; CHECK-NEXT: ret float [[TMP26]]
;
%5 = fmul double %1, 0.000000e+00
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-replace-extractelement.ll b/llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-replace-extractelement.ll
index 9c86e81f0df5b..a0624bfaafd00 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-replace-extractelement.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-replace-extractelement.ll
@@ -7,11 +7,11 @@ define void @test() {
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 0 to i32
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
-; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ zeroinitializer, %[[BB]] ], [ [[TMP4:%.*]], %[[BB1]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ zeroinitializer, %[[BB]] ], [ [[TMP2:%.*]], %[[BB1]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1
; CHECK-NEXT: [[OP_RDX:%.*]] = mul i32 0, [[TMP1]]
; CHECK-NEXT: [[OP_RDX1:%.*]] = mul i32 [[OP_RDX]], [[TRUNC]]
-; CHECK-NEXT: [[TMP4]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[OP_RDX1]], i32 1
+; CHECK-NEXT: [[TMP2]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[OP_RDX1]], i64 1
; CHECK-NEXT: br label %[[BB1]]
;
bb:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/revec-scalar-insertelement.ll b/llvm/test/Transforms/SLPVectorizer/X86/revec-scalar-insertelement.ll
index 6a53cfa5ec1c8..5072e5d2245c4 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/revec-scalar-insertelement.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/revec-scalar-insertelement.ll
@@ -6,7 +6,7 @@ define <8 x i16> @test(ptr %0) {
; CHECK-SAME: ptr [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[VECTOR_PH:.*:]]
; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> poison, i16 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> poison, i16 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 2, i32 poison, i32 3, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i16> zeroinitializer, <8 x i16> [[TMP4]], <8 x i32> <i32 8, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 7>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-different-parents.ll b/llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-different-parents.ll
index 3c9582a23360a..45e4c8334613c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-different-parents.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/same-last-instruction-different-parents.ll
@@ -4,7 +4,7 @@
define i32 @test(i32 %0, i1 %1) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = sitofp <2 x i32> [[TMP4]] to <2 x double>
; CHECK-NEXT: [[TMP5:%.*]] = sitofp <2 x i32> [[TMP4]] to <2 x double>
@@ -24,8 +24,8 @@ define i32 @test(i32 %0, i1 %1) {
; CHECK-NEXT: br label %[[BB16]]
; CHECK: [[BB16]]:
; CHECK-NEXT: [[TMP17:%.*]] = phi <2 x double> [ [[TMP15]], %[[BB14]] ], [ [[TMP8]], %[[BB7]] ]
-; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x double> [[TMP17]], i32 0
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x double> [[TMP17]], i32 1
+; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x double> [[TMP17]], i64 0
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x double> [[TMP17]], i64 1
; CHECK-NEXT: [[TMP20:%.*]] = fmul double [[TMP19]], [[TMP18]]
; CHECK-NEXT: [[TMP21:%.*]] = fptosi double [[TMP20]] to i32
; CHECK-NEXT: ret i32 [[TMP21]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/same-operands-but-copyable.ll b/llvm/test/Transforms/SLPVectorizer/X86/same-operands-but-copyable.ll
index 667a16685ca14..db444ba738ab2 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/same-operands-but-copyable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/same-operands-but-copyable.ll
@@ -8,7 +8,7 @@ define void @test(ptr %0, ptr %1, float %.sroa.3232.0.copyload) {
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i64 12
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr [[TMP0]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = fmul <2 x float> [[TMP3]], <float 0.000000e+00, float 1.000000e+00>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x float> [[TMP3]], float [[DOTSROA_3232_0_COPYLOAD]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x float> [[TMP3]], float [[DOTSROA_3232_0_COPYLOAD]], i64 0
; CHECK-NEXT: [[TMP8:%.*]] = fmul <2 x float> [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP12:%.*]] = fmul <2 x float> [[TMP8]], zeroinitializer
; CHECK-NEXT: [[TMP13:%.*]] = fmul <2 x float> [[TMP12]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/same-values-sub-node-with-poisons.ll b/llvm/test/Transforms/SLPVectorizer/X86/same-values-sub-node-with-poisons.ll
index 38f49791c570d..3e9b1563f1a50 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/same-values-sub-node-with-poisons.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/same-values-sub-node-with-poisons.ll
@@ -13,7 +13,7 @@ define i32 @test(ptr %f, i1 %tobool.i.4, i32 %retval.0.i.219) {
; CHECK-NEXT: br i1 false, label %[[D_EXIT_3]], label %[[D_EXIT_6:.*]]
; CHECK: [[D_EXIT_3]]:
; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x i32> [ poison, %[[IF_END_I_2]] ], [ zeroinitializer, %[[ENTRY]] ], [ poison, %[[IF_END_I_1]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> <i32 poison, i32 1>, i32 [[RETVAL_0_I_219]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> <i32 poison, i32 1>, i32 [[RETVAL_0_I_219]], i64 0
; CHECK-NEXT: br i1 [[TOBOOL_I_4]], label %[[D_EXIT_4:.*]], label %[[D_EXIT_6]]
; CHECK: [[D_EXIT_4]]:
; CHECK-NEXT: br label %[[D_EXIT_6]]
@@ -30,8 +30,8 @@ define i32 @test(ptr %f, i1 %tobool.i.4, i32 %retval.0.i.219) {
; CHECK-NEXT: [[TMP7:%.*]] = phi <2 x i32> [ [[TMP4]], %[[D_EXIT_6]] ], [ poison, %[[IF_END_I_5]] ]
; CHECK-NEXT: [[TMP9:%.*]] = phi <4 x i32> [ [[TMP13]], %[[D_EXIT_6]] ], [ poison, %[[IF_END_I_5]] ]
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> <i32 poison, i32 1, i32 1, i32 poison>, i32 [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[RETVAL_0_I_219]], i32 3
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> <i32 poison, i32 1, i32 1, i32 poison>, i32 [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[RETVAL_0_I_219]], i64 3
; CHECK-NEXT: [[TMP16:%.*]] = add <4 x i32> [[TMP15]], [[TMP9]]
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <4 x i32> [[TMP14]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/saxpy.ll b/llvm/test/Transforms/SLPVectorizer/X86/saxpy.ll
index af323a81f152f..baaff8940bed7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/saxpy.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/saxpy.ll
@@ -10,7 +10,7 @@ define void @SAXPY(ptr noalias nocapture %x, ptr noalias nocapture %y, i32 %a, i
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i64 [[I:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[Y:%.*]], i64 [[I]]
; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[A:%.*]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[A:%.*]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = mul nsw <4 x i32> [[TMP4]], [[SHUFFLE]]
; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder-non-empty.ll b/llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder-non-empty.ll
index a1930398ecd55..b83d10d1c24cf 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder-non-empty.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder-non-empty.ll
@@ -11,7 +11,7 @@ define double @test01() {
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double poison>, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 poison>
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x double> [[TMP7]], double [[TMP4]], i32 3
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x double> [[TMP7]], double [[TMP4]], i64 3
; CHECK-NEXT: [[TMP9:%.*]] = fadd <4 x double> [[TMP6]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = call double @llvm.vector.reduce.fadd.v4f64(double -0.000000e+00, <4 x double> [[TMP9]])
; CHECK-NEXT: ret double [[TMP10]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder.ll b/llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder.ll
index 533b0df21e160..a6246afcd8ba8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder.ll
@@ -12,8 +12,8 @@ define void @test() {
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr undef, align 4
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr undef, align 4
; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x float> zeroinitializer, [[TMP0]]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP2]], i32 1
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP2]], i64 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[TMP2]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[TMP4]], <2 x float> [[TMP3]], <2 x float> [[TMP6]])
; CHECK-NEXT: br i1 false, label [[BB2:%.*]], label [[BB3:%.*]]
; CHECK: bb2:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/schedule_budget.ll b/llvm/test/Transforms/SLPVectorizer/X86/schedule_budget.ll
index b5c7e0e3cde06..d9c8a76d208c1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/schedule_budget.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/schedule_budget.ll
@@ -43,16 +43,16 @@ define void @test(ptr %a, ptr %b, ptr %c, ptr %d) {
; LOBUDGET-NEXT: call void @unknown()
; LOBUDGET-NEXT: call void @unknown()
; LOBUDGET-NEXT: call void @unknown()
-; LOBUDGET-NEXT: [[L00:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; LOBUDGET-NEXT: [[L00:%.*]] = extractelement <4 x float> [[TMP1]], i64 0
; LOBUDGET-NEXT: store float [[L00]], ptr [[B:%.*]], align 4
; LOBUDGET-NEXT: [[B1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 1
-; LOBUDGET-NEXT: [[L10:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; LOBUDGET-NEXT: [[L10:%.*]] = extractelement <4 x float> [[TMP1]], i64 1
; LOBUDGET-NEXT: store float [[L10]], ptr [[B1]], align 4
; LOBUDGET-NEXT: [[B2:%.*]] = getelementptr inbounds float, ptr [[B]], i64 2
-; LOBUDGET-NEXT: [[L20:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; LOBUDGET-NEXT: [[L20:%.*]] = extractelement <4 x float> [[TMP1]], i64 2
; LOBUDGET-NEXT: store float [[L20]], ptr [[B2]], align 4
; LOBUDGET-NEXT: [[B3:%.*]] = getelementptr inbounds float, ptr [[B]], i64 3
-; LOBUDGET-NEXT: [[L30:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; LOBUDGET-NEXT: [[L30:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; LOBUDGET-NEXT: store float [[L30]], ptr [[B3]], align 4
; LOBUDGET-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[C:%.*]], align 4
; LOBUDGET-NEXT: store <4 x float> [[TMP0]], ptr [[D:%.*]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll b/llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
index e0f70ea861cb4..155603d1f2a04 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
@@ -10,7 +10,7 @@ define i32 @foo(i32 %v2, ptr byval(%struct.S2) align 8 %v5, i1 %cmp3644) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[BB4:.*]]
; CHECK: [[BB4]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[V2]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[V2]], i64 1
; CHECK-NEXT: br label %[[BB5:.*]]
; CHECK: [[BB5]]:
; CHECK-NEXT: [[F1783:%.*]] = getelementptr i8, ptr [[V5]], i64 108
@@ -23,10 +23,10 @@ define i32 @foo(i32 %v2, ptr byval(%struct.S2) align 8 %v5, i1 %cmp3644) {
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP5:%.*]] = freeze <2 x i32> [[TMP4]]
; CHECK-NEXT: [[DOTFR5726:%.*]] = freeze i32 [[TMP1]]
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP0]], i32 [[DOTFR5727]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP0]], i32 [[DOTFR5727]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <8 x i32> <i32 1, i32 poison, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP31:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> [[TMP7]], <8 x i32> <i32 0, i32 1, i32 poison, i32 8, i32 poison, i32 10, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP32:%.*]] = insertelement <8 x i32> [[TMP31]], i32 [[DOTFR5726]], i32 6
+; CHECK-NEXT: [[TMP32:%.*]] = insertelement <8 x i32> [[TMP31]], i32 [[DOTFR5726]], i64 6
; CHECK-NEXT: [[TMP33:%.*]] = shufflevector <8 x i32> [[TMP32]], <8 x i32> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 0, i32 5, i32 6, i32 1>
; CHECK-NEXT: [[TMP34:%.*]] = srem <8 x i32> [[TMP33]], splat (i32 46337)
; CHECK-NEXT: [[TMP35:%.*]] = shufflevector <8 x i32> [[TMP34]], <8 x i32> poison, <8 x i32> <i32 2, i32 1, i32 0, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -64,7 +64,7 @@ define i32 @foo(i32 %v2, ptr byval(%struct.S2) align 8 %v5, i1 %cmp3644) {
; CHECK: [[BB15]]:
; CHECK-NEXT: br i1 false, label %[[BB4]], label %[[BB12]]
; CHECK: [[BB18]]:
-; CHECK-NEXT: [[TMP30:%.*]] = extractelement <8 x i32> [[TMP24]], i32 4
+; CHECK-NEXT: [[TMP30:%.*]] = extractelement <8 x i32> [[TMP24]], i64 4
; CHECK-NEXT: ret i32 [[TMP30]]
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll b/llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll
index 1c532ef31bc39..979701609b499 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll
@@ -12,28 +12,28 @@ define void @select_logical_or_i1(ptr %dst,
; CHECK-LABEL: define void @select_logical_or_i1(
; CHECK-SAME: ptr [[DST:%.*]], float [[D0:%.*]], float [[D1:%.*]], float [[D2:%.*]], float [[D3:%.*]], float [[THRESHOLD:%.*]], float [[HPHB_VAL:%.*]], i1 [[SCALAR_COND:%.*]], float [[Y0:%.*]], float [[Y1:%.*]], float [[Y2:%.*]], float [[Y3:%.*]], float [[E0:%.*]], float [[E1:%.*]], float [[E2:%.*]], float [[E3:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[D0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[D1]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[D2]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[D3]], i32 3
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> poison, float [[THRESHOLD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[D0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[D1]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[D2]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[D3]], i64 3
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> poison, float [[THRESHOLD]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = fcmp fast uge <4 x float> [[TMP3]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i1> poison, i1 [[SCALAR_COND]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i1> poison, i1 [[SCALAR_COND]], i64 0
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i1> [[TMP7]], <4 x i1> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[TMP6]], <4 x i1> splat (i1 true), <4 x i1> [[TMP8]]
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> poison, float [[HPHB_VAL]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> poison, float [[HPHB_VAL]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x float> [[TMP10]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP9]], <4 x float> zeroinitializer, <4 x float> [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x float> poison, float [[Y0]], i32 0
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x float> [[TMP13]], float [[Y1]], i32 1
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x float> [[TMP14]], float [[Y2]], i32 2
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x float> [[TMP15]], float [[Y3]], i32 3
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x float> poison, float [[Y0]], i64 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x float> [[TMP13]], float [[Y1]], i64 1
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x float> [[TMP14]], float [[Y2]], i64 2
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x float> [[TMP15]], float [[Y3]], i64 3
; CHECK-NEXT: [[TMP17:%.*]] = fmul fast <4 x float> [[TMP12]], [[TMP16]]
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x float> poison, float [[E0]], i32 0
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x float> [[TMP18]], float [[E1]], i32 1
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x float> [[TMP19]], float [[E2]], i32 2
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x float> [[TMP20]], float [[E3]], i32 3
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x float> poison, float [[E0]], i64 0
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x float> [[TMP18]], float [[E1]], i64 1
+; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x float> [[TMP19]], float [[E2]], i64 2
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x float> [[TMP20]], float [[E3]], i64 3
; CHECK-NEXT: [[TMP22:%.*]] = fadd fast <4 x float> [[TMP21]], [[TMP17]]
; CHECK-NEXT: store <4 x float> [[TMP22]], ptr [[DST]], align 4
; CHECK-NEXT: ret void
@@ -84,28 +84,28 @@ define void @select_logical_and_i1(ptr %dst,
; CHECK-LABEL: define void @select_logical_and_i1(
; CHECK-SAME: ptr [[DST:%.*]], float [[D0:%.*]], float [[D1:%.*]], float [[D2:%.*]], float [[D3:%.*]], float [[THRESHOLD:%.*]], float [[HPHB_VAL:%.*]], i1 [[SCALAR_COND:%.*]], float [[Y0:%.*]], float [[Y1:%.*]], float [[Y2:%.*]], float [[Y3:%.*]], float [[E0:%.*]], float [[E1:%.*]], float [[E2:%.*]], float [[E3:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[D0]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[D1]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[D2]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[D3]], i32 3
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> poison, float [[THRESHOLD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> poison, float [[D0]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[D1]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[D2]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[D3]], i64 3
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> poison, float [[THRESHOLD]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = fcmp fast uge <4 x float> [[TMP3]], [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i1> poison, i1 [[SCALAR_COND]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i1> poison, i1 [[SCALAR_COND]], i64 0
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i1> [[TMP7]], <4 x i1> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[TMP6]], <4 x i1> [[TMP8]], <4 x i1> zeroinitializer
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> poison, float [[HPHB_VAL]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> poison, float [[HPHB_VAL]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x float> [[TMP10]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP9]], <4 x float> zeroinitializer, <4 x float> [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x float> poison, float [[Y0]], i32 0
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x float> [[TMP13]], float [[Y1]], i32 1
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x float> [[TMP14]], float [[Y2]], i32 2
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x float> [[TMP15]], float [[Y3]], i32 3
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x float> poison, float [[Y0]], i64 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x float> [[TMP13]], float [[Y1]], i64 1
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x float> [[TMP14]], float [[Y2]], i64 2
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x float> [[TMP15]], float [[Y3]], i64 3
; CHECK-NEXT: [[TMP17:%.*]] = fmul fast <4 x float> [[TMP12]], [[TMP16]]
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x float> poison, float [[E0]], i32 0
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x float> [[TMP18]], float [[E1]], i32 1
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x float> [[TMP19]], float [[E2]], i32 2
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x float> [[TMP20]], float [[E3]], i32 3
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x float> poison, float [[E0]], i64 0
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x float> [[TMP18]], float [[E1]], i64 1
+; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x float> [[TMP19]], float [[E2]], i64 2
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x float> [[TMP20]], float [[E3]], i64 3
; CHECK-NEXT: [[TMP22:%.*]] = fadd fast <4 x float> [[TMP21]], [[TMP17]]
; CHECK-NEXT: store <4 x float> [[TMP22]], ptr [[DST]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/select-reduction-op.ll b/llvm/test/Transforms/SLPVectorizer/X86/select-reduction-op.ll
index f16bf31f85ecc..a28ab906f0132 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/select-reduction-op.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/select-reduction-op.ll
@@ -4,7 +4,7 @@
define i1 @src(i1 %cmp4.118.i) {
; CHECK-LABEL: define i1 @src(
; CHECK-SAME: i1 [[CMP4_118_I:%.*]]) {
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i1> <i1 poison, i1 true, i1 true, i1 true>, i1 [[CMP4_118_I]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i1> <i1 poison, i1 true, i1 true, i1 true>, i1 [[CMP4_118_I]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i1> [[TMP4]], <i1 true, i1 poison, i1 poison, i1 poison>
; CHECK-NEXT: [[DOTNOT7:%.*]] = xor i1 poison, true
; CHECK-NEXT: [[TMP1:%.*]] = freeze <4 x i1> [[TMP5]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shl-compatible-with-add.ll b/llvm/test/Transforms/SLPVectorizer/X86/shl-compatible-with-add.ll
index 06efaf926d72a..ac768c7aa4483 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/shl-compatible-with-add.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/shl-compatible-with-add.ll
@@ -5,7 +5,7 @@ define void @intrapred_luma(ptr %0, i16 %1, i32 %conv593) {
; CHECK-LABEL: define void @intrapred_luma(
; CHECK-SAME: ptr [[TMP0:%.*]], i16 [[TMP1:%.*]], i32 [[CONV593:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i16> poison, i16 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i16> poison, i16 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = zext <2 x i16> [[TMP3]] to <2 x i32>
; CHECK-NEXT: [[DOTPRE:%.*]] = load ptr, ptr [[TMP0]], align 8
@@ -14,11 +14,11 @@ define void @intrapred_luma(ptr %0, i16 %1, i32 %conv593) {
; CHECK-NEXT: [[ADD633:%.*]] = add i32 [[CONV635]], 1
; CHECK-NEXT: [[ADD636:%.*]] = add i32 [[ADD633]], [[CONV593]]
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 poison>
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[ADD636]], i32 3
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[ADD636]], i64 3
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <4 x i32> <i32 1, i32 poison, i32 0, i32 1>, <4 x i32> [[TMP5]], <4 x i32> <i32 0, i32 4, i32 2, i32 3>
; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i32> [[TMP17]], [[TMP18]]
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 poison, i32 poison>, i32 [[CONV593]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 poison, i32 poison>, i32 [[CONV593]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP9]], [[TMP11]]
; CHECK-NEXT: [[TMP15:%.*]] = lshr <4 x i32> [[TMP12]], <i32 1, i32 2, i32 1, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll
index d0379db8af49b..7a9a815ff79bc 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll
@@ -7,15 +7,15 @@ define void @test(ptr %src, i8 %0, i32 %conv2) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[ARRAYIDX41:%.*]] = getelementptr i8, ptr [[SRC]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[SRC]], align 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[TMP1]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 0>
; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i8> [[TMP6]] to <4 x i32>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> <i32 1, i32 1, i32 poison, i32 1>, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i32> [[TMP5]], [[TMP8]]
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 1, i32 0>, i32 [[CONV2]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> <i32 poison, i32 poison, i32 1, i32 0>, i32 [[CONV2]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP9]], [[TMP11]]
; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP12]], [[TMP7]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll
index a6786c98bb474..597fed290b9b0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll
@@ -7,9 +7,9 @@ define i32 @test(i32 %0, i32 %1) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <2 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = add <2 x i32> [[TMP3]], [[TMP4]]
; CHECK-NEXT: [[DOTNEG_NEG:%.*]] = shl i32 [[TMP0]], 1
; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i32>, ptr getelementptr inbounds nuw (i8, ptr @st, i64 8), align 8
@@ -17,11 +17,11 @@ define i32 @test(i32 %0, i32 %1) {
; CHECK-NEXT: [[SUB120_3:%.*]] = or i32 [[TMP5]], [[DOTNEG_NEG]]
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> <i32 poison, i32 poison, i32 poison, i32 0, i32 poison, i32 poison, i32 0, i32 0>, <8 x i32> <i32 0, i32 1, i32 poison, i32 11, i32 poison, i32 poison, i32 14, i32 15>
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i32> [[TMP9]], i32 [[TMP0]], i32 2
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i32> [[TMP10]], i32 [[SUB120_3]], i32 5
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i32> [[TMP9]], i32 [[TMP0]], i64 2
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i32> [[TMP10]], i32 [[SUB120_3]], i64 5
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <8 x i32> [[TMP11]], <8 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i32> [[TMP11]], <8 x i32> poison, <5 x i32> <i32 2, i32 poison, i32 poison, i32 5, i32 poison>
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <5 x i32> [[TMP13]], i32 [[DOTNEG_NEG]], i32 1
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <5 x i32> [[TMP13]], i32 [[DOTNEG_NEG]], i64 1
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <5 x i32> <i32 0, i32 poison, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <5 x i32> [[TMP14]], <5 x i32> [[TMP15]], <5 x i32> <i32 0, i32 1, i32 5, i32 3, i32 7>
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <5 x i32> [[TMP16]], <5 x i32> poison, <8 x i32> <i32 0, i32 1, i32 0, i32 2, i32 0, i32 3, i32 4, i32 2>
@@ -63,23 +63,23 @@ define i32 @test1(ptr %0, ptr %1, i32 %2) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 1
; CHECK-NEXT: [[ADD53_1:%.*]] = add i32 [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[TMP3]], i64 0
; CHECK-NEXT: [[TMP8:%.*]] = add <2 x i32> [[TMP7]], splat (i32 1)
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ADD53_1]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ADD53_1]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> [[TMP8]], <2 x i32> <i32 2, i32 1>
; CHECK-NEXT: [[TMP10:%.*]] = sub <2 x i32> [[TMP5]], [[TMP9]]
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[TMP10]], i32 1
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[TMP10]], i64 1
; CHECK-NEXT: [[SHL_1:%.*]] = shl i32 [[TMP11]], 1
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i32> poison, i32 [[ADD53_1]], i32 0
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i32> [[TMP12]], i32 [[SHL_1]], i32 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i32> poison, i32 [[ADD53_1]], i64 0
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i32> [[TMP12]], i32 [[SHL_1]], i64 1
; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP8]], [[TMP13]]
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> <i32 1, i32 poison>, <2 x i32> <i32 2, i32 1>
; CHECK-NEXT: [[TMP16:%.*]] = add <2 x i32> [[TMP14]], [[TMP15]]
; CHECK-NEXT: [[TMP17:%.*]] = or <2 x i32> [[TMP14]], [[TMP15]]
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <2 x i32> [[TMP16]], <2 x i32> [[TMP17]], <2 x i32> <i32 0, i32 3>
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP10]], i32 0
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP10]], i64 0
; CHECK-NEXT: store i32 [[TMP19]], ptr @st, align 8
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <2 x i32> [[TMP18]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <2 x i32> [[TMP10]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
@@ -117,7 +117,7 @@ define i32 @test2(i32 %0) {
; CHECK-LABEL: define i32 @test2(
; CHECK-SAME: i32 [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, i32 [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, i32 [[TMP0]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> <i32 0, i32 1, i32 0, i32 1>, [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <4 x i32> <i32 1, i32 2, i32 2, i32 2>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll b/llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll
index 23e37b845ce1b..bc5d5b9449d62 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/shuffle-mask-emission.ll
@@ -5,9 +5,9 @@ define i1 @test() {
; CHECK-LABEL: define i1 @test() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[H_PROMOTED118_I_FR:%.*]] = freeze i32 1
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[H_PROMOTED118_I_FR]], i32 2
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 0, i32 poison, i32 0>, i32 [[H_PROMOTED118_I_FR]], i64 2
; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> zeroinitializer, [[TMP0]]
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[H_PROMOTED118_I_FR]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[H_PROMOTED118_I_FR]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i32> zeroinitializer, [[TMP3]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 0>
; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP1]], [[TMP2]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sibling-loops-mismatched-tripcount.ll b/llvm/test/Transforms/SLPVectorizer/X86/sibling-loops-mismatched-tripcount.ll
index 6f138b32f845f..99ac92416340d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sibling-loops-mismatched-tripcount.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sibling-loops-mismatched-tripcount.ll
@@ -49,7 +49,7 @@ define void @sibling_root_loops_mismatched_tripcount(ptr %dst, i64 %n, i64 %m, i
; CHECK-NEXT: ]
; CHECK: [[LOOP_A]]:
; CHECK-NEXT: [[JA:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[JA_NEXT:%.*]], %[[LOOP_A]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[JA]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[JA]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = mul <2 x i64> [[TMP1]], <i64 2, i64 3>
; CHECK-NEXT: [[TMP3:%.*]] = mul <2 x i64> [[TMP1]], <i64 5, i64 7>
@@ -58,7 +58,7 @@ define void @sibling_root_loops_mismatched_tripcount(ptr %dst, i64 %n, i64 %m, i
; CHECK-NEXT: br i1 [[CA]], label %[[LOOP_A]], label %[[MERGE:.*]]
; CHECK: [[LOOP_B]]:
; CHECK-NEXT: [[JB:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[JB_NEXT:%.*]], %[[LOOP_B]] ]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> poison, i64 [[JB]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> poison, i64 [[JB]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = mul <2 x i64> [[TMP5]], <i64 11, i64 13>
; CHECK-NEXT: [[TMP7:%.*]] = mul <2 x i64> [[TMP5]], <i64 17, i64 19>
@@ -67,7 +67,7 @@ define void @sibling_root_loops_mismatched_tripcount(ptr %dst, i64 %n, i64 %m, i
; CHECK-NEXT: br i1 [[CB]], label %[[LOOP_B]], label %[[MERGE]]
; CHECK: [[LOOP_C]]:
; CHECK-NEXT: [[JC:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[JC_NEXT:%.*]], %[[LOOP_C]] ]
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> poison, i64 [[JC]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> poison, i64 [[JC]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i64> [[TMP8]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP10:%.*]] = mul <2 x i64> [[TMP9]], <i64 23, i64 29>
; CHECK-NEXT: [[TMP11:%.*]] = mul <2 x i64> [[TMP9]], <i64 31, i64 37>
@@ -200,11 +200,11 @@ define void @sibling_inner_loops_mismatched_tripcount(ptr %dst, i64 %n, i64 %m,
; CHECK-NEXT: [[OFF3:%.*]] = add i64 [[BASE]], 2
; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[BASE]]
; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[OFF3]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[P1]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[P2]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[P1]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[P2]], i64 1
; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr [[G1]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[P3]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[P4]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[P3]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[P4]], i64 1
; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr [[G3]], align 8
; CHECK-NEXT: br label %[[OUTER_LATCH]]
; CHECK: [[OUTER_LATCH]]:
@@ -347,11 +347,11 @@ define void @sibling_inner_loops_matching_tripcount(ptr %dst, i64 %n, i32 %sel)
; CHECK-NEXT: [[OFF3:%.*]] = add i64 [[BASE]], 2
; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[BASE]]
; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[OFF3]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[P1]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[P2]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[P1]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[P2]], i64 1
; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr [[G1]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[P3]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[P4]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> poison, i64 [[P3]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> [[TMP2]], i64 [[P4]], i64 1
; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr [[G3]], align 8
; CHECK-NEXT: br label %[[OUTER_LATCH]]
; CHECK: [[OUTER_LATCH]]:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/simplebb.ll b/llvm/test/Transforms/SLPVectorizer/X86/simplebb.ll
index c63bac27d08ed..7782cc34125f7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/simplebb.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/simplebb.ll
@@ -86,10 +86,10 @@ define void @test_volatile_store(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[B:%.*]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[MUL:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
+; CHECK-NEXT: [[MUL:%.*]] = extractelement <2 x double> [[TMP3]], i64 0
; CHECK-NEXT: store volatile double [[MUL]], ptr [[C:%.*]], align 8
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds double, ptr [[C]], i64 1
-; CHECK-NEXT: [[MUL5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
+; CHECK-NEXT: [[MUL5:%.*]] = extractelement <2 x double> [[TMP3]], i64 1
; CHECK-NEXT: store volatile double [[MUL5]], ptr [[ARRAYIDX5]], align 8
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
index d65e5b37c6f0e..bbc197b446fe0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
@@ -1086,11 +1086,11 @@ define void @sitofp_16i8_16f32() #0 {
define <4 x double> @sitofp_4xi32_4f64(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
; SSE-LABEL: @sitofp_4xi32_4f64(
-; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A0:%.*]], i32 0
-; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
+; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A0:%.*]], i64 0
+; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A1:%.*]], i64 1
; SSE-NEXT: [[TMP3:%.*]] = sitofp <2 x i32> [[TMP2]] to <2 x double>
-; SSE-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[A2:%.*]], i32 0
-; SSE-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[A3:%.*]], i32 1
+; SSE-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[A2:%.*]], i64 0
+; SSE-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[A3:%.*]], i64 1
; SSE-NEXT: [[TMP6:%.*]] = sitofp <2 x i32> [[TMP5]] to <2 x double>
; SSE-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; SSE-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
@@ -1098,10 +1098,10 @@ define <4 x double> @sitofp_4xi32_4f64(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
; SSE-NEXT: ret <4 x double> [[RES31]]
;
; AVX-LABEL: @sitofp_4xi32_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i32 0
-; AVX-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
-; AVX-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A2:%.*]], i32 2
-; AVX-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A3:%.*]], i32 3
+; AVX-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i64 0
+; AVX-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i64 1
+; AVX-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A2:%.*]], i64 2
+; AVX-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A3:%.*]], i64 3
; AVX-NEXT: [[TMP5:%.*]] = sitofp <4 x i32> [[TMP4]] to <4 x double>
; AVX-NEXT: ret <4 x double> [[TMP5]]
;
@@ -1118,10 +1118,10 @@ define <4 x double> @sitofp_4xi32_4f64(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
define <4 x float> @sitofp_4xi32_4f32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
; CHECK-LABEL: @sitofp_4xi32_4f32(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A2:%.*]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A2:%.*]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = sitofp <4 x i32> [[TMP4]] to <4 x float>
; CHECK-NEXT: ret <4 x float> [[TMP5]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll
index 917baaa86460c..361b67755ad2e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll
@@ -15,8 +15,8 @@ define void @foo(ptr %ptr) {
; CHECK-NEXT: [[TMP7:%.*]] = sub nsw <2 x i32> [[TMP6]], [[TMP2]]
; CHECK-NEXT: [[TMP8:%.*]] = sitofp <2 x i32> [[TMP7]] to <2 x double>
; CHECK-NEXT: [[TMP9:%.*]] = fdiv <2 x double> [[TMP4]], [[TMP8]]
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x double> [[TMP9]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x double> [[TMP9]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x double> [[TMP9]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x double> [[TMP9]], i64 1
; CHECK-NEXT: [[FCMP:%.*]] = fcmp olt double [[TMP11]], [[TMP10]]
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
index a22245a75c629..06222affea9b7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
@@ -1086,11 +1086,11 @@ define void @sitofp_16i8_16f32() #0 {
define <4 x double> @sitofp_4xi32_4f64(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
; SSE-LABEL: @sitofp_4xi32_4f64(
-; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A0:%.*]], i32 0
-; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
+; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A0:%.*]], i64 0
+; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A1:%.*]], i64 1
; SSE-NEXT: [[TMP3:%.*]] = sitofp <2 x i32> [[TMP2]] to <2 x double>
-; SSE-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[A2:%.*]], i32 0
-; SSE-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[A3:%.*]], i32 1
+; SSE-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> poison, i32 [[A2:%.*]], i64 0
+; SSE-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[A3:%.*]], i64 1
; SSE-NEXT: [[TMP6:%.*]] = sitofp <2 x i32> [[TMP5]] to <2 x double>
; SSE-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; SSE-NEXT: [[RES11:%.*]] = shufflevector <4 x double> zeroinitializer, <4 x double> [[TMP7]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
@@ -1099,10 +1099,10 @@ define <4 x double> @sitofp_4xi32_4f64(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
; SSE-NEXT: ret <4 x double> [[RES31]]
;
; AVX-LABEL: @sitofp_4xi32_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i32 0
-; AVX-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
-; AVX-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A2:%.*]], i32 2
-; AVX-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A3:%.*]], i32 3
+; AVX-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i64 0
+; AVX-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i64 1
+; AVX-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A2:%.*]], i64 2
+; AVX-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A3:%.*]], i64 3
; AVX-NEXT: [[TMP5:%.*]] = sitofp <4 x i32> [[TMP4]] to <4 x double>
; AVX-NEXT: ret <4 x double> [[TMP5]]
;
@@ -1119,8 +1119,8 @@ define <4 x double> @sitofp_4xi32_4f64(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
define <4 x double> @sitofp_with_const_4xi32_4f64(i32 %a2, i32 %a3) #0 {
; SSE-LABEL: @sitofp_with_const_4xi32_4f64(
-; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A2:%.*]], i32 0
-; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A3:%.*]], i32 1
+; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A2:%.*]], i64 0
+; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A3:%.*]], i64 1
; SSE-NEXT: [[TMP3:%.*]] = sitofp <2 x i32> [[TMP2]] to <2 x double>
; SSE-NEXT: [[RES0:%.*]] = insertelement <4 x double> zeroinitializer, double 1.000000e+00, i32 3
; SSE-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
@@ -1145,8 +1145,8 @@ define <4 x double> @sitofp_with_const_4xi32_4f64(i32 %a2, i32 %a3) #0 {
define <4 x double> @sitofp_with_zeroinitializer_4xi32_4f64(i32 %a2, i32 %a3) #0 {
; SSE-LABEL: @sitofp_with_zeroinitializer_4xi32_4f64(
-; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A2:%.*]], i32 0
-; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A3:%.*]], i32 1
+; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A2:%.*]], i64 0
+; SSE-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A3:%.*]], i64 1
; SSE-NEXT: [[TMP3:%.*]] = sitofp <2 x i32> [[TMP2]] to <2 x double>
; SSE-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; SSE-NEXT: [[RES31:%.*]] = shufflevector <4 x double> zeroinitializer, <4 x double> [[TMP4]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
@@ -1168,10 +1168,10 @@ define <4 x double> @sitofp_with_zeroinitializer_4xi32_4f64(i32 %a2, i32 %a3) #0
define <4 x float> @sitofp_4xi32_4f32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
; CHECK-LABEL: @sitofp_4xi32_4f32(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A2:%.*]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A3:%.*]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[A1:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A2:%.*]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[A3:%.*]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = sitofp <4 x i32> [[TMP4]] to <4 x float>
; CHECK-NEXT: ret <4 x float> [[TMP5]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll b/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
index 8b65461028fb1..f48748dd137b6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
@@ -13,7 +13,7 @@ define void @hr() {
; SSE4: loop:
; SSE4-NEXT: [[PHI0:%.*]] = phi double [ 0.000000e+00, [[TMP0:%.*]] ], [ [[OP_RDX:%.*]], [[LOOP]] ]
; SSE4-NEXT: [[CVT0:%.*]] = uitofp i16 0 to double
-; SSE4-NEXT: [[TMP1:%.*]] = insertelement <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, double [[CVT0]], i32 0
+; SSE4-NEXT: [[TMP1:%.*]] = insertelement <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, double [[CVT0]], i64 0
; SSE4-NEXT: [[TMP2:%.*]] = fmul fast <4 x double> zeroinitializer, [[TMP1]]
; SSE4-NEXT: [[TMP3:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> [[TMP2]])
; SSE4-NEXT: [[OP_RDX]] = fadd fast double [[TMP3]], [[PHI0]]
@@ -40,7 +40,7 @@ define void @hr() {
; AVX2: loop:
; AVX2-NEXT: [[PHI0:%.*]] = phi double [ 0.000000e+00, [[TMP0:%.*]] ], [ [[OP_RDX:%.*]], [[LOOP]] ]
; AVX2-NEXT: [[CVT0:%.*]] = uitofp i16 0 to double
-; AVX2-NEXT: [[TMP1:%.*]] = insertelement <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, double [[CVT0]], i32 0
+; AVX2-NEXT: [[TMP1:%.*]] = insertelement <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, double [[CVT0]], i64 0
; AVX2-NEXT: [[TMP2:%.*]] = fmul fast <4 x double> zeroinitializer, [[TMP1]]
; AVX2-NEXT: [[TMP3:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> [[TMP2]])
; AVX2-NEXT: [[OP_RDX]] = fadd fast double [[TMP3]], [[PHI0]]
@@ -75,7 +75,7 @@ exit:
define double @hr_or_mul() {
; SSE4-LABEL: @hr_or_mul(
; SSE4-NEXT: [[CVT0:%.*]] = uitofp i16 3 to double
-; SSE4-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[CVT0]], i32 0
+; SSE4-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[CVT0]], i64 0
; SSE4-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> poison, <4 x i32> zeroinitializer
; SSE4-NEXT: [[TMP3:%.*]] = fmul fast <4 x double> <double 7.000000e+00, double -4.300000e+01, double 2.200000e-02, double 9.500000e+00>, [[TMP2]]
; SSE4-NEXT: [[TMP4:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> [[TMP3]])
@@ -96,7 +96,7 @@ define double @hr_or_mul() {
;
; AVX2-LABEL: @hr_or_mul(
; AVX2-NEXT: [[CVT0:%.*]] = uitofp i16 3 to double
-; AVX2-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[CVT0]], i32 0
+; AVX2-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[CVT0]], i64 0
; AVX2-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> poison, <4 x i32> zeroinitializer
; AVX2-NEXT: [[TMP3:%.*]] = fmul fast <4 x double> <double 7.000000e+00, double -4.300000e+01, double 2.200000e-02, double 9.500000e+00>, [[TMP2]]
; AVX2-NEXT: [[TMP4:%.*]] = call fast double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> [[TMP3]])
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll b/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
index d6edf69882e82..faecdaee31f14 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
@@ -11,7 +11,7 @@ define void @rftbsub(ptr %a) {
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[ARRAYIDX6]], align 8
; CHECK-NEXT: [[ADD16:%.*]] = fadd double [[TMP1]], undef
; CHECK-NEXT: [[MUL18:%.*]] = fmul double undef, [[ADD16]]
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[MUL18]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[MUL18]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> undef, [[TMP3]]
; CHECK-NEXT: [[TMP7:%.*]] = fsub <2 x double> undef, [[TMP3]]
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> [[TMP7]], <2 x i32> <i32 0, i32 3>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/small-graph-diff-block-instructions.ll b/llvm/test/Transforms/SLPVectorizer/X86/small-graph-diff-block-instructions.ll
index 62c40cd5810bb..3d2d2edb861cf 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/small-graph-diff-block-instructions.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/small-graph-diff-block-instructions.ll
@@ -6,7 +6,7 @@ define i32 @test(i32 %arg, i32 %arg1) {
; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ARG1]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[ARG]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[ARG]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
@@ -14,9 +14,9 @@ define i32 @test(i32 %arg, i32 %arg1) {
; CHECK-NEXT: br label %[[BB3:.*]]
; CHECK: [[BB3]]:
; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr i64, ptr addrspace(1) null, i64 [[ZEXT]]
-; CHECK-NEXT: [[ZEXT2:%.*]] = extractelement <2 x i64> [[TMP4]], i32 0
+; CHECK-NEXT: [[ZEXT2:%.*]] = extractelement <2 x i64> [[TMP4]], i64 0
; CHECK-NEXT: [[GETELEMENTPTR4:%.*]] = getelementptr i64, ptr addrspace(1) null, i64 [[ZEXT2]]
-; CHECK-NEXT: [[SEXT:%.*]] = extractelement <2 x i64> [[TMP4]], i32 1
+; CHECK-NEXT: [[SEXT:%.*]] = extractelement <2 x i64> [[TMP4]], i64 1
; CHECK-NEXT: [[GETELEMENTPTR5:%.*]] = getelementptr i64, ptr addrspace(1) null, i64 [[SEXT]]
; CHECK-NEXT: [[ZEXT6:%.*]] = zext i32 0 to i64
; CHECK-NEXT: [[GETELEMENTPTR7:%.*]] = getelementptr i64, ptr addrspace(1) null, i64 [[ZEXT6]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-load8_2_unord_geps.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-load8_2_unord_geps.ll
index 58571b546b6a4..266eb8e2f7f84 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-load8_2_unord_geps.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-load8_2_unord_geps.ll
@@ -7,7 +7,7 @@ define void @test(ptr noalias %p, ptr noalias %addr, ptr noalias %s) {
; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i32, ptr [[ADDR:%.*]], i32 1
; CHECK-NEXT: [[TMP0:%.*]] = call <15 x i32> @llvm.masked.load.v15i32.p0(ptr align 8 [[ADDR]], <15 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <15 x i32> poison)
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <15 x i32> [[TMP0]], <15 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x ptr> poison, ptr [[P:%.*]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x ptr> poison, ptr [[P:%.*]], i64 0
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x ptr> [[TMP4]], <8 x ptr> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, <8 x ptr> [[SHUFFLE2]], <8 x i32> [[TMP3]]
; CHECK-NEXT: [[TMP6:%.*]] = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> align 4 [[TMP5]], <8 x i1> splat (i1 true), <8 x i32> poison)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-node-full-match.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-node-full-match.ll
index 80d0c40ee422e..445e5fb27ec7f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-node-full-match.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-node-full-match.ll
@@ -10,13 +10,13 @@ define void @test(double %0) {
; CHECK-NEXT: br i1 false, label %[[BB3:.*]], label %[[BB7:.*]]
; CHECK: [[BB3]]:
; CHECK-NEXT: [[TMP4:%.*]] = call double null(ptr null, ptr null, ptr null)
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x double> <double poison, double 0.000000e+00, double poison, double 0.000000e+00>, double [[TMP0]], i32 2
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x double> [[TMP5]], double [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x double> <double poison, double 0.000000e+00, double poison, double 0.000000e+00>, double [[TMP0]], i64 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x double> [[TMP5]], double [[TMP4]], i64 0
; CHECK-NEXT: br label %[[BB7]]
; CHECK: [[BB7]]:
; CHECK-NEXT: [[TMP8:%.*]] = phi <4 x double> [ [[TMP6]], %[[BB3]] ], [ zeroinitializer, [[DOTTHREAD:%.*]] ]
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x double> [[TMP9]], double [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x double> [[TMP9]], double [[TMP1]], i64 1
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP8]], <4 x double> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x double> [[TMP10]], <2 x double> poison, <6 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <6 x double> [[TMP11]], <6 x double> [[TMP13]], <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 6, i32 7>
@@ -29,10 +29,10 @@ define void @test(double %0) {
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <6 x double> [[TMP15]], <6 x double> <double +qnan, double +qnan, double undef, double undef, double undef, double undef>, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 6, i32 7>
; CHECK-NEXT: br i1 false, label %[[BB18:.*]], [[DOT_CRIT_EDGE]]
; CHECK: [[BB18]]:
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <6 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double poison, double 0.000000e+00, double 0.000000e+00>, double [[TMP0]], i32 3
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <6 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double poison, double 0.000000e+00, double 0.000000e+00>, double [[TMP0]], i64 3
; CHECK-NEXT: br [[DOT_CRIT_EDGE]]
; CHECK: [[__CRIT_EDGE:.*:]]
-; CHECK-NEXT: [[TMP20:%.*]] = phi <6 x double> [ [[TMP12]], %[[BB7]] ], [ [[TMP18]], %[[BB18]] ], [ [[TMP17]], %[[BB14]] ], [ [[TMP12]], %[[DOTLR_PH272_PREHEADER]] ]
+; CHECK-NEXT: [[TMP20:%.*]] = phi <6 x double> [ [[TMP12]], %[[BB7]] ], [ [[TMP19]], %[[BB18]] ], [ [[TMP17]], %[[BB14]] ], [ [[TMP12]], %[[DOTLR_PH272_PREHEADER]] ]
; CHECK-NEXT: ret void
;
.thread:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-node-last-inst-vectorized.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-node-last-inst-vectorized.ll
index 47a25a089c69e..fe716c6b6904f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-node-last-inst-vectorized.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-node-last-inst-vectorized.ll
@@ -11,8 +11,8 @@ define void @test(ptr %0, <8 x i8> %1) {
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i64 13544
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i64 13536
; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i8>, ptr [[TMP4]], align 4
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i8> poison, i8 [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> [[TMP12]], i8 [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i8> poison, i8 [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> [[TMP12]], i8 [[TMP3]], i64 1
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i8> [[TMP9]], <8 x i8> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i8> [[TMP10]], [[TMP7]]
; CHECK-NEXT: store <8 x i8> [[TMP13]], ptr [[TMP11]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-node-no-reorder-copy.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-node-no-reorder-copy.ll
index 680f950fae975..8e89f3a5e77d8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-node-no-reorder-copy.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-node-no-reorder-copy.ll
@@ -8,17 +8,17 @@ define i1 @test(ptr %0, ptr %1, <2 x float> %2, <2 x float> %3, <2 x float> %4)
; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[TMP0]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP0]], align 4
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP4]], i64 0
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x float> poison, float [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x float> [[TMP10]], float [[TMP7]], i32 1
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x float> [[TMP11]], float [[TMP8]], i32 6
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x float> poison, float [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x float> [[TMP10]], float [[TMP7]], i64 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x float> [[TMP11]], float [[TMP8]], i64 6
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x float> [[TMP12]], <8 x float> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 6, i32 6>
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> [[TMP3]], <8 x i32> <i32 0, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0, i32 poison>
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x float> [[TMP14]], float [[TMP9]], i32 7
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x float> [[TMP14]], float [[TMP9]], i64 7
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <8 x float> [[TMP13]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <8 x float> [[TMP15]], <8 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <16 x float> [[TMP16]], <16 x float> [[TMP23]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <8 x float> [[TMP14]], <8 x float> [[TMP12]], <16 x i32> <i32 8, i32 9, i32 9, i32 9, i32 9, i32 9, i32 14, i32 14, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 poison>
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <16 x float> [[TMP19]], float [[TMP9]], i32 15
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <16 x float> [[TMP19]], float [[TMP9]], i64 15
; CHECK-NEXT: [[TMP20:%.*]] = fmul <16 x float> [[TMP18]], [[TMP17]]
; CHECK-NEXT: [[TMP21:%.*]] = call reassoc nsz float @llvm.vector.reduce.fadd.v16f32(float 0.000000e+00, <16 x float> [[TMP20]])
; CHECK-NEXT: [[TMP22:%.*]] = call float @foo(float [[TMP21]])
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-node-num-operands.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-node-num-operands.ll
index 5aa4dba2b8a1b..604063fd15230 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-node-num-operands.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-node-num-operands.ll
@@ -11,12 +11,12 @@ define i64 @Foo(ptr align 8 dereferenceable(344) %0, i64 %1) {
; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP4]], align 8
; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP5]], align 8
; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP0]], align 8
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i64> poison, i64 [[TMP6]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i64> [[TMP10]], i64 [[TMP9]], i32 1
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i64> poison, i64 [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i64> [[TMP12]], i64 [[TMP8]], i32 1
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x i64> poison, i64 0, i32 0
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x i64> <i64 0, i64 poison>, i64 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i64> poison, i64 [[TMP6]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i64> [[TMP10]], i64 [[TMP9]], i64 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i64> poison, i64 [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i64> [[TMP12]], i64 [[TMP8]], i64 1
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x i64> poison, i64 0, i64 0
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x i64> <i64 0, i64 poison>, i64 [[TMP1]], i64 1
; CHECK-NEXT: br label %[[BB16:.*]]
; CHECK: [[BB16]]:
; CHECK-NEXT: [[TMP17:%.*]] = phi <2 x i64> [ [[TMP11]], [[TMP2:%.*]] ], [ zeroinitializer, %[[TMP25:.*]] ]
@@ -26,8 +26,8 @@ define i64 @Foo(ptr align 8 dereferenceable(344) %0, i64 %1) {
; CHECK-NEXT: ]
; CHECK: [[BB19]]:
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <2 x i64> [[TMP18]], <2 x i64> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i64> [[TMP20]], i64 0, i32 1
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i64> [[TMP21]], i64 0, i32 2
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i64> [[TMP20]], i64 0, i64 1
+; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i64> [[TMP21]], i64 0, i64 2
; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <4 x i64> [[TMP22]], <4 x i64> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <2 x i64> [[TMP14]], <2 x i64> [[TMP18]], <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: br label %[[TMP25]]
@@ -46,10 +46,10 @@ define i64 @Foo(ptr align 8 dereferenceable(344) %0, i64 %1) {
; CHECK-NEXT: [[TMP31:%.*]] = shufflevector <4 x i64> [[TMP27]], <4 x i64> <i64 0, i64 0, i64 poison, i64 0>, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
; CHECK-NEXT: br [[DOTCONT174]]
; CHECK: [[BB32]]:
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <4 x i64> [[TMP27]], i64 0, i32 1
-; CHECK-NEXT: [[TMP34:%.*]] = insertelement <4 x i64> [[TMP33]], i64 0, i32 2
+; CHECK-NEXT: [[TMP33:%.*]] = insertelement <4 x i64> [[TMP27]], i64 0, i64 1
+; CHECK-NEXT: [[TMP34:%.*]] = insertelement <4 x i64> [[TMP33]], i64 0, i64 2
; CHECK-NEXT: [[TMP35:%.*]] = shufflevector <4 x i64> [[TMP34]], <4 x i64> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
-; CHECK-NEXT: [[TMP36:%.*]] = insertelement <2 x i64> [[TMP28]], i64 0, i32 0
+; CHECK-NEXT: [[TMP36:%.*]] = insertelement <2 x i64> [[TMP28]], i64 0, i64 0
; CHECK-NEXT: br [[DOTCONT174]]
; CHECK: [[_CONT174:.*:]]
; CHECK-NEXT: [[TMP37:%.*]] = phi <2 x i64> [ [[TMP26]], %[[BB32]] ], [ zeroinitializer, %[[BB30]] ], [ [[TMP26]], %[[DOTLOOPEXIT206]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-node-parent-operands-in-spill.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-node-parent-operands-in-spill.ll
index cd3663e28eb75..a60ace16330c0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-node-parent-operands-in-spill.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-node-parent-operands-in-spill.ll
@@ -23,10 +23,10 @@ define void @test(i32 %arg) {
; CHECK-NEXT: ret void
; CHECK: [[BB8]]:
; CHECK-NEXT: [[TMP0:%.*]] = phi <4 x i32> [ zeroinitializer, %[[BB4]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[LOAD]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[LOAD1]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[LOAD3]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[LOAD2]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[LOAD]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[LOAD1]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[LOAD3]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[LOAD2]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP5]], <8 x i32> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-node-reduce-root.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-node-reduce-root.ll
index c010ce5586e53..891ff262e2ee0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-node-reduce-root.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-node-reduce-root.ll
@@ -8,7 +8,7 @@ define i64 @test(i64 %0) {
; CHECK-NEXT: [[TMP1:%.*]] = alloca [20 x i64], align 8
; CHECK-NEXT: store i64 0, ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i64 72
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i64> [[TMP4]], splat (i64 1)
; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
index 2b3f00dc21769..037e586081572 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
@@ -4,26 +4,26 @@
define void @test(i32 %0, i8 %1, i64 %2, float %3) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[TMP0:%.*]], i8 [[TMP1:%.*]], i64 [[TMP2:%.*]], float [[TMP3:%.*]]) {
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = and <2 x i64> [[TMP6]], <i64 -65536, i64 255>
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP7]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP7]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP2]], [[TMP8]]
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP7]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP7]], i64 1
; CHECK-NEXT: [[TMP52:%.*]] = add i64 [[TMP10]], 1
; CHECK-NEXT: [[TMP53:%.*]] = lshr i64 [[TMP9]], 16
; CHECK-NEXT: [[TMP58:%.*]] = lshr i64 [[TMP52]], 1
; CHECK-NEXT: [[TMP90:%.*]] = trunc i64 [[TMP53]] to i8
; CHECK-NEXT: [[TMP91:%.*]] = trunc i64 [[TMP58]] to i8
-; CHECK-NEXT: [[TMP92:%.*]] = insertelement <2 x i8> poison, i8 [[TMP91]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i8> [[TMP92]], i8 [[TMP90]], i32 1
+; CHECK-NEXT: [[TMP92:%.*]] = insertelement <2 x i8> poison, i8 [[TMP91]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i8> [[TMP92]], i8 [[TMP90]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = call <2 x i8> @llvm.smax.v2i8(<2 x i8> [[TMP11]], <2 x i8> zeroinitializer)
; CHECK-NEXT: [[TMP13:%.*]] = uitofp <2 x i8> [[TMP12]] to <2 x float>
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i8> poison, i8 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i8> poison, i8 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <4 x i8> [[TMP14]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP16:%.*]] = uitofp <4 x i8> [[TMP15]] to <4 x float>
; CHECK-NEXT: [[TMP17:%.*]] = fdiv <2 x float> [[TMP13]], zeroinitializer
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <2 x i32> [[TMP18]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP20:%.*]] = sitofp <2 x i32> [[TMP19]] to <2 x float>
; CHECK-NEXT: [[TMP21:%.*]] = fdiv <2 x float> zeroinitializer, [[TMP20]]
@@ -39,23 +39,23 @@ define void @test(i32 %0, i8 %1, i64 %2, float %3) {
; CHECK-NEXT: [[TMP30:%.*]] = call <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP29]])
; CHECK-NEXT: [[TMP31:%.*]] = bitcast <8 x float> [[TMP30]] to <8 x i32>
; CHECK-NEXT: [[TMP32:%.*]] = icmp ult <8 x i32> [[TMP31]], splat (i32 1325400064)
-; CHECK-NEXT: [[TMP33:%.*]] = extractelement <8 x i1> [[TMP32]], i32 6
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <8 x i1> [[TMP32]], i64 6
; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i64 0, i64 2147483648
-; CHECK-NEXT: [[TMP35:%.*]] = extractelement <8 x i1> [[TMP32]], i32 5
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <8 x i1> [[TMP32]], i64 5
; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i64 0, i64 4286578688
; CHECK-NEXT: [[TMP37:%.*]] = or i64 [[TMP34]], [[TMP36]]
-; CHECK-NEXT: [[TMP38:%.*]] = extractelement <8 x i1> [[TMP32]], i32 7
+; CHECK-NEXT: [[TMP38:%.*]] = extractelement <8 x i1> [[TMP32]], i64 7
; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], i64 0, i64 128
-; CHECK-NEXT: [[TMP40:%.*]] = extractelement <8 x i1> [[TMP32]], i32 4
+; CHECK-NEXT: [[TMP40:%.*]] = extractelement <8 x i1> [[TMP32]], i64 4
; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i64 0, i64 128
-; CHECK-NEXT: [[TMP42:%.*]] = extractelement <8 x i1> [[TMP32]], i32 2
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <8 x i1> [[TMP32]], i64 2
; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i64 0, i64 8388608
-; CHECK-NEXT: [[TMP44:%.*]] = extractelement <8 x i1> [[TMP32]], i32 3
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <8 x i1> [[TMP32]], i64 3
; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i64 0, i64 32768
; CHECK-NEXT: [[TMP46:%.*]] = or i64 [[TMP43]], [[TMP45]]
-; CHECK-NEXT: [[TMP47:%.*]] = extractelement <8 x i1> [[TMP32]], i32 0
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <8 x i1> [[TMP32]], i64 0
; CHECK-NEXT: [[TMP48:%.*]] = select i1 [[TMP47]], i64 0, i64 8388608
-; CHECK-NEXT: [[TMP49:%.*]] = extractelement <8 x i1> [[TMP32]], i32 1
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <8 x i1> [[TMP32]], i64 1
; CHECK-NEXT: [[TMP50:%.*]] = select i1 [[TMP49]], i64 0, i64 32768
; CHECK-NEXT: br label %[[BB59:.*]]
; CHECK: [[BB58:.*]]:
@@ -65,7 +65,7 @@ define void @test(i32 %0, i8 %1, i64 %2, float %3) {
; CHECK: [[BB60]]:
; CHECK-NEXT: [[TMP54:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP17]])
; CHECK-NEXT: [[TMP55:%.*]] = call <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP21]])
-; CHECK-NEXT: [[TMP56:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP56:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i64 0
; CHECK-NEXT: [[TMP57:%.*]] = shufflevector <8 x float> [[TMP56]], <8 x float> poison, <8 x i32> <i32 poison, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP87:%.*]] = shufflevector <2 x float> [[TMP55]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP88:%.*]] = shufflevector <8 x float> [[TMP57]], <8 x float> [[TMP87]], <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>
@@ -73,30 +73,30 @@ define void @test(i32 %0, i8 %1, i64 %2, float %3) {
; CHECK-NEXT: [[TMP59:%.*]] = shufflevector <8 x float> [[TMP88]], <8 x float> [[TMP89]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; CHECK-NEXT: [[TMP60:%.*]] = bitcast <8 x float> [[TMP59]] to <8 x i32>
; CHECK-NEXT: [[TMP61:%.*]] = icmp ult <8 x i32> [[TMP60]], splat (i32 1325400064)
-; CHECK-NEXT: [[TMP62:%.*]] = extractelement <8 x i1> [[TMP61]], i32 5
+; CHECK-NEXT: [[TMP62:%.*]] = extractelement <8 x i1> [[TMP61]], i64 5
; CHECK-NEXT: [[TMP63:%.*]] = select i1 [[TMP62]], i64 [[TMP37]], i64 0
-; CHECK-NEXT: [[TMP64:%.*]] = extractelement <8 x i1> [[TMP61]], i32 4
+; CHECK-NEXT: [[TMP64:%.*]] = extractelement <8 x i1> [[TMP61]], i64 4
; CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i64 0, i64 4294967168
; CHECK-NEXT: [[TMP66:%.*]] = or i64 [[TMP63]], [[TMP65]]
-; CHECK-NEXT: [[TMP67:%.*]] = extractelement <8 x i1> [[TMP61]], i32 7
+; CHECK-NEXT: [[TMP67:%.*]] = extractelement <8 x i1> [[TMP61]], i64 7
; CHECK-NEXT: [[TMP68:%.*]] = select i1 [[TMP67]], i64 0, i64 8388608
-; CHECK-NEXT: [[TMP69:%.*]] = extractelement <8 x i1> [[TMP61]], i32 6
+; CHECK-NEXT: [[TMP69:%.*]] = extractelement <8 x i1> [[TMP61]], i64 6
; CHECK-NEXT: [[TMP70:%.*]] = select i1 [[TMP69]], i64 0, i64 32768
; CHECK-NEXT: [[TMP71:%.*]] = or i64 [[TMP68]], [[TMP70]]
; CHECK-NEXT: [[TMP72:%.*]] = or i64 [[TMP71]], [[TMP66]]
; CHECK-NEXT: [[TMP73:%.*]] = or i64 [[TMP72]], [[TMP39]]
; CHECK-NEXT: store i64 [[TMP73]], ptr null, align 1
; CHECK-NEXT: store i64 [[TMP41]], ptr null, align 1
-; CHECK-NEXT: [[TMP74:%.*]] = extractelement <8 x i1> [[TMP61]], i32 3
+; CHECK-NEXT: [[TMP74:%.*]] = extractelement <8 x i1> [[TMP61]], i64 3
; CHECK-NEXT: [[TMP75:%.*]] = select i1 [[TMP74]], i64 0, i64 -9223372036854775808
-; CHECK-NEXT: [[TMP76:%.*]] = extractelement <8 x i1> [[TMP61]], i32 2
+; CHECK-NEXT: [[TMP76:%.*]] = extractelement <8 x i1> [[TMP61]], i64 2
; CHECK-NEXT: [[TMP77:%.*]] = zext i1 [[TMP76]] to i64
; CHECK-NEXT: [[TMP78:%.*]] = or i64 [[TMP46]], [[TMP77]]
; CHECK-NEXT: [[TMP79:%.*]] = or i64 [[TMP78]], [[TMP75]]
; CHECK-NEXT: store i64 [[TMP79]], ptr null, align 1
-; CHECK-NEXT: [[TMP80:%.*]] = extractelement <8 x i1> [[TMP61]], i32 1
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <8 x i1> [[TMP61]], i64 1
; CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i64 0, i64 2147483648
-; CHECK-NEXT: [[TMP82:%.*]] = extractelement <8 x i1> [[TMP61]], i32 0
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <8 x i1> [[TMP61]], i64 0
; CHECK-NEXT: [[TMP83:%.*]] = select i1 [[TMP82]], i64 0, i64 128
; CHECK-NEXT: [[TMP84:%.*]] = or i64 [[TMP83]], [[TMP50]]
; CHECK-NEXT: [[TMP85:%.*]] = or i64 [[TMP84]], [[TMP48]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-node-reused-in-later-vector.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-node-reused-in-later-vector.ll
index 4a24fdbe337c6..ff2684bca8aba 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-node-reused-in-later-vector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-node-reused-in-later-vector.ll
@@ -4,11 +4,11 @@
define i1 @test() {
; CHECK-LABEL: define i1 @test() {
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 0, 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i1> <i1 poison, i1 false>, i1 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i1> <i1 poison, i1 false>, i1 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> <i32 1, i32 0>, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 0, i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 0, i64 1
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP8]], <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
@@ -32,7 +32,7 @@ define i1 @test() {
; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <8 x i32> [[TMP25]], <8 x i32> [[TMP26]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 5, i32 14, i32 7>
; CHECK-NEXT: [[TMP28:%.*]] = urem <8 x i32> [[TMP27]], splat (i32 46337)
; CHECK-NEXT: [[TMP29:%.*]] = icmp ult <8 x i32> [[TMP28]], zeroinitializer
-; CHECK-NEXT: [[TMP30:%.*]] = extractelement <8 x i1> [[TMP29]], i32 0
+; CHECK-NEXT: [[TMP30:%.*]] = extractelement <8 x i1> [[TMP29]], i64 0
; CHECK-NEXT: ret i1 [[TMP30]]
;
%1 = select i1 false, i32 0, i32 0
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-node-throttled.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-node-throttled.ll
index 62c89d07b527a..5c882d80fc870 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-node-throttled.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-node-throttled.ll
@@ -7,8 +7,8 @@ define fastcc void @test(i32 %arg) {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 false, i32 0, i32 0
; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr i8, ptr poison, i64 16
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[ARG]], i32 1
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[SELECT]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[ARG]], i64 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[SELECT]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[TMP0]] to <2 x i64>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> <i32 0, i32 poison>, <2 x i32> <i32 2, i32 0>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-vector-operand-with-reuses.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-vector-operand-with-reuses.ll
index 972a58cecc822..77e4463fbbee1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-vector-operand-with-reuses.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-vector-operand-with-reuses.ll
@@ -20,7 +20,7 @@ define void @test(ptr %p) {
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <16 x i32> <i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <16 x i32> [[TMP9]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 18, i32 poison, i32 poison, i32 poison, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i32> [[TMP10]], i32 [[TMP0]], i32 6
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i32> [[TMP10]], i32 [[TMP0]], i64 6
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <16 x i32> [[TMP11]], <16 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 6, i32 6, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP13:%.*]] = add <16 x i32> [[TMP3]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = srem <16 x i32> [[TMP13]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/split-vectorize-gathered-def-after-use.ll b/llvm/test/Transforms/SLPVectorizer/X86/split-vectorize-gathered-def-after-use.ll
index 247daa7701341..f8af48bb48a67 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/split-vectorize-gathered-def-after-use.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/split-vectorize-gathered-def-after-use.ll
@@ -12,19 +12,19 @@ define i32 @test(i32 %add.i64326, i32 %call119) {
; CHECK-NEXT: [[CALL1193:%.*]] = tail call i32 (...) null()
; CHECK-NEXT: [[CALL211:%.*]] = tail call i32 (...) null()
; CHECK-NEXT: [[CALL239:%.*]] = tail call i32 (...) null()
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <6 x i32> poison, i32 [[CALL]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x i32> [[TMP0]], i32 [[CALL35]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x i32> [[TMP1]], i32 [[CALL91]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i32> [[TMP2]], i32 [[CALL1193]], i32 3
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i32> [[TMP3]], i32 [[CALL211]], i32 4
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i32> [[TMP4]], i32 [[CALL239]], i32 5
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <6 x i32> poison, i32 [[CALL]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x i32> [[TMP0]], i32 [[CALL35]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x i32> [[TMP1]], i32 [[CALL91]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i32> [[TMP2]], i32 [[CALL1193]], i64 3
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i32> [[TMP3]], i32 [[CALL211]], i64 4
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i32> [[TMP4]], i32 [[CALL239]], i64 5
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <6 x i32> [[TMP5]], <6 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> <i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ADD_I64326]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[CALL35]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ADD_I64326]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[CALL35]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = add <2 x i32> [[TMP8]], [[TMP9]]
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <8 x i32> [[TMP7]], <8 x i32> poison, <16 x i32> <i32 0, i32 poison, i32 1, i32 poison, i32 poison, i32 2, i32 poison, i32 3, i32 poison, i32 4, i32 poison, i32 5, i32 6, i32 7, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i32> [[TMP11]], i32 [[ADD_R131]], i32 14
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <16 x i32> [[TMP11]], i32 [[ADD_R131]], i64 14
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <16 x i32> [[TMP12]], <16 x i32> poison, <16 x i32> <i32 0, i32 0, i32 2, i32 poison, i32 poison, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 12, i32 13, i32 14, i32 14>
; CHECK-NEXT: [[TMP14:%.*]] = and <16 x i32> [[TMP13]], <i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <2 x i32> [[TMP10]], <2 x i32> poison, <8 x i32> <i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/stacksave-dependence.ll b/llvm/test/Transforms/SLPVectorizer/X86/stacksave-dependence.ll
index 977942aa06c51..93bb1b3869bb0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/stacksave-dependence.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/stacksave-dependence.ll
@@ -32,8 +32,8 @@ define void @allocas(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: @allocas(
; CHECK-NEXT: [[V1:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[V2:%.*]] = alloca i8, align 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i32> splat (i32 1)
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[V1]], i32 1
; CHECK-NEXT: store ptr [[TMP4]], ptr [[A:%.*]], align 8
@@ -124,8 +124,8 @@ define void @stacksave2(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[V1:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[V2:%.*]] = alloca inalloca i8, align 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i32> splat (i32 1)
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[V1]], i32 1
; CHECK-NEXT: store ptr [[TMP4]], ptr [[A:%.*]], align 8
@@ -159,8 +159,8 @@ define void @stacksave3(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: [[V2:%.*]] = alloca inalloca i8, align 1
; CHECK-NEXT: call void @use(ptr inalloca(i8) [[V2]]) #[[ATTR4]]
; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[STACK]])
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i32> splat (i32 1)
; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -256,8 +256,8 @@ define void @stackrestore1(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[STACK]])
; CHECK-NEXT: [[V2:%.*]] = alloca i8, align 1
; CHECK-NEXT: store i8 0, ptr [[V2]], align 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i32> splat (i32 1)
; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void
@@ -302,11 +302,11 @@ define void @ham() #1 {
; CHECK-NEXT: [[VAR24:%.*]] = alloca inalloca i32, align 4
; CHECK-NEXT: call void @quux(ptr inalloca(i32) [[VAR24]])
; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[VAR23]])
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x ptr> poison, ptr [[VAR4]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x ptr> poison, ptr [[VAR4]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x ptr> [[TMP1]], <4 x ptr> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: store <4 x ptr> [[TMP2]], ptr [[VAR12]], align 8
; CHECK-NEXT: [[VAR36:%.*]] = getelementptr inbounds [12 x ptr], ptr [[VAR12]], i32 0, i32 4
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x ptr> [[TMP1]], ptr [[VAR5]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x ptr> [[TMP1]], ptr [[VAR5]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x ptr> [[TMP3]], <4 x ptr> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: store <4 x ptr> [[TMP4]], ptr [[VAR36]], align 8
; CHECK-NEXT: ret void
@@ -347,8 +347,8 @@ define void @spam() #1 {
; CHECK-NEXT: [[VAR5:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[VAR12:%.*]] = alloca [12 x ptr], align 8
; CHECK-NEXT: [[VAR36:%.*]] = getelementptr inbounds [12 x ptr], ptr [[VAR12]], i32 0, i32 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x ptr> poison, ptr [[VAR4]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x ptr> [[TMP1]], ptr [[VAR5]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x ptr> poison, ptr [[VAR4]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x ptr> [[TMP1]], ptr [[VAR5]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x ptr> [[TMP2]], <4 x ptr> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: store <4 x ptr> [[TMP3]], ptr [[VAR36]], align 8
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/store-load-forward-conflict.ll b/llvm/test/Transforms/SLPVectorizer/X86/store-load-forward-conflict.ll
index 245a537489d8f..b705f5cea5347 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/store-load-forward-conflict.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/store-load-forward-conflict.ll
@@ -32,7 +32,7 @@ define void @stlf_conflict_backward_misaligned(ptr noalias %A, i64 %n) {
; CHECK-NEXT: [[BACK_GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[BACK_IDX]]
; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[BACK_GEP]], align 4
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[GEP0]], align 4
@@ -103,7 +103,7 @@ define void @stlf_no_conflict_backward_aligned(ptr noalias %A, i64 %n) {
; CHECK-NEXT: [[BACK_GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[BACK_IDX]]
; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[BACK_GEP]], align 4
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[GEP0]], align 4
@@ -168,7 +168,7 @@ define void @stlf_no_conflict_forward(ptr noalias %A, i64 %n) {
; CHECK-NEXT: [[FWD_GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[FWD_IDX]]
; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[FWD_GEP]], align 4
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[GEP0]], align 4
@@ -227,7 +227,7 @@ define void @stlf_no_conflict_no_loop(ptr noalias %A) {
; CHECK-SAME: ptr noalias [[A:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[BACK_GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 -5
; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[BACK_GEP]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[TMP2]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr [[A]], align 4
@@ -271,7 +271,7 @@ define void @stlf_no_conflict_different_base(ptr noalias %A, ptr noalias %B,
; CHECK-NEXT: [[B_GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[B_IDX]]
; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[B_GEP]], align 4
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[GEP0]], align 4
@@ -338,7 +338,7 @@ define void @stlf_volatile_load_skipped(ptr noalias %A, i64 %n) {
; CHECK-NEXT: [[BACK_GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[BACK_IDX]]
; CHECK-NEXT: [[T:%.*]] = load volatile i32, ptr [[BACK_GEP]], align 4
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[GEP0]], align 4
@@ -410,7 +410,7 @@ define void @stlf_multiple_conflicting_loads(ptr noalias %A, i64 %n) {
; CHECK-NEXT: [[T7:%.*]] = load i32, ptr [[BACK7_GEP]], align 4
; CHECK-NEXT: [[SUM:%.*]] = add nsw i32 [[T5]], [[T7]]
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[SUM]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[SUM]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[GEP0]], align 4
@@ -483,7 +483,7 @@ define void @stlf_pointer_diff_unknown(ptr noalias %A, ptr noalias %IdxA, i64 %n
; CHECK-NEXT: [[DYN_GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[DYN_IDX]]
; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[DYN_GEP]], align 4
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[GEP0]], align 4
@@ -552,7 +552,7 @@ define void @stlf_no_conflict_within_prev_store(ptr noalias %A, i64 %n) {
; CHECK-NEXT: [[BACK_GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[BACK_IDX]]
; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[BACK_GEP]], align 4
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[GEP0]], align 4
@@ -624,7 +624,7 @@ define void @stlf_large_loop_bypassed(ptr noalias %A, i64 %n) {
; CHECK-NEXT: [[BACK_GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[BACK_IDX]]
; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[BACK_GEP]], align 4
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[GEP0]], align 4
@@ -693,7 +693,7 @@ define void @stlf_no_conflict_iter_safety_boundary(ptr noalias %A, i64 %n) {
; CHECK-NEXT: [[BACK_GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[BACK_IDX]]
; CHECK-NEXT: [[T:%.*]] = load i32, ptr [[BACK_GEP]], align 4
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[T]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4>
; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr [[GEP0]], align 4
@@ -762,7 +762,7 @@ define void @stlf_conflict_backward_misaligned_i64(ptr noalias %A, i64 %n) {
; CHECK-NEXT: [[BACK_GEP:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[BACK_IDX]]
; CHECK-NEXT: [[T:%.*]] = load i64, ptr [[BACK_GEP]], align 8
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[I]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[T]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[T]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i64> [[TMP1]], <i64 1, i64 2>
; CHECK-NEXT: store <2 x i64> [[TMP2]], ptr [[GEP0]], align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/stores_vectorize.ll b/llvm/test/Transforms/SLPVectorizer/X86/stores_vectorize.ll
index 02f8c552fec88..7879b6e6e9a6a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/stores_vectorize.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/stores_vectorize.ll
@@ -29,7 +29,7 @@ define void @_Z8DistanceIlLi5EEvPfiPmS0_(ptr %p1, i32 %p2, ptr %p3, ptr %p4) {
; CHECK-NEXT: [[TMP4:%.*]] = lshr <4 x i64> [[TMP3]], splat (i64 5)
; CHECK-NEXT: store <4 x i64> [[TMP4]], ptr [[P3]], align 8
; CHECK-NEXT: [[ADD_PTR11:%.*]] = getelementptr inbounds float, ptr [[ADD_PTR]], i64 [[IDX_EXT]]
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i64> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i64> [[TMP4]], i64 0
; CHECK-NEXT: [[AND:%.*]] = and i64 [[TMP6]], 5
; CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, ptr [[ADD_PTR11]], i64 [[AND]]
; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX13]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/struct-return-extract-dominance.ll b/llvm/test/Transforms/SLPVectorizer/X86/struct-return-extract-dominance.ll
index 35ea43071af99..8c79ca660b6fc 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/struct-return-extract-dominance.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/struct-return-extract-dominance.ll
@@ -16,10 +16,10 @@ define void @test() {
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @b, align 4
; CHECK-NEXT: [[TMP3:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, <4 x i1> } [[TMP3]], 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i32 1
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP4]], i32 2
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP4]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i64 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP4]], i64 2
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP4]], i64 3
; CHECK-NEXT: [[M0:%.*]] = mul i32 [[TMP5]], 7
; CHECK-NEXT: [[M1:%.*]] = mul i32 [[TMP6]], 7
; CHECK-NEXT: [[M2:%.*]] = mul i32 [[TMP7]], 7
@@ -87,10 +87,10 @@ define void @store_two_fields_different_orders() {
; CHECK-NEXT: [[TMP5:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[TMP2]], <4 x i32> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, <4 x i1> } [[TMP5]], 0
; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { <4 x i32>, <4 x i1> } [[TMP5]], 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP7]], i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP7]], i32 3
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP7]], i32 2
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP7]], i64 1
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP7]], i64 3
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP7]], i64 2
; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @r, align 4
; CHECK-NEXT: store i1 [[TMP8]], ptr @flags, align 1
; CHECK-NEXT: store i1 [[TMP9]], ptr getelementptr inbounds ([4 x i1], ptr @flags, i64 0, i64 1), align 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/struct-return-ordering-stress.ll b/llvm/test/Transforms/SLPVectorizer/X86/struct-return-ordering-stress.ll
index c7a3d43c27a8f..709b9f4aa2f79 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/struct-return-ordering-stress.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/struct-return-ordering-stress.ll
@@ -21,10 +21,10 @@ define void @store_both_fields_different_permutations() {
; CHECK-NEXT: [[TMP5:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[TMP2]], <4 x i32> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, <4 x i1> } [[TMP5]], 0
; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { <4 x i32>, <4 x i1> } [[TMP5]], 1
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP7]], i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP7]], i32 3
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP7]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP7]], i32 2
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP7]], i64 1
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP7]], i64 3
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP7]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP7]], i64 2
; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @r, align 4
; CHECK-NEXT: store i1 [[TMP11]], ptr @flags, align 1
; CHECK-NEXT: store i1 [[TMP10]], ptr getelementptr inbounds ([4 x i1], ptr @flags, i64 0, i64 1), align 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll b/llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
index 428f54f153887..6308f01135d55 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
@@ -9,42 +9,42 @@ define i1 @test(i64 %v1, ptr %v2, i32 %v3, i1 %v4) {
; CHECK-NEXT: [[TT3:%.*]] = lshr i64 [[V1]], 32
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TT3]] to i32
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i32> [[TMP4]], <i32 1, i32 255>
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <2 x i32> [[TMP5]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> poison, i32 [[V3]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> poison, i32 [[V3]], i64 0
; CHECK-NEXT: [[TMP30:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> poison, <4 x i32> <i32 poison, i32 poison, i32 0, i32 0>
; CHECK-NEXT: [[TMP31:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i32> [[TMP30]], <4 x i32> [[TMP31]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP11:%.*]] = uitofp <4 x i32> [[TMP10]] to <4 x float>
; CHECK-NEXT: [[TMP12:%.*]] = fdiv <4 x float> zeroinitializer, [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i1> poison, i1 [[V4]], i32 0
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i1> poison, i1 [[V4]], i64 0
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i1> [[TMP13]], <4 x i1> poison, <4 x i32> <i32 poison, i32 poison, i32 0, i32 0>
; CHECK-NEXT: [[TMP32:%.*]] = shufflevector <2 x i1> [[TMP6]], <2 x i1> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <4 x i1> [[TMP14]], <4 x i1> [[TMP32]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP16:%.*]] = select <4 x i1> [[TMP15]], <4 x float> zeroinitializer, <4 x float> [[TMP12]]
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x float> [[TMP16]], i32 3
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x float> [[TMP16]], i64 3
; CHECK-NEXT: [[CONV_I_I1743_3:%.*]] = fptoui float [[TMP17]] to i32
; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i32 [[CONV_I_I1743_3]], 0
; CHECK-NEXT: [[TMP19:%.*]] = bitcast <4 x float> [[TMP16]] to <4 x i32>
; CHECK-NEXT: [[TMP20:%.*]] = icmp ult <4 x i32> [[TMP19]], splat (i32 1333788672)
-; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i1> [[TMP20]], i32 3
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i1> [[TMP20]], i64 3
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP21]], i1 [[TMP18]], i1 false
-; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x float> [[TMP16]], i32 2
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x float> [[TMP16]], i64 2
; CHECK-NEXT: [[CONV_I_I1743_2:%.*]] = fptoui float [[TMP22]] to i32
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i1> [[TMP20]], i32 2
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i1> [[TMP20]], i64 2
; CHECK-NEXT: [[NARROW1:%.*]] = select i1 [[TMP23]], i32 [[CONV_I_I1743_2]], i32 0
; CHECK-NEXT: [[TMP24:%.*]] = zext i1 [[NARROW]] to i32
; CHECK-NEXT: [[TMP25:%.*]] = or i32 [[NARROW1]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x float> [[TMP16]], i32 1
+; CHECK-NEXT: [[TMP26:%.*]] = extractelement <4 x float> [[TMP16]], i64 1
; CHECK-NEXT: [[CONV_I_I1743_1:%.*]] = fptoui float [[TMP26]] to i32
-; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i1> [[TMP20]], i32 1
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i1> [[TMP20]], i64 1
; CHECK-NEXT: [[NARROW2:%.*]] = select i1 [[TMP27]], i32 [[CONV_I_I1743_1]], i32 0
; CHECK-NEXT: [[RV3:%.*]] = or i32 [[TMP25]], [[NARROW2]]
-; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x float> [[TMP16]], i32 0
+; CHECK-NEXT: [[TMP28:%.*]] = extractelement <4 x float> [[TMP16]], i64 0
; CHECK-NEXT: [[CONV_I_I1743:%.*]] = fptoui float [[TMP28]] to i32
-; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x i1> [[TMP20]], i32 0
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <4 x i1> [[TMP20]], i64 0
; CHECK-NEXT: [[NARROW4:%.*]] = select i1 [[TMP29]], i32 [[CONV_I_I1743]], i32 0
; CHECK-NEXT: [[RT5:%.*]] = or i32 [[RV3]], [[NARROW4]]
; CHECK-NEXT: [[RT:%.*]] = zext i32 [[RT5]] to i64
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/supernode.ll b/llvm/test/Transforms/SLPVectorizer/X86/supernode.ll
index 02fad2f0e7d41..717523079d19a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/supernode.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/supernode.ll
@@ -163,9 +163,9 @@ define void @supernode_scheduling(ptr %Aarray, ptr %Barray, ptr %Carray, ptr %Da
; ENABLED-NEXT: [[D:%.*]] = load double, ptr [[DARRAY:%.*]], align 8
; ENABLED-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[AARRAY:%.*]], align 8
; ENABLED-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[BARRAY:%.*]], align 8
-; ENABLED-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[C]], i32 0
+; ENABLED-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[C]], i64 0
; ENABLED-NEXT: [[TMP3:%.*]] = fadd fast <2 x double> [[TMP0]], [[TMP2]]
-; ENABLED-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP1]], double [[D]], i32 1
+; ENABLED-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP1]], double [[D]], i64 1
; ENABLED-NEXT: [[TMP5:%.*]] = fadd fast <2 x double> [[TMP3]], [[TMP4]]
; ENABLED-NEXT: store <2 x double> [[TMP5]], ptr [[SARRAY:%.*]], align 8
; ENABLED-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/tiny-tree.ll b/llvm/test/Transforms/SLPVectorizer/X86/tiny-tree.ll
index 6073a264b9b12..d592c49725483 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/tiny-tree.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/tiny-tree.ll
@@ -158,8 +158,8 @@ define void @tiny_tree_not_fully_vectorizable2(ptr noalias nocapture %dst, ptr n
; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[SRC_ADDR_021]], i64 2
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[ARRAYIDX4]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[TMP1]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: store <4 x float> [[TMP5]], ptr [[DST_ADDR_022]], align 4
@@ -205,7 +205,7 @@ for.end: ; preds = %for.body, %entry
define void @store_splat(ptr, float) {
; CHECK-LABEL: @store_splat(
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[TMP1:%.*]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[TMP1:%.*]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: store <4 x float> [[TMP4]], ptr [[TMP0:%.*]], align 4
; CHECK-NEXT: ret void
@@ -241,8 +241,8 @@ define void @tiny_vector_gather(ptr %a, ptr %v1, ptr %v2) {
; CHECK-LABEL: @tiny_vector_gather(
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[V1:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[V2:%.*]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> poison, i32 [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> poison, i32 [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[TMP2]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i32> [[TMP4]], <8 x i32> poison, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: store <8 x i32> [[TMP5]], ptr [[A:%.*]], align 16
; CHECK-NEXT: ret void
@@ -271,8 +271,8 @@ define void @tiny_vector_with_diff_opcode(ptr %a, ptr %v1) {
; CHECK-LABEL: @tiny_vector_with_diff_opcode(
; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[V1:%.*]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 undef to i16
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> poison, i16 [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> poison, i16 [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[TMP2]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i16> [[TMP4]], <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: store <8 x i16> [[TMP5]], ptr [[A:%.*]], align 16
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/trunc-store-value-ty-not-power-of-2.ll b/llvm/test/Transforms/SLPVectorizer/X86/trunc-store-value-ty-not-power-of-2.ll
index 2f0fad70b593b..b5ee5487ad497 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/trunc-store-value-ty-not-power-of-2.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/trunc-store-value-ty-not-power-of-2.ll
@@ -64,7 +64,7 @@ define void @test_8_trunc_i24_to_i8(i24 %x, ptr %A) {
; CHECK-LABEL: define void @test_8_trunc_i24_to_i8(
; CHECK-SAME: i24 [[X:%.*]], ptr [[A:%.*]]) {
; CHECK-NEXT: [[T:%.*]] = trunc i24 [[X]] to i8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[T]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[T]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: store <8 x i8> [[TMP2]], ptr [[A]], align 1
; CHECK-NEXT: ret void
@@ -92,7 +92,7 @@ define void @test_4_trunc_i24_to_i16(i24 %x, ptr %A) {
; CHECK-LABEL: define void @test_4_trunc_i24_to_i16(
; CHECK-SAME: i24 [[X:%.*]], ptr [[A:%.*]]) {
; CHECK-NEXT: [[T:%.*]] = trunc i24 [[X]] to i16
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[T]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[T]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: store <4 x i16> [[TMP2]], ptr [[A]], align 1
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/trunced-buildvector-scalar-extended.ll b/llvm/test/Transforms/SLPVectorizer/X86/trunced-buildvector-scalar-extended.ll
index 11b76256c42a4..9da7b52d4dc8b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/trunced-buildvector-scalar-extended.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/trunced-buildvector-scalar-extended.ll
@@ -5,13 +5,13 @@ define <4 x float> @test(i64 %0) {
; CHECK-LABEL: define <4 x float> @test(
; CHECK-SAME: i64 [[TMP0:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> <i64 0, i64 0, i64 poison, i64 0>, i64 [[TMP0]], i32 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> <i64 0, i64 0, i64 poison, i64 0>, i64 [[TMP0]], i64 2
; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i64> [[TMP3]] to <4 x i32>
; CHECK-NEXT: [[TMP13:%.*]] = sitofp i64 [[TMP0]] to float
; CHECK-NEXT: [[TMP14:%.*]] = sitofp i64 0 to float
; CHECK-NEXT: [[TMP5:%.*]] = sitofp <4 x i32> [[TMP2]] to <4 x float>
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float undef, float undef>, float [[TMP13]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP10]], float [[TMP14]], i32 3
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float undef, float undef>, float [[TMP13]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP8]], float [[TMP14]], i64 3
; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = fcmp ogt <4 x float> [[TMP6]], zeroinitializer
; CHECK-NEXT: ret <4 x float> [[TMP6]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/uitofp-with-signed-value-bitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/uitofp-with-signed-value-bitwidth.ll
index 9f0e8bc6bfa37..1998c8778875e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/uitofp-with-signed-value-bitwidth.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/uitofp-with-signed-value-bitwidth.ll
@@ -5,17 +5,17 @@ define i32 @test(ptr %d, i32 %0) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: ptr [[D:%.*]], i32 [[TMP0:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = sext <2 x i32> [[TMP2]] to <2 x i64>
; CHECK-NEXT: [[TMP3:%.*]] = uitofp <2 x i64> [[TMP8]] to <2 x double>
; CHECK-NEXT: [[TMP4:%.*]] = fdiv <2 x double> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = fcmp ogt <2 x double> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i1> [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i1> [[TMP5]], i64 1
; CHECK-NEXT: [[G_0_I_I:%.*]] = select i1 [[TMP6]], double 1.000000e+00, double 0.000000e+00
; CHECK-NEXT: [[CONV3_I_I:%.*]] = fptosi double [[G_0_I_I]] to i32
; CHECK-NEXT: store i32 [[CONV3_I_I]], ptr [[D]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP5]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP5]], i64 0
; CHECK-NEXT: br i1 [[TMP7]], label %[[K_EXIT:.*]], label %[[IF_THEN_I:.*]]
; CHECK: [[IF_THEN_I]]:
; CHECK-NEXT: unreachable
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll b/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
index e5fba188a5be3..38aebe9f47ca6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
@@ -22,7 +22,7 @@ define void @n() local_unnamed_addr #0 {
; CHECK-NEXT: [[B_0:%.*]] = phi i32 [ [[SPEC_SELECT8_3_7:%.*]], [[FOR_COND]] ], [ undef, [[ENTRY]] ]
; CHECK-NEXT: [[TMP29:%.*]] = trunc i64 [[INDVARS_IV]] to i32
; CHECK-NEXT: [[TMP30:%.*]] = add i32 [[TMP29]], -183
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP30]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP30]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP12:%.*]] = sub <4 x i32> [[TMP11]], [[TMP0]]
; CHECK-NEXT: [[TMP9:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP12]], i1 true)
@@ -30,122 +30,122 @@ define void @n() local_unnamed_addr #0 {
; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP37]], i32 [[B_0]])
; CHECK-NEXT: [[TMP16:%.*]] = sub <4 x i32> [[TMP11]], [[TMP1]]
; CHECK-NEXT: [[TMP17:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP16]], i1 true)
-; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i32> [[TMP17]], i32 0
+; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i32> [[TMP17]], i64 0
; CHECK-NEXT: [[SPEC_SELECT8_120:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP18]], i32 [[TMP15]])
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i32> [[TMP17]], i32 1
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i32> [[TMP17]], i64 1
; CHECK-NEXT: [[SPEC_SELECT8_1_1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP19]], i32 [[SPEC_SELECT8_120]])
-; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i32> [[TMP17]], i32 2
+; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i32> [[TMP17]], i64 2
; CHECK-NEXT: [[SPEC_SELECT8_2_1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP20]], i32 [[SPEC_SELECT8_1_1]])
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> poison, i32 [[TMP15]], i32 0
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i32> [[TMP21]], i32 [[SPEC_SELECT8_120]], i32 1
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i32> [[TMP22]], i32 [[SPEC_SELECT8_1_1]], i32 2
-; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> [[TMP23]], i32 [[SPEC_SELECT8_2_1]], i32 3
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> poison, i32 [[TMP15]], i64 0
+; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i32> [[TMP21]], i32 [[SPEC_SELECT8_120]], i64 1
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i32> [[TMP22]], i32 [[SPEC_SELECT8_1_1]], i64 2
+; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> [[TMP23]], i32 [[SPEC_SELECT8_2_1]], i64 3
; CHECK-NEXT: [[TMP25:%.*]] = icmp slt <4 x i32> [[TMP17]], [[TMP24]]
; CHECK-NEXT: [[NARROW35:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP25]])
; CHECK-NEXT: [[SPEC_SELECT_3_1:%.*]] = zext i1 [[NARROW35]] to i32
-; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP17]], i32 3
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <4 x i32> [[TMP17]], i64 3
; CHECK-NEXT: [[SPEC_SELECT8_3_1:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP27]], i32 [[SPEC_SELECT8_2_1]])
; CHECK-NEXT: [[TMP28:%.*]] = sub <4 x i32> [[TMP11]], [[TMP2]]
; CHECK-NEXT: [[TMP38:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP28]], i1 true)
-; CHECK-NEXT: [[TMP50:%.*]] = extractelement <4 x i32> [[TMP38]], i32 0
+; CHECK-NEXT: [[TMP50:%.*]] = extractelement <4 x i32> [[TMP38]], i64 0
; CHECK-NEXT: [[SPEC_SELECT8_226:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP50]], i32 [[SPEC_SELECT8_3_1]])
-; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i32> [[TMP38]], i32 1
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <4 x i32> [[TMP38]], i64 1
; CHECK-NEXT: [[SPEC_SELECT8_1_2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP31]], i32 [[SPEC_SELECT8_226]])
-; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x i32> [[TMP38]], i32 2
+; CHECK-NEXT: [[TMP32:%.*]] = extractelement <4 x i32> [[TMP38]], i64 2
; CHECK-NEXT: [[SPEC_SELECT8_2_2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP32]], i32 [[SPEC_SELECT8_1_2]])
-; CHECK-NEXT: [[TMP33:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_1]], i32 0
-; CHECK-NEXT: [[TMP34:%.*]] = insertelement <4 x i32> [[TMP33]], i32 [[SPEC_SELECT8_226]], i32 1
-; CHECK-NEXT: [[TMP35:%.*]] = insertelement <4 x i32> [[TMP34]], i32 [[SPEC_SELECT8_1_2]], i32 2
-; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i32> [[TMP35]], i32 [[SPEC_SELECT8_2_2]], i32 3
+; CHECK-NEXT: [[TMP33:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_1]], i64 0
+; CHECK-NEXT: [[TMP34:%.*]] = insertelement <4 x i32> [[TMP33]], i32 [[SPEC_SELECT8_226]], i64 1
+; CHECK-NEXT: [[TMP35:%.*]] = insertelement <4 x i32> [[TMP34]], i32 [[SPEC_SELECT8_1_2]], i64 2
+; CHECK-NEXT: [[TMP36:%.*]] = insertelement <4 x i32> [[TMP35]], i32 [[SPEC_SELECT8_2_2]], i64 3
; CHECK-NEXT: [[TMP62:%.*]] = icmp slt <4 x i32> [[TMP38]], [[TMP36]]
; CHECK-NEXT: [[TMP56:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP62]])
; CHECK-NEXT: [[SPEC_SELECT_3_2:%.*]] = select i1 [[TMP56]], i32 2, i32 [[SPEC_SELECT_3_1]]
-; CHECK-NEXT: [[TMP39:%.*]] = extractelement <4 x i32> [[TMP38]], i32 3
+; CHECK-NEXT: [[TMP39:%.*]] = extractelement <4 x i32> [[TMP38]], i64 3
; CHECK-NEXT: [[SPEC_SELECT8_3_2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP39]], i32 [[SPEC_SELECT8_2_2]])
; CHECK-NEXT: [[TMP40:%.*]] = sub <4 x i32> [[TMP11]], [[TMP3]]
; CHECK-NEXT: [[TMP41:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP40]], i1 true)
-; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i32> [[TMP41]], i32 0
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i32> [[TMP41]], i64 0
; CHECK-NEXT: [[SPEC_SELECT8_332:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP42]], i32 [[SPEC_SELECT8_3_2]])
-; CHECK-NEXT: [[TMP43:%.*]] = extractelement <4 x i32> [[TMP41]], i32 1
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <4 x i32> [[TMP41]], i64 1
; CHECK-NEXT: [[SPEC_SELECT8_1_3:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP43]], i32 [[SPEC_SELECT8_332]])
-; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i32> [[TMP41]], i32 2
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i32> [[TMP41]], i64 2
; CHECK-NEXT: [[SPEC_SELECT8_2_3:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP44]], i32 [[SPEC_SELECT8_1_3]])
-; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_2]], i32 0
-; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i32> [[TMP45]], i32 [[SPEC_SELECT8_332]], i32 1
-; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i32> [[TMP46]], i32 [[SPEC_SELECT8_1_3]], i32 2
-; CHECK-NEXT: [[TMP48:%.*]] = insertelement <4 x i32> [[TMP47]], i32 [[SPEC_SELECT8_2_3]], i32 3
+; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_2]], i64 0
+; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i32> [[TMP45]], i32 [[SPEC_SELECT8_332]], i64 1
+; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i32> [[TMP46]], i32 [[SPEC_SELECT8_1_3]], i64 2
+; CHECK-NEXT: [[TMP48:%.*]] = insertelement <4 x i32> [[TMP47]], i32 [[SPEC_SELECT8_2_3]], i64 3
; CHECK-NEXT: [[TMP49:%.*]] = icmp slt <4 x i32> [[TMP41]], [[TMP48]]
; CHECK-NEXT: [[TMP67:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP49]])
; CHECK-NEXT: [[SPEC_SELECT_3_3:%.*]] = select i1 [[TMP67]], i32 3, i32 [[SPEC_SELECT_3_2]]
-; CHECK-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[TMP41]], i32 3
+; CHECK-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[TMP41]], i64 3
; CHECK-NEXT: [[SPEC_SELECT8_3_3:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP51]], i32 [[SPEC_SELECT8_2_3]])
; CHECK-NEXT: [[TMP52:%.*]] = sub <4 x i32> [[TMP11]], [[TMP4]]
; CHECK-NEXT: [[TMP53:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP52]], i1 true)
-; CHECK-NEXT: [[TMP54:%.*]] = extractelement <4 x i32> [[TMP53]], i32 0
+; CHECK-NEXT: [[TMP54:%.*]] = extractelement <4 x i32> [[TMP53]], i64 0
; CHECK-NEXT: [[SPEC_SELECT8_4:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP54]], i32 [[SPEC_SELECT8_3_3]])
-; CHECK-NEXT: [[TMP55:%.*]] = extractelement <4 x i32> [[TMP53]], i32 1
+; CHECK-NEXT: [[TMP55:%.*]] = extractelement <4 x i32> [[TMP53]], i64 1
; CHECK-NEXT: [[SPEC_SELECT8_1_4:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP55]], i32 [[SPEC_SELECT8_4]])
-; CHECK-NEXT: [[TMP74:%.*]] = extractelement <4 x i32> [[TMP53]], i32 2
+; CHECK-NEXT: [[TMP74:%.*]] = extractelement <4 x i32> [[TMP53]], i64 2
; CHECK-NEXT: [[SPEC_SELECT8_2_4:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP74]], i32 [[SPEC_SELECT8_1_4]])
-; CHECK-NEXT: [[TMP57:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_3]], i32 0
-; CHECK-NEXT: [[TMP58:%.*]] = insertelement <4 x i32> [[TMP57]], i32 [[SPEC_SELECT8_4]], i32 1
-; CHECK-NEXT: [[TMP59:%.*]] = insertelement <4 x i32> [[TMP58]], i32 [[SPEC_SELECT8_1_4]], i32 2
-; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i32> [[TMP59]], i32 [[SPEC_SELECT8_2_4]], i32 3
+; CHECK-NEXT: [[TMP57:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_3]], i64 0
+; CHECK-NEXT: [[TMP58:%.*]] = insertelement <4 x i32> [[TMP57]], i32 [[SPEC_SELECT8_4]], i64 1
+; CHECK-NEXT: [[TMP59:%.*]] = insertelement <4 x i32> [[TMP58]], i32 [[SPEC_SELECT8_1_4]], i64 2
+; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i32> [[TMP59]], i32 [[SPEC_SELECT8_2_4]], i64 3
; CHECK-NEXT: [[TMP61:%.*]] = icmp slt <4 x i32> [[TMP53]], [[TMP60]]
; CHECK-NEXT: [[TMP78:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP61]])
; CHECK-NEXT: [[SPEC_SELECT_3_4:%.*]] = select i1 [[TMP78]], i32 4, i32 [[SPEC_SELECT_3_3]]
-; CHECK-NEXT: [[TMP63:%.*]] = extractelement <4 x i32> [[TMP53]], i32 3
+; CHECK-NEXT: [[TMP63:%.*]] = extractelement <4 x i32> [[TMP53]], i64 3
; CHECK-NEXT: [[SPEC_SELECT8_3_4:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP63]], i32 [[SPEC_SELECT8_2_4]])
; CHECK-NEXT: [[TMP64:%.*]] = sub <4 x i32> [[TMP11]], [[TMP5]]
; CHECK-NEXT: [[TMP65:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP64]], i1 true)
-; CHECK-NEXT: [[TMP66:%.*]] = extractelement <4 x i32> [[TMP65]], i32 0
+; CHECK-NEXT: [[TMP66:%.*]] = extractelement <4 x i32> [[TMP65]], i64 0
; CHECK-NEXT: [[SPEC_SELECT8_5:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP66]], i32 [[SPEC_SELECT8_3_4]])
-; CHECK-NEXT: [[TMP86:%.*]] = extractelement <4 x i32> [[TMP65]], i32 1
+; CHECK-NEXT: [[TMP86:%.*]] = extractelement <4 x i32> [[TMP65]], i64 1
; CHECK-NEXT: [[SPEC_SELECT8_1_5:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP86]], i32 [[SPEC_SELECT8_5]])
-; CHECK-NEXT: [[TMP68:%.*]] = extractelement <4 x i32> [[TMP65]], i32 2
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <4 x i32> [[TMP65]], i64 2
; CHECK-NEXT: [[SPEC_SELECT8_2_5:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP68]], i32 [[SPEC_SELECT8_1_5]])
-; CHECK-NEXT: [[TMP69:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_4]], i32 0
-; CHECK-NEXT: [[TMP70:%.*]] = insertelement <4 x i32> [[TMP69]], i32 [[SPEC_SELECT8_5]], i32 1
-; CHECK-NEXT: [[TMP71:%.*]] = insertelement <4 x i32> [[TMP70]], i32 [[SPEC_SELECT8_1_5]], i32 2
-; CHECK-NEXT: [[TMP72:%.*]] = insertelement <4 x i32> [[TMP71]], i32 [[SPEC_SELECT8_2_5]], i32 3
+; CHECK-NEXT: [[TMP69:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_4]], i64 0
+; CHECK-NEXT: [[TMP70:%.*]] = insertelement <4 x i32> [[TMP69]], i32 [[SPEC_SELECT8_5]], i64 1
+; CHECK-NEXT: [[TMP71:%.*]] = insertelement <4 x i32> [[TMP70]], i32 [[SPEC_SELECT8_1_5]], i64 2
+; CHECK-NEXT: [[TMP72:%.*]] = insertelement <4 x i32> [[TMP71]], i32 [[SPEC_SELECT8_2_5]], i64 3
; CHECK-NEXT: [[TMP73:%.*]] = icmp slt <4 x i32> [[TMP65]], [[TMP72]]
; CHECK-NEXT: [[TMP89:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP73]])
; CHECK-NEXT: [[SPEC_SELECT_3_5:%.*]] = select i1 [[TMP89]], i32 5, i32 [[SPEC_SELECT_3_4]]
-; CHECK-NEXT: [[TMP75:%.*]] = extractelement <4 x i32> [[TMP65]], i32 3
+; CHECK-NEXT: [[TMP75:%.*]] = extractelement <4 x i32> [[TMP65]], i64 3
; CHECK-NEXT: [[SPEC_SELECT8_3_5:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP75]], i32 [[SPEC_SELECT8_2_5]])
; CHECK-NEXT: [[TMP76:%.*]] = sub <4 x i32> [[TMP11]], [[TMP6]]
; CHECK-NEXT: [[TMP77:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP76]], i1 true)
-; CHECK-NEXT: [[TMP98:%.*]] = extractelement <4 x i32> [[TMP77]], i32 0
+; CHECK-NEXT: [[TMP98:%.*]] = extractelement <4 x i32> [[TMP77]], i64 0
; CHECK-NEXT: [[SPEC_SELECT8_6:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP98]], i32 [[SPEC_SELECT8_3_5]])
-; CHECK-NEXT: [[TMP79:%.*]] = extractelement <4 x i32> [[TMP77]], i32 1
+; CHECK-NEXT: [[TMP79:%.*]] = extractelement <4 x i32> [[TMP77]], i64 1
; CHECK-NEXT: [[SPEC_SELECT8_1_6:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP79]], i32 [[SPEC_SELECT8_6]])
-; CHECK-NEXT: [[TMP80:%.*]] = extractelement <4 x i32> [[TMP77]], i32 2
+; CHECK-NEXT: [[TMP80:%.*]] = extractelement <4 x i32> [[TMP77]], i64 2
; CHECK-NEXT: [[SPEC_SELECT8_2_6:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP80]], i32 [[SPEC_SELECT8_1_6]])
-; CHECK-NEXT: [[TMP81:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_5]], i32 0
-; CHECK-NEXT: [[TMP82:%.*]] = insertelement <4 x i32> [[TMP81]], i32 [[SPEC_SELECT8_6]], i32 1
-; CHECK-NEXT: [[TMP83:%.*]] = insertelement <4 x i32> [[TMP82]], i32 [[SPEC_SELECT8_1_6]], i32 2
-; CHECK-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> [[TMP83]], i32 [[SPEC_SELECT8_2_6]], i32 3
+; CHECK-NEXT: [[TMP81:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_5]], i64 0
+; CHECK-NEXT: [[TMP82:%.*]] = insertelement <4 x i32> [[TMP81]], i32 [[SPEC_SELECT8_6]], i64 1
+; CHECK-NEXT: [[TMP83:%.*]] = insertelement <4 x i32> [[TMP82]], i32 [[SPEC_SELECT8_1_6]], i64 2
+; CHECK-NEXT: [[TMP84:%.*]] = insertelement <4 x i32> [[TMP83]], i32 [[SPEC_SELECT8_2_6]], i64 3
; CHECK-NEXT: [[TMP85:%.*]] = icmp slt <4 x i32> [[TMP77]], [[TMP84]]
; CHECK-NEXT: [[TMP100:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP85]])
; CHECK-NEXT: [[SPEC_SELECT_3_6:%.*]] = select i1 [[TMP100]], i32 6, i32 [[SPEC_SELECT_3_5]]
-; CHECK-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[TMP77]], i32 3
+; CHECK-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[TMP77]], i64 3
; CHECK-NEXT: [[SPEC_SELECT8_3_6:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP87]], i32 [[SPEC_SELECT8_2_6]])
; CHECK-NEXT: [[TMP88:%.*]] = sub <4 x i32> [[TMP11]], [[TMP7]]
; CHECK-NEXT: [[TMP101:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP88]], i1 true)
-; CHECK-NEXT: [[TMP90:%.*]] = extractelement <4 x i32> [[TMP101]], i32 0
+; CHECK-NEXT: [[TMP90:%.*]] = extractelement <4 x i32> [[TMP101]], i64 0
; CHECK-NEXT: [[SPEC_SELECT8_7:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP90]], i32 [[SPEC_SELECT8_3_6]])
-; CHECK-NEXT: [[TMP91:%.*]] = extractelement <4 x i32> [[TMP101]], i32 1
+; CHECK-NEXT: [[TMP91:%.*]] = extractelement <4 x i32> [[TMP101]], i64 1
; CHECK-NEXT: [[SPEC_SELECT8_1_7:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP91]], i32 [[SPEC_SELECT8_7]])
-; CHECK-NEXT: [[TMP92:%.*]] = extractelement <4 x i32> [[TMP101]], i32 2
+; CHECK-NEXT: [[TMP92:%.*]] = extractelement <4 x i32> [[TMP101]], i64 2
; CHECK-NEXT: [[SPEC_SELECT8_2_7:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP92]], i32 [[SPEC_SELECT8_1_7]])
-; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_6]], i32 0
-; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[SPEC_SELECT8_7]], i32 1
-; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[SPEC_SELECT8_1_7]], i32 2
-; CHECK-NEXT: [[TMP96:%.*]] = insertelement <4 x i32> [[TMP95]], i32 [[SPEC_SELECT8_2_7]], i32 3
+; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> poison, i32 [[SPEC_SELECT8_3_6]], i64 0
+; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[SPEC_SELECT8_7]], i64 1
+; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[SPEC_SELECT8_1_7]], i64 2
+; CHECK-NEXT: [[TMP96:%.*]] = insertelement <4 x i32> [[TMP95]], i32 [[SPEC_SELECT8_2_7]], i64 3
; CHECK-NEXT: [[TMP97:%.*]] = icmp slt <4 x i32> [[TMP101]], [[TMP96]]
; CHECK-NEXT: [[TMP111:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP97]])
; CHECK-NEXT: [[SPEC_SELECT_3_7:%.*]] = select i1 [[TMP111]], i32 7, i32 [[SPEC_SELECT_3_6]]
-; CHECK-NEXT: [[TMP99:%.*]] = extractelement <4 x i32> [[TMP101]], i32 3
+; CHECK-NEXT: [[TMP99:%.*]] = extractelement <4 x i32> [[TMP101]], i64 3
; CHECK-NEXT: [[SPEC_SELECT8_3_7]] = call i32 @llvm.smin.i32(i32 [[TMP99]], i32 [[SPEC_SELECT8_2_7]])
; CHECK-NEXT: [[K:%.*]] = getelementptr inbounds [4 x i8], ptr @l, i64 [[INDVARS_IV]]
; CHECK-NEXT: store i32 [[SPEC_SELECT_3_7]], ptr [[K]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/user-node-with-same-last-instr.ll b/llvm/test/Transforms/SLPVectorizer/X86/user-node-with-same-last-instr.ll
index c3135f19a326d..7b887ed1f7886 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/user-node-with-same-last-instr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/user-node-with-same-last-instr.ll
@@ -10,8 +10,8 @@ define void @wombat(i32 %arg) {
; CHECK-NEXT: br i1 false, label %[[BB2:.*]], label %[[BB5:.*]]
; CHECK: [[BB2]]:
; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ [[TMP4:%.*]], %[[BB4:.*]] ], [ zeroinitializer, %[[BB1]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 poison, i32 1>, i32 [[ARG]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 poison, i32 1>, i32 [[ARG]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP4]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> <i32 0, i32 3>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll b/llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll
index edf628d010f7a..5646ea61af73d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/user-with-multi-copyable-ops.ll
@@ -10,18 +10,18 @@ define void @test(ptr %this, ptr %0, double %1) {
; CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[THIS]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[TMP0]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[THIS]], align 8
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x double> <double 1.000000e+00, double poison>, double [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x double> <double 1.000000e+00, double poison>, double [[TMP1]], i64 1
; CHECK-NEXT: [[TMP23:%.*]] = fmul <2 x double> <double 1.000000e+00, double 0.000000e+00>, [[TMP13]]
; CHECK-NEXT: [[TMP22:%.*]] = shufflevector <2 x double> [[TMP23]], <2 x double> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <3 x i32> <i32 1, i32 poison, i32 0>
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <3 x double> [[TMP8]], double [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <3 x double> [[TMP8]], double [[TMP4]], i64 1
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <3 x double> [[TMP9]], <3 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 1>
; CHECK-NEXT: [[TMP11:%.*]] = fmul <4 x double> [[TMP10]], <double 1.000000e+00, double 0.000000e+00, double 1.000000e+00, double 1.000000e+00>
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x double> <double poison, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>, double [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x double> <double poison, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>, double [[TMP4]], i64 0
; CHECK-NEXT: [[TMP27:%.*]] = fmul <4 x double> zeroinitializer, [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <3 x double> [[TMP9]], <3 x double> poison, <4 x i32> <i32 2, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[TMP15:%.*]] = fmul <4 x double> [[TMP14]], <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 0.000000e+00>
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x double> <double 1.000000e+00, double 1.000000e+00, double poison, double 1.000000e+00>, double [[TMP4]], i32 2
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x double> <double 1.000000e+00, double 1.000000e+00, double poison, double 1.000000e+00>, double [[TMP4]], i64 2
; CHECK-NEXT: [[TMP17:%.*]] = fmul <4 x double> zeroinitializer, [[TMP16]]
; CHECK-NEXT: [[TMP18:%.*]] = fneg <4 x double> [[TMP11]]
; CHECK-NEXT: [[TMP19:%.*]] = fneg <4 x double> [[TMP15]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll b/llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
index 4c394f6805cce..ae36b559e50cd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
@@ -293,7 +293,7 @@ define void @vec3_fpext_cost(ptr %Colour, float %0) {
; CHECK-LABEL: @vec3_fpext_cost(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ARRAYIDX80:%.*]] = getelementptr float, ptr [[COLOUR:%.*]], i64 2
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0:%.*]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = fpext <2 x float> [[TMP2]] to <2 x double>
; CHECK-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP3]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
@@ -350,11 +350,11 @@ define void @fpext_gather(ptr %dst, double %conv) {
;
; NO-INST-COUNT-LABEL: @fpext_gather(
; NO-INST-COUNT-NEXT: entry:
-; NO-INST-COUNT-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV:%.*]], i32 0
+; NO-INST-COUNT-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV:%.*]], i64 0
; NO-INST-COUNT-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer
; NO-INST-COUNT-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float>
; NO-INST-COUNT-NEXT: [[LENGTHS:%.*]] = getelementptr float, ptr [[DST:%.*]], i64 0
-; NO-INST-COUNT-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
+; NO-INST-COUNT-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
; NO-INST-COUNT-NEXT: store float [[TMP3]], ptr [[LENGTHS]], align 4
; NO-INST-COUNT-NEXT: [[ARRAYIDX32:%.*]] = getelementptr float, ptr [[DST]], i64 1
; NO-INST-COUNT-NEXT: store <2 x float> [[TMP2]], ptr [[ARRAYIDX32]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll b/llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll
index fd3c1a57aff34..8552b0e26f007 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vec3-calls.ll
@@ -6,7 +6,7 @@ define void @vec3_vectorize_call(ptr %Colour, float %0) {
; NON-POW2-LABEL: @vec3_vectorize_call(
; NON-POW2-NEXT: entry:
; NON-POW2-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[COLOUR:%.*]], align 4
-; NON-POW2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP0:%.*]], i32 2
+; NON-POW2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP0:%.*]], i64 2
; NON-POW2-NEXT: [[TMP3:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; NON-POW2-NEXT: [[TMP4:%.*]] = shufflevector <3 x float> [[TMP2]], <3 x float> [[TMP3]], <3 x i32> <i32 3, i32 4, i32 2>
; NON-POW2-NEXT: [[TMP5:%.*]] = call <3 x float> @llvm.fmuladd.v3f32(<3 x float> [[TMP4]], <3 x float> zeroinitializer, <3 x float> zeroinitializer)
@@ -41,7 +41,7 @@ define void @vec3_fmuladd_64(ptr %Colour, double %0) {
; CHECK-LABEL: @vec3_fmuladd_64(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ARRAYIDX80:%.*]] = getelementptr float, ptr [[COLOUR:%.*]], i64 2
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP2]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
; CHECK-NEXT: [[TMP4:%.*]] = fptrunc <2 x double> [[TMP3]] to <2 x float>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vec3-gather-some-loads.ll b/llvm/test/Transforms/SLPVectorizer/X86/vec3-gather-some-loads.ll
index e8adda0bdc703..ad20f0031bca3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vec3-gather-some-loads.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vec3-gather-some-loads.ll
@@ -14,12 +14,12 @@ define void @test_insert_loads(ptr %A, ptr noalias %B, float %0) #0 {
; NON-POW2-NEXT: [[L_A_12:%.*]] = load float, ptr [[A_12]], align 4
; NON-POW2-NEXT: [[GEP_4:%.*]] = getelementptr i8, ptr [[B]], i64 4
; NON-POW2-NEXT: [[L_B_0:%.*]] = load float, ptr [[B]], align 4
-; NON-POW2-NEXT: [[TMP1:%.*]] = insertelement <7 x float> poison, float [[TMP0]], i32 0
+; NON-POW2-NEXT: [[TMP1:%.*]] = insertelement <7 x float> poison, float [[TMP0]], i64 0
; NON-POW2-NEXT: [[TMP2:%.*]] = shufflevector <7 x float> [[TMP1]], <7 x float> poison, <7 x i32> zeroinitializer
-; NON-POW2-NEXT: [[TMP3:%.*]] = insertelement <7 x float> <float poison, float poison, float poison, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>, float [[L_A_12]], i32 0
-; NON-POW2-NEXT: [[TMP4:%.*]] = insertelement <7 x float> [[TMP3]], float [[L_A_28]], i32 1
+; NON-POW2-NEXT: [[TMP3:%.*]] = insertelement <7 x float> <float poison, float poison, float poison, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>, float [[L_A_12]], i64 0
+; NON-POW2-NEXT: [[TMP4:%.*]] = insertelement <7 x float> [[TMP3]], float [[L_A_28]], i64 1
; NON-POW2-NEXT: [[TMP5:%.*]] = shufflevector <7 x float> [[TMP4]], <7 x float> poison, <7 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6>
-; NON-POW2-NEXT: [[TMP6:%.*]] = insertelement <7 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>, float [[L_B_0]], i32 0
+; NON-POW2-NEXT: [[TMP6:%.*]] = insertelement <7 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>, float [[L_B_0]], i64 0
; NON-POW2-NEXT: [[TMP7:%.*]] = call <7 x float> @llvm.fmuladd.v7f32(<7 x float> [[TMP2]], <7 x float> [[TMP5]], <7 x float> [[TMP6]])
; NON-POW2-NEXT: store <7 x float> [[TMP7]], ptr [[GEP_4]], align 4
; NON-POW2-NEXT: ret void
@@ -28,7 +28,7 @@ define void @test_insert_loads(ptr %A, ptr noalias %B, float %0) #0 {
; POW2-ONLY-SAME: ptr [[A:%.*]], ptr noalias [[B:%.*]], float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
; POW2-ONLY-NEXT: entry:
; POW2-ONLY-NEXT: [[MULADD_0:%.*]] = tail call float @llvm.fmuladd.f32(float [[TMP0]], float 1.000000e+00, float 1.000000e+00)
-; POW2-ONLY-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 0
+; POW2-ONLY-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i64 0
; POW2-ONLY-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
; POW2-ONLY-NEXT: [[TMP3:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[TMP2]], <2 x float> <float 3.000000e+00, float 2.000000e+00>, <2 x float> <float 3.000000e+00, float 2.000000e+00>)
; POW2-ONLY-NEXT: [[A_28:%.*]] = getelementptr i8, ptr [[A]], i64 28
@@ -39,12 +39,12 @@ define void @test_insert_loads(ptr %A, ptr noalias %B, float %0) #0 {
; POW2-ONLY-NEXT: [[L_B_0:%.*]] = load float, ptr [[B]], align 4
; POW2-ONLY-NEXT: [[GEP_28:%.*]] = getelementptr i8, ptr [[B]], i64 28
; POW2-ONLY-NEXT: [[GEP_20:%.*]] = getelementptr i8, ptr [[B]], i64 20
-; POW2-ONLY-NEXT: [[TMP4:%.*]] = insertelement <4 x float> poison, float [[TMP0]], i32 0
+; POW2-ONLY-NEXT: [[TMP4:%.*]] = insertelement <4 x float> poison, float [[TMP0]], i64 0
; POW2-ONLY-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> poison, <4 x i32> zeroinitializer
-; POW2-ONLY-NEXT: [[TMP6:%.*]] = insertelement <4 x float> <float poison, float poison, float poison, float 4.000000e+00>, float [[L_A_12]], i32 0
-; POW2-ONLY-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[TMP6]], float [[L_A_28]], i32 1
+; POW2-ONLY-NEXT: [[TMP6:%.*]] = insertelement <4 x float> <float poison, float poison, float poison, float 4.000000e+00>, float [[L_A_12]], i64 0
+; POW2-ONLY-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[TMP6]], float [[L_A_28]], i64 1
; POW2-ONLY-NEXT: [[TMP8:%.*]] = shufflevector <4 x float> [[TMP7]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 3>
-; POW2-ONLY-NEXT: [[TMP9:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 4.000000e+00>, float [[L_B_0]], i32 0
+; POW2-ONLY-NEXT: [[TMP9:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 4.000000e+00>, float [[L_B_0]], i64 0
; POW2-ONLY-NEXT: [[TMP10:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP5]], <4 x float> [[TMP8]], <4 x float> [[TMP9]])
; POW2-ONLY-NEXT: store <4 x float> [[TMP10]], ptr [[GEP_4]], align 4
; POW2-ONLY-NEXT: store <2 x float> [[TMP3]], ptr [[GEP_20]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll b/llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
index b7b26d18dc115..adefe58ff51fe 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
@@ -74,13 +74,13 @@ define void @extract_mask(ptr %object, double %conv503, double %conv520) {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[BBOX483]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[CONV503]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[CONV503]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = fcmp ogt <2 x double> [[TMP4]], <double 0.000000e+00, double -2.000000e+10>
; CHECK-NEXT: [[TMP6:%.*]] = select <2 x i1> [[TMP5]], <2 x double> [[TMP3]], <2 x double> <double 0.000000e+00, double -2.000000e+10>
; CHECK-NEXT: [[TMP7:%.*]] = fsub <2 x double> zeroinitializer, [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = fptrunc <2 x double> [[TMP7]] to <2 x float>
-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP8]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x float> [[TMP8]], i32 1
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP8]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x float> [[TMP8]], i64 1
; CHECK-NEXT: [[MUL646:%.*]] = fmul float [[TMP9]], [[TMP10]]
; CHECK-NEXT: [[CMP663:%.*]] = fcmp olt float [[MUL646]], 0.000000e+00
; CHECK-NEXT: br i1 [[CMP663]], label [[IF_THEN665:%.*]], label [[IF_END668:%.*]]
@@ -90,7 +90,7 @@ define void @extract_mask(ptr %object, double %conv503, double %conv520) {
; CHECK-NEXT: [[CONV613:%.*]] = fptrunc double [[CONV503]] to float
; CHECK-NEXT: store float [[CONV613]], ptr [[BBOX651]], align 8
; CHECK-NEXT: [[BBOX_SROA_6_0_BBOX666_SROA_IDX:%.*]] = getelementptr float, ptr [[OBJECT]], i64 1
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x double> [[TMP6]], double [[CONV520]], i32 1
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x double> [[TMP6]], double [[CONV520]], i64 1
; CHECK-NEXT: [[TMP12:%.*]] = fptrunc <2 x double> [[TMP11]] to <2 x float>
; CHECK-NEXT: store <2 x float> [[TMP12]], ptr [[BBOX_SROA_6_0_BBOX666_SROA_IDX]], align 4
; CHECK-NEXT: store <2 x float> [[TMP8]], ptr [[ARRAYIDX656]], align 8
@@ -142,9 +142,9 @@ define void @gather_2(ptr %mat1, float %0, float %1) {
; NON-POW2-LABEL: define void @gather_2(
; NON-POW2-SAME: ptr [[MAT1:%.*]], float [[TMP0:%.*]], float [[TMP1:%.*]]) {
; NON-POW2-NEXT: entry:
-; NON-POW2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP0]], i32 0
+; NON-POW2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP0]], i64 0
; NON-POW2-NEXT: [[TMP4:%.*]] = shufflevector <3 x float> [[TMP2]], <3 x float> poison, <3 x i32> zeroinitializer
-; NON-POW2-NEXT: [[TMP5:%.*]] = insertelement <3 x float> <float 0.000000e+00, float poison, float poison>, float [[TMP1]], i32 1
+; NON-POW2-NEXT: [[TMP5:%.*]] = insertelement <3 x float> <float 0.000000e+00, float poison, float poison>, float [[TMP1]], i64 1
; NON-POW2-NEXT: [[TMP6:%.*]] = shufflevector <3 x float> [[TMP5]], <3 x float> poison, <3 x i32> <i32 0, i32 1, i32 1>
; NON-POW2-NEXT: [[TMP7:%.*]] = call <3 x float> @llvm.fmuladd.v3f32(<3 x float> [[TMP4]], <3 x float> [[TMP6]], <3 x float> zeroinitializer)
; NON-POW2-NEXT: [[ARRAYIDX163:%.*]] = getelementptr [4 x [4 x float]], ptr [[MAT1]], i64 0, i64 1
@@ -155,9 +155,9 @@ define void @gather_2(ptr %mat1, float %0, float %1) {
; POW2-ONLY-LABEL: define void @gather_2(
; POW2-ONLY-SAME: ptr [[MAT1:%.*]], float [[TMP0:%.*]], float [[TMP1:%.*]]) {
; POW2-ONLY-NEXT: entry:
-; POW2-ONLY-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 0
+; POW2-ONLY-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i64 0
; POW2-ONLY-NEXT: [[TMP3:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <2 x i32> zeroinitializer
-; POW2-ONLY-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP1]], i32 1
+; POW2-ONLY-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP1]], i64 1
; POW2-ONLY-NEXT: [[TMP5:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[TMP3]], <2 x float> [[TMP4]], <2 x float> zeroinitializer)
; POW2-ONLY-NEXT: [[TMP6:%.*]] = call float @llvm.fmuladd.f32(float [[TMP0]], float [[TMP1]], float 0.000000e+00)
; POW2-ONLY-NEXT: [[TMP7:%.*]] = fmul float [[TMP6]], 0.000000e+00
@@ -192,7 +192,7 @@ define i32 @reorder_indices_1(float %0) {
; NON-POW2-NEXT: [[TMP1:%.*]] = load <3 x float>, ptr [[NOR1]], align 4
; NON-POW2-NEXT: [[TMP2:%.*]] = shufflevector <3 x float> [[TMP1]], <3 x float> poison, <3 x i32> <i32 1, i32 2, i32 0>
; NON-POW2-NEXT: [[TMP3:%.*]] = fneg <3 x float> [[TMP2]]
-; NON-POW2-NEXT: [[TMP4:%.*]] = insertelement <3 x float> poison, float [[TMP0]], i32 0
+; NON-POW2-NEXT: [[TMP4:%.*]] = insertelement <3 x float> poison, float [[TMP0]], i64 0
; NON-POW2-NEXT: [[TMP5:%.*]] = shufflevector <3 x float> [[TMP4]], <3 x float> poison, <3 x i32> zeroinitializer
; NON-POW2-NEXT: [[TMP6:%.*]] = fmul <3 x float> [[TMP3]], [[TMP5]]
; NON-POW2-NEXT: [[TMP7:%.*]] = call <3 x float> @llvm.fmuladd.v3f32(<3 x float> [[TMP1]], <3 x float> zeroinitializer, <3 x float> [[TMP6]])
@@ -210,12 +210,12 @@ define i32 @reorder_indices_1(float %0) {
; POW2-ONLY-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX2_I265]], align 4
; POW2-ONLY-NEXT: [[TMP7:%.*]] = load <2 x float>, ptr [[ARRAYIDX_I]], align 4
; POW2-ONLY-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[NOR1]], align 4
-; POW2-ONLY-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
+; POW2-ONLY-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
; POW2-ONLY-NEXT: [[TMP4:%.*]] = fneg float [[TMP3]]
; POW2-ONLY-NEXT: [[NEG11_I:%.*]] = fmul float [[TMP4]], [[TMP0]]
; POW2-ONLY-NEXT: [[TMP5:%.*]] = call float @llvm.fmuladd.f32(float [[TMP1]], float 0.000000e+00, float [[NEG11_I]])
; POW2-ONLY-NEXT: [[TMP8:%.*]] = fneg <2 x float> [[TMP7]]
-; POW2-ONLY-NEXT: [[TMP9:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 0
+; POW2-ONLY-NEXT: [[TMP9:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i64 0
; POW2-ONLY-NEXT: [[TMP10:%.*]] = shufflevector <2 x float> [[TMP9]], <2 x float> poison, <2 x i32> zeroinitializer
; POW2-ONLY-NEXT: [[TMP11:%.*]] = fmul <2 x float> [[TMP8]], [[TMP10]]
; POW2-ONLY-NEXT: [[TMP12:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[TMP2]], <2 x float> zeroinitializer, <2 x float> [[TMP11]])
@@ -333,8 +333,8 @@ define void @reuse_shuffle_indidces_1(ptr %col, float %0, float %1) {
; NON-POW2-LABEL: define void @reuse_shuffle_indidces_1(
; NON-POW2-SAME: ptr [[COL:%.*]], float [[TMP0:%.*]], float [[TMP1:%.*]]) {
; NON-POW2-NEXT: entry:
-; NON-POW2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP1]], i32 0
-; NON-POW2-NEXT: [[TMP3:%.*]] = insertelement <3 x float> [[TMP2]], float [[TMP0]], i32 1
+; NON-POW2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP1]], i64 0
+; NON-POW2-NEXT: [[TMP3:%.*]] = insertelement <3 x float> [[TMP2]], float [[TMP0]], i64 1
; NON-POW2-NEXT: [[TMP4:%.*]] = shufflevector <3 x float> [[TMP3]], <3 x float> poison, <3 x i32> <i32 0, i32 1, i32 1>
; NON-POW2-NEXT: [[TMP5:%.*]] = fmul <3 x float> [[TMP4]], zeroinitializer
; NON-POW2-NEXT: [[TMP6:%.*]] = fadd <3 x float> [[TMP5]], zeroinitializer
@@ -344,8 +344,8 @@ define void @reuse_shuffle_indidces_1(ptr %col, float %0, float %1) {
; POW2-ONLY-LABEL: define void @reuse_shuffle_indidces_1(
; POW2-ONLY-SAME: ptr [[COL:%.*]], float [[TMP0:%.*]], float [[TMP1:%.*]]) {
; POW2-ONLY-NEXT: entry:
-; POW2-ONLY-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i32 0
-; POW2-ONLY-NEXT: [[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[TMP0]], i32 1
+; POW2-ONLY-NEXT: [[TMP2:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i64 0
+; POW2-ONLY-NEXT: [[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[TMP0]], i64 1
; POW2-ONLY-NEXT: [[TMP4:%.*]] = fmul <2 x float> [[TMP3]], zeroinitializer
; POW2-ONLY-NEXT: [[TMP5:%.*]] = fadd <2 x float> [[TMP4]], zeroinitializer
; POW2-ONLY-NEXT: store <2 x float> [[TMP5]], ptr [[COL]], align 4
@@ -405,9 +405,9 @@ define void @reuse_shuffle_indices_cost_crash_2(ptr %bezt, float %0) {
; NON-POW2-SAME: ptr [[BEZT:%.*]], float [[TMP0:%.*]]) {
; NON-POW2-NEXT: entry:
; NON-POW2-NEXT: [[FNEG:%.*]] = fmul float [[TMP0]], 0.000000e+00
-; NON-POW2-NEXT: [[TMP1:%.*]] = insertelement <3 x float> poison, float [[FNEG]], i32 0
+; NON-POW2-NEXT: [[TMP1:%.*]] = insertelement <3 x float> poison, float [[FNEG]], i64 0
; NON-POW2-NEXT: [[TMP2:%.*]] = shufflevector <3 x float> [[TMP1]], <3 x float> poison, <3 x i32> zeroinitializer
-; NON-POW2-NEXT: [[TMP3:%.*]] = insertelement <3 x float> <float poison, float poison, float 0.000000e+00>, float [[TMP0]], i32 0
+; NON-POW2-NEXT: [[TMP3:%.*]] = insertelement <3 x float> <float poison, float poison, float 0.000000e+00>, float [[TMP0]], i64 0
; NON-POW2-NEXT: [[TMP4:%.*]] = shufflevector <3 x float> [[TMP3]], <3 x float> poison, <3 x i32> <i32 0, i32 0, i32 2>
; NON-POW2-NEXT: [[TMP5:%.*]] = call <3 x float> @llvm.fmuladd.v3f32(<3 x float> [[TMP2]], <3 x float> [[TMP4]], <3 x float> zeroinitializer)
; NON-POW2-NEXT: store <3 x float> [[TMP5]], ptr [[BEZT]], align 4
@@ -417,9 +417,9 @@ define void @reuse_shuffle_indices_cost_crash_2(ptr %bezt, float %0) {
; POW2-ONLY-SAME: ptr [[BEZT:%.*]], float [[TMP0:%.*]]) {
; POW2-ONLY-NEXT: entry:
; POW2-ONLY-NEXT: [[FNEG:%.*]] = fmul float [[TMP0]], 0.000000e+00
-; POW2-ONLY-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 0
+; POW2-ONLY-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i64 0
; POW2-ONLY-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
-; POW2-ONLY-NEXT: [[TMP3:%.*]] = insertelement <2 x float> poison, float [[FNEG]], i32 0
+; POW2-ONLY-NEXT: [[TMP3:%.*]] = insertelement <2 x float> poison, float [[FNEG]], i64 0
; POW2-ONLY-NEXT: [[TMP4:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <2 x i32> zeroinitializer
; POW2-ONLY-NEXT: [[TMP5:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[TMP2]], <2 x float> [[TMP4]], <2 x float> zeroinitializer)
; POW2-ONLY-NEXT: store <2 x float> [[TMP5]], ptr [[BEZT]], align 4
@@ -445,8 +445,8 @@ define void @reuse_shuffle_indices_cost_crash_3(ptr %m, double %conv, double %co
; CHECK-LABEL: define void @reuse_shuffle_indices_cost_crash_3(
; CHECK-SAME: ptr [[M:%.*]], double [[CONV:%.*]], double [[CONV2:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[CONV]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double -0.000000e+00>, double [[CONV2]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[CONV]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> <double poison, double -0.000000e+00>, double [[CONV2]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> [[TMP0]], [[TMP3]]
; CHECK-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float>
; CHECK-NEXT: store <2 x float> [[TMP2]], ptr [[M]], align 4
@@ -479,7 +479,7 @@ define void @reuse_shuffle_indices_cost_crash_4(double %conv7.i) {
; CHECK-NEXT: [[ARRAYIDX_2_I:%.*]] = getelementptr [3 x float], ptr [[DATA_I111]], i64 0, i64 2
; CHECK-NEXT: [[MUL17_I_US:%.*]] = fmul double [[CONV7_I]], 0.000000e+00
; CHECK-NEXT: [[MUL_2_I_I_US:%.*]] = fmul double [[MUL17_I_US]], 0.000000e+00
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV7_I]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV7_I]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[ADD_2_I_I_US:%.*]] = fadd double [[MUL_2_I_I_US]], 0.000000e+00
@@ -519,8 +519,8 @@ define void @common_mask(ptr %m, double %conv, double %conv2) {
; CHECK-LABEL: define void @common_mask(
; CHECK-SAME: ptr [[M:%.*]], double [[CONV:%.*]], double [[CONV2:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP0]], double [[CONV2]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[CONV]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP0]], double [[CONV2]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> <double poison, double -0.000000e+00>, <2 x i32> <i32 0, i32 3>
; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> [[TMP3]], [[TMP4]]
; CHECK-NEXT: [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
index ccc413486f6fb..ccec272ad3197 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
@@ -38,15 +38,15 @@ define void @test(ptr nocapture %t2) {
; CHECK-NEXT: [[T30:%.*]] = add nsw i32 [[T27]], [[T29]]
; CHECK-NEXT: [[T31:%.*]] = mul nsw i32 [[T30]], 4433
; CHECK-NEXT: [[T34:%.*]] = mul nsw i32 [[T29]], -15137
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[T27]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[T37]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[T27]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[T37]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 5, i32 poison>
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[T39]], i32 3
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[T39]], i64 3
; CHECK-NEXT: [[TMP6:%.*]] = mul nsw <4 x i32> [[TMP13]], <i32 6270, i32 -16069, i32 1, i32 9633>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, <4 x i32> [[TMP6]], <4 x i32> <i32 0, i32 7, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 poison>
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[T48]], i32 3
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[T48]], i64 3
; CHECK-NEXT: [[TMP10:%.*]] = add nsw <4 x i32> [[TMP6]], [[TMP9]]
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll b/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
index 9e87385c64df9..2b18b55489c36 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
@@ -38,15 +38,15 @@ define void @test(ptr nocapture %t2) {
; CHECK-NEXT: [[T30:%.*]] = add nsw i32 [[T27]], [[T29]]
; CHECK-NEXT: [[T31:%.*]] = mul nsw i32 [[T30]], 4433
; CHECK-NEXT: [[T34:%.*]] = mul nsw i32 [[T29]], -15137
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[T27]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[T37]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[T27]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[T37]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 5, i32 poison>
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[T39]], i32 3
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[T39]], i64 3
; CHECK-NEXT: [[TMP6:%.*]] = mul nsw <4 x i32> [[TMP13]], <i32 6270, i32 -16069, i32 1, i32 9633>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, <4 x i32> [[TMP6]], <4 x i32> <i32 0, i32 7, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 poison>
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[T48]], i32 3
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[T48]], i64 3
; CHECK-NEXT: [[TMP10:%.*]] = add nsw <4 x i32> [[TMP6]], [[TMP9]]
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <8 x i32> <i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias_external_insert_shuffled.ll b/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias_external_insert_shuffled.ll
index 6736e621ced66..34d65b767591b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias_external_insert_shuffled.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias_external_insert_shuffled.ll
@@ -32,15 +32,15 @@ define void @test(ptr nocapture %t2) {
; CHECK-NEXT: [[T30:%.*]] = add nsw i32 [[T27]], [[T29]]
; CHECK-NEXT: [[T31:%.*]] = mul nsw i32 [[T30]], 4433
; CHECK-NEXT: [[T34:%.*]] = mul nsw i32 [[T29]], -15137
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[T27]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[T37]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[T27]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[T37]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 5, i32 poison>
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[T39]], i32 3
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[T39]], i64 3
; CHECK-NEXT: [[TMP6:%.*]] = mul nsw <4 x i32> [[TMP13]], <i32 6270, i32 -16069, i32 1, i32 9633>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, <4 x i32> [[TMP6]], <4 x i32> <i32 0, i32 7, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 poison>
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[T48]], i32 3
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[T48]], i64 3
; CHECK-NEXT: [[TMP10:%.*]] = add nsw <4 x i32> [[TMP6]], [[TMP9]]
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <8 x i32> <i32 2, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll b/llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll
index 9719e60a6a695..b6edc389fafa9 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vect-gather-same-nodes.ll
@@ -9,13 +9,13 @@ define void @test(ptr %a, ptr %b) {
; CHECK-NEXT: [[ARRAYIDX120:%.*]] = getelementptr [4 x float], ptr [[B:%.*]], i64 0, i64 3
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[ARRAYIDX120]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 0>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP2]], float [[TMP0]], i32 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP2]], float [[TMP0]], i64 2
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr null, align 4
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x float>, ptr [[A:%.*]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 1, i32 0, i32 1, i32 0>
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[TMP6]], float [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[TMP6]], float [[TMP3]], i64 1
; CHECK-NEXT: [[TMP8:%.*]] = fmul <4 x float> [[TMP5]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[TMP10:%.*]] = fmul <4 x float> [[TMP9]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-pair-path.ll b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-pair-path.ll
index e0b14b06ea513..7a280ab2b1ec8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-pair-path.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-pair-path.ll
@@ -13,17 +13,17 @@ target triple = "x86_64-unknown-linux-gnu"
define double @root_selection(double %a, double %b, double %c, double %d) local_unnamed_addr {
; CHECK-LABEL: @root_selection(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[A:%.*]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[B:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fdiv fast <2 x double> [[TMP2]], <double 7.000000e+00, double 5.000000e+00>
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i64 1
; CHECK-NEXT: [[I09:%.*]] = fmul fast double [[TMP4]], undef
; CHECK-NEXT: [[I10:%.*]] = fsub fast double undef, [[I09]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul fast <2 x double> [[TMP3]], <double 3.000000e+00, double undef>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> <double undef, double poison>, double [[I10]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> <double undef, double poison>, double [[I10]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = fmul fast <2 x double> [[TMP6]], [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x double> poison, double [[C:%.*]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x double> [[TMP8]], double [[D:%.*]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x double> poison, double [[C:%.*]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x double> [[TMP8]], double [[D:%.*]], i64 1
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP7]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP9]], <4 x double> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: [[TMP12:%.*]] = fsub reassoc nsz arcp contract afn <4 x double> [[TMP11]], <double 0.000000e+00, double 0.000000e+00, double undef, double 1.100000e+01>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-widest-phis.ll b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-widest-phis.ll
index 03089b581f352..fef9f0d503be2 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-widest-phis.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-widest-phis.ll
@@ -8,8 +8,8 @@ define void @foo(i1 %arg) {
; CHECK-NEXT: [[SUB:%.*]] = fsub float 6.553500e+04, 0.000000e+00
; CHECK-NEXT: br label [[BB1:%.*]]
; CHECK: bb1:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> <float poison, float poison, float 0.000000e+00, float 0.000000e+00>, float [[SUB]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[CONV]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x float> <float poison, float poison, float 0.000000e+00, float 0.000000e+00>, float [[SUB]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[CONV]], i64 1
; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb2:
; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x float> [ [[TMP1]], [[BB1]] ], [ [[TMP14:%.*]], [[BB3:%.*]] ]
@@ -18,8 +18,8 @@ define void @foo(i1 %arg) {
; CHECK: bb4:
; CHECK-NEXT: [[TMP4:%.*]] = fpext <4 x float> [[TMP2]] to <4 x double>
; CHECK-NEXT: [[CONV2:%.*]] = uitofp i16 0 to double
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x double> <double 0.000000e+00, double poison, double 0.000000e+00, double -0.000000e+00>, double [[TMP3]], i32 1
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x double> <double -0.000000e+00, double poison, double -0.000000e+00, double 0.000000e+00>, double [[CONV2]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x double> <double 0.000000e+00, double poison, double 0.000000e+00, double -0.000000e+00>, double [[TMP3]], i64 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x double> <double -0.000000e+00, double poison, double -0.000000e+00, double 0.000000e+00>, double [[CONV2]], i64 1
; CHECK-NEXT: [[TMP10:%.*]] = fadd <4 x double> [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP11:%.*]] = fcmp ogt <4 x double> [[TMP10]], [[TMP4]]
; CHECK-NEXT: [[TMP12:%.*]] = fptrunc <4 x double> [[TMP10]] to <4 x float>
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/whole-registers-compare.ll b/llvm/test/Transforms/SLPVectorizer/X86/whole-registers-compare.ll
index 5e52bd7cc954c..f750cc390dad0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/whole-registers-compare.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/whole-registers-compare.ll
@@ -9,11 +9,11 @@ define void @test() {
; CHECK-NEXT: [[TMP0:%.*]] = phi <12 x float> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP7:%.*]], %[[DO_BODY]] ]
; CHECK-NEXT: [[CMP119:%.*]] = fcmp uge float 0.000000e+00, 0.000000e+00
; CHECK-NEXT: [[VAL_SROA_6_1:%.*]] = select i1 [[CMP119]], float 0.000000e+00, float 0.000000e+00
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[VAL_SROA_6_1]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[VAL_SROA_6_1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = fcmp uge <2 x float> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i1> [[TMP2]], <2 x i1> poison, <12 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <12 x i1> <i1 true, i1 undef, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 undef, i1 undef, i1 undef>, <12 x i1> [[TMP3]], <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 12, i32 13, i32 11>
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <12 x i1> [[TMP4]], i1 [[CMP119]], i32 11
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <12 x i1> [[TMP4]], i1 [[CMP119]], i64 11
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <12 x i1> [[TMP5]], <12 x i1> poison, <12 x i32> <i32 0, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: [[TMP7]] = select <12 x i1> [[TMP6]], <12 x float> zeroinitializer, <12 x float> zeroinitializer
; CHECK-NEXT: br label %[[DO_BODY]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll b/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll
index 9cdcdf1b5d5ca..738593db3b51a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/xor-combined-opcode.ll
@@ -4,11 +4,11 @@ define i1 @foo(i1 %v) { ; assume %v is 1
; CHECK-LABEL: define i1 @foo(
; CHECK-SAME: i1 [[V:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i1> poison, i1 [[V]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i1> poison, i1 [[V]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i1> [[TMP0]], <2 x i1> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i1> zeroinitializer, [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP2]], i64 1
; CHECK-NEXT: [[SUB:%.*]] = sub i1 [[TMP3]], [[TMP4]]
; CHECK-NEXT: ret i1 [[SUB]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/xor-with-zero-and-incompat.ll b/llvm/test/Transforms/SLPVectorizer/X86/xor-with-zero-and-incompat.ll
index ad6c3c77a2e11..1eb5f082df9c4 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/xor-with-zero-and-incompat.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/xor-with-zero-and-incompat.ll
@@ -4,8 +4,8 @@
define void @src_test_xor_and_identity_mismatch(i32 %a, i32 %b, ptr %dst) {
; CHECK-LABEL: define void @src_test_xor_and_identity_mismatch(
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], ptr [[DST:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[B]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[B]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i32> [[TMP2]], zeroinitializer
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr [[DST]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/abs-overflow-incorrect-minbws.ll b/llvm/test/Transforms/SLPVectorizer/abs-overflow-incorrect-minbws.ll
index da1b87b28a304..73b3e1f9c4dd1 100644
--- a/llvm/test/Transforms/SLPVectorizer/abs-overflow-incorrect-minbws.ll
+++ b/llvm/test/Transforms/SLPVectorizer/abs-overflow-incorrect-minbws.ll
@@ -5,15 +5,15 @@ define i32 @test(i32 %n) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[N]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[N]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i32> [[TMP1]], <i32 1, i32 2>
; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>
; CHECK-NEXT: [[TMP7:%.*]] = mul nuw nsw <2 x i64> [[TMP3]], splat (i64 273837369)
; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.abs.v2i64(<2 x i64> [[TMP7]], i1 true)
; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i64> [[TMP8]] to <2 x i32>
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP4]], i64 1
; CHECK-NEXT: [[RES1:%.*]] = add i32 [[TMP5]], [[TMP6]]
; CHECK-NEXT: ret i32 [[RES1]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/alt-cmp-vectorize.ll b/llvm/test/Transforms/SLPVectorizer/alt-cmp-vectorize.ll
index ff6f0bdd3db8f..f652ad373faf5 100644
--- a/llvm/test/Transforms/SLPVectorizer/alt-cmp-vectorize.ll
+++ b/llvm/test/Transforms/SLPVectorizer/alt-cmp-vectorize.ll
@@ -5,8 +5,8 @@ define i32 @alt_cmp(i16 %call46) {
; CHECK-LABEL: @alt_cmp(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CALL47:%.*]] = tail call i16 null(i16 0)
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[CALL46:%.*]], i32 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[CALL47]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[CALL46:%.*]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[CALL47]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <4 x i16> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt <4 x i16> [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
diff --git a/llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll b/llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
index afca39ad8938a..dd84918956e11 100644
--- a/llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
+++ b/llvm/test/Transforms/SLPVectorizer/alternate-cmp-swapped-pred-parent.ll
@@ -9,11 +9,11 @@ define void @test() {
; CHECK-NEXT: br label [[BB:%.*]]
; CHECK: bb:
; CHECK-NEXT: [[CALL:%.*]] = load i16, ptr poison, align 2
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 poison, i16 poison, i16 0, i16 poison>, i16 [[CALL37]], i32 3
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[CALL]], i32 5
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 poison, i16 poison, i16 0, i16 poison>, i16 [[CALL37]], i64 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[CALL]], i64 5
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 3>
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 poison, i16 poison>, i16 [[CALL37]], i32 6
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[CALL]], i32 7
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 poison, i16 poison>, i16 [[CALL37]], i64 6
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[CALL]], i64 7
; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <8 x i16> [[TMP2]], [[TMP3]]
; CHECK-NEXT: ret void
;
@@ -41,11 +41,11 @@ define void @test1() {
; CHECK-NEXT: br label [[BB:%.*]]
; CHECK: bb:
; CHECK-NEXT: [[CALL37:%.*]] = load i16, ptr poison, align 2
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 poison, i16 poison, i16 poison, i16 0>, i16 [[CALL]], i32 3
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[CALL37]], i32 4
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 poison, i16 poison, i16 poison, i16 0>, i16 [[CALL]], i64 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[CALL37]], i64 4
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 7>
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 poison, i16 poison>, i16 [[CALL]], i32 6
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[CALL37]], i32 7
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 poison, i16 poison>, i16 [[CALL]], i64 6
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[CALL37]], i64 7
; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <8 x i16> [[TMP2]], [[TMP3]]
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll b/llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll
index 7cb81ea165781..97628b26e65e5 100644
--- a/llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll
+++ b/llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll
@@ -32,7 +32,7 @@ define <2 x float> @test_frem(float %a, i1 %cmp) {
define <2 x float> @replace_through_casts(i16 %inp) {
; CHECK-LABEL: define <2 x float> @replace_through_casts(
; CHECK-SAME: i16 [[INP:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i16> [[TMP2]], <i16 0, i16 -10>
; CHECK-NEXT: [[TMP4:%.*]] = uitofp <2 x i16> [[TMP3]] to <2 x float>
@@ -51,7 +51,7 @@ define <2 x float> @replace_through_casts(i16 %inp) {
define <2 x float> @replace_through_casts_and_binop(i16 %inp) {
; CHECK-LABEL: define <2 x float> @replace_through_casts_and_binop(
; CHECK-SAME: i16 [[INP:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP7:%.*]] = mul nsw <2 x i16> [[TMP6]], <i16 5, i16 -10>
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <2 x i16> [[TMP6]], <i16 5, i16 -10>
@@ -119,7 +119,7 @@ define <2 x float> @replace_through_casts_through_splat(i16 %inp) {
define <2 x i32> @replace_through_int_casts(i16 %inp, <2 x i16> %dead) {
; CHECK-LABEL: define <2 x i32> @replace_through_int_casts(
; CHECK-SAME: i16 [[INP:%.*]], <2 x i16> [[DEAD:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i16> [[TMP2]], <i16 0, i16 -10>
; CHECK-NEXT: [[TMP4:%.*]] = zext <2 x i16> [[TMP3]] to <2 x i32>
@@ -138,7 +138,7 @@ define <2 x i32> @replace_through_int_casts(i16 %inp, <2 x i16> %dead) {
define <2 x i32> @replace_through_int_casts_ele0_only(i16 %inp, <2 x i16> %dead) {
; CHECK-LABEL: define <2 x i32> @replace_through_int_casts_ele0_only(
; CHECK-SAME: i16 [[INP:%.*]], <2 x i16> [[DEAD:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = sext <2 x i16> [[TMP2]] to <2 x i32>
@@ -155,7 +155,7 @@ define <2 x i32> @replace_through_int_casts_ele0_only(i16 %inp, <2 x i16> %dead)
define <2 x i8> @replace_through_binop_fail_cant_speculate(i8 %inp, <2 x i8> %d, <2 x i8> %any) {
; CHECK-LABEL: define <2 x i8> @replace_through_binop_fail_cant_speculate(
; CHECK-SAME: i8 [[INP:%.*]], <2 x i8> [[D:%.*]], <2 x i8> [[ANY:%.*]]) {
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i8> poison, i8 [[INP]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i8> poison, i8 [[INP]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i8> [[TMP3]], <2 x i8> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[V:%.*]] = add <2 x i8> [[TMP2]], <i8 0, i8 5>
; CHECK-NEXT: [[DIV0:%.*]] = sdiv <2 x i8> splat (i8 -128), [[V]]
@@ -175,7 +175,7 @@ define <2 x i8> @replace_through_binop_fail_cant_speculate(i8 %inp, <2 x i8> %d,
define <2 x i8> @replace_through_binop_preserve_flags(i8 %inp, <2 x i8> %d, <2 x i8> %any) {
; CHECK-LABEL: define <2 x i8> @replace_through_binop_preserve_flags(
; CHECK-SAME: i8 [[INP:%.*]], <2 x i8> [[D:%.*]], <2 x i8> [[ANY:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> poison, i8 [[INP]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> poison, i8 [[INP]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i8> [[TMP1]], <2 x i8> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i8> [[TMP2]], <i8 123, i8 5>
; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i8> [[TMP3]], <i8 0, i8 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll b/llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
index 769b3604d41c5..779cb822852c7 100644
--- a/llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
@@ -8,7 +8,7 @@ define i1 @test(i32 %0, i32 %1, i32 %p) {
; X86-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[P:%.*]]) {
; X86-NEXT: entry:
; X86-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP0]], 0
-; X86-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
+; X86-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i64 0
; X86-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; X86-NEXT: [[TMP4:%.*]] = shl <4 x i32> zeroinitializer, [[TMP3]]
; X86-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], zeroinitializer
@@ -27,10 +27,10 @@ define i1 @test(i32 %0, i32 %1, i32 %p) {
; AARCH64-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP0]], 0
; AARCH64-NEXT: [[SHL4:%.*]] = shl i32 0, [[TMP1]]
; AARCH64-NEXT: [[CMP5:%.*]] = icmp slt i32 [[SHL4]], 0
-; AARCH64-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, i32 [[TMP1]], i32 1
+; AARCH64-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, i32 [[TMP1]], i64 1
; AARCH64-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; AARCH64-NEXT: [[TMP4:%.*]] = shl <4 x i32> zeroinitializer, [[TMP3]]
-; AARCH64-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, i32 [[P]], i32 0
+; AARCH64-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, i32 [[P]], i64 0
; AARCH64-NEXT: [[TMP6:%.*]] = icmp slt <4 x i32> [[TMP4]], [[TMP5]]
; AARCH64-NEXT: [[TMP7:%.*]] = freeze <4 x i1> [[TMP6]]
; AARCH64-NEXT: [[TMP8:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP7]])
diff --git a/llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll b/llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
index a2876b9c06bc5..3d102ff09356f 100644
--- a/llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
+++ b/llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll
@@ -8,7 +8,7 @@ define double @test() {
; X86-NEXT: [[TMP0:%.*]] = load double, ptr null, align 8
; X86-NEXT: br label [[COND_TRUE:%.*]]
; X86: cond.true:
-; X86-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP0]], i32 1
+; X86-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP0]], i64 1
; X86-NEXT: [[TMP2:%.*]] = fmul <2 x double> zeroinitializer, [[TMP1]]
; X86-NEXT: [[TMP3:%.*]] = fmul <2 x double> zeroinitializer, [[TMP1]]
; X86-NEXT: [[TMP15:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
@@ -30,8 +30,8 @@ define double @test() {
; X86-NEXT: [[TMP22:%.*]] = fmul <2 x double> [[TMP17]], zeroinitializer
; X86-NEXT: [[TMP23:%.*]] = fmul <2 x double> zeroinitializer, [[TMP22]]
; X86-NEXT: [[TMP24:%.*]] = fadd <2 x double> [[TMP23]], [[TMP21]]
-; X86-NEXT: [[ADD12:%.*]] = extractelement <2 x double> [[TMP24]], i32 0
-; X86-NEXT: [[ADD27:%.*]] = extractelement <2 x double> [[TMP24]], i32 1
+; X86-NEXT: [[ADD12:%.*]] = extractelement <2 x double> [[TMP24]], i64 0
+; X86-NEXT: [[ADD27:%.*]] = extractelement <2 x double> [[TMP24]], i64 1
; X86-NEXT: [[ADD29:%.*]] = fadd double [[ADD12]], [[ADD27]]
; X86-NEXT: ret double [[ADD29]]
;
@@ -40,7 +40,7 @@ define double @test() {
; AARCH64-NEXT: [[TMP0:%.*]] = load double, ptr null, align 8
; AARCH64-NEXT: br label [[COND_TRUE:%.*]]
; AARCH64: cond.true:
-; AARCH64-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP0]], i32 1
+; AARCH64-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP0]], i64 1
; AARCH64-NEXT: [[TMP2:%.*]] = fmul <2 x double> zeroinitializer, [[TMP1]]
; AARCH64-NEXT: [[TMP6:%.*]] = fmul <2 x double> zeroinitializer, [[TMP1]]
; AARCH64-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
@@ -62,8 +62,8 @@ define double @test() {
; AARCH64-NEXT: [[TMP22:%.*]] = fmul <2 x double> [[TMP5]], zeroinitializer
; AARCH64-NEXT: [[TMP23:%.*]] = fmul <2 x double> zeroinitializer, [[TMP22]]
; AARCH64-NEXT: [[TMP24:%.*]] = fadd <2 x double> [[TMP23]], [[TMP21]]
-; AARCH64-NEXT: [[TMP25:%.*]] = extractelement <2 x double> [[TMP24]], i32 0
-; AARCH64-NEXT: [[TMP26:%.*]] = extractelement <2 x double> [[TMP24]], i32 1
+; AARCH64-NEXT: [[TMP25:%.*]] = extractelement <2 x double> [[TMP24]], i64 0
+; AARCH64-NEXT: [[TMP26:%.*]] = extractelement <2 x double> [[TMP24]], i64 1
; AARCH64-NEXT: [[ADD29:%.*]] = fadd double [[TMP25]], [[TMP26]]
; AARCH64-NEXT: ret double [[ADD29]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
index 3cf359fd47351..61fb569c93a5a 100644
--- a/llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
+++ b/llvm/test/Transforms/SLPVectorizer/call-arg-reduced-by-minbitwidth.ll
@@ -6,9 +6,9 @@ define void @test(ptr %0, i8 %1, i1 %cmp12.i) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[TMP0:%.*]], i8 [[TMP1:%.*]], i1 [[CMP12_I:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i1> poison, i1 [[CMP12_I]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i1> poison, i1 [[CMP12_I]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> poison, <8 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i8> poison, i8 [[TMP1]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i8> poison, i8 [[TMP1]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i8> [[TMP4]], <8 x i8> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: br label [[PRE:%.*]]
; CHECK: pre:
diff --git a/llvm/test/Transforms/SLPVectorizer/consecutive-access.ll b/llvm/test/Transforms/SLPVectorizer/consecutive-access.ll
index ab5f7fd8ee3f5..27e88a5b6d73e 100644
--- a/llvm/test/Transforms/SLPVectorizer/consecutive-access.ll
+++ b/llvm/test/Transforms/SLPVectorizer/consecutive-access.ll
@@ -182,8 +182,8 @@ define i32 @foo_loop(ptr %A, i32 %n) {
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[IDXPROM]]
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> splat (double 7.000000e+00), [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i64 1
; CHECK-NEXT: [[ADD6:%.*]] = fadd double [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[ADD7]] = fadd double [[TMP1]], [[ADD6]]
; CHECK-NEXT: store double [[ADD7]], ptr [[SUM]], align 8
@@ -356,8 +356,8 @@ define i32 @foo_loop_non_power_of_2(ptr %A, i32 %n) {
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[IDXPROM]]
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[ARRAYIDX]], align 8
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> splat (double 7.000000e+00), [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP3]], i64 1
; CHECK-NEXT: [[ADD6:%.*]] = fadd double [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[ADD7]] = fadd double [[TMP1]], [[ADD6]]
; CHECK-NEXT: store double [[ADD7]], ptr [[SUM]], align 8
@@ -445,8 +445,8 @@ define double @bar(ptr nocapture readonly %a, i32 %n) local_unnamed_addr {
; CHECK-NEXT: br i1 [[CMP15]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY:%.*]]
; CHECK: for.cond.cleanup:
; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x double> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[TMP5:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x double> [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x double> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP0]], i64 1
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret double [[MUL]]
; CHECK: for.body:
diff --git a/llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll b/llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
index 2276dc340b3d9..b2ed641fcf399 100644
--- a/llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
+++ b/llvm/test/Transforms/SLPVectorizer/crash_exceed_scheduling.ll
@@ -5,12 +5,12 @@
define void @exceed(double %0, double %1) {
; X86-LABEL: @exceed(
; X86-NEXT: entry:
-; X86-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i32 0
+; X86-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i64 0
; X86-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
-; X86-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[TMP1:%.*]], i32 0
+; X86-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[TMP1:%.*]], i64 0
; X86-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <2 x i32> zeroinitializer
; X86-NEXT: [[TMP6:%.*]] = fdiv fast <2 x double> [[TMP3]], [[TMP5]]
-; X86-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i32 1
+; X86-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i64 1
; X86-NEXT: [[IX:%.*]] = fmul double [[TMP7]], undef
; X86-NEXT: [[IXX0:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX1:%.*]] = fsub double undef, undef
@@ -28,7 +28,7 @@ define void @exceed(double %0, double %1) {
; X86-NEXT: [[IXX20:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX21:%.*]] = fsub double undef, undef
; X86-NEXT: [[IXX22:%.*]] = fsub double undef, undef
-; X86-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP6]], i32 0
+; X86-NEXT: [[TMP8:%.*]] = extractelement <2 x double> [[TMP6]], i64 0
; X86-NEXT: [[IX2:%.*]] = fmul double [[TMP8]], [[TMP8]]
; X86-NEXT: [[TMP9:%.*]] = fadd fast <2 x double> [[TMP3]], [[TMP5]]
; X86-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP5]], <2 x i32> <i32 0, i32 2>
@@ -65,18 +65,18 @@ define void @exceed(double %0, double %1) {
; AARCH64-NEXT: [[IXX20:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX21:%.*]] = fsub double undef, undef
; AARCH64-NEXT: [[IXX22:%.*]] = fsub double undef, undef
-; AARCH64-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i32 0
+; AARCH64-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i64 0
; AARCH64-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
-; AARCH64-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[TMP1:%.*]], i32 0
+; AARCH64-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[TMP1:%.*]], i64 0
; AARCH64-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <2 x i32> zeroinitializer
; AARCH64-NEXT: [[TMP6:%.*]] = fdiv fast <2 x double> [[TMP3]], [[TMP5]]
-; AARCH64-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i32 0
+; AARCH64-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i64 0
; AARCH64-NEXT: [[IX2:%.*]] = fmul double [[TMP7]], [[TMP7]]
; AARCH64-NEXT: [[TMP8:%.*]] = fadd fast <2 x double> [[TMP3]], [[TMP5]]
; AARCH64-NEXT: [[TMP9:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP5]], <2 x i32> <i32 0, i32 2>
; AARCH64-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> <double poison, double 1.000000e+00>, <2 x i32> <i32 0, i32 3>
; AARCH64-NEXT: [[TMP11:%.*]] = fdiv reassoc nsz arcp contract afn <2 x double> [[TMP9]], [[TMP10]]
-; AARCH64-NEXT: [[TMP12:%.*]] = extractelement <2 x double> [[TMP6]], i32 1
+; AARCH64-NEXT: [[TMP12:%.*]] = extractelement <2 x double> [[TMP6]], i64 1
; AARCH64-NEXT: [[IX:%.*]] = fmul double [[TMP12]], undef
; AARCH64-NEXT: [[IX1:%.*]] = fmul double [[TMP12]], undef
; AARCH64-NEXT: [[TMP13:%.*]] = fadd fast <2 x double> [[TMP6]], [[TMP9]]
diff --git a/llvm/test/Transforms/SLPVectorizer/crash_extractelement_poison.ll b/llvm/test/Transforms/SLPVectorizer/crash_extractelement_poison.ll
index 32ea3984cc4cb..798db60219f0c 100644
--- a/llvm/test/Transforms/SLPVectorizer/crash_extractelement_poison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/crash_extractelement_poison.ll
@@ -8,9 +8,9 @@ define void @test(i8 %0, i8 %1) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[L:%.*]] = load <4 x i8>, ptr getelementptr (i8, ptr null, i32 8), align 1
; CHECK-NEXT: [[LI15:%.*]] = extractelement <4 x i8> [[L]], i64 15
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> [[TMP3]], i8 [[LI15]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> [[TMP3]], i8 [[LI15]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i8> [[TMP4]], <4 x i8> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i8> [[TMP5]], zeroinitializer
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll b/llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
index 6fe286fbbff61..1b1da682b09c5 100644
--- a/llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
+++ b/llvm/test/Transforms/SLPVectorizer/diamond_broadcast.ll
@@ -6,7 +6,7 @@ define i32 @diamond_broadcast(ptr noalias nocapture %B, ptr noalias nocapture %A
; CHECK-LABEL: @diamond_broadcast(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[A:%.*]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LD]], i64 0
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[SHUFFLE]], [[SHUFFLE]]
; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[B:%.*]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/ext-after-phi-node.ll b/llvm/test/Transforms/SLPVectorizer/ext-after-phi-node.ll
index 0abfdc91e7295..f168cb3578498 100644
--- a/llvm/test/Transforms/SLPVectorizer/ext-after-phi-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/ext-after-phi-node.ll
@@ -9,9 +9,9 @@ define double @test() {
; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ poison, [[BB9:%.*]] ], [ zeroinitializer, [[BB:%.*]] ]
; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x i32> [ zeroinitializer, [[BB9]] ], [ zeroinitializer, [[BB]] ]
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP0]] to <2 x i64>
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP0]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i64 [[TMP6]], [[TMP4]]
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i64> zeroinitializer, <2 x i64> [[TMP2]], <2 x i32> <i32 3, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll b/llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll
index b1c1623b070d2..1924d6f17a26b 100644
--- a/llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll
+++ b/llvm/test/Transforms/SLPVectorizer/ext-int-reduced-not-operand.ll
@@ -10,12 +10,12 @@ define i64 @wombat() {
; CHECK-NEXT: br label [[BB2]]
; CHECK: bb2:
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ 0, [[BB1:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[PHI]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[PHI]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i1>
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i64
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP2]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i64
; CHECK-NEXT: [[OR:%.*]] = or i64 [[TMP4]], [[TMP6]]
; CHECK-NEXT: ret i64 [[OR]]
diff --git a/llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll b/llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll
index 118507c790bfc..1c950f045b7c7 100644
--- a/llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll
+++ b/llvm/test/Transforms/SLPVectorizer/extended-vectorized-gathered-inst.ll
@@ -8,10 +8,10 @@ define void @test(ptr %top) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[TOP]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = mul <4 x i8> [[TMP0]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i8> [[TMP0]], i32 2
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i8> [[TMP0]], i64 2
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> <i8 0, i8 0, i8 0, i8 poison>, i8 [[TMP4]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> <i8 0, i8 0, i8 0, i8 poison>, i8 [[TMP4]], i64 3
; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i8> [[TMP1]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i8> [[TMP6]], zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = lshr <4 x i8> [[TMP7]], splat (i8 2)
diff --git a/llvm/test/Transforms/SLPVectorizer/external-user-instruction-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/external-user-instruction-minbitwidth.ll
index 07dab9f53b1b0..df823810f6d91 100644
--- a/llvm/test/Transforms/SLPVectorizer/external-user-instruction-minbitwidth.ll
+++ b/llvm/test/Transforms/SLPVectorizer/external-user-instruction-minbitwidth.ll
@@ -14,10 +14,10 @@ define i8 @test() {
; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr @c, align 2
; CHECK-NEXT: [[CONV1:%.*]] = zext i16 [[TMP1]] to i32
; CHECK-NEXT: [[TMP13:%.*]] = or i32 [[CONV]], 32769
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[CONV]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[CONV]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i32> [[TMP3]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 32769>
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> poison, i32 [[CONV1]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> poison, i32 [[CONV1]], i64 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i32> [[TMP6]], <8 x i32> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = add nsw <8 x i32> [[TMP4]], [[TMP7]]
; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP8]])
diff --git a/llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll b/llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
index 400901d3c7b92..ddf2d694c54da 100644
--- a/llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/extract-many-users-buildvector.ll
@@ -8,12 +8,12 @@ define i1 @test(float %0, double %1) {
; X86-NEXT: [[TMP3:%.*]] = fpext float [[TMP0]] to double
; X86-NEXT: [[TMP4:%.*]] = fpext float 0.000000e+00 to double
; X86-NEXT: [[TMP5:%.*]] = fmul double 0.000000e+00, 0.000000e+00
-; X86-NEXT: [[TMP6:%.*]] = insertelement <8 x double> <double 0.000000e+00, double undef, double 0.000000e+00, double undef, double undef, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>, double [[TMP1]], i32 4
-; X86-NEXT: [[TMP7:%.*]] = insertelement <8 x double> [[TMP6]], double [[TMP4]], i32 1
-; X86-NEXT: [[TMP8:%.*]] = insertelement <8 x double> [[TMP7]], double [[TMP3]], i32 3
+; X86-NEXT: [[TMP6:%.*]] = insertelement <8 x double> <double 0.000000e+00, double undef, double 0.000000e+00, double undef, double undef, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>, double [[TMP1]], i64 4
+; X86-NEXT: [[TMP7:%.*]] = insertelement <8 x double> [[TMP6]], double [[TMP4]], i64 1
+; X86-NEXT: [[TMP8:%.*]] = insertelement <8 x double> [[TMP7]], double [[TMP3]], i64 3
; X86-NEXT: [[TMP9:%.*]] = fmul <8 x double> zeroinitializer, [[TMP8]]
; X86-NEXT: [[TMP10:%.*]] = shufflevector <8 x double> [[TMP8]], <8 x double> <double 0.000000e+00, double poison, double poison, double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, <8 x i32> <i32 8, i32 4, i32 poison, i32 poison, i32 12, i32 13, i32 14, i32 15>
-; X86-NEXT: [[TMP11:%.*]] = insertelement <8 x double> poison, double [[TMP5]], i32 0
+; X86-NEXT: [[TMP11:%.*]] = insertelement <8 x double> poison, double [[TMP5]], i64 0
; X86-NEXT: [[TMP12:%.*]] = shufflevector <8 x double> [[TMP11]], <8 x double> poison, <8 x i32> <i32 poison, i32 poison, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison>
; X86-NEXT: [[TMP13:%.*]] = shufflevector <8 x double> [[TMP10]], <8 x double> [[TMP12]], <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; X86-NEXT: [[TMP14:%.*]] = shufflevector <8 x double> [[TMP8]], <8 x double> [[TMP13]], <8 x i32> <i32 poison, i32 poison, i32 1, i32 poison, i32 poison, i32 10, i32 poison, i32 poison>
@@ -30,16 +30,16 @@ define i1 @test(float %0, double %1) {
;
; AARCH64-LABEL: define i1 @test
; AARCH64-SAME: (float [[TMP0:%.*]], double [[TMP1:%.*]]) {
-; AARCH64-NEXT: [[TMP3:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP0]], i32 1
+; AARCH64-NEXT: [[TMP3:%.*]] = insertelement <2 x float> <float 0.000000e+00, float poison>, float [[TMP0]], i64 1
; AARCH64-NEXT: [[TMP4:%.*]] = fpext <2 x float> [[TMP3]] to <2 x double>
; AARCH64-NEXT: [[TMP5:%.*]] = fmul double 0.000000e+00, 0.000000e+00
-; AARCH64-NEXT: [[TMP6:%.*]] = insertelement <8 x double> <double undef, double undef, double 0.000000e+00, double undef, double undef, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>, double [[TMP1]], i32 4
-; AARCH64-NEXT: [[TMP7:%.*]] = insertelement <8 x double> [[TMP6]], double 0.000000e+00, i32 0
+; AARCH64-NEXT: [[TMP6:%.*]] = insertelement <8 x double> <double undef, double undef, double 0.000000e+00, double undef, double undef, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>, double [[TMP1]], i64 4
+; AARCH64-NEXT: [[TMP7:%.*]] = insertelement <8 x double> [[TMP6]], double 0.000000e+00, i64 0
; AARCH64-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP4]], <2 x double> poison, <8 x i32> <i32 0, i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AARCH64-NEXT: [[TMP9:%.*]] = shufflevector <8 x double> [[TMP7]], <8 x double> [[TMP8]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 5, i32 6, i32 7>
; AARCH64-NEXT: [[TMP10:%.*]] = fmul <8 x double> zeroinitializer, [[TMP9]]
; AARCH64-NEXT: [[TMP11:%.*]] = shufflevector <8 x double> [[TMP9]], <8 x double> <double 0.000000e+00, double poison, double poison, double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, <8 x i32> <i32 8, i32 4, i32 poison, i32 poison, i32 12, i32 13, i32 14, i32 15>
-; AARCH64-NEXT: [[TMP12:%.*]] = insertelement <8 x double> poison, double [[TMP5]], i32 0
+; AARCH64-NEXT: [[TMP12:%.*]] = insertelement <8 x double> poison, double [[TMP5]], i64 0
; AARCH64-NEXT: [[TMP13:%.*]] = shufflevector <8 x double> [[TMP12]], <8 x double> poison, <8 x i32> <i32 poison, i32 poison, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison>
; AARCH64-NEXT: [[TMP14:%.*]] = shufflevector <8 x double> [[TMP11]], <8 x double> [[TMP13]], <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; AARCH64-NEXT: [[TMP15:%.*]] = shufflevector <8 x double> [[TMP14]], <8 x double> <double poison, double poison, double poison, double 0.000000e+00, double 1.000000e+00, double poison, double 0.000000e+00, double 0.000000e+00>, <8 x i32> <i32 poison, i32 poison, i32 poison, i32 11, i32 12, i32 2, i32 14, i32 15>
diff --git a/llvm/test/Transforms/SLPVectorizer/extractelement-insertpoint.ll b/llvm/test/Transforms/SLPVectorizer/extractelement-insertpoint.ll
index 0688a235f80e4..dae4734e8838a 100644
--- a/llvm/test/Transforms/SLPVectorizer/extractelement-insertpoint.ll
+++ b/llvm/test/Transforms/SLPVectorizer/extractelement-insertpoint.ll
@@ -9,8 +9,8 @@ define i32 @crash() {
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[ADD]], <2 x double> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[SHUFFLE]], <2 x i32> <i32 2, i32 1>
; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x double> [[SHUFFLE]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i64 1
; CHECK-NEXT: [[ADD1:%.*]] = fadd double [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[MUL1:%.*]] = fmul double [[ADD1]], 0.000000e+00
; CHECK-NEXT: store double [[MUL1]], ptr null, align 16
diff --git a/llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll b/llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
index 4723a23f48ec2..d1e6e4ed2ec72 100644
--- a/llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
+++ b/llvm/test/Transforms/SLPVectorizer/extracts-with-undefs.ll
@@ -9,7 +9,7 @@ define void @test() {
; X86: body:
; X86-NEXT: [[PHI1:%.*]] = phi double [ 0.000000e+00, [[ENTRY:%.*]] ], [ 0.000000e+00, [[BODY]] ]
; X86-NEXT: [[TMP0:%.*]] = phi <2 x double> [ zeroinitializer, [[ENTRY]] ], [ zeroinitializer, [[BODY]] ]
-; X86-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[PHI1]], i32 0
+; X86-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[PHI1]], i64 0
; X86-NEXT: [[TMP2:%.*]] = fmul fast <2 x double> <double 0.000000e+00, double undef>, [[TMP1]]
; X86-NEXT: [[TMP3:%.*]] = call fast double @llvm.vector.reduce.fadd.v2f64(double 0.000000e+00, <2 x double> [[TMP2]])
; X86-NEXT: [[CMP42_I:%.*]] = fcmp fast ole double [[TMP3]], 0.000000e+00
@@ -34,7 +34,7 @@ define void @test() {
; AARCH64: body:
; AARCH64-NEXT: [[PHI1:%.*]] = phi double [ 0.000000e+00, [[ENTRY:%.*]] ], [ 0.000000e+00, [[BODY]] ]
; AARCH64-NEXT: [[TMP0:%.*]] = phi <2 x double> [ zeroinitializer, [[ENTRY]] ], [ zeroinitializer, [[BODY]] ]
-; AARCH64-NEXT: [[TMP8:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[PHI1]], i32 0
+; AARCH64-NEXT: [[TMP8:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[PHI1]], i64 0
; AARCH64-NEXT: [[TMP9:%.*]] = fmul fast <2 x double> <double 0.000000e+00, double undef>, [[TMP8]]
; AARCH64-NEXT: [[ADD8_I_I:%.*]] = call fast double @llvm.vector.reduce.fadd.v2f64(double 0.000000e+00, <2 x double> [[TMP9]])
; AARCH64-NEXT: [[CMP42_I:%.*]] = fcmp fast ole double [[ADD8_I_I]], 0.000000e+00
diff --git a/llvm/test/Transforms/SLPVectorizer/freeze-signedness-missed.ll b/llvm/test/Transforms/SLPVectorizer/freeze-signedness-missed.ll
index b4c6f18aa3a33..01990d7770f60 100644
--- a/llvm/test/Transforms/SLPVectorizer/freeze-signedness-missed.ll
+++ b/llvm/test/Transforms/SLPVectorizer/freeze-signedness-missed.ll
@@ -4,13 +4,13 @@
define i32 @test(i1 %.b, i8 %conv18, i32 %k.promoted61) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i1 [[DOTB:%.*]], i8 [[CONV18:%.*]], i32 [[K_PROMOTED61:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i1> poison, i1 [[DOTB]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i1> poison, i1 [[DOTB]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i1> [[TMP1]], <4 x i1> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i1> [[TMP2]], splat (i1 true)
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <4 x i1> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i1> [[TMP3]] to <4 x i8>
; CHECK-NEXT: [[TMP7:%.*]] = freeze <4 x i8> [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i8> poison, i8 [[CONV18]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i8> poison, i8 [[CONV18]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i8> [[TMP8]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt <4 x i8> [[TMP7]], [[TMP9]]
; CHECK-NEXT: [[TMP11:%.*]] = select <4 x i1> [[TMP10]], <4 x i8> zeroinitializer, <4 x i8> [[TMP7]]
diff --git a/llvm/test/Transforms/SLPVectorizer/gather_extract_from_vectorbuild.ll b/llvm/test/Transforms/SLPVectorizer/gather_extract_from_vectorbuild.ll
index 840767ac511a5..745a3b8fcf695 100644
--- a/llvm/test/Transforms/SLPVectorizer/gather_extract_from_vectorbuild.ll
+++ b/llvm/test/Transforms/SLPVectorizer/gather_extract_from_vectorbuild.ll
@@ -13,8 +13,8 @@ define void @test() {
; X86: loop:
; X86-NEXT: [[PH0:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[I4:%.*]], [[LOOP]] ]
; X86-NEXT: [[PH1:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ 0.000000e+00, [[LOOP]] ]
-; X86-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[PH0]], i32 0
-; X86-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[PH1]], i32 1
+; X86-NEXT: [[TMP0:%.*]] = insertelement <2 x float> poison, float [[PH0]], i64 0
+; X86-NEXT: [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float [[PH1]], i64 1
; X86-NEXT: [[TMP2:%.*]] = fadd <2 x float> zeroinitializer, [[TMP1]]
; X86-NEXT: [[TMP3:%.*]] = select <2 x i1> zeroinitializer, <2 x float> [[TMP2]], <2 x float> zeroinitializer
; X86-NEXT: [[I4]] = extractelement <2 x float> [[TMP3]], i64 0
diff --git a/llvm/test/Transforms/SLPVectorizer/gathered-consecutive-loads-different-types.ll b/llvm/test/Transforms/SLPVectorizer/gathered-consecutive-loads-different-types.ll
index 580225456b90a..2c784b3b7ca58 100644
--- a/llvm/test/Transforms/SLPVectorizer/gathered-consecutive-loads-different-types.ll
+++ b/llvm/test/Transforms/SLPVectorizer/gathered-consecutive-loads-different-types.ll
@@ -16,19 +16,19 @@ define i32 @test(i8 %0) {
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <2 x i8> zeroinitializer, [[TMP32]]
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i8> [[TMP5]], <2 x i8> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP33:%.*]] = shufflevector <8 x i8> <i8 0, i8 0, i8 poison, i8 0, i8 0, i8 poison, i8 0, i8 0>, <8 x i8> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 poison, i32 6, i32 7>
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[TMP33]], i8 [[TMP2]], i32 5
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[TMP33]], i8 [[TMP2]], i64 5
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq <8 x i8> [[TMP7]], zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i48> <i48 poison, i48 0, i48 0, i48 0>, i48 [[TEST_STRUCTCOPY_14_S14_CM_COERCE_SROA_2_0_COPYLOAD]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i48> <i48 poison, i48 0, i48 0, i48 0>, i48 [[TEST_STRUCTCOPY_14_S14_CM_COERCE_SROA_2_0_COPYLOAD]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = trunc <4 x i48> [[TMP9]] to <4 x i8>
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <4 x i8> zeroinitializer, [[TMP10]]
; CHECK-NEXT: [[TMP14:%.*]] = load <2 x i8>, ptr addrspace(21) getelementptr inbounds (i8, ptr addrspace(21) null, i64 8), align 8
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i8> <i8 0, i8 poison, i8 0, i8 poison, i8 poison, i8 0, i8 0, i8 0>, i8 [[TMP12]], i32 1
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i8> <i8 0, i8 poison, i8 0, i8 poison, i8 poison, i8 0, i8 0, i8 0>, i8 [[TMP12]], i64 1
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x i8> [[TMP14]], <2 x i8> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <8 x i8> [[TMP15]], <8 x i8> [[TMP16]], <8 x i32> <i32 0, i32 1, i32 2, i32 8, i32 9, i32 5, i32 6, i32 7>
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <8 x i8> <i8 0, i8 poison, i8 0, i8 poison, i8 0, i8 0, i8 0, i8 0>, i8 [[TMP0]], i32 3
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <8 x i8> [[TMP18]], i8 [[TMP13]], i32 1
+; CHECK-NEXT: [[TMP34:%.*]] = insertelement <8 x i8> <i8 0, i8 poison, i8 0, i8 poison, i8 0, i8 0, i8 0, i8 0>, i8 [[TMP0]], i64 3
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <8 x i8> [[TMP34]], i8 [[TMP13]], i64 1
; CHECK-NEXT: [[TMP20:%.*]] = icmp eq <8 x i8> [[TMP17]], [[TMP19]]
-; CHECK-NEXT: [[TMP21:%.*]] = insertelement <64 x i1> <i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 poison, i1 poison, i1 poison, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison>, i1 [[CMP13_NOT_5]], i32 0
+; CHECK-NEXT: [[TMP21:%.*]] = insertelement <64 x i1> <i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 poison, i1 poison, i1 poison, i1 poison, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison, i1 poison>, i1 [[CMP13_NOT_5]], i64 0
; CHECK-NEXT: [[TMP22:%.*]] = shufflevector <8 x i1> [[TMP8]], <8 x i1> poison, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <64 x i1> [[TMP21]], <64 x i1> [[TMP22]], <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <8 x i1> [[TMP20]], <8 x i1> poison, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
index 70f2e1a4cc725..bf35b3fb0c07f 100644
--- a/llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/insert-element-build-vector-inseltpoison.ll
@@ -382,10 +382,10 @@ define <4 x float> @take_credit(<4 x float> %a, <4 x float> %b) {
; Make sure we handle multiple trees that feed one build vector correctly.
define <4 x double> @multi_tree(double %w, double %x, double %y, double %z) {
; CHECK-LABEL: @multi_tree(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[Z:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[Y:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[X:%.*]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[W:%.*]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[Z:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[Y:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[X:%.*]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[W:%.*]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x double> [[TMP4]], <double 3.000000e+00, double 2.000000e+00, double 1.000000e+00, double 0.000000e+00>
; CHECK-NEXT: [[TMP6:%.*]] = fmul <4 x double> [[TMP5]], splat (double 1.000000e+00)
; CHECK-NEXT: ret <4 x double> [[TMP6]]
diff --git a/llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll b/llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
index c71d04f64bd6c..ee07f451c5a1d 100644
--- a/llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/insert-element-build-vector.ll
@@ -418,10 +418,10 @@ define <4 x float> @take_credit(<4 x float> %a, <4 x float> %b) {
; Make sure we handle multiple trees that feed one build vector correctly.
define <4 x double> @multi_tree(double %w, double %x, double %y, double %z) {
; CHECK-LABEL: @multi_tree(
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[Z:%.*]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[Y:%.*]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[X:%.*]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[W:%.*]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[Z:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[Y:%.*]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[X:%.*]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[W:%.*]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x double> [[TMP4]], <double 3.000000e+00, double 2.000000e+00, double 1.000000e+00, double 0.000000e+00>
; CHECK-NEXT: [[TMP6:%.*]] = fmul <4 x double> [[TMP5]], splat (double 1.000000e+00)
; CHECK-NEXT: ret <4 x double> [[TMP6]]
diff --git a/llvm/test/Transforms/SLPVectorizer/insert-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/insert-shuffle.ll
index 2d6e83b4add41..2dd075e6c44b8 100644
--- a/llvm/test/Transforms/SLPVectorizer/insert-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/insert-shuffle.ll
@@ -11,8 +11,8 @@ define { <2 x float>, <2 x float> } @foo(ptr %v) {
; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr undef, align 4
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr [[V:%.*]], align 16
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> <float undef, float poison, float poison, float undef>, float [[TMP0]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> <float undef, float poison, float poison, float undef>, float [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[TMP1]], i64 2
; CHECK-NEXT: [[TMP6:%.*]] = fmul <4 x float> [[SHUFFLE]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = fadd <4 x float> [[TMP6]], undef
; CHECK-NEXT: [[TMP8:%.*]] = fadd <4 x float> [[TMP7]], undef
diff --git a/llvm/test/Transforms/SLPVectorizer/insertelement-across-zero.ll b/llvm/test/Transforms/SLPVectorizer/insertelement-across-zero.ll
index a7fa1607d8f32..ae87f68d03899 100644
--- a/llvm/test/Transforms/SLPVectorizer/insertelement-across-zero.ll
+++ b/llvm/test/Transforms/SLPVectorizer/insertelement-across-zero.ll
@@ -9,8 +9,8 @@ define void @test(i8 %0, i8 %1) {
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i8> [[TMP2]], <8 x i8> poison, <16 x i32> <i32 7, i32 6, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 poison, i32 poison>
; CHECK-NEXT: [[LUPTO132421:%.*]] = shufflevector <16 x i8> zeroinitializer, <16 x i8> [[TMP3]], <16 x i32> <i32 16, i32 17, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 14, i32 15>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <16 x i8> [[LUPTO132421]], <16 x i8> <i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> [[TMP6]], i8 [[TMP0]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x i8> [[TMP4]], i8 [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP6]], i8 [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[TMP1]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i8> [[TMP2]], <8 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <16 x i8> [[TMP5]], <16 x i8> [[TMP7]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i8> [[TMP8]], <16 x i8> poison, <16 x i32> <i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 7, i32 0, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0, i32 15>
diff --git a/llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll b/llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
index 664814d12851b..ebd263785e2d1 100644
--- a/llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
+++ b/llvm/test/Transforms/SLPVectorizer/insertelement-postpone.ll
@@ -8,9 +8,9 @@ define <4 x double> @test(ptr %p2, double %i1754, double %i1781, double %i1778)
; X86-NEXT: [[I1771:%.*]] = getelementptr inbounds double, ptr [[P2:%.*]], i64 54
; X86-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[I1771]], align 8
; X86-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 0>
-; X86-NEXT: [[TMP0:%.*]] = insertelement <4 x double> [[TMP4]], double [[I1754:%.*]], i32 0
-; X86-NEXT: [[TMP1:%.*]] = insertelement <4 x double> [[TMP0]], double [[I1778:%.*]], i32 1
-; X86-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[I1781:%.*]], i32 2
+; X86-NEXT: [[TMP12:%.*]] = insertelement <4 x double> [[TMP4]], double [[I1754:%.*]], i64 0
+; X86-NEXT: [[TMP13:%.*]] = insertelement <4 x double> [[TMP12]], double [[I1778:%.*]], i64 1
+; X86-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP13]], double [[I1781:%.*]], i64 2
; X86-NEXT: [[TMP10:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <4 x i32> zeroinitializer
; X86-NEXT: [[TMP5:%.*]] = fmul fast <4 x double> [[TMP2]], [[TMP10]]
; X86-NEXT: [[TMP11:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 poison, i32 poison, i32 poison, i32 1>
@@ -25,9 +25,9 @@ define <4 x double> @test(ptr %p2, double %i1754, double %i1781, double %i1778)
; AARCH86-NEXT: [[I1771:%.*]] = getelementptr inbounds double, ptr [[P2:%.*]], i64 54
; AARCH86-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[I1771]], align 8
; AARCH86-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 0>
-; AARCH86-NEXT: [[TMP0:%.*]] = insertelement <4 x double> [[TMP4]], double [[I1754:%.*]], i32 0
-; AARCH86-NEXT: [[TMP1:%.*]] = insertelement <4 x double> [[TMP0]], double [[I1778:%.*]], i32 1
-; AARCH86-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[I1781:%.*]], i32 2
+; AARCH86-NEXT: [[TMP11:%.*]] = insertelement <4 x double> [[TMP4]], double [[I1754:%.*]], i64 0
+; AARCH86-NEXT: [[TMP12:%.*]] = insertelement <4 x double> [[TMP11]], double [[I1778:%.*]], i64 1
+; AARCH86-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP12]], double [[I1781:%.*]], i64 2
; AARCH86-NEXT: [[TMP10:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> poison, <4 x i32> zeroinitializer
; AARCH86-NEXT: [[TMP5:%.*]] = fmul fast <4 x double> [[TMP2]], [[TMP10]]
; AARCH86-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 poison, i32 poison, i32 poison, i32 1>
diff --git a/llvm/test/Transforms/SLPVectorizer/insertelement-uses-vectorized-index.ll b/llvm/test/Transforms/SLPVectorizer/insertelement-uses-vectorized-index.ll
index 0734fd80709f7..7e4b2c72a23d7 100644
--- a/llvm/test/Transforms/SLPVectorizer/insertelement-uses-vectorized-index.ll
+++ b/llvm/test/Transforms/SLPVectorizer/insertelement-uses-vectorized-index.ll
@@ -6,7 +6,7 @@ define void @test(ptr %0) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[TMP0:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> <ptr null, ptr poison>, ptr [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> <ptr null, ptr poison>, ptr [[TMP0]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint <2 x ptr> [[TMP1]] to <2 x i64>
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP0]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP8]] to i32
diff --git a/llvm/test/Transforms/SLPVectorizer/int-bitcast-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/int-bitcast-minbitwidth.ll
index 766deccf1250b..beee99138586d 100644
--- a/llvm/test/Transforms/SLPVectorizer/int-bitcast-minbitwidth.ll
+++ b/llvm/test/Transforms/SLPVectorizer/int-bitcast-minbitwidth.ll
@@ -7,7 +7,7 @@ define void @t(i64 %v) {
; CHECK-SAME: i64 [[V:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[V]] to i16
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i16> [[TMP2]], <i16 2, i16 3, i16 6, i16 5>
; CHECK-NEXT: [[TMP4:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP3]])
diff --git a/llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll b/llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll
index 7a31474d8cb88..f8c0dbdf63142 100644
--- a/llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll
+++ b/llvm/test/Transforms/SLPVectorizer/jumbled_store_crash.ll
@@ -26,18 +26,18 @@ define dso_local void @j() local_unnamed_addr {
; CHECK-NEXT: [[TMP8:%.*]] = fmul <2 x float> [[TMP7]], splat (float 1.000000e+01)
; CHECK-NEXT: [[TMP9:%.*]] = fsub <2 x float> <float 1.000000e+00, float 0.000000e+00>, [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x float> [[TMP9]], <2 x float> poison, <4 x i32> <i32 1, i32 0, i32 1, i32 0>
-; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x float> [[TMP10]], i32 1
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x float> [[TMP10]], i64 1
; CHECK-NEXT: store float [[TMP11]], ptr @g, align 4
; CHECK-NEXT: [[TMP12:%.*]] = fadd <4 x float> [[TMP10]], <float -1.000000e+00, float -1.000000e+00, float 1.000000e+00, float 1.000000e+00>
-; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP12]], i32 2
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP12]], i64 2
; CHECK-NEXT: store float [[TMP13]], ptr @c, align 4
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x float> [[TMP12]], i32 0
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x float> [[TMP12]], i64 0
; CHECK-NEXT: store float [[TMP14]], ptr @d, align 4
-; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x float> [[TMP12]], i32 3
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x float> [[TMP12]], i64 3
; CHECK-NEXT: store float [[TMP15]], ptr @e, align 4
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x float> [[TMP12]], i32 1
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x float> [[TMP12]], i64 1
; CHECK-NEXT: store float [[TMP16]], ptr @f, align 4
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x float> <float poison, float 1.000000e+00, float poison, float 1.000000e+00>, float [[CONV19]], i32 0
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x float> <float poison, float 1.000000e+00, float poison, float 1.000000e+00>, float [[CONV19]], i64 0
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <2 x float> [[TMP9]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <4 x float> [[TMP17]], <4 x float> [[TMP18]], <4 x i32> <i32 0, i32 1, i32 5, i32 3>
; CHECK-NEXT: [[TMP20:%.*]] = fsub <4 x float> [[TMP12]], [[TMP19]]
diff --git a/llvm/test/Transforms/SLPVectorizer/last-buildvector-node.ll b/llvm/test/Transforms/SLPVectorizer/last-buildvector-node.ll
index efd418a071345..145079b73959b 100644
--- a/llvm/test/Transforms/SLPVectorizer/last-buildvector-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/last-buildvector-node.ll
@@ -10,11 +10,11 @@ define i16 @test(i40 %0) {
; CHECK-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD63_I]] to i16
; CHECK-NEXT: tail call void null(i16 0, i16 [[CONV6]], i16 0)
; CHECK-NEXT: [[TMP1:%.*]] = tail call i40 asm "copy $1, $0", "=a,a"(i40 0)
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i40> <i40 0, i40 0, i40 0, i40 poison, i40 poison, i40 -1, i40 0, i40 0>, i40 [[TMP0]], i32 3
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i40> [[TMP2]], i40 [[TMP1]], i32 4
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i40> <i40 0, i40 0, i40 0, i40 poison, i40 poison, i40 -1, i40 0, i40 0>, i40 [[TMP0]], i64 3
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i40> [[TMP2]], i40 [[TMP1]], i64 4
; CHECK-NEXT: [[TMP4:%.*]] = add <8 x i40> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i40> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i40> <i40 0, i40 0, i40 0, i40 0, i40 0, i40 0, i40 poison, i40 0>, i40 [[TMP1]], i32 6
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i40> <i40 0, i40 0, i40 0, i40 0, i40 0, i40 0, i40 poison, i40 0>, i40 [[TMP1]], i64 6
; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i40> zeroinitializer, [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i40> [[TMP5]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i40> [[TMP8]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/materialize-vector-of-consts.ll b/llvm/test/Transforms/SLPVectorizer/materialize-vector-of-consts.ll
index 2f58bd25b7564..cc7ff7b147bee 100644
--- a/llvm/test/Transforms/SLPVectorizer/materialize-vector-of-consts.ll
+++ b/llvm/test/Transforms/SLPVectorizer/materialize-vector-of-consts.ll
@@ -4,8 +4,8 @@
define <2 x float> @v2f32_diff_consts(float %a, float %b)
; CHECK-LABEL: define <2 x float> @v2f32_diff_consts(
; CHECK-SAME: float [[A:%.*]], float [[B:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[A]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[B]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[A]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[B]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP2]], <float 2.200000e+01, float 2.300000e+01>
; CHECK-NEXT: ret <2 x float> [[TMP3]]
;
@@ -20,8 +20,8 @@ define <2 x float> @v2f32_diff_consts(float %a, float %b)
define <2 x float> @v2f32_const_splat(float %a, float %b)
; CHECK-LABEL: define <2 x float> @v2f32_const_splat(
; CHECK-SAME: float [[A:%.*]], float [[B:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[A]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[B]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[A]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[B]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x float> [[TMP2]], splat (float 2.200000e+01)
; CHECK-NEXT: ret <2 x float> [[TMP3]]
;
@@ -36,10 +36,10 @@ define <2 x float> @v2f32_const_splat(float %a, float %b)
define <4 x double> @v4f64_illegal_type(double %a, double %b, double %c, double %d)
; CHECK-LABEL: define <4 x double> @v4f64_illegal_type(
; CHECK-SAME: double [[A:%.*]], double [[B:%.*]], double [[C:%.*]], double [[D:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[A]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[B]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[C]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[D]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x double> poison, double [[A]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[B]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[C]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[D]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = fmul <4 x double> [[TMP4]], <double 2.100000e+01, double 2.200000e+01, double 2.300000e+01, double 2.400000e+01>
; CHECK-NEXT: ret <4 x double> [[TMP5]]
;
@@ -58,11 +58,11 @@ define <4 x double> @v4f64_illegal_type(double %a, double %b, double %c, double
define <2 x double> @v2f64_dup_const_vector_case1(double %a, double %b, double %c, double %d)
; CHECK-LABEL: define <2 x double> @v2f64_dup_const_vector_case1(
; CHECK-SAME: double [[A:%.*]], double [[B:%.*]], double [[C:%.*]], double [[D:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[B]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[B]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP2]], <double 2.100000e+01, double 2.200000e+01>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[C]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> [[TMP4]], double [[D]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> poison, double [[C]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> [[TMP4]], double [[D]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x double> [[TMP5]], <double 2.100000e+01, double 2.200000e+01>
; CHECK-NEXT: [[TMP7:%.*]] = fadd <2 x double> [[TMP3]], [[TMP6]]
; CHECK-NEXT: ret <2 x double> [[TMP7]]
@@ -83,8 +83,8 @@ define <2 x double> @v2f64_dup_const_vector_case1(double %a, double %b, double %
define <2 x double> @v2f64_dup_const_vector_case2(double %a, double %b, double %c, double %d)
; CHECK-LABEL: define <2 x double> @v2f64_dup_const_vector_case2(
; CHECK-SAME: double [[A:%.*]], double [[B:%.*]], double [[C:%.*]], double [[D:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[B]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[B]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = fmul <2 x double> [[TMP2]], <double 2.100000e+01, double 2.200000e+01>
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP3]], <double 2.100000e+01, double 2.200000e+01>
; CHECK-NEXT: ret <2 x double> [[TMP4]]
diff --git a/llvm/test/Transforms/SLPVectorizer/minbitwidth-multiuse-with-insertelement.ll b/llvm/test/Transforms/SLPVectorizer/minbitwidth-multiuse-with-insertelement.ll
index 97341d1b49037..3351afab47207 100644
--- a/llvm/test/Transforms/SLPVectorizer/minbitwidth-multiuse-with-insertelement.ll
+++ b/llvm/test/Transforms/SLPVectorizer/minbitwidth-multiuse-with-insertelement.ll
@@ -6,12 +6,12 @@ define void @test(i8 %0) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i8 [[TMP0:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> <i8 0, i8 poison>, i8 [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> <i8 0, i8 poison>, i8 [[TMP0]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = mul <2 x i8> [[TMP1]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i8> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i8> [[TMP3]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP4]] to i32
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[TMP3]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = zext i8 [[TMP6]] to i32
; CHECK-NEXT: [[ADD:%.*]] = or i32 [[TMP5]], [[TMP7]]
; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[ADD]], 1
diff --git a/llvm/test/Transforms/SLPVectorizer/minbitwidth-user-not-min.ll b/llvm/test/Transforms/SLPVectorizer/minbitwidth-user-not-min.ll
index 28def6968b3fb..57e4c67cdd255 100644
--- a/llvm/test/Transforms/SLPVectorizer/minbitwidth-user-not-min.ll
+++ b/llvm/test/Transforms/SLPVectorizer/minbitwidth-user-not-min.ll
@@ -6,7 +6,7 @@ define void @test(ptr %block, ptr noalias %pixels, i1 %b) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[BLOCK:%.*]], ptr noalias [[PIXELS:%.*]], i1 [[B:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i1> <i1 true, i1 poison, i1 false, i1 false>, i1 [[B]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i1> <i1 true, i1 poison, i1 false, i1 false>, i1 [[B]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i1> [[TMP0]] to <4 x i8>
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[BLOCK]], align 2
; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <4 x i16> [[TMP2]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/multi-node-vectorized-insts.ll b/llvm/test/Transforms/SLPVectorizer/multi-node-vectorized-insts.ll
index 8abc6ef236a3c..e8836afbc55bc 100644
--- a/llvm/test/Transforms/SLPVectorizer/multi-node-vectorized-insts.ll
+++ b/llvm/test/Transforms/SLPVectorizer/multi-node-vectorized-insts.ll
@@ -5,7 +5,7 @@
define void @test(double %0) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label [[TMP4:%.*]]
; CHECK: 4:
@@ -37,7 +37,7 @@ define void @test1(double %0, <4 x double> %v) {
; CHECK-LABEL: define void @test1(
; CHECK-SAME: double [[TMP0:%.*]], <4 x double> [[V:%.*]]) {
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[V]], <4 x double> poison, <2 x i32> <i32 poison, i32 0>
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[TMP0]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 0>
; CHECK-NEXT: br label [[TMP5:%.*]]
; CHECK: 5:
@@ -80,7 +80,7 @@ define void @test1(double %0, <4 x double> %v) {
define void @test2(double %0) {
; CHECK-LABEL: define void @test2(
; CHECK-SAME: double [[TMP0:%.*]]) {
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label [[TMP4:%.*]]
; CHECK: 4:
diff --git a/llvm/test/Transforms/SLPVectorizer/multi-uses-with-deps-in-first.ll b/llvm/test/Transforms/SLPVectorizer/multi-uses-with-deps-in-first.ll
index a8942596a99de..2cfb0f9b18e46 100644
--- a/llvm/test/Transforms/SLPVectorizer/multi-uses-with-deps-in-first.ll
+++ b/llvm/test/Transforms/SLPVectorizer/multi-uses-with-deps-in-first.ll
@@ -7,7 +7,7 @@ define void @test(double %add) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: double [[ADD:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[ADD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[ADD]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x double> [[TMP0]], zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[TMP0]], zeroinitializer
; CHECK-NEXT: br label [[COND_TRUE45:%.*]]
diff --git a/llvm/test/Transforms/SLPVectorizer/operand-is-reduced-val.ll b/llvm/test/Transforms/SLPVectorizer/operand-is-reduced-val.ll
index 5480b9867b32e..950780bdc2b84 100644
--- a/llvm/test/Transforms/SLPVectorizer/operand-is-reduced-val.ll
+++ b/llvm/test/Transforms/SLPVectorizer/operand-is-reduced-val.ll
@@ -7,7 +7,7 @@ define i64 @src(i32 %a) {
; X86-SAME: i32 [[A:%.*]]) {
; X86-NEXT: [[ENTRY:.*:]]
; X86-NEXT: [[TMP0:%.*]] = sext i32 [[A]] to i64
-; X86-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0
+; X86-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0
; X86-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; X86-NEXT: [[TMP3:%.*]] = sext <4 x i32> [[TMP2]] to <4 x i64>
; X86-NEXT: [[TMP4:%.*]] = add nsw <4 x i64> [[TMP3]], splat (i64 4294967297)
@@ -22,7 +22,7 @@ define i64 @src(i32 %a) {
; AARCH64-SAME: i32 [[A:%.*]]) {
; AARCH64-NEXT: [[ENTRY:.*:]]
; AARCH64-NEXT: [[TMP0:%.*]] = sext i32 [[A]] to i64
-; AARCH64-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0
+; AARCH64-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0
; AARCH64-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; AARCH64-NEXT: [[TMP3:%.*]] = sext <4 x i32> [[TMP2]] to <4 x i64>
; AARCH64-NEXT: [[TMP4:%.*]] = add nsw <4 x i64> [[TMP3]], splat (i64 4294967297)
diff --git a/llvm/test/Transforms/SLPVectorizer/partial-register-extract.ll b/llvm/test/Transforms/SLPVectorizer/partial-register-extract.ll
index c0a0318efd19e..9f3a3a8966df3 100644
--- a/llvm/test/Transforms/SLPVectorizer/partial-register-extract.ll
+++ b/llvm/test/Transforms/SLPVectorizer/partial-register-extract.ll
@@ -8,10 +8,10 @@ define i32 @test(i32 %v, ptr %p) {
; CHECK-NEXT: [[LD:%.*]] = load i32, ptr [[P]], align 4
; CHECK-NEXT: br i1 false, label %[[INC:.*]], label %[[PH:.*]]
; CHECK: [[PH]]:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LD]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[LD]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <4 x i32> [[TMP1]], zeroinitializer
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 0>, i32 [[V]], i32 13
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison, i32 0, i32 0>, i32 [[V]], i64 13
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <16 x i32> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <16 x i1> [[TMP5]], <16 x i1> [[TMP4]], <4 x i32> <i32 0, i32 31, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/phi-undef-input.ll b/llvm/test/Transforms/SLPVectorizer/phi-undef-input.ll
index b9802a0adb8aa..c899c4b73da88 100644
--- a/llvm/test/Transforms/SLPVectorizer/phi-undef-input.ll
+++ b/llvm/test/Transforms/SLPVectorizer/phi-undef-input.ll
@@ -9,10 +9,10 @@ define i32 @phi3UndefInput(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i64 3
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 undef, i8 undef, i8 undef>, [[ENTRY:%.*]] ]
@@ -46,10 +46,10 @@ define i32 @phi2UndefInput(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i64 3
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 0, i8 undef, i8 undef>, [[ENTRY:%.*]] ]
@@ -83,10 +83,10 @@ define i32 @phi1UndefInput(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i64 3
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 0, i8 0, i8 undef>, [[ENTRY:%.*]] ]
@@ -121,10 +121,10 @@ define i32 @phi1Undef1PoisonInput(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %ar
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG0:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG1:%.*]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i64 3
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 0, i8 poison, i8 undef>, [[ENTRY:%.*]] ]
@@ -159,10 +159,10 @@ define i32 @phi1Undef2PoisonInputs(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8 %a
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG1:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG0:%.*]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG1:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG0:%.*]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG2:%.*]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG3:%.*]], i64 3
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 poison, i8 poison, i8 undef>, [[ENTRY:%.*]] ]
@@ -196,10 +196,10 @@ define i32 @phi1Undef1PoisonGapInput(i1 %cond, i8 %arg0, i8 %arg1, i8 %arg2, i8
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG1:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG3:%.*]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG0:%.*]], i32 2
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG2:%.*]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[ARG1:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i8> [[TMP0]], i8 [[ARG3:%.*]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> [[TMP1]], i8 [[ARG0:%.*]], i64 2
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[ARG2:%.*]], i64 3
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
; CHECK-NEXT: [[TMP4:%.*]] = phi <4 x i8> [ [[TMP3]], [[BB2]] ], [ <i8 0, i8 0, i8 poison, i8 undef>, [[ENTRY:%.*]] ]
diff --git a/llvm/test/Transforms/SLPVectorizer/postponed_gathers.ll b/llvm/test/Transforms/SLPVectorizer/postponed_gathers.ll
index f6bed797b9ba9..2fc6684cdad5a 100644
--- a/llvm/test/Transforms/SLPVectorizer/postponed_gathers.ll
+++ b/llvm/test/Transforms/SLPVectorizer/postponed_gathers.ll
@@ -6,7 +6,7 @@ define void @foo() {
; CHECK-LABEL: define void @foo() {
; CHECK-NEXT: bci_0:
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(1) null, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label [[BCI_252:%.*]]
; CHECK: bci_252:
diff --git a/llvm/test/Transforms/SLPVectorizer/reduced-gathered-vectorized.ll b/llvm/test/Transforms/SLPVectorizer/reduced-gathered-vectorized.ll
index 5f9175a917b63..88ad2921273ab 100644
--- a/llvm/test/Transforms/SLPVectorizer/reduced-gathered-vectorized.ll
+++ b/llvm/test/Transforms/SLPVectorizer/reduced-gathered-vectorized.ll
@@ -19,10 +19,10 @@ define i16 @test() {
; X86-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> poison, <2 x i32> <i32 1, i32 0>
; X86-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr [[A1]], align 16
; X86-NEXT: [[TMP6:%.*]] = load i64, ptr [[A3]], align 16
-; X86-NEXT: [[TMP7:%.*]] = insertelement <8 x i64> poison, i64 [[TMP1]], i32 0
+; X86-NEXT: [[TMP7:%.*]] = insertelement <8 x i64> poison, i64 [[TMP1]], i64 0
; X86-NEXT: [[TMP12:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; X86-NEXT: [[TMP9:%.*]] = shufflevector <8 x i64> [[TMP7]], <8 x i64> [[TMP12]], <8 x i32> <i32 0, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; X86-NEXT: [[TMP10:%.*]] = insertelement <8 x i64> [[TMP9]], i64 [[TMP0]], i32 3
+; X86-NEXT: [[TMP10:%.*]] = insertelement <8 x i64> [[TMP9]], i64 [[TMP0]], i64 3
; X86-NEXT: [[TMP13:%.*]] = shufflevector <2 x i64> [[TMP8]], <2 x i64> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; X86-NEXT: [[TMP16:%.*]] = shufflevector <8 x i64> [[TMP10]], <8 x i64> [[TMP13]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; X86-NEXT: [[TMP18:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -49,10 +49,10 @@ define i16 @test() {
; AARCH64-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP8]], <2 x i64> poison, <2 x i32> <i32 1, i32 0>
; AARCH64-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr [[A1]], align 16
; AARCH64-NEXT: [[TMP6:%.*]] = load i64, ptr [[A3]], align 16
-; AARCH64-NEXT: [[TMP7:%.*]] = insertelement <8 x i64> poison, i64 [[TMP2]], i32 0
+; AARCH64-NEXT: [[TMP7:%.*]] = insertelement <8 x i64> poison, i64 [[TMP2]], i64 0
; AARCH64-NEXT: [[TMP9:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AARCH64-NEXT: [[TMP15:%.*]] = shufflevector <8 x i64> [[TMP7]], <8 x i64> [[TMP9]], <8 x i32> <i32 0, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; AARCH64-NEXT: [[TMP10:%.*]] = insertelement <8 x i64> [[TMP15]], i64 [[TMP0]], i32 3
+; AARCH64-NEXT: [[TMP10:%.*]] = insertelement <8 x i64> [[TMP15]], i64 [[TMP0]], i64 3
; AARCH64-NEXT: [[TMP13:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AARCH64-NEXT: [[TMP16:%.*]] = shufflevector <8 x i64> [[TMP10]], <8 x i64> [[TMP13]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; AARCH64-NEXT: [[TMP17:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
diff --git a/llvm/test/Transforms/SLPVectorizer/reorder-clustered-node.ll b/llvm/test/Transforms/SLPVectorizer/reorder-clustered-node.ll
index ea720198b831e..f386da228fe1c 100644
--- a/llvm/test/Transforms/SLPVectorizer/reorder-clustered-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/reorder-clustered-node.ll
@@ -12,15 +12,15 @@ define i1 @test(ptr %arg, ptr %i233, i64 %i241, ptr %i235, ptr %i237, ptr %i227)
; X86-NEXT: [[I250:%.*]] = getelementptr double, ptr [[I227:%.*]], i64 [[I241]]
; X86-NEXT: [[TMP0:%.*]] = load <4 x ptr>, ptr [[I226]], align 8
; X86-NEXT: [[TMP6:%.*]] = shufflevector <4 x ptr> [[TMP0]], <4 x ptr> poison, <4 x i32> <i32 1, i32 3, i32 0, i32 2>
-; X86-NEXT: [[TMP2:%.*]] = insertelement <8 x ptr> <ptr null, ptr null, ptr poison, ptr poison, ptr null, ptr null, ptr null, ptr null>, ptr [[I242]], i32 2
-; X86-NEXT: [[TMP3:%.*]] = insertelement <8 x ptr> [[TMP2]], ptr [[I250]], i32 3
+; X86-NEXT: [[TMP2:%.*]] = insertelement <8 x ptr> <ptr null, ptr null, ptr poison, ptr poison, ptr null, ptr null, ptr null, ptr null>, ptr [[I242]], i64 2
+; X86-NEXT: [[TMP3:%.*]] = insertelement <8 x ptr> [[TMP2]], ptr [[I250]], i64 3
; X86-NEXT: [[TMP1:%.*]] = shufflevector <4 x ptr> [[TMP0]], <4 x ptr> poison, <8 x i32> <i32 1, i32 3, i32 0, i32 2, i32 0, i32 2, i32 1, i32 3>
; X86-NEXT: [[TMP5:%.*]] = shufflevector <4 x ptr> [[TMP6]], <4 x ptr> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; X86-NEXT: [[TMP4:%.*]] = icmp ult <8 x ptr> [[TMP3]], [[TMP1]]
-; X86-NEXT: [[TMP7:%.*]] = insertelement <8 x ptr> poison, ptr [[I242]], i32 0
-; X86-NEXT: [[TMP8:%.*]] = insertelement <8 x ptr> [[TMP7]], ptr [[I248]], i32 1
-; X86-NEXT: [[TMP14:%.*]] = insertelement <8 x ptr> [[TMP8]], ptr [[I250]], i32 2
-; X86-NEXT: [[TMP15:%.*]] = insertelement <8 x ptr> [[TMP14]], ptr [[I245]], i32 3
+; X86-NEXT: [[TMP7:%.*]] = insertelement <8 x ptr> poison, ptr [[I242]], i64 0
+; X86-NEXT: [[TMP8:%.*]] = insertelement <8 x ptr> [[TMP7]], ptr [[I248]], i64 1
+; X86-NEXT: [[TMP14:%.*]] = insertelement <8 x ptr> [[TMP8]], ptr [[I250]], i64 2
+; X86-NEXT: [[TMP15:%.*]] = insertelement <8 x ptr> [[TMP14]], ptr [[I245]], i64 3
; X86-NEXT: [[TMP9:%.*]] = shufflevector <8 x ptr> [[TMP15]], <8 x ptr> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1>
; X86-NEXT: [[TMP16:%.*]] = shufflevector <4 x ptr> [[TMP6]], <4 x ptr> poison, <8 x i32> <i32 0, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; X86-NEXT: [[TMP17:%.*]] = shufflevector <4 x ptr> [[TMP0]], <4 x ptr> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -40,12 +40,12 @@ define i1 @test(ptr %arg, ptr %i233, i64 %i241, ptr %i235, ptr %i237, ptr %i227)
; AARCH64-NEXT: [[I250:%.*]] = getelementptr double, ptr [[I227:%.*]], i64 [[I241]]
; AARCH64-NEXT: [[TMP0:%.*]] = load <4 x ptr>, ptr [[I226]], align 8
; AARCH64-NEXT: [[TMP1:%.*]] = shufflevector <4 x ptr> [[TMP0]], <4 x ptr> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
-; AARCH64-NEXT: [[TMP2:%.*]] = insertelement <8 x ptr> <ptr poison, ptr null, ptr poison, ptr null, ptr null, ptr null, ptr null, ptr null>, ptr [[I242]], i32 0
-; AARCH64-NEXT: [[TMP3:%.*]] = insertelement <8 x ptr> [[TMP2]], ptr [[I250]], i32 2
+; AARCH64-NEXT: [[TMP2:%.*]] = insertelement <8 x ptr> <ptr poison, ptr null, ptr poison, ptr null, ptr null, ptr null, ptr null, ptr null>, ptr [[I242]], i64 0
+; AARCH64-NEXT: [[TMP3:%.*]] = insertelement <8 x ptr> [[TMP2]], ptr [[I250]], i64 2
; AARCH64-NEXT: [[TMP4:%.*]] = icmp ult <8 x ptr> [[TMP3]], [[TMP1]]
; AARCH64-NEXT: [[TMP5:%.*]] = shufflevector <8 x ptr> [[TMP3]], <8 x ptr> poison, <8 x i32> <i32 2, i32 0, i32 poison, i32 poison, i32 2, i32 0, i32 poison, i32 poison>
-; AARCH64-NEXT: [[TMP6:%.*]] = insertelement <8 x ptr> [[TMP5]], ptr [[I245]], i32 2
-; AARCH64-NEXT: [[TMP7:%.*]] = insertelement <8 x ptr> [[TMP6]], ptr [[I248]], i32 3
+; AARCH64-NEXT: [[TMP6:%.*]] = insertelement <8 x ptr> [[TMP5]], ptr [[I245]], i64 2
+; AARCH64-NEXT: [[TMP7:%.*]] = insertelement <8 x ptr> [[TMP6]], ptr [[I248]], i64 3
; AARCH64-NEXT: [[TMP8:%.*]] = shufflevector <8 x ptr> [[TMP7]], <8 x ptr> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 2, i32 3>
; AARCH64-NEXT: [[TMP9:%.*]] = shufflevector <8 x ptr> [[TMP1]], <8 x ptr> <ptr poison, ptr null, ptr poison, ptr null, ptr null, ptr null, ptr null, ptr null>, <8 x i32> <i32 1, i32 9, i32 0, i32 11, i32 12, i32 13, i32 14, i32 15>
; AARCH64-NEXT: [[TMP10:%.*]] = icmp ult <8 x ptr> [[TMP8]], [[TMP9]]
diff --git a/llvm/test/Transforms/SLPVectorizer/reordered-top-scalars.ll b/llvm/test/Transforms/SLPVectorizer/reordered-top-scalars.ll
index 1de5ee2298837..bd8c06f5340c9 100644
--- a/llvm/test/Transforms/SLPVectorizer/reordered-top-scalars.ll
+++ b/llvm/test/Transforms/SLPVectorizer/reordered-top-scalars.ll
@@ -14,8 +14,8 @@ define i32 @test(ptr %isec) {
; CHECK-NEXT: br label [[BLOCK3]]
; CHECK: block3:
; CHECK-NEXT: [[TMP3:%.*]] = phi <2 x i32> [ [[TMP1]], [[BLOCK1]] ], [ [[TMP1]], [[BLOCK2]] ], [ [[TMP2]], [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP3]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP3]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP3]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP4]]
; CHECK-NEXT: ret i32 [[TMP6]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll b/llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
index cf7faf8448c11..b06032bb4929d 100644
--- a/llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
+++ b/llvm/test/Transforms/SLPVectorizer/reordering-single-phi.ll
@@ -19,7 +19,7 @@ define void @test() {
; CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX31]], align 4
; CHECK-NEXT: [[TMP14:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP14]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 1, i32 2>
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> poison, float [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> poison, float [[TMP0]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP7]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP15:%.*]] = fmul fast <4 x float> [[TMP11]], [[TMP14]]
; CHECK-NEXT: store <4 x float> [[TMP15]], ptr [[ARRAYIDX6]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/reschedule.ll b/llvm/test/Transforms/SLPVectorizer/reschedule.ll
index 825329b5af97e..068ee6b958c53 100644
--- a/llvm/test/Transforms/SLPVectorizer/reschedule.ll
+++ b/llvm/test/Transforms/SLPVectorizer/reschedule.ll
@@ -16,11 +16,11 @@ define void @test() {
; CHECK-NEXT: [[I6:%.*]] = load double, ptr null, align 8
; CHECK-NEXT: [[MUL746:%.*]] = fmul double 0.000000e+00, [[I6]]
; CHECK-NEXT: [[MUL747:%.*]] = fmul double 0.000000e+00, [[I5]]
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[MUL746]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[MUL701]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[MUL746]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[MUL701]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, <2 x double> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[MUL747]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[MUL703]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[MUL747]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[MUL703]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP2]], <2 x double> zeroinitializer, <2 x double> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP5]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
; CHECK-NEXT: [[TMP7:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> zeroinitializer, <2 x double> [[TMP6]], <2 x double> zeroinitializer)
diff --git a/llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll b/llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
index 69b275c796ccd..995ef0703db48 100644
--- a/llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
+++ b/llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
@@ -4,14 +4,14 @@
define void @func(i32 %0) {
; CHECK-LABEL: define void @func(
; CHECK-SAME: i32 [[TMP0:%.*]]) {
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 [[TMP0]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP0]], 0
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <32 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP9:%.*]] = sext i32 [[TMP6]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 0
; CHECK-NEXT: [[TMP11:%.*]] = trunc i64 [[TMP9]] to i32
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 [[TMP11]], i32 30
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>, i32 [[TMP11]], i64 30
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <32 x i32> [[TMP12]], <32 x i32> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 30, i32 30>
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <32 x i32> [[TMP13]], <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 poison, i32 poison, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 30, i32 31>
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <32 x i32> [[TMP15]], <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 poison, i32 poison, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 32, i32 33, i32 34, i32 35, i32 poison, i32 poison, i32 30, i32 31>
@@ -19,64 +19,64 @@ define void @func(i32 %0) {
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <32 x i32> [[TMP14]], <32 x i32> <i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 32, i32 33, i32 30, i32 31>
; CHECK-NEXT: [[TMP18:%.*]] = or <32 x i32> [[TMP8]], [[TMP17]]
; CHECK-NEXT: [[TMP20:%.*]] = icmp slt <32 x i32> [[TMP18]], zeroinitializer
-; CHECK-NEXT: [[TMP21:%.*]] = extractelement <32 x i1> [[TMP20]], i32 31
+; CHECK-NEXT: [[TMP53:%.*]] = extractelement <32 x i1> [[TMP20]], i64 31
+; CHECK-NEXT: [[TMP74:%.*]] = and i1 false, [[TMP53]]
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <32 x i1> [[TMP20]], i64 30
+; CHECK-NEXT: [[TMP75:%.*]] = and i1 false, [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = extractelement <32 x i1> [[TMP20]], i64 29
; CHECK-NEXT: [[TMP22:%.*]] = and i1 false, [[TMP21]]
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <32 x i1> [[TMP20]], i32 30
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <32 x i1> [[TMP20]], i64 28
; CHECK-NEXT: [[TMP24:%.*]] = and i1 false, [[TMP23]]
-; CHECK-NEXT: [[TMP25:%.*]] = extractelement <32 x i1> [[TMP20]], i32 29
+; CHECK-NEXT: [[TMP25:%.*]] = extractelement <32 x i1> [[TMP20]], i64 27
; CHECK-NEXT: [[TMP26:%.*]] = and i1 false, [[TMP25]]
-; CHECK-NEXT: [[TMP27:%.*]] = extractelement <32 x i1> [[TMP20]], i32 28
+; CHECK-NEXT: [[TMP27:%.*]] = extractelement <32 x i1> [[TMP20]], i64 26
; CHECK-NEXT: [[TMP28:%.*]] = and i1 false, [[TMP27]]
-; CHECK-NEXT: [[TMP29:%.*]] = extractelement <32 x i1> [[TMP20]], i32 27
+; CHECK-NEXT: [[TMP29:%.*]] = extractelement <32 x i1> [[TMP20]], i64 25
; CHECK-NEXT: [[TMP30:%.*]] = and i1 false, [[TMP29]]
-; CHECK-NEXT: [[TMP31:%.*]] = extractelement <32 x i1> [[TMP20]], i32 26
+; CHECK-NEXT: [[TMP31:%.*]] = extractelement <32 x i1> [[TMP20]], i64 24
; CHECK-NEXT: [[TMP32:%.*]] = and i1 false, [[TMP31]]
-; CHECK-NEXT: [[TMP33:%.*]] = extractelement <32 x i1> [[TMP20]], i32 25
+; CHECK-NEXT: [[TMP33:%.*]] = extractelement <32 x i1> [[TMP20]], i64 23
; CHECK-NEXT: [[TMP34:%.*]] = and i1 false, [[TMP33]]
-; CHECK-NEXT: [[TMP35:%.*]] = extractelement <32 x i1> [[TMP20]], i32 24
+; CHECK-NEXT: [[TMP35:%.*]] = extractelement <32 x i1> [[TMP20]], i64 22
; CHECK-NEXT: [[TMP36:%.*]] = and i1 false, [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = extractelement <32 x i1> [[TMP20]], i32 23
+; CHECK-NEXT: [[TMP37:%.*]] = extractelement <32 x i1> [[TMP20]], i64 21
; CHECK-NEXT: [[TMP38:%.*]] = and i1 false, [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = extractelement <32 x i1> [[TMP20]], i32 22
+; CHECK-NEXT: [[TMP39:%.*]] = extractelement <32 x i1> [[TMP20]], i64 20
; CHECK-NEXT: [[TMP40:%.*]] = and i1 false, [[TMP39]]
-; CHECK-NEXT: [[TMP41:%.*]] = extractelement <32 x i1> [[TMP20]], i32 21
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <32 x i1> [[TMP20]], i64 19
; CHECK-NEXT: [[TMP42:%.*]] = and i1 false, [[TMP41]]
-; CHECK-NEXT: [[TMP43:%.*]] = extractelement <32 x i1> [[TMP20]], i32 20
+; CHECK-NEXT: [[TMP43:%.*]] = extractelement <32 x i1> [[TMP20]], i64 18
; CHECK-NEXT: [[TMP44:%.*]] = and i1 false, [[TMP43]]
-; CHECK-NEXT: [[TMP45:%.*]] = extractelement <32 x i1> [[TMP20]], i32 19
+; CHECK-NEXT: [[TMP45:%.*]] = extractelement <32 x i1> [[TMP20]], i64 17
; CHECK-NEXT: [[TMP46:%.*]] = and i1 false, [[TMP45]]
-; CHECK-NEXT: [[TMP47:%.*]] = extractelement <32 x i1> [[TMP20]], i32 18
+; CHECK-NEXT: [[TMP47:%.*]] = extractelement <32 x i1> [[TMP20]], i64 16
; CHECK-NEXT: [[TMP48:%.*]] = and i1 false, [[TMP47]]
-; CHECK-NEXT: [[TMP49:%.*]] = extractelement <32 x i1> [[TMP20]], i32 17
+; CHECK-NEXT: [[TMP49:%.*]] = extractelement <32 x i1> [[TMP20]], i64 15
; CHECK-NEXT: [[TMP50:%.*]] = and i1 false, [[TMP49]]
-; CHECK-NEXT: [[TMP51:%.*]] = extractelement <32 x i1> [[TMP20]], i32 16
+; CHECK-NEXT: [[TMP51:%.*]] = extractelement <32 x i1> [[TMP20]], i64 14
; CHECK-NEXT: [[TMP52:%.*]] = and i1 false, [[TMP51]]
-; CHECK-NEXT: [[TMP53:%.*]] = extractelement <32 x i1> [[TMP20]], i32 15
-; CHECK-NEXT: [[TMP54:%.*]] = and i1 false, [[TMP53]]
-; CHECK-NEXT: [[TMP55:%.*]] = extractelement <32 x i1> [[TMP20]], i32 14
-; CHECK-NEXT: [[TMP56:%.*]] = and i1 false, [[TMP55]]
; CHECK-NEXT: [[TMP80:%.*]] = icmp eq i32 [[TMP6]], 0
-; CHECK-NEXT: [[TMP57:%.*]] = extractelement <32 x i1> [[TMP20]], i32 13
-; CHECK-NEXT: [[TMP58:%.*]] = and i1 false, [[TMP57]]
-; CHECK-NEXT: [[TMP59:%.*]] = extractelement <32 x i1> [[TMP20]], i32 12
-; CHECK-NEXT: [[TMP60:%.*]] = and i1 false, [[TMP59]]
-; CHECK-NEXT: [[TMP61:%.*]] = extractelement <32 x i1> [[TMP20]], i32 11
-; CHECK-NEXT: [[TMP62:%.*]] = and i1 false, [[TMP61]]
-; CHECK-NEXT: [[TMP63:%.*]] = extractelement <32 x i1> [[TMP20]], i32 10
-; CHECK-NEXT: [[TMP64:%.*]] = and i1 false, [[TMP63]]
-; CHECK-NEXT: [[TMP65:%.*]] = extractelement <32 x i1> [[TMP20]], i32 9
-; CHECK-NEXT: [[TMP66:%.*]] = and i1 false, [[TMP65]]
-; CHECK-NEXT: [[TMP67:%.*]] = extractelement <32 x i1> [[TMP20]], i32 8
-; CHECK-NEXT: [[TMP68:%.*]] = and i1 false, [[TMP67]]
-; CHECK-NEXT: [[TMP69:%.*]] = extractelement <32 x i1> [[TMP20]], i32 7
-; CHECK-NEXT: [[TMP70:%.*]] = and i1 false, [[TMP69]]
-; CHECK-NEXT: [[TMP71:%.*]] = extractelement <32 x i1> [[TMP20]], i32 6
-; CHECK-NEXT: [[TMP72:%.*]] = and i1 false, [[TMP71]]
-; CHECK-NEXT: [[TMP73:%.*]] = extractelement <32 x i1> [[TMP20]], i32 5
-; CHECK-NEXT: [[TMP74:%.*]] = and i1 false, [[TMP73]]
-; CHECK-NEXT: [[TMP75:%.*]] = extractelement <32 x i1> [[TMP20]], i32 4
-; CHECK-NEXT: [[TMP76:%.*]] = and i1 false, [[TMP75]]
-; CHECK-NEXT: [[TMP77:%.*]] = extractelement <32 x i32> [[TMP18]], i32 0
+; CHECK-NEXT: [[TMP54:%.*]] = extractelement <32 x i1> [[TMP20]], i64 13
+; CHECK-NEXT: [[TMP55:%.*]] = and i1 false, [[TMP54]]
+; CHECK-NEXT: [[TMP56:%.*]] = extractelement <32 x i1> [[TMP20]], i64 12
+; CHECK-NEXT: [[TMP57:%.*]] = and i1 false, [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = extractelement <32 x i1> [[TMP20]], i64 11
+; CHECK-NEXT: [[TMP59:%.*]] = and i1 false, [[TMP58]]
+; CHECK-NEXT: [[TMP60:%.*]] = extractelement <32 x i1> [[TMP20]], i64 10
+; CHECK-NEXT: [[TMP61:%.*]] = and i1 false, [[TMP60]]
+; CHECK-NEXT: [[TMP62:%.*]] = extractelement <32 x i1> [[TMP20]], i64 9
+; CHECK-NEXT: [[TMP63:%.*]] = and i1 false, [[TMP62]]
+; CHECK-NEXT: [[TMP64:%.*]] = extractelement <32 x i1> [[TMP20]], i64 8
+; CHECK-NEXT: [[TMP65:%.*]] = and i1 false, [[TMP64]]
+; CHECK-NEXT: [[TMP66:%.*]] = extractelement <32 x i1> [[TMP20]], i64 7
+; CHECK-NEXT: [[TMP67:%.*]] = and i1 false, [[TMP66]]
+; CHECK-NEXT: [[TMP68:%.*]] = extractelement <32 x i1> [[TMP20]], i64 6
+; CHECK-NEXT: [[TMP69:%.*]] = and i1 false, [[TMP68]]
+; CHECK-NEXT: [[TMP70:%.*]] = extractelement <32 x i1> [[TMP20]], i64 5
+; CHECK-NEXT: [[TMP71:%.*]] = and i1 false, [[TMP70]]
+; CHECK-NEXT: [[TMP72:%.*]] = extractelement <32 x i1> [[TMP20]], i64 4
+; CHECK-NEXT: [[TMP73:%.*]] = and i1 false, [[TMP72]]
+; CHECK-NEXT: [[TMP77:%.*]] = extractelement <32 x i32> [[TMP18]], i64 0
; CHECK-NEXT: [[TMP78:%.*]] = zext i32 [[TMP77]] to i64
; CHECK-NEXT: [[TMP79:%.*]] = getelementptr float, ptr addrspace(1) null, i64 [[TMP78]]
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/return.ll b/llvm/test/Transforms/SLPVectorizer/return.ll
index 1ea4112eb6064..a2c08211d3b1b 100644
--- a/llvm/test/Transforms/SLPVectorizer/return.ll
+++ b/llvm/test/Transforms/SLPVectorizer/return.ll
@@ -18,8 +18,8 @@ define double @return1() {
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr @a, align 8
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @b, align 8
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[TMP0]], [[TMP1]]
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP2]], i64 1
; CHECK-NEXT: [[ADD2:%.*]] = fadd double [[TMP3]], [[TMP4]]
; CHECK-NEXT: ret double [[ADD2]]
;
@@ -45,8 +45,8 @@ define double @return2(ptr nocapture readonly %x) {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[X]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[ARRAYIDX1]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = fadd <2 x double> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i64 1
; CHECK-NEXT: [[ADD5:%.*]] = fadd double [[TMP5]], [[TMP6]]
; CHECK-NEXT: ret double [[ADD5]]
;
diff --git a/llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll b/llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll
index 48a46662fef08..66c3664065968 100644
--- a/llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll
+++ b/llvm/test/Transforms/SLPVectorizer/reudction-or-non-poisoned.ll
@@ -4,10 +4,10 @@
define i1 @test(i32 %x, i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: define i1 @test(
; CHECK-SAME: i32 [[X:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[D]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[B]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[C]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[X]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[D]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[B]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[C]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[X]], i64 3
; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[TMP4]], splat (i32 1)
; CHECK-NEXT: [[TMP7:%.*]] = freeze <4 x i1> [[TMP5]]
; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP7]])
diff --git a/llvm/test/Transforms/SLPVectorizer/reused-buildvector-matching-vectorized-node.ll b/llvm/test/Transforms/SLPVectorizer/reused-buildvector-matching-vectorized-node.ll
index b37c4c97a5d13..606c995e52a5a 100644
--- a/llvm/test/Transforms/SLPVectorizer/reused-buildvector-matching-vectorized-node.ll
+++ b/llvm/test/Transforms/SLPVectorizer/reused-buildvector-matching-vectorized-node.ll
@@ -8,10 +8,10 @@ define void @blam(ptr %arg, double %load2, i1 %fcmp3) {
; CHECK-NEXT: bb:
; CHECK-NEXT: [[GETELEMENTPTR13:%.*]] = getelementptr double, ptr [[ARG]], i64 3
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[ARG]], align 8
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i1> poison, i1 [[FCMP3]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i1> poison, i1 [[FCMP3]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i1> [[TMP1]], <2 x i1> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x double> zeroinitializer, <2 x double> [[TMP0]]
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP0]], double [[LOAD2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP0]], double [[LOAD2]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = fcmp olt <2 x double> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = select <2 x i1> [[TMP5]], <2 x double> zeroinitializer, <2 x double> [[TMP0]]
; CHECK-NEXT: [[TMP7:%.*]] = fcmp olt <2 x double> [[TMP3]], zeroinitializer
diff --git a/llvm/test/Transforms/SLPVectorizer/revec.ll b/llvm/test/Transforms/SLPVectorizer/revec.ll
index 1eefceb249717..659b1ae79ebb8 100644
--- a/llvm/test/Transforms/SLPVectorizer/revec.ll
+++ b/llvm/test/Transforms/SLPVectorizer/revec.ll
@@ -63,8 +63,8 @@ entry:
define void @test3(ptr %x, ptr %y, ptr %z) {
; CHECK-LABEL: @test3(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr> poison, ptr [[X:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP0]], ptr [[Y:%.*]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x ptr> poison, ptr [[X:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> [[TMP0]], ptr [[Y:%.*]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x ptr> [[TMP1]], splat (ptr null)
; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr [[X]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr [[Y]], align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/root-trunc-extract-reuse.ll b/llvm/test/Transforms/SLPVectorizer/root-trunc-extract-reuse.ll
index d4b737a6bc421..e2c99e6009c43 100644
--- a/llvm/test/Transforms/SLPVectorizer/root-trunc-extract-reuse.ll
+++ b/llvm/test/Transforms/SLPVectorizer/root-trunc-extract-reuse.ll
@@ -10,16 +10,16 @@ define i1 @test() {
; CHECK-NEXT: br label [[ELSE]]
; CHECK: else:
; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ zeroinitializer, [[THEN]] ], [ zeroinitializer, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1
; CHECK-NEXT: [[BF_CAST162:%.*]] = and i32 [[TMP1]], 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> zeroinitializer, <2 x i32> [[TMP0]], <2 x i32> <i32 2, i32 1>
; CHECK-NEXT: [[T13:%.*]] = and <2 x i32> [[TMP2]], zeroinitializer
; CHECK-NEXT: br label [[ELSE1:%.*]]
; CHECK: else1:
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[T13]], <2 x i32> poison, <2 x i32> <i32 poison, i32 0>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[BF_CAST162]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[BF_CAST162]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt <2 x i32> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i1> [[TMP5]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i1> [[TMP5]], i64 1
; CHECK-NEXT: ret i1 [[TMP6]]
;
entry:
diff --git a/llvm/test/Transforms/SLPVectorizer/same-scalar-in-same-phi-extract.ll b/llvm/test/Transforms/SLPVectorizer/same-scalar-in-same-phi-extract.ll
index fe0813542f309..15feef7759d58 100644
--- a/llvm/test/Transforms/SLPVectorizer/same-scalar-in-same-phi-extract.ll
+++ b/llvm/test/Transforms/SLPVectorizer/same-scalar-in-same-phi-extract.ll
@@ -6,7 +6,7 @@ define void @test(i32 %arg) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: i32 [[ARG:%.*]]) {
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i64 0
; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb2:
; CHECK-NEXT: switch i32 0, label [[BB10:%.*]] [
@@ -15,7 +15,7 @@ define void @test(i32 %arg) {
; CHECK-NEXT: i32 1, label [[BB4:%.*]]
; CHECK-NEXT: ]
; CHECK: bb3:
-; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: switch i32 0, label [[BB10]] [
; CHECK-NEXT: i32 18, label [[BB7:%.*]]
@@ -24,10 +24,10 @@ define void @test(i32 %arg) {
; CHECK-NEXT: ]
; CHECK: bb4:
; CHECK-NEXT: [[TMP3:%.*]] = phi <2 x i32> [ [[TMP0]], [[BB2]] ]
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP3]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP3]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr i32, ptr null, i64 [[TMP5]]
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP3]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP3]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP7]] to i64
; CHECK-NEXT: [[GETELEMENTPTR6:%.*]] = getelementptr i32, ptr null, i64 [[TMP6]]
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/semanticly-same.ll b/llvm/test/Transforms/SLPVectorizer/semanticly-same.ll
index 5914c0a2f32ee..0d83bea456618 100644
--- a/llvm/test/Transforms/SLPVectorizer/semanticly-same.ll
+++ b/llvm/test/Transforms/SLPVectorizer/semanticly-same.ll
@@ -321,17 +321,17 @@ define void @lshr_div2(ptr %p, ptr %s) {
; X86-NEXT: [[P3:%.*]] = getelementptr i16, ptr [[P]], i64 3
; X86-NEXT: [[L0:%.*]] = load i16, ptr [[P]], align 2
; X86-NEXT: [[L3:%.*]] = load i16, ptr [[P3]], align 2
-; X86-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[L0]], i32 0
-; X86-NEXT: [[TMP4:%.*]] = insertelement <2 x i16> [[TMP3]], i16 [[L3]], i32 1
+; X86-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[L0]], i64 0
+; X86-NEXT: [[TMP4:%.*]] = insertelement <2 x i16> [[TMP3]], i16 [[L3]], i64 1
; X86-NEXT: [[TMP2:%.*]] = lshr <2 x i16> [[TMP4]], <i16 3, i16 5>
; X86-NEXT: [[S1:%.*]] = getelementptr i16, ptr [[S:%.*]], i64 1
; X86-NEXT: [[S3:%.*]] = getelementptr i16, ptr [[S]], i64 3
; X86-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[P1]], align 2
; X86-NEXT: [[TMP1:%.*]] = udiv <2 x i16> [[TMP0]], <i16 8, i16 2>
-; X86-NEXT: [[DIV0:%.*]] = extractelement <2 x i16> [[TMP2]], i32 0
+; X86-NEXT: [[DIV0:%.*]] = extractelement <2 x i16> [[TMP2]], i64 0
; X86-NEXT: store i16 [[DIV0]], ptr [[S]], align 2
; X86-NEXT: store <2 x i16> [[TMP1]], ptr [[S1]], align 2
-; X86-NEXT: [[DIV3:%.*]] = extractelement <2 x i16> [[TMP2]], i32 1
+; X86-NEXT: [[DIV3:%.*]] = extractelement <2 x i16> [[TMP2]], i64 1
; X86-NEXT: store i16 [[DIV3]], ptr [[S3]], align 2
; X86-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/shrink_after_reorder2.ll b/llvm/test/Transforms/SLPVectorizer/shrink_after_reorder2.ll
index 179c5b2f7f91c..302fe93098df6 100644
--- a/llvm/test/Transforms/SLPVectorizer/shrink_after_reorder2.ll
+++ b/llvm/test/Transforms/SLPVectorizer/shrink_after_reorder2.ll
@@ -8,7 +8,7 @@
define void @foo(ptr %this, ptr %p, i32 %add7) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[ADD7:%.*]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[ADD7:%.*]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = sdiv <2 x i32> [[TMP0]], splat (i32 2)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 1, i32 0>
; CHECK-NEXT: switch i32 undef, label [[SW_EPILOG:%.*]] [
diff --git a/llvm/test/Transforms/SLPVectorizer/shuffle-multivector.ll b/llvm/test/Transforms/SLPVectorizer/shuffle-multivector.ll
index 0d7b26e0299e6..eb48bf4d36b28 100644
--- a/llvm/test/Transforms/SLPVectorizer/shuffle-multivector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/shuffle-multivector.ll
@@ -5,12 +5,12 @@
define void @test1(i128 %p0, i128 %p1, i128 %p2, i128 %p3, <4 x i128> %vec) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i128> poison, i128 [[P0:%.*]], i32 0
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i128> [[TMP0]], i128 [[P1:%.*]], i32 1
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i128> poison, i128 [[P0:%.*]], i64 0
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i128> [[TMP0]], i128 [[P1:%.*]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i128> [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i128> poison, i128 [[P2:%.*]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i128> [[TMP4]], i128 [[P3:%.*]], i32 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i128> poison, i128 [[P2:%.*]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i128> [[TMP4]], i128 [[P3:%.*]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = trunc <2 x i128> [[TMP5]] to <2 x i32>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[T5:%.*]] = trunc i128 [[P1]] to i32
diff --git a/llvm/test/Transforms/SLPVectorizer/shufflebuilder-bug.ll b/llvm/test/Transforms/SLPVectorizer/shufflebuilder-bug.ll
index 019c9eadd7c09..e04afc5cce9cb 100644
--- a/llvm/test/Transforms/SLPVectorizer/shufflebuilder-bug.ll
+++ b/llvm/test/Transforms/SLPVectorizer/shufflebuilder-bug.ll
@@ -8,7 +8,7 @@ define void @foo(<4 x float> %vec, float %val, ptr %ptr) {
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds float, ptr [[PTR]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[GEP0]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[VEC]], <4 x float> poison, <2 x i32> <i32 3, i32 poison>
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[VAL]], i32 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[VAL]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[TMP5:%.*]] = fadd <4 x float> [[TMP1]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = fmul <4 x float> [[TMP5]], [[TMP4]]
diff --git a/llvm/test/Transforms/SLPVectorizer/slp-deleted-inst.ll b/llvm/test/Transforms/SLPVectorizer/slp-deleted-inst.ll
index d3995f1bb7f85..da09c6c2a783c 100644
--- a/llvm/test/Transforms/SLPVectorizer/slp-deleted-inst.ll
+++ b/llvm/test/Transforms/SLPVectorizer/slp-deleted-inst.ll
@@ -13,12 +13,12 @@ define void @foo() {
; CHECK-NEXT: [[TMP2:%.*]] = mul <2 x i1> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i1> zeroinitializer, [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = and <2 x i1> [[TMP3]], zeroinitializer
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP4]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP4]], i64 1
; CHECK-NEXT: [[TMP8:%.*]] = zext i1 [[TMP7]] to i32
; CHECK-NEXT: [[I22:%.*]] = or i32 [[TMP6]], [[TMP8]]
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[I22]], i32 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[I22]], i64 0
; CHECK-NEXT: [[TMP10:%.*]] = icmp ult <2 x i32> [[TMP9]], zeroinitializer
; CHECK-NEXT: [[TMP11]] = select <2 x i1> [[TMP10]], <2 x i32> zeroinitializer, <2 x i32> zeroinitializer
; CHECK-NEXT: br label %[[BB1]]
diff --git a/llvm/test/Transforms/SLPVectorizer/slp-max-phi-size.ll b/llvm/test/Transforms/SLPVectorizer/slp-max-phi-size.ll
index b9db7236106a1..5c6120ed90903 100644
--- a/llvm/test/Transforms/SLPVectorizer/slp-max-phi-size.ll
+++ b/llvm/test/Transforms/SLPVectorizer/slp-max-phi-size.ll
@@ -82,9 +82,9 @@ define void @phi_float32(half %hval, float %fval) {
; MAX32-NEXT: [[I66:%.*]] = fmul float [[I9]], [[FVAL]]
; MAX32-NEXT: [[I67:%.*]] = fadd float 0.000000e+00, [[I66]]
; MAX32-NEXT: switch i32 undef, label [[BB5:%.*]] [
-; MAX32-NEXT: i32 0, label [[BB2:%.*]]
-; MAX32-NEXT: i32 1, label [[BB3:%.*]]
-; MAX32-NEXT: i32 2, label [[BB4:%.*]]
+; MAX32-NEXT: i32 0, label [[BB2:%.*]]
+; MAX32-NEXT: i32 1, label [[BB3:%.*]]
+; MAX32-NEXT: i32 2, label [[BB4:%.*]]
; MAX32-NEXT: ]
; MAX32: bb3:
; MAX32-NEXT: br label [[BB2]]
@@ -136,28 +136,28 @@ define void @phi_float32(half %hval, float %fval) {
; MAX256-NEXT: [[I3:%.*]] = fpext half [[HVAL]] to float
; MAX256-NEXT: [[I6:%.*]] = fpext half [[HVAL]] to float
; MAX256-NEXT: [[I9:%.*]] = fpext half [[HVAL]] to float
-; MAX256-NEXT: [[TMP0:%.*]] = insertelement <8 x float> poison, float [[I]], i32 0
+; MAX256-NEXT: [[TMP0:%.*]] = insertelement <8 x float> poison, float [[I]], i64 0
; MAX256-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[TMP0]], <8 x float> poison, <8 x i32> zeroinitializer
-; MAX256-NEXT: [[TMP2:%.*]] = insertelement <8 x float> poison, float [[FVAL:%.*]], i32 0
+; MAX256-NEXT: [[TMP2:%.*]] = insertelement <8 x float> poison, float [[FVAL:%.*]], i64 0
; MAX256-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[TMP2]], <8 x float> poison, <8 x i32> zeroinitializer
; MAX256-NEXT: [[TMP4:%.*]] = fmul <8 x float> [[TMP1]], [[TMP3]]
; MAX256-NEXT: [[TMP5:%.*]] = fadd <8 x float> zeroinitializer, [[TMP4]]
-; MAX256-NEXT: [[TMP6:%.*]] = insertelement <8 x float> poison, float [[I3]], i32 0
+; MAX256-NEXT: [[TMP6:%.*]] = insertelement <8 x float> poison, float [[I3]], i64 0
; MAX256-NEXT: [[TMP7:%.*]] = shufflevector <8 x float> [[TMP6]], <8 x float> poison, <8 x i32> zeroinitializer
; MAX256-NEXT: [[TMP8:%.*]] = fmul <8 x float> [[TMP7]], [[TMP3]]
; MAX256-NEXT: [[TMP9:%.*]] = fadd <8 x float> zeroinitializer, [[TMP8]]
-; MAX256-NEXT: [[TMP10:%.*]] = insertelement <8 x float> poison, float [[I6]], i32 0
+; MAX256-NEXT: [[TMP10:%.*]] = insertelement <8 x float> poison, float [[I6]], i64 0
; MAX256-NEXT: [[TMP11:%.*]] = shufflevector <8 x float> [[TMP10]], <8 x float> poison, <8 x i32> zeroinitializer
; MAX256-NEXT: [[TMP12:%.*]] = fmul <8 x float> [[TMP11]], [[TMP3]]
; MAX256-NEXT: [[TMP13:%.*]] = fadd <8 x float> zeroinitializer, [[TMP12]]
-; MAX256-NEXT: [[TMP14:%.*]] = insertelement <8 x float> poison, float [[I9]], i32 0
+; MAX256-NEXT: [[TMP14:%.*]] = insertelement <8 x float> poison, float [[I9]], i64 0
; MAX256-NEXT: [[TMP15:%.*]] = shufflevector <8 x float> [[TMP14]], <8 x float> poison, <8 x i32> zeroinitializer
; MAX256-NEXT: [[TMP16:%.*]] = fmul <8 x float> [[TMP15]], [[TMP3]]
; MAX256-NEXT: [[TMP17:%.*]] = fadd <8 x float> zeroinitializer, [[TMP16]]
; MAX256-NEXT: switch i32 undef, label [[BB5:%.*]] [
-; MAX256-NEXT: i32 0, label [[BB2:%.*]]
-; MAX256-NEXT: i32 1, label [[BB3:%.*]]
-; MAX256-NEXT: i32 2, label [[BB4:%.*]]
+; MAX256-NEXT: i32 0, label [[BB2:%.*]]
+; MAX256-NEXT: i32 1, label [[BB3:%.*]]
+; MAX256-NEXT: i32 2, label [[BB4:%.*]]
; MAX256-NEXT: ]
; MAX256: bb3:
; MAX256-NEXT: br label [[BB2]]
@@ -170,7 +170,7 @@ define void @phi_float32(half %hval, float %fval) {
; MAX256-NEXT: [[TMP19:%.*]] = phi <8 x float> [ [[TMP17]], [[BB3]] ], [ [[TMP17]], [[BB4]] ], [ [[TMP3]], [[BB5]] ], [ [[TMP17]], [[BB1]] ]
; MAX256-NEXT: [[TMP20:%.*]] = phi <8 x float> [ [[TMP13]], [[BB3]] ], [ [[TMP3]], [[BB4]] ], [ [[TMP13]], [[BB5]] ], [ [[TMP13]], [[BB1]] ]
; MAX256-NEXT: [[TMP21:%.*]] = phi <8 x float> [ [[TMP9]], [[BB3]] ], [ [[TMP3]], [[BB4]] ], [ [[TMP3]], [[BB5]] ], [ [[TMP3]], [[BB1]] ]
-; MAX256-NEXT: [[TMP22:%.*]] = extractelement <8 x float> [[TMP20]], i32 7
+; MAX256-NEXT: [[TMP22:%.*]] = extractelement <8 x float> [[TMP20]], i64 7
; MAX256-NEXT: store float [[TMP22]], ptr undef, align 4
; MAX256-NEXT: ret void
;
@@ -182,28 +182,28 @@ define void @phi_float32(half %hval, float %fval) {
; MAX1024-NEXT: [[I3:%.*]] = fpext half [[HVAL]] to float
; MAX1024-NEXT: [[I6:%.*]] = fpext half [[HVAL]] to float
; MAX1024-NEXT: [[I9:%.*]] = fpext half [[HVAL]] to float
-; MAX1024-NEXT: [[TMP0:%.*]] = insertelement <8 x float> poison, float [[I]], i32 0
+; MAX1024-NEXT: [[TMP0:%.*]] = insertelement <8 x float> poison, float [[I]], i64 0
; MAX1024-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[TMP0]], <8 x float> poison, <8 x i32> zeroinitializer
-; MAX1024-NEXT: [[TMP2:%.*]] = insertelement <8 x float> poison, float [[FVAL:%.*]], i32 0
+; MAX1024-NEXT: [[TMP2:%.*]] = insertelement <8 x float> poison, float [[FVAL:%.*]], i64 0
; MAX1024-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[TMP2]], <8 x float> poison, <8 x i32> zeroinitializer
; MAX1024-NEXT: [[TMP4:%.*]] = fmul <8 x float> [[TMP1]], [[TMP3]]
; MAX1024-NEXT: [[TMP5:%.*]] = fadd <8 x float> zeroinitializer, [[TMP4]]
-; MAX1024-NEXT: [[TMP6:%.*]] = insertelement <8 x float> poison, float [[I3]], i32 0
+; MAX1024-NEXT: [[TMP6:%.*]] = insertelement <8 x float> poison, float [[I3]], i64 0
; MAX1024-NEXT: [[TMP7:%.*]] = shufflevector <8 x float> [[TMP6]], <8 x float> poison, <8 x i32> zeroinitializer
; MAX1024-NEXT: [[TMP8:%.*]] = fmul <8 x float> [[TMP7]], [[TMP3]]
; MAX1024-NEXT: [[TMP9:%.*]] = fadd <8 x float> zeroinitializer, [[TMP8]]
-; MAX1024-NEXT: [[TMP10:%.*]] = insertelement <8 x float> poison, float [[I6]], i32 0
+; MAX1024-NEXT: [[TMP10:%.*]] = insertelement <8 x float> poison, float [[I6]], i64 0
; MAX1024-NEXT: [[TMP11:%.*]] = shufflevector <8 x float> [[TMP10]], <8 x float> poison, <8 x i32> zeroinitializer
; MAX1024-NEXT: [[TMP12:%.*]] = fmul <8 x float> [[TMP11]], [[TMP3]]
; MAX1024-NEXT: [[TMP13:%.*]] = fadd <8 x float> zeroinitializer, [[TMP12]]
-; MAX1024-NEXT: [[TMP14:%.*]] = insertelement <8 x float> poison, float [[I9]], i32 0
+; MAX1024-NEXT: [[TMP14:%.*]] = insertelement <8 x float> poison, float [[I9]], i64 0
; MAX1024-NEXT: [[TMP15:%.*]] = shufflevector <8 x float> [[TMP14]], <8 x float> poison, <8 x i32> zeroinitializer
; MAX1024-NEXT: [[TMP16:%.*]] = fmul <8 x float> [[TMP15]], [[TMP3]]
; MAX1024-NEXT: [[TMP17:%.*]] = fadd <8 x float> zeroinitializer, [[TMP16]]
; MAX1024-NEXT: switch i32 undef, label [[BB5:%.*]] [
-; MAX1024-NEXT: i32 0, label [[BB2:%.*]]
-; MAX1024-NEXT: i32 1, label [[BB3:%.*]]
-; MAX1024-NEXT: i32 2, label [[BB4:%.*]]
+; MAX1024-NEXT: i32 0, label [[BB2:%.*]]
+; MAX1024-NEXT: i32 1, label [[BB3:%.*]]
+; MAX1024-NEXT: i32 2, label [[BB4:%.*]]
; MAX1024-NEXT: ]
; MAX1024: bb3:
; MAX1024-NEXT: br label [[BB2]]
@@ -216,7 +216,7 @@ define void @phi_float32(half %hval, float %fval) {
; MAX1024-NEXT: [[TMP19:%.*]] = phi <8 x float> [ [[TMP17]], [[BB3]] ], [ [[TMP17]], [[BB4]] ], [ [[TMP3]], [[BB5]] ], [ [[TMP17]], [[BB1]] ]
; MAX1024-NEXT: [[TMP20:%.*]] = phi <8 x float> [ [[TMP13]], [[BB3]] ], [ [[TMP3]], [[BB4]] ], [ [[TMP13]], [[BB5]] ], [ [[TMP13]], [[BB1]] ]
; MAX1024-NEXT: [[TMP21:%.*]] = phi <8 x float> [ [[TMP9]], [[BB3]] ], [ [[TMP3]], [[BB4]] ], [ [[TMP3]], [[BB5]] ], [ [[TMP3]], [[BB1]] ]
-; MAX1024-NEXT: [[TMP22:%.*]] = extractelement <8 x float> [[TMP20]], i32 7
+; MAX1024-NEXT: [[TMP22:%.*]] = extractelement <8 x float> [[TMP20]], i64 7
; MAX1024-NEXT: store float [[TMP22]], ptr undef, align 4
; MAX1024-NEXT: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/splat-buildvector.ll b/llvm/test/Transforms/SLPVectorizer/splat-buildvector.ll
index c60ef6a18cbab..a3f8f7bfdc2c9 100644
--- a/llvm/test/Transforms/SLPVectorizer/splat-buildvector.ll
+++ b/llvm/test/Transforms/SLPVectorizer/splat-buildvector.ll
@@ -9,8 +9,8 @@ define i8 @foo(i64 %val_i64_57) {
; CHECK-SAME: i64 [[VAL_I64_57:%.*]]) {
; CHECK-NEXT: entry_1:
; CHECK-NEXT: [[VAL_I64_58:%.*]] = call i64 @llvm.smax.i64(i64 0, i64 1)
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> <i64 0, i64 poison, i64 poison, i64 0>, i64 [[VAL_I64_57]], i32 1
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[VAL_I64_58]], i32 2
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> <i64 0, i64 poison, i64 poison, i64 0>, i64 [[VAL_I64_57]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[VAL_I64_58]], i64 2
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> <i64 poison, i64 poison, i64 poison, i64 undef>, <4 x i32> <i32 2, i32 2, i32 2, i32 7>
; CHECK-NEXT: [[TMP3:%.*]] = icmp ule <4 x i64> [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = icmp sle <4 x i64> [[TMP1]], [[TMP2]]
diff --git a/llvm/test/Transforms/SLPVectorizer/stores-non-ordered.ll b/llvm/test/Transforms/SLPVectorizer/stores-non-ordered.ll
index aaa6be73056bd..f825344b02c0d 100644
--- a/llvm/test/Transforms/SLPVectorizer/stores-non-ordered.ll
+++ b/llvm/test/Transforms/SLPVectorizer/stores-non-ordered.ll
@@ -18,15 +18,15 @@ define i32 @non-ordered-stores(ptr noalias nocapture %in, ptr noalias nocapture
; CHECK-NEXT: [[LOAD_7:%.*]] = load i32, ptr [[GEP_5]], align 4
; CHECK-NEXT: [[GEP_6:%.*]] = getelementptr inbounds i32, ptr [[INN]], i64 3
; CHECK-NEXT: [[LOAD_8:%.*]] = load i32, ptr [[GEP_6]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD_1]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[LOAD_3]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD_5]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[LOAD_7]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD_1]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[LOAD_3]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD_5]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[LOAD_7]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = mul <2 x i32> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD_2]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[LOAD_4]], i32 1
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD_6]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[LOAD_8]], i32 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD_2]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[LOAD_4]], i64 1
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD_6]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[LOAD_8]], i64 1
; CHECK-NEXT: [[TMP10:%.*]] = mul <2 x i32> [[TMP7]], [[TMP9]]
; CHECK-NEXT: br label [[BLOCK1:%.*]]
; CHECK: block1:
diff --git a/llvm/test/Transforms/SLPVectorizer/unknown-entries.ll b/llvm/test/Transforms/SLPVectorizer/unknown-entries.ll
index ca9aa451a9a3a..35da7aa5f0fee 100644
--- a/llvm/test/Transforms/SLPVectorizer/unknown-entries.ll
+++ b/llvm/test/Transforms/SLPVectorizer/unknown-entries.ll
@@ -6,7 +6,7 @@ define <3 x i64> @ahyes(i64 %position, i64 %value) {
; CHECK-LABEL: define <3 x i64> @ahyes(
; CHECK-SAME: i64 [[POSITION:%.*]], i64 [[VALUE:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[VALUE]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[VALUE]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i64> [[TMP1]], <i64 1, i64 2>
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i64> poison, i64 [[VALUE]], i64 [[POSITION]]
diff --git a/llvm/test/Transforms/SLPVectorizer/vectorize-reorder-alt-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/vectorize-reorder-alt-shuffle.ll
index 13d47e5c11181..c2f07de9fc6b5 100644
--- a/llvm/test/Transforms/SLPVectorizer/vectorize-reorder-alt-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/vectorize-reorder-alt-shuffle.ll
@@ -18,11 +18,11 @@ define void @foo(ptr %c, ptr %d) {
; X86-NEXT: [[TMP2:%.*]] = load <2 x i8>, ptr [[ARRAYIDX12]], align 1
; X86-NEXT: [[TMP3:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i16>
; X86-NEXT: [[TMP4:%.*]] = shl <2 x i16> [[TMP3]], splat (i16 2)
-; X86-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[SHL6]], i32 0
+; X86-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> poison, i32 [[SHL6]], i64 0
; X86-NEXT: [[TMP6:%.*]] = zext <2 x i16> [[TMP4]] to <2 x i32>
; X86-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; X86-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> [[TMP7]], <4 x i32> <i32 0, i32 4, i32 5, i32 poison>
-; X86-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[AND]], i32 3
+; X86-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[AND]], i64 3
; X86-NEXT: [[TMP10:%.*]] = add nsw <4 x i32> undef, [[TMP9]]
; X86-NEXT: [[TMP11:%.*]] = sitofp <4 x i32> [[TMP10]] to <4 x float>
; X86-NEXT: [[TMP12:%.*]] = fdiv <4 x float> [[TMP11]], undef
diff --git a/llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll b/llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
index 303e31dfa5e64..0e4b38a48d509 100644
--- a/llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
@@ -6,10 +6,10 @@ define i32 @test(i32 %a, i8 %b, i8 %c) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: i32 [[A:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[C]], i32 0
+; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[C]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[TMP1]], <i8 -1, i8 -2, i8 -3, i8 -4>
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>
; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i8> [[TMP4]] to <4 x i16>
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