[llvm] [LoadStoreVectorizer] Use constant 64-bit indices for Extract/InsertElement (PR #208941)
Andreas Jonson via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 11 12:38:20 PDT 2026
https://github.com/andjo403 created https://github.com/llvm/llvm-project/pull/208941
The canonical form preferred by instCombine is to use 64-bit values for constant index in ExtractElement and InsertElement see
https://github.com/llvm/llvm-project/blob/9d5d8834793da9efe297620db3ef39633688f830/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp#L401-L411
>From 498560287fff80ad1aba52d0696986ff9a2b7386 Mon Sep 17 00:00:00 2001
From: Andreas Jonson <andjo403 at hotmail.com>
Date: Sat, 11 Jul 2026 18:19:07 +0200
Subject: [PATCH] [LoadStoreVectorizer] Use constant 64-bit indices for
Extract/InsertElement
---
.../Vectorize/LoadStoreVectorizer.cpp | 8 +-
.../AMDGPU/adjust-alloca-alignment.ll | 44 +-
.../AMDGPU/fence-noalias-metadata.ll | 8 +-
.../AMDGPU/merge-stores.ll | 156 ++---
.../AMDGPU/merge-vectors-complex.ll | 72 +--
.../AMDGPU/missing-alignment.ll | 4 +-
.../AMDGPU/multiple_tails.ll | 16 +-
.../LoadStoreVectorizer/AMDGPU/opaque_ptr.ll | 4 +-
.../AMDGPU/pointer-elements.ll | 32 +-
.../AMDGPU/unaligned-buffer.ll | 24 +-
.../AMDGPU/vectorize-redund-loads.ll | 26 +-
.../LoadStoreVectorizer/NVPTX/4x2xhalf.ll | 36 +-
.../LoadStoreVectorizer/NVPTX/extend-chain.ll | 44 +-
.../NVPTX/gap-fill-cleanup.ll | 8 +-
.../NVPTX/gap-fill-invariant.ll | 24 +-
.../NVPTX/gap-fill-with-redundant-elements.ll | 12 +-
.../LoadStoreVectorizer/NVPTX/gap-fill.ll | 80 +--
.../NVPTX/load-store-256-bit.ll | 609 +++++++++---------
.../LoadStoreVectorizer/NVPTX/masked-store.ll | 160 ++---
.../NVPTX/propagate-invariance-metadata.ll | 6 +-
.../LoadStoreVectorizer/NVPTX/vectorize_i8.ll | 276 ++++----
.../LoadStoreVectorizer/X86/correct-order.ll | 8 +-
.../X86/massive_indirection.ll | 24 +-
.../LoadStoreVectorizer/X86/opaque-ptr.ll | 4 +-
.../X86/or-disjoint-nested-add.ll | 16 +-
.../X86/or-disjoint-zext.ll | 12 +-
.../X86/scev-range-zext.ll | 4 +-
.../vectorize-i8-nested-add-inseltpoison.ll | 10 +-
.../X86/vectorize-i8-nested-add.ll | 100 +--
.../X86/vectorize-redund-loads.ll | 6 +-
.../LoadStoreVectorizer/int_sideeffect.ll | 32 +-
31 files changed, 932 insertions(+), 933 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
index b5437ad8705bf..897285f722089 100644
--- a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
@@ -1175,8 +1175,7 @@ bool Vectorizer::vectorizeChain(Chain &C) {
llvm::seq<int>(VecIdx, VecIdx + VT->getNumElements()));
V = Builder.CreateShuffleVector(VecInst, Mask, I->getName());
} else {
- V = Builder.CreateExtractElement(VecInst, Builder.getInt32(VecIdx),
- I->getName());
+ V = Builder.CreateExtractElement(VecInst, VecIdx, I->getName());
}
if (V->getType() != I->getType())
V = Builder.CreateBitOrPointerCast(V, I->getType());
@@ -1214,7 +1213,7 @@ bool Vectorizer::vectorizeChain(Chain &C) {
auto InsertElem = [&](Value *V, unsigned VecIdx) {
if (V->getType() != VecElemTy)
V = Builder.CreateBitOrPointerCast(V, VecElemTy);
- Vec = Builder.CreateInsertElement(Vec, V, Builder.getInt32(VecIdx));
+ Vec = Builder.CreateInsertElement(Vec, V, VecIdx);
};
for (const ChainElem &E : C) {
auto *I = cast<StoreInst>(E.Inst);
@@ -1224,8 +1223,7 @@ bool Vectorizer::vectorizeChain(Chain &C) {
if (FixedVectorType *VT =
dyn_cast<FixedVectorType>(getLoadStoreType(I))) {
for (int J = 0, JE = VT->getNumElements(); J < JE; ++J) {
- InsertElem(Builder.CreateExtractElement(I->getValueOperand(),
- Builder.getInt32(J)),
+ InsertElem(Builder.CreateExtractElement(I->getValueOperand(), J),
VecIdx++);
}
} else {
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
index 6ad5e002a5ddd..69385c5e801f1 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
@@ -21,8 +21,8 @@ define amdgpu_kernel void @load_unknown_offset_align1_i8(ptr addrspace(1) noalia
; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i8], align 1, addrspace(5)
; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i8], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]
; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr addrspace(5) [[PTR0]], align 1
-; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i8> [[TMP1]], i32 0
-; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i8> [[TMP1]], i32 1
+; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i8> [[TMP1]], i64 0
+; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i8> [[TMP1]], i64 1
; UNALIGNED-NEXT: [[ADD:%.*]] = add i8 [[VAL01]], [[VAL12]]
; UNALIGNED-NEXT: store i8 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 1
; UNALIGNED-NEXT: ret void
@@ -52,8 +52,8 @@ define amdgpu_kernel void @load_unknown_offset_align1_i16(ptr addrspace(1) noali
; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i16], align 1, addrspace(5)
; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i16], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]
; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr addrspace(5) [[PTR0]], align 1
-; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i16> [[TMP1]], i32 0
-; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i16> [[TMP1]], i32 1
+; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i16> [[TMP1]], i64 0
+; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i16> [[TMP1]], i64 1
; UNALIGNED-NEXT: [[ADD:%.*]] = add i16 [[VAL01]], [[VAL12]]
; UNALIGNED-NEXT: store i16 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 2
; UNALIGNED-NEXT: ret void
@@ -85,8 +85,8 @@ define amdgpu_kernel void @load_unknown_offset_align1_i32(ptr addrspace(1) noali
; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i32], align 1, addrspace(5)
; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]
; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(5) [[PTR0]], align 1
-; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; UNALIGNED-NEXT: [[ADD:%.*]] = add i32 [[VAL01]], [[VAL12]]
; UNALIGNED-NEXT: store i32 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 4
; UNALIGNED-NEXT: ret void
@@ -117,8 +117,8 @@ define amdgpu_kernel void @load_alloca16_unknown_offset_align1_i32(ptr addrspace
; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i32], align 16, addrspace(5)
; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]
; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(5) [[PTR0]], align 4
-; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; UNALIGNED-NEXT: [[ADD:%.*]] = add i32 [[VAL01]], [[VAL12]]
; UNALIGNED-NEXT: store i32 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 4
; UNALIGNED-NEXT: ret void
@@ -245,10 +245,10 @@ define amdgpu_kernel void @merge_private_load_4_vector_elts_loads_v4i32() {
; CHECK-LABEL: @merge_private_load_4_vector_elts_loads_v4i32(
; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [8 x i32], align 4, addrspace(5)
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(5) [[ALLOCA]], align 4
-; CHECK-NEXT: [[LOAD01:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD12:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[LOAD23:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LOAD34:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[LOAD01:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD12:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[LOAD23:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LOAD34:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: ret void
;
%alloca = alloca [8 x i32], align 1, addrspace(5)
@@ -267,10 +267,10 @@ define amdgpu_kernel void @merge_private_load_4_vector_elts_loads_v4i8() {
; CHECK-LABEL: @merge_private_load_4_vector_elts_loads_v4i8(
; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [8 x i8], align 4, addrspace(5)
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr addrspace(5) [[ALLOCA]], align 4
-; CHECK-NEXT: [[LOAD01:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD12:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[LOAD23:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[LOAD34:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[LOAD01:%.*]] = extractelement <4 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD12:%.*]] = extractelement <4 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[LOAD23:%.*]] = extractelement <4 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[LOAD34:%.*]] = extractelement <4 x i8> [[TMP1]], i64 3
; CHECK-NEXT: ret void
;
%alloca = alloca [8 x i8], align 1, addrspace(5)
@@ -333,8 +333,8 @@ define i32 @private_load_2xi16_align2_not_alloca(ptr addrspace(5) %p) #0 {
;
; UNALIGNED-LABEL: @private_load_2xi16_align2_not_alloca(
; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr addrspace(5) [[P:%.*]], align 2
-; UNALIGNED-NEXT: [[P_01:%.*]] = extractelement <2 x i16> [[TMP1]], i32 0
-; UNALIGNED-NEXT: [[P_12:%.*]] = extractelement <2 x i16> [[TMP1]], i32 1
+; UNALIGNED-NEXT: [[P_01:%.*]] = extractelement <2 x i16> [[TMP1]], i64 0
+; UNALIGNED-NEXT: [[P_12:%.*]] = extractelement <2 x i16> [[TMP1]], i64 1
; UNALIGNED-NEXT: [[ZEXT_0:%.*]] = zext i16 [[P_01]] to i32
; UNALIGNED-NEXT: [[ZEXT_1:%.*]] = zext i16 [[P_12]] to i32
; UNALIGNED-NEXT: [[SHL_1:%.*]] = shl i32 [[ZEXT_1]], 16
@@ -364,8 +364,8 @@ define i32 @private_load_2xi16_align1_not_alloca(ptr addrspace(5) %p) #0 {
;
; UNALIGNED-LABEL: @private_load_2xi16_align1_not_alloca(
; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr addrspace(5) [[P:%.*]], align 1
-; UNALIGNED-NEXT: [[P_01:%.*]] = extractelement <2 x i16> [[TMP1]], i32 0
-; UNALIGNED-NEXT: [[P_12:%.*]] = extractelement <2 x i16> [[TMP1]], i32 1
+; UNALIGNED-NEXT: [[P_01:%.*]] = extractelement <2 x i16> [[TMP1]], i64 0
+; UNALIGNED-NEXT: [[P_12:%.*]] = extractelement <2 x i16> [[TMP1]], i64 1
; UNALIGNED-NEXT: [[ZEXT_0:%.*]] = zext i16 [[P_01]] to i32
; UNALIGNED-NEXT: [[ZEXT_1:%.*]] = zext i16 [[P_12]] to i32
; UNALIGNED-NEXT: [[SHL_1:%.*]] = shl i32 [[ZEXT_1]], 16
@@ -397,8 +397,8 @@ define void @load_alloca16_unknown_offset_align1_i8(ptr addrspace(1) noalias %ou
; UNALIGNED-NEXT: [[ALLOCA:%.*]] = alloca [128 x i8], align 16, addrspace(5)
; UNALIGNED-NEXT: [[PTR0:%.*]] = getelementptr inbounds [128 x i8], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[OFFSET:%.*]]
; UNALIGNED-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr addrspace(5) [[PTR0]], align 1
-; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i8> [[TMP1]], i32 0
-; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i8> [[TMP1]], i32 1
+; UNALIGNED-NEXT: [[VAL01:%.*]] = extractelement <2 x i8> [[TMP1]], i64 0
+; UNALIGNED-NEXT: [[VAL12:%.*]] = extractelement <2 x i8> [[TMP1]], i64 1
; UNALIGNED-NEXT: [[ADD:%.*]] = add i8 [[VAL01]], [[VAL12]]
; UNALIGNED-NEXT: store i8 [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 1
; UNALIGNED-NEXT: ret void
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll
index bc0c027156451..5a73e7b31ca54 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/fence-noalias-metadata.ll
@@ -16,8 +16,8 @@ define void @vectorize_loads_across_fence_with_noalias(ptr addrspace(1) %ptr) {
; CHECK-LABEL: define void @vectorize_loads_across_fence_with_noalias(
; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[PTR]], align 8, !alias.scope [[META0:![0-9]+]], !noalias [[META3:![0-9]+]]
-; CHECK-NEXT: [[LOAD01:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD12:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD01:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD12:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: fence syncscope("workgroup") release, !noalias [[META5:![0-9]+]]
; CHECK-NEXT: fence syncscope("workgroup") acquire, !noalias [[META5]]
; CHECK-NEXT: [[SUM:%.*]] = add i32 [[LOAD01]], [[LOAD12]]
@@ -40,8 +40,8 @@ define void @vectorize_loads_across_fence_with_alias_scope(ptr addrspace(1) %ptr
; CHECK-LABEL: define void @vectorize_loads_across_fence_with_alias_scope(
; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[PTR]], align 8, !alias.scope [[META0]], !noalias [[META6:![0-9]+]]
-; CHECK-NEXT: [[LOAD01:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD12:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD01:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD12:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: fence syncscope("workgroup") release, !alias.scope [[META6]]
; CHECK-NEXT: fence syncscope("workgroup") acquire, !alias.scope [[META6]]
; CHECK-NEXT: [[SUM:%.*]] = add i32 [[LOAD01]], [[LOAD12]]
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
index f8c4a92c0cfc3..fc0e552969726 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
@@ -249,10 +249,10 @@ define amdgpu_kernel void @merge_global_store_4_constants_i64(ptr addrspace(1) %
define amdgpu_kernel void @merge_global_store_2_adjacent_loads_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; CHECK-LABEL: @merge_global_store_2_adjacent_loads_i32(
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[IN:%.*]], align 4
-; CHECK-NEXT: [[LO1:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[HI2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[LO1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[HI2]], i32 1
+; CHECK-NEXT: [[LO1:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[HI2:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[LO1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[HI2]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -272,10 +272,10 @@ define amdgpu_kernel void @merge_global_store_2_adjacent_loads_i32_nonzero_base(
; CHECK-NEXT: [[IN_GEP_0:%.*]] = getelementptr i32, ptr addrspace(1) [[IN:%.*]], i32 2
; CHECK-NEXT: [[OUT_GEP_0:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT:%.*]], i32 2
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[IN_GEP_0]], align 4
-; CHECK-NEXT: [[LO1:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[HI2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[LO1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[HI2]], i32 1
+; CHECK-NEXT: [[LO1:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[HI2:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[LO1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[HI2]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr addrspace(1) [[OUT_GEP_0]], align 4
; CHECK-NEXT: ret void
;
@@ -295,10 +295,10 @@ define amdgpu_kernel void @merge_global_store_2_adjacent_loads_i32_nonzero_base(
define amdgpu_kernel void @merge_global_store_2_adjacent_loads_shuffle_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; CHECK-LABEL: @merge_global_store_2_adjacent_loads_shuffle_i32(
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[IN:%.*]], align 4
-; CHECK-NEXT: [[LO1:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[HI2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[HI2]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[LO1]], i32 1
+; CHECK-NEXT: [[LO1:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[HI2:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[HI2]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[LO1]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -316,14 +316,14 @@ define amdgpu_kernel void @merge_global_store_2_adjacent_loads_shuffle_i32(ptr a
define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; CHECK-LABEL: @merge_global_store_4_adjacent_loads_i32(
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(1) [[IN:%.*]], align 4
-; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Y2]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Z3]], i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[W4]], i32 3
+; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Y2]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Z3]], i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[W4]], i64 3
; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -349,12 +349,12 @@ define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i32(ptr addrspace
define amdgpu_kernel void @merge_global_store_3_adjacent_loads_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; CHECK-LABEL: @merge_global_store_3_adjacent_loads_i32(
; CHECK-NEXT: [[TMP1:%.*]] = load <3 x i32>, ptr addrspace(1) [[IN:%.*]], align 4
-; CHECK-NEXT: [[X1:%.*]] = extractelement <3 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[Y2:%.*]] = extractelement <3 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[Z3:%.*]] = extractelement <3 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i32> poison, i32 [[X1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i32> [[TMP2]], i32 [[Y2]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <3 x i32> [[TMP3]], i32 [[Z3]], i32 2
+; CHECK-NEXT: [[X1:%.*]] = extractelement <3 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[Y2:%.*]] = extractelement <3 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[Z3:%.*]] = extractelement <3 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i32> poison, i32 [[X1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i32> [[TMP2]], i32 [[Y2]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <3 x i32> [[TMP3]], i32 [[Z3]], i64 2
; CHECK-NEXT: store <3 x i32> [[TMP4]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -376,14 +376,14 @@ define amdgpu_kernel void @merge_global_store_3_adjacent_loads_i32(ptr addrspace
define amdgpu_kernel void @merge_global_store_4_adjacent_loads_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; CHECK-LABEL: @merge_global_store_4_adjacent_loads_f32(
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr addrspace(1) [[IN:%.*]], align 4
-; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
-; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
-; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
-; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> poison, float [[X1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[Y2]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[Z3]], i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[W4]], i32 3
+; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x float> [[TMP1]], i64 0
+; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x float> [[TMP1]], i64 1
+; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x float> [[TMP1]], i64 2
+; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> poison, float [[X1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float [[Y2]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[Z3]], i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[W4]], i64 3
; CHECK-NEXT: store <4 x float> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -411,14 +411,14 @@ define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i32_nonzero_base(
; CHECK-NEXT: [[IN_GEP_0:%.*]] = getelementptr i32, ptr addrspace(1) [[IN:%.*]], i32 11
; CHECK-NEXT: [[OUT_GEP_0:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT:%.*]], i32 7
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(1) [[IN_GEP_0]], align 4
-; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Y2]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Z3]], i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[W4]], i32 3
+; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Y2]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Z3]], i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[W4]], i64 3
; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr addrspace(1) [[OUT_GEP_0]], align 4
; CHECK-NEXT: ret void
;
@@ -446,15 +446,15 @@ define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i32_nonzero_base(
define amdgpu_kernel void @merge_global_store_4_adjacent_loads_inverse_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; CHECK-LABEL: @merge_global_store_4_adjacent_loads_inverse_i32(
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(1) [[IN:%.*]], align 4
-; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier() #[[ATTR3:[0-9]+]]
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Y2]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Z3]], i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[W4]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Y2]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Z3]], i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[W4]], i64 3
; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -484,15 +484,15 @@ define amdgpu_kernel void @merge_global_store_4_adjacent_loads_inverse_i32(ptr a
define amdgpu_kernel void @merge_global_store_4_adjacent_loads_shuffle_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; CHECK-LABEL: @merge_global_store_4_adjacent_loads_shuffle_i32(
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(1) [[IN:%.*]], align 4
-; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier() #[[ATTR3]]
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[W4]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Z3]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Y2]], i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[X1]], i32 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[W4]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Z3]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[Y2]], i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[X1]], i64 3
; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -522,14 +522,14 @@ define amdgpu_kernel void @merge_global_store_4_adjacent_loads_shuffle_i32(ptr a
define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i8(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; CHECK-LABEL: @merge_global_store_4_adjacent_loads_i8(
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr addrspace(1) [[IN:%.*]], align 4
-; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[X1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[Y2]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> [[TMP3]], i8 [[Z3]], i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> [[TMP4]], i8 [[W4]], i32 3
+; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i8> [[TMP1]], i64 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[X1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[Y2]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> [[TMP3]], i8 [[Z3]], i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> [[TMP4]], i8 [[W4]], i64 3
; CHECK-NEXT: store <4 x i8> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
@@ -555,14 +555,14 @@ define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i8(ptr addrspace(
define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i8_natural_align(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
; CHECK-LABEL: @merge_global_store_4_adjacent_loads_i8_natural_align(
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr addrspace(1) [[IN:%.*]], align 1
-; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[X1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[Y2]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> [[TMP3]], i8 [[Z3]], i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> [[TMP4]], i8 [[W4]], i32 3
+; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[Z3:%.*]] = extractelement <4 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[W4:%.*]] = extractelement <4 x i8> [[TMP1]], i64 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i8> poison, i8 [[X1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> [[TMP2]], i8 [[Y2]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> [[TMP3]], i8 [[Z3]], i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> [[TMP4]], i8 [[W4]], i64 3
; CHECK-NEXT: store <4 x i8> [[TMP5]], ptr addrspace(1) [[OUT:%.*]], align 1
; CHECK-NEXT: ret void
;
@@ -592,10 +592,10 @@ define amdgpu_kernel void @merge_global_store_4_vector_elts_loads_v4i32(ptr addr
; CHECK-NEXT: [[Y:%.*]] = extractelement <4 x i32> [[VEC]], i32 1
; CHECK-NEXT: [[Z:%.*]] = extractelement <4 x i32> [[VEC]], i32 2
; CHECK-NEXT: [[W:%.*]] = extractelement <4 x i32> [[VEC]], i32 3
-; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i32 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[Y]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Z]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[W]], i32 3
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[Y]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[Z]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[W]], i64 3
; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
index 928baab8b38e1..df136fb63168f 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
@@ -119,13 +119,13 @@ define void @merge_i32_p3(ptr addrspace(1) %ptr1, ptr addrspace(2) %ptr2) {
; CHECK-SAME: ptr addrspace(1) [[PTR1:%.*]], ptr addrspace(2) [[PTR2:%.*]]) {
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[PTR1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[GEP1]], align 4
-; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i32 [[LOAD22]] to ptr addrspace(3)
; CHECK-NEXT: [[STORE_GEP1:%.*]] = getelementptr inbounds i32, ptr addrspace(2) [[PTR2]], i64 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD11]], i32 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD11]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr addrspace(3) [[TMP2]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP4]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP5]], ptr addrspace(2) [[STORE_GEP1]], align 4
; CHECK-NEXT: ret void
;
@@ -150,9 +150,9 @@ define void @split_i32_p1_p1(ptr addrspace(1) %ptr1, ptr addrspace(2) %ptr2) {
; CHECK-NEXT: [[LOAD1:%.*]] = load i32, ptr addrspace(1) [[GEP1]], align 8
; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) [[PTR1]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr addrspace(1) [[GEP2]], align 8
-; CHECK-NEXT: [[LOAD21:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
+; CHECK-NEXT: [[LOAD21:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[LOAD21]] to ptr addrspace(1)
-; CHECK-NEXT: [[LOAD32:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD32:%.*]] = extractelement <2 x i64> [[TMP1]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[LOAD32]] to ptr addrspace(1)
; CHECK-NEXT: [[STORE_GEP1:%.*]] = getelementptr inbounds i32, ptr addrspace(2) [[PTR2]], i64 0
; CHECK-NEXT: store i32 [[LOAD1]], ptr addrspace(2) [[STORE_GEP1]], align 8
@@ -185,17 +185,17 @@ define void @split_i32_i32_p1_p1(ptr addrspace(1) %ptr1, ptr addrspace(2) %ptr2)
; CHECK-SAME: ptr addrspace(1) [[PTR1:%.*]], ptr addrspace(2) [[PTR2:%.*]]) {
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[PTR1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[GEP1]], align 8
-; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) [[PTR1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr addrspace(1) [[GEP3]], align 8
-; CHECK-NEXT: [[LOAD33:%.*]] = extractelement <2 x i64> [[TMP2]], i32 0
+; CHECK-NEXT: [[LOAD33:%.*]] = extractelement <2 x i64> [[TMP2]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[LOAD33]] to ptr addrspace(1)
-; CHECK-NEXT: [[LOAD44:%.*]] = extractelement <2 x i64> [[TMP2]], i32 1
+; CHECK-NEXT: [[LOAD44:%.*]] = extractelement <2 x i64> [[TMP2]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[LOAD44]] to ptr addrspace(1)
; CHECK-NEXT: [[STORE_GEP1:%.*]] = getelementptr inbounds i32, ptr addrspace(2) [[PTR2]], i64 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD11]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP5]], i32 [[LOAD22]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD11]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP5]], i32 [[LOAD22]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP6]], ptr addrspace(2) [[STORE_GEP1]], align 8
; CHECK-NEXT: [[STORE_GEP3:%.*]] = getelementptr inbounds ptr addrspace(1), ptr addrspace(2) [[PTR2]], i64 1
; CHECK-NEXT: store ptr addrspace(1) [[TMP3]], ptr addrspace(2) [[STORE_GEP3]], align 8
@@ -230,13 +230,13 @@ define void @split_i32_i32_p1(ptr addrspace(1) %ptr1, ptr addrspace(2) %ptr2) {
; CHECK-SAME: ptr addrspace(1) [[PTR1:%.*]], ptr addrspace(2) [[PTR2:%.*]]) {
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[PTR1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[GEP1]], align 8
-; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) [[PTR1]], i64 1
; CHECK-NEXT: [[LOAD3:%.*]] = load ptr addrspace(1), ptr addrspace(1) [[GEP3]], align 8
; CHECK-NEXT: [[STORE_GEP1:%.*]] = getelementptr inbounds i32, ptr addrspace(2) [[PTR2]], i64 0
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD11]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[LOAD22]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[LOAD11]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> [[TMP2]], i32 [[LOAD22]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr addrspace(2) [[STORE_GEP1]], align 8
; CHECK-NEXT: [[STORE_GEP3:%.*]] = getelementptr inbounds ptr addrspace(1), ptr addrspace(2) [[PTR2]], i64 1
; CHECK-NEXT: store ptr addrspace(1) [[LOAD3]], ptr addrspace(2) [[STORE_GEP3]], align 8
@@ -264,15 +264,15 @@ define void @no_split_p3_p3(ptr addrspace(1) %ptr1, ptr addrspace(2) %ptr2) {
; CHECK-SAME: ptr addrspace(1) [[PTR1:%.*]], ptr addrspace(2) [[PTR2:%.*]]) {
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(1) [[PTR1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[GEP1]], align 4
-; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
+; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i32 [[LOAD11]] to ptr addrspace(3)
-; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i32 [[LOAD22]] to ptr addrspace(3)
; CHECK-NEXT: [[STORE_GEP1:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(2) [[PTR2]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr addrspace(3) [[TMP2]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[TMP4]], i64 0
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr addrspace(3) [[TMP3]] to i32
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP5]], i32 [[TMP6]], i32 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP5]], i32 [[TMP6]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP7]], ptr addrspace(2) [[STORE_GEP1]], align 4
; CHECK-NEXT: ret void
;
@@ -295,15 +295,15 @@ define void @split_p1_p1_p3_p3(ptr addrspace(1) %ptr1, ptr addrspace(2) %ptr2) {
; CHECK-SAME: ptr addrspace(1) [[PTR1:%.*]], ptr addrspace(2) [[PTR2:%.*]]) {
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) [[PTR1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr addrspace(1) [[GEP1]], align 8
-; CHECK-NEXT: [[LOAD13:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
+; CHECK-NEXT: [[LOAD13:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[LOAD13]] to ptr addrspace(1)
-; CHECK-NEXT: [[LOAD24:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD24:%.*]] = extractelement <2 x i64> [[TMP1]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[LOAD24]] to ptr addrspace(1)
; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(1) [[PTR1]], i64 4
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr addrspace(1) [[GEP3]], align 4
-; CHECK-NEXT: [[LOAD31:%.*]] = extractelement <2 x i32> [[TMP4]], i32 0
+; CHECK-NEXT: [[LOAD31:%.*]] = extractelement <2 x i32> [[TMP4]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i32 [[LOAD31]] to ptr addrspace(3)
-; CHECK-NEXT: [[LOAD42:%.*]] = extractelement <2 x i32> [[TMP4]], i32 1
+; CHECK-NEXT: [[LOAD42:%.*]] = extractelement <2 x i32> [[TMP4]], i64 1
; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i32 [[LOAD42]] to ptr addrspace(3)
; CHECK-NEXT: [[STORE_GEP1:%.*]] = getelementptr inbounds ptr addrspace(1), ptr addrspace(2) [[PTR2]], i64 0
; CHECK-NEXT: store ptr addrspace(1) [[TMP2]], ptr addrspace(2) [[STORE_GEP1]], align 8
@@ -311,9 +311,9 @@ define void @split_p1_p1_p3_p3(ptr addrspace(1) %ptr1, ptr addrspace(2) %ptr2) {
; CHECK-NEXT: store ptr addrspace(1) [[TMP3]], ptr addrspace(2) [[STORE_GEP2]], align 8
; CHECK-NEXT: [[STORE_GEP3:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(2) [[PTR2]], i64 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr addrspace(3) [[TMP5]] to i32
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr addrspace(3) [[TMP6]] to i32
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP9]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP9]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP10]], ptr addrspace(2) [[STORE_GEP3]], align 4
; CHECK-NEXT: ret void
;
@@ -343,9 +343,9 @@ define void @no_split_p1_p1(ptr addrspace(1) %ptr1, ptr addrspace(2) %ptr2) {
; CHECK-SAME: ptr addrspace(1) [[PTR1:%.*]], ptr addrspace(2) [[PTR2:%.*]]) {
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) [[PTR1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr addrspace(1) [[GEP1]], align 8
-; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
+; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[LOAD11]] to ptr addrspace(1)
-; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i64> [[TMP1]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[LOAD22]] to ptr addrspace(1)
; CHECK-NEXT: [[STORE_GEP1:%.*]] = getelementptr inbounds ptr addrspace(1), ptr addrspace(2) [[PTR2]], i64 0
; CHECK-NEXT: store ptr addrspace(1) [[TMP2]], ptr addrspace(2) [[STORE_GEP1]], align 8
@@ -372,23 +372,23 @@ define void @split_i16_i16_p3_p3(ptr addrspace(1) %ptr1, ptr addrspace(2) %ptr2)
; CHECK-SAME: ptr addrspace(1) [[PTR1:%.*]], ptr addrspace(2) [[PTR2:%.*]]) {
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i16, ptr addrspace(1) [[PTR1]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr addrspace(1) [[GEP1]], align 4
-; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i16> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i16> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i16> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i16> [[TMP1]], i64 1
; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(1) [[PTR1]], i64 1
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr addrspace(1) [[GEP3]], align 4
-; CHECK-NEXT: [[LOAD33:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; CHECK-NEXT: [[LOAD33:%.*]] = extractelement <2 x i32> [[TMP2]], i64 0
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i32 [[LOAD33]] to ptr addrspace(3)
-; CHECK-NEXT: [[LOAD44:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; CHECK-NEXT: [[LOAD44:%.*]] = extractelement <2 x i32> [[TMP2]], i64 1
; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i32 [[LOAD44]] to ptr addrspace(3)
; CHECK-NEXT: [[STORE_GEP1:%.*]] = getelementptr inbounds i16, ptr addrspace(2) [[PTR2]], i64 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i16> poison, i16 [[LOAD11]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i16> [[TMP5]], i16 [[LOAD22]], i32 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i16> poison, i16 [[LOAD11]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i16> [[TMP5]], i16 [[LOAD22]], i64 1
; CHECK-NEXT: store <2 x i16> [[TMP6]], ptr addrspace(2) [[STORE_GEP1]], align 4
; CHECK-NEXT: [[STORE_GEP3:%.*]] = getelementptr inbounds ptr addrspace(3), ptr addrspace(2) [[PTR2]], i64 1
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr addrspace(3) [[TMP3]] to i32
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> poison, i32 [[TMP7]], i64 0
; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr addrspace(3) [[TMP4]] to i32
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP9]], i32 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i32> [[TMP8]], i32 [[TMP9]], i64 1
; CHECK-NEXT: store <2 x i32> [[TMP10]], ptr addrspace(2) [[STORE_GEP3]], align 4
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll
index cfe99b3aff162..7b7538557f516 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll
@@ -10,8 +10,8 @@ define amdgpu_kernel void @load_keep_base_alignment_missing_align(ptr addrspace(
; CHECK-LABEL: @load_keep_base_alignment_missing_align(
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [512 x float], ptr addrspace(3) @lds, i32 0, i32 11
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr addrspace(3) [[PTR0]], align 4
-; CHECK-NEXT: [[VAL01:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
-; CHECK-NEXT: [[VAL12:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; CHECK-NEXT: [[VAL01:%.*]] = extractelement <2 x float> [[TMP2]], i64 0
+; CHECK-NEXT: [[VAL12:%.*]] = extractelement <2 x float> [[TMP2]], i64 1
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[VAL01]], [[VAL12]]
; CHECK-NEXT: store float [[ADD]], ptr addrspace(1) [[OUT:%.*]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
index b86e1e8d13b2d..0cd76a8b1f2e1 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
@@ -41,17 +41,17 @@ define amdgpu_kernel void @interleave_get_longest(i32 %arg) {
; GCN-NEXT: [[TEMP2:%.*]] = getelementptr [16384 x i32], ptr addrspace(3) @[[GLOB0]], i32 0, i32 [[A1]]
; GCN-NEXT: [[TEMP4:%.*]] = getelementptr [16384 x i32], ptr addrspace(3) @[[GLOB0]], i32 0, i32 [[A3]]
; GCN-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(3) [[TEMP1]], align 4
-; GCN-NEXT: [[L21:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; GCN-NEXT: [[L12:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; GCN-NEXT: [[L21:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; GCN-NEXT: [[L12:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; GCN-NEXT: store <2 x i32> zeroinitializer, ptr addrspace(3) [[TEMP1]], align 4
; GCN-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr addrspace(3) [[TEMP2]], align 4
-; GCN-NEXT: [[L33:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
-; GCN-NEXT: [[L44:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; GCN-NEXT: [[L33:%.*]] = extractelement <2 x i32> [[TMP2]], i64 0
+; GCN-NEXT: [[L44:%.*]] = extractelement <2 x i32> [[TMP2]], i64 1
; GCN-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr addrspace(3) [[TEMP4]], align 4
-; GCN-NEXT: [[L55:%.*]] = extractelement <2 x i32> [[TMP3]], i32 0
-; GCN-NEXT: [[L66:%.*]] = extractelement <2 x i32> [[TMP3]], i32 1
-; GCN-NEXT: [[L77:%.*]] = extractelement <2 x i32> [[TMP3]], i32 1
-; GCN-NEXT: [[L88:%.*]] = extractelement <2 x i32> [[TMP3]], i32 1
+; GCN-NEXT: [[L55:%.*]] = extractelement <2 x i32> [[TMP3]], i64 0
+; GCN-NEXT: [[L66:%.*]] = extractelement <2 x i32> [[TMP3]], i64 1
+; GCN-NEXT: [[L77:%.*]] = extractelement <2 x i32> [[TMP3]], i64 1
+; GCN-NEXT: [[L88:%.*]] = extractelement <2 x i32> [[TMP3]], i64 1
; GCN-NEXT: ret void
;
%a1 = add i32 %arg, 1
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll
index 9516ffd742a2b..55ec15c84f33a 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll
@@ -10,8 +10,8 @@ define i64 @order() {
; CHECK-LABEL: @order(
; CHECK-NEXT: [[IDX0:%.*]] = getelementptr inbounds [[S:%.*]], ptr @S, i32 0, i32 0
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[IDX0]], align 8
-; CHECK-NEXT: [[L01:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
+; CHECK-NEXT: [[L01:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <2 x i64> [[TMP1]], i64 1
; CHECK-NEXT: [[ADD:%.*]] = add i64 [[L01]], [[L12]]
; CHECK-NEXT: ret i64 [[ADD]]
;
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll
index eb336c9b7e21e..57db73a0dd749 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll
@@ -90,7 +90,7 @@ entry:
; CHECK-LABEL: @merge_load_i64_ptr64(
; CHECK: load <2 x i64>
-; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 1
+; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i64 1
; CHECK: inttoptr i64 [[ELT1]] to ptr addrspace(1)
define amdgpu_kernel void @merge_load_i64_ptr64(ptr addrspace(1) nocapture %a) #0 {
entry:
@@ -104,7 +104,7 @@ entry:
; CHECK-LABEL: @merge_load_ptr64_i64(
; CHECK: load <2 x i64>
-; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 0
+; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i64 0
; CHECK: inttoptr i64 [[ELT0]] to ptr addrspace(1)
define amdgpu_kernel void @merge_load_ptr64_i64(ptr addrspace(1) nocapture %a) #0 {
entry:
@@ -118,7 +118,7 @@ entry:
; CHECK-LABEL: @merge_store_ptr64_i64(
; CHECK: [[ELT0:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr0 to i64
-; CHECK: insertelement <2 x i64> poison, i64 [[ELT0]], i32 0
+; CHECK: insertelement <2 x i64> poison, i64 [[ELT0]], i64 0
; CHECK: store <2 x i64>
define amdgpu_kernel void @merge_store_ptr64_i64(ptr addrspace(1) nocapture %a, ptr addrspace(1) %ptr0, i64 %val1) #0 {
entry:
@@ -133,7 +133,7 @@ entry:
; CHECK-LABEL: @merge_store_i64_ptr64(
; CHECK: [[ELT1:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr1 to i64
-; CHECK: insertelement <2 x i64> %{{[^ ]+}}, i64 [[ELT1]], i32 1
+; CHECK: insertelement <2 x i64> %{{[^ ]+}}, i64 [[ELT1]], i64 1
; CHECK: store <2 x i64>
define amdgpu_kernel void @merge_store_i64_ptr64(ptr addrspace(1) nocapture %a, i64 %val0, ptr addrspace(1) %ptr1) #0 {
entry:
@@ -147,7 +147,7 @@ entry:
; CHECK-LABEL: @merge_load_i32_ptr32(
; CHECK: load <2 x i32>
-; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i32> %{{[^ ]+}}, i32 1
+; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i32> %{{[^ ]+}}, i64 1
; CHECK: inttoptr i32 [[ELT1]] to ptr addrspace(3)
define amdgpu_kernel void @merge_load_i32_ptr32(ptr addrspace(3) nocapture %a) #0 {
entry:
@@ -161,7 +161,7 @@ entry:
; CHECK-LABEL: @merge_load_ptr32_i32(
; CHECK: load <2 x i32>
-; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i32> %{{[^ ]+}}, i32 0
+; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i32> %{{[^ ]+}}, i64 0
; CHECK: inttoptr i32 [[ELT0]] to ptr addrspace(3)
define amdgpu_kernel void @merge_load_ptr32_i32(ptr addrspace(3) nocapture %a) #0 {
entry:
@@ -175,7 +175,7 @@ entry:
; CHECK-LABEL: @merge_store_ptr32_i32(
; CHECK: [[ELT0:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr0 to i32
-; CHECK: insertelement <2 x i32> poison, i32 [[ELT0]], i32 0
+; CHECK: insertelement <2 x i32> poison, i32 [[ELT0]], i64 0
; CHECK: store <2 x i32>
define amdgpu_kernel void @merge_store_ptr32_i32(ptr addrspace(3) nocapture %a, ptr addrspace(3) %ptr0, i32 %val1) #0 {
entry:
@@ -189,7 +189,7 @@ entry:
; CHECK-LABEL: @merge_store_i32_ptr32(
; CHECK: [[ELT1:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr1 to i32
-; CHECK: insertelement <2 x i32> %{{[^ ]+}}, i32 [[ELT1]], i32 1
+; CHECK: insertelement <2 x i32> %{{[^ ]+}}, i32 [[ELT1]], i64 1
; CHECK: store <2 x i32>
define amdgpu_kernel void @merge_store_i32_ptr32(ptr addrspace(3) nocapture %a, i32 %val0, ptr addrspace(3) %ptr1) #0 {
entry:
@@ -275,9 +275,9 @@ entry:
; CHECK-LABEL: @merge_load_ptr64_f64(
; CHECK: load <2 x i64>
-; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 0
+; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i64 0
; CHECK: [[ELT0_INT:%[^ ]+]] = inttoptr i64 [[ELT0]] to ptr addrspace(1)
-; CHECK: [[ELT1_INT:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 1
+; CHECK: [[ELT1_INT:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i64 1
; CHECK: bitcast i64 [[ELT1_INT]] to double
define amdgpu_kernel void @merge_load_ptr64_f64(ptr addrspace(1) nocapture %a) #0 {
entry:
@@ -291,9 +291,9 @@ entry:
; CHECK-LABEL: @merge_load_f64_ptr64(
; CHECK: load <2 x i64>
-; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 0
+; CHECK: [[ELT0:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i64 0
; CHECK: bitcast i64 [[ELT0]] to double
-; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i32 1
+; CHECK: [[ELT1:%[^ ]+]] = extractelement <2 x i64> %{{[^ ]+}}, i64 1
; CHECK: inttoptr i64 [[ELT1]] to ptr addrspace(1)
define amdgpu_kernel void @merge_load_f64_ptr64(ptr addrspace(1) nocapture %a) #0 {
entry:
@@ -307,9 +307,9 @@ entry:
; CHECK-LABEL: @merge_store_ptr64_f64(
; CHECK: [[ELT0_INT:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr0 to i64
-; CHECK: insertelement <2 x i64> poison, i64 [[ELT0_INT]], i32 0
+; CHECK: insertelement <2 x i64> poison, i64 [[ELT0_INT]], i64 0
; CHECK: [[ELT1_INT:%[^ ]+]] = bitcast double %val1 to i64
-; CHECK: insertelement <2 x i64> %{{[^ ]+}}, i64 [[ELT1_INT]], i32 1
+; CHECK: insertelement <2 x i64> %{{[^ ]+}}, i64 [[ELT1_INT]], i64 1
; CHECK: store <2 x i64>
define amdgpu_kernel void @merge_store_ptr64_f64(ptr addrspace(1) nocapture %a, ptr addrspace(1) %ptr0, double %val1) #0 {
entry:
@@ -323,9 +323,9 @@ entry:
; CHECK-LABEL: @merge_store_f64_ptr64(
; CHECK: [[ELT0_INT:%[^ ]+]] = bitcast double %val0 to i64
-; CHECK: insertelement <2 x i64> poison, i64 [[ELT0_INT]], i32 0
+; CHECK: insertelement <2 x i64> poison, i64 [[ELT0_INT]], i64 0
; CHECK: [[ELT1_INT:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr1 to i64
-; CHECK: insertelement <2 x i64> %{{[^ ]+}}, i64 [[ELT1_INT]], i32 1
+; CHECK: insertelement <2 x i64> %{{[^ ]+}}, i64 [[ELT1_INT]], i64 1
; CHECK: store <2 x i64>
define amdgpu_kernel void @merge_store_f64_ptr64(ptr addrspace(1) nocapture %a, double %val0, ptr addrspace(1) %ptr1) #0 {
entry:
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll
index 7772a9393d37b..1bc6ffcbeb938 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/unaligned-buffer.ll
@@ -28,10 +28,10 @@ define amdgpu_kernel void @merge_align_4(ptr addrspace(7) captures(none) %p) #0
; OOB-RELAXED-NEXT: [[ENTRY:.*:]]
; OOB-RELAXED-NEXT: [[GEP_M8:%.*]] = getelementptr i8, ptr addrspace(7) [[P]], i32 -8
; OOB-RELAXED-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr addrspace(7) [[GEP_M8]], align 4
-; OOB-RELAXED-NEXT: [[LD_M81:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0
-; OOB-RELAXED-NEXT: [[LD_M42:%.*]] = extractelement <4 x i32> [[TMP0]], i32 1
-; OOB-RELAXED-NEXT: [[LD_03:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2
-; OOB-RELAXED-NEXT: [[LD_44:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3
+; OOB-RELAXED-NEXT: [[LD_M81:%.*]] = extractelement <4 x i32> [[TMP0]], i64 0
+; OOB-RELAXED-NEXT: [[LD_M42:%.*]] = extractelement <4 x i32> [[TMP0]], i64 1
+; OOB-RELAXED-NEXT: [[LD_03:%.*]] = extractelement <4 x i32> [[TMP0]], i64 2
+; OOB-RELAXED-NEXT: [[LD_44:%.*]] = extractelement <4 x i32> [[TMP0]], i64 3
; OOB-RELAXED-NEXT: ret void
;
entry:
@@ -55,10 +55,10 @@ define amdgpu_kernel void @merge_align_16(ptr addrspace(7) captures(none) %p) #0
; OOB-STRICT-NEXT: [[ENTRY:.*:]]
; OOB-STRICT-NEXT: [[GEP_M8:%.*]] = getelementptr i8, ptr addrspace(7) [[P]], i32 -8
; OOB-STRICT-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr addrspace(7) [[GEP_M8]], align 16
-; OOB-STRICT-NEXT: [[LD_M81:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0
-; OOB-STRICT-NEXT: [[LD_M42:%.*]] = extractelement <4 x i32> [[TMP0]], i32 1
-; OOB-STRICT-NEXT: [[LD_03:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2
-; OOB-STRICT-NEXT: [[LD_44:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3
+; OOB-STRICT-NEXT: [[LD_M81:%.*]] = extractelement <4 x i32> [[TMP0]], i64 0
+; OOB-STRICT-NEXT: [[LD_M42:%.*]] = extractelement <4 x i32> [[TMP0]], i64 1
+; OOB-STRICT-NEXT: [[LD_03:%.*]] = extractelement <4 x i32> [[TMP0]], i64 2
+; OOB-STRICT-NEXT: [[LD_44:%.*]] = extractelement <4 x i32> [[TMP0]], i64 3
; OOB-STRICT-NEXT: ret void
;
; OOB-RELAXED-LABEL: define amdgpu_kernel void @merge_align_16(
@@ -66,10 +66,10 @@ define amdgpu_kernel void @merge_align_16(ptr addrspace(7) captures(none) %p) #0
; OOB-RELAXED-NEXT: [[ENTRY:.*:]]
; OOB-RELAXED-NEXT: [[GEP_M8:%.*]] = getelementptr i8, ptr addrspace(7) [[P]], i32 -8
; OOB-RELAXED-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr addrspace(7) [[GEP_M8]], align 16
-; OOB-RELAXED-NEXT: [[LD_M81:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0
-; OOB-RELAXED-NEXT: [[LD_M42:%.*]] = extractelement <4 x i32> [[TMP0]], i32 1
-; OOB-RELAXED-NEXT: [[LD_03:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2
-; OOB-RELAXED-NEXT: [[LD_44:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3
+; OOB-RELAXED-NEXT: [[LD_M81:%.*]] = extractelement <4 x i32> [[TMP0]], i64 0
+; OOB-RELAXED-NEXT: [[LD_M42:%.*]] = extractelement <4 x i32> [[TMP0]], i64 1
+; OOB-RELAXED-NEXT: [[LD_03:%.*]] = extractelement <4 x i32> [[TMP0]], i64 2
+; OOB-RELAXED-NEXT: [[LD_44:%.*]] = extractelement <4 x i32> [[TMP0]], i64 3
; OOB-RELAXED-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll
index bb0e6067bf248..1fd5a6682a7d0 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/vectorize-redund-loads.ll
@@ -32,10 +32,10 @@ define void @test(ptr %ptr) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[PTR]], align 4
-; CHECK-NEXT: [[LD01:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
+; CHECK-NEXT: [[LD01:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
; CHECK-NEXT: [[LD12:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <2 x i32> <i32 1, i32 2>
; CHECK-NEXT: [[LD23:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: [[LD34:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
+; CHECK-NEXT: [[LD34:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
; CHECK-NEXT: ret void
;
%ld0 = load i32, ptr %ptr, align 4
@@ -54,13 +54,13 @@ define void @test2() {
; CHECK-LABEL: define void @test2() {
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr addrspace(1) @ptr, align 4
; CHECK-NEXT: [[VECINS1:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x float> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x float> [[TMP1]], i32 2
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x float> [[TMP1]], i32 3
-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x float> [[TMP1]], i32 4
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x float> [[TMP1]], i32 5
-; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x float> [[TMP1]], i32 6
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x float> [[TMP1]], i32 7
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x float> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x float> [[TMP1]], i64 2
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x float> [[TMP1]], i64 3
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x float> [[TMP1]], i64 4
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x float> [[TMP1]], i64 5
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x float> [[TMP1]], i64 6
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x float> [[TMP1]], i64 7
; CHECK-NEXT: [[VECINS_1:%.*]] = insertelement <8 x float> [[VECINS1]], float [[TMP2]], i64 1
; CHECK-NEXT: [[VECINS_2:%.*]] = insertelement <8 x float> [[VECINS_1]], float [[TMP3]], i64 2
; CHECK-NEXT: [[VECINS_3:%.*]] = insertelement <8 x float> [[VECINS_2]], float [[TMP4]], i64 3
@@ -95,8 +95,8 @@ define void @vect_zext_bitcast_i8_st4_to_i32_idx(ptr addrspace(1) %arg1, i32 %ba
; CHECK-NEXT: [[ZEXT1:%.*]] = zext i32 [[ADD1]] to i64
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG1]], i64 [[ZEXT1]]
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[GEP1]], align 4
-; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[LOAD11:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD22:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[ADD25:%.*]] = add nuw i32 [[BASE]], 6
; CHECK-NEXT: [[ZEXT25:%.*]] = zext i32 [[ADD25]] to i64
; CHECK-NEXT: [[GEP25:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG1]], i64 [[ZEXT25]]
@@ -105,8 +105,8 @@ define void @vect_zext_bitcast_i8_st4_to_i32_idx(ptr addrspace(1) %arg1, i32 %ba
; CHECK-NEXT: [[ZEXT3:%.*]] = zext i32 [[ADD3]] to i64
; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG1]], i64 [[ZEXT3]]
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr addrspace(1) [[GEP3]], align 4
-; CHECK-NEXT: [[LOAD33:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
-; CHECK-NEXT: [[LOAD44:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; CHECK-NEXT: [[LOAD33:%.*]] = extractelement <2 x i32> [[TMP2]], i64 0
+; CHECK-NEXT: [[LOAD44:%.*]] = extractelement <2 x i32> [[TMP2]], i64 1
; CHECK-NEXT: ret void
;
%add1 = add nuw i32 %base, 0
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
index 89f2be8494f67..995640bc4af28 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/4x2xhalf.ll
@@ -17,22 +17,22 @@ define void @ldg_f16(ptr nocapture align 16 %rd0) {
; CHECK-NEXT: [[S3:%.*]] = select <2 x i1> [[P3]], <2 x half> [[LOAD33]], <2 x half> zeroinitializer
; CHECK-NEXT: [[P4:%.*]] = fcmp ogt <2 x half> [[LOAD44]], zeroinitializer
; CHECK-NEXT: [[S4:%.*]] = select <2 x i1> [[P4]], <2 x half> [[LOAD44]], <2 x half> zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x half> [[S1]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x half> poison, half [[TMP2]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x half> [[S1]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x half> [[TMP3]], half [[TMP4]], i32 1
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x half> [[S2]], i32 0
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x half> [[TMP5]], half [[TMP6]], i32 2
-; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x half> [[S2]], i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x half> [[TMP7]], half [[TMP8]], i32 3
-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x half> [[S3]], i32 0
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x half> [[TMP9]], half [[TMP10]], i32 4
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x half> [[S3]], i32 1
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x half> [[TMP11]], half [[TMP12]], i32 5
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x half> [[S4]], i32 0
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x half> [[TMP13]], half [[TMP14]], i32 6
-; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x half> [[S4]], i32 1
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <8 x half> [[TMP15]], half [[TMP16]], i32 7
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x half> [[S1]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x half> poison, half [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x half> [[S1]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x half> [[TMP3]], half [[TMP4]], i64 1
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x half> [[S2]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x half> [[TMP5]], half [[TMP6]], i64 2
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x half> [[S2]], i64 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x half> [[TMP7]], half [[TMP8]], i64 3
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x half> [[S3]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x half> [[TMP9]], half [[TMP10]], i64 4
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x half> [[S3]], i64 1
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x half> [[TMP11]], half [[TMP12]], i64 5
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x half> [[S4]], i64 0
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x half> [[TMP13]], half [[TMP14]], i64 6
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x half> [[S4]], i64 1
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <8 x half> [[TMP15]], half [[TMP16]], i64 7
; CHECK-NEXT: store <8 x half> [[TMP17]], ptr [[RD0]], align 16
; CHECK-NEXT: ret void
;
@@ -65,8 +65,8 @@ define void @no_nonpow2_vector(ptr nocapture align 16 %rd0) {
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x half> @llvm.masked.load.v8f16.p0(ptr align 16 [[RD0]], <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false>, <8 x half> poison)
; CHECK-NEXT: [[LOAD13:%.*]] = shufflevector <8 x half> [[TMP1]], <8 x half> poison, <3 x i32> <i32 0, i32 1, i32 2>
; CHECK-NEXT: [[LOAD24:%.*]] = shufflevector <8 x half> [[TMP1]], <8 x half> poison, <3 x i32> <i32 3, i32 4, i32 5>
-; CHECK-NEXT: [[EXTEND5:%.*]] = extractelement <8 x half> [[TMP1]], i32 6
-; CHECK-NEXT: [[EXTEND26:%.*]] = extractelement <8 x half> [[TMP1]], i32 7
+; CHECK-NEXT: [[EXTEND5:%.*]] = extractelement <8 x half> [[TMP1]], i64 6
+; CHECK-NEXT: [[EXTEND26:%.*]] = extractelement <8 x half> [[TMP1]], i64 7
; CHECK-NEXT: [[P1:%.*]] = fcmp ogt <3 x half> [[LOAD13]], zeroinitializer
; CHECK-NEXT: [[S1:%.*]] = select <3 x i1> [[P1]], <3 x half> [[LOAD13]], <3 x half> zeroinitializer
; CHECK-NEXT: store <3 x half> [[S1]], ptr [[RD0]], align 16
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/extend-chain.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/extend-chain.ll
index 5c3757867f71f..b843834a6352b 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/extend-chain.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/extend-chain.ll
@@ -11,10 +11,10 @@ define void @load3to4(ptr %p) {
; CHECK-SAME: ptr [[P:%.*]]) {
; CHECK-NEXT: [[P_0:%.*]] = getelementptr i32, ptr [[P]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[P_0]], <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i32> poison)
-; CHECK-NEXT: [[V01:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[V12:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[V23:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[EXTEND4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[V01:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[V12:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[V23:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[EXTEND4:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: ret void
;
%p.0 = getelementptr i32, ptr %p, i32 0
@@ -33,14 +33,14 @@ define void @load5to8(ptr %p) {
; CHECK-SAME: ptr [[P:%.*]]) {
; CHECK-NEXT: [[P_0:%.*]] = getelementptr i16, ptr [[P]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 16 [[P_0]], <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false>, <8 x i16> poison)
-; CHECK-NEXT: [[V05:%.*]] = extractelement <8 x i16> [[TMP1]], i32 0
-; CHECK-NEXT: [[V16:%.*]] = extractelement <8 x i16> [[TMP1]], i32 1
-; CHECK-NEXT: [[V27:%.*]] = extractelement <8 x i16> [[TMP1]], i32 2
-; CHECK-NEXT: [[V38:%.*]] = extractelement <8 x i16> [[TMP1]], i32 3
-; CHECK-NEXT: [[V49:%.*]] = extractelement <8 x i16> [[TMP1]], i32 4
-; CHECK-NEXT: [[EXTEND10:%.*]] = extractelement <8 x i16> [[TMP1]], i32 5
-; CHECK-NEXT: [[EXTEND211:%.*]] = extractelement <8 x i16> [[TMP1]], i32 6
-; CHECK-NEXT: [[EXTEND412:%.*]] = extractelement <8 x i16> [[TMP1]], i32 7
+; CHECK-NEXT: [[V05:%.*]] = extractelement <8 x i16> [[TMP1]], i64 0
+; CHECK-NEXT: [[V16:%.*]] = extractelement <8 x i16> [[TMP1]], i64 1
+; CHECK-NEXT: [[V27:%.*]] = extractelement <8 x i16> [[TMP1]], i64 2
+; CHECK-NEXT: [[V38:%.*]] = extractelement <8 x i16> [[TMP1]], i64 3
+; CHECK-NEXT: [[V49:%.*]] = extractelement <8 x i16> [[TMP1]], i64 4
+; CHECK-NEXT: [[EXTEND10:%.*]] = extractelement <8 x i16> [[TMP1]], i64 5
+; CHECK-NEXT: [[EXTEND211:%.*]] = extractelement <8 x i16> [[TMP1]], i64 6
+; CHECK-NEXT: [[EXTEND412:%.*]] = extractelement <8 x i16> [[TMP1]], i64 7
; CHECK-NEXT: ret void
;
%p.0 = getelementptr i16, ptr %p, i32 0
@@ -63,14 +63,14 @@ define void @load6to8(ptr %p) {
; CHECK-SAME: ptr [[P:%.*]]) {
; CHECK-NEXT: [[P_0:%.*]] = getelementptr i16, ptr [[P]], i32 0
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 16 [[P_0]], <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false>, <8 x i16> poison)
-; CHECK-NEXT: [[V05:%.*]] = extractelement <8 x i16> [[TMP1]], i32 0
-; CHECK-NEXT: [[V16:%.*]] = extractelement <8 x i16> [[TMP1]], i32 1
-; CHECK-NEXT: [[V27:%.*]] = extractelement <8 x i16> [[TMP1]], i32 2
-; CHECK-NEXT: [[V38:%.*]] = extractelement <8 x i16> [[TMP1]], i32 3
-; CHECK-NEXT: [[V49:%.*]] = extractelement <8 x i16> [[TMP1]], i32 4
-; CHECK-NEXT: [[EXTEND10:%.*]] = extractelement <8 x i16> [[TMP1]], i32 5
-; CHECK-NEXT: [[EXTEND211:%.*]] = extractelement <8 x i16> [[TMP1]], i32 6
-; CHECK-NEXT: [[EXTEND412:%.*]] = extractelement <8 x i16> [[TMP1]], i32 7
+; CHECK-NEXT: [[V03:%.*]] = extractelement <8 x i16> [[TMP1]], i64 0
+; CHECK-NEXT: [[V14:%.*]] = extractelement <8 x i16> [[TMP1]], i64 1
+; CHECK-NEXT: [[V25:%.*]] = extractelement <8 x i16> [[TMP1]], i64 2
+; CHECK-NEXT: [[V36:%.*]] = extractelement <8 x i16> [[TMP1]], i64 3
+; CHECK-NEXT: [[V47:%.*]] = extractelement <8 x i16> [[TMP1]], i64 4
+; CHECK-NEXT: [[V58:%.*]] = extractelement <8 x i16> [[TMP1]], i64 5
+; CHECK-NEXT: [[EXTEND9:%.*]] = extractelement <8 x i16> [[TMP1]], i64 6
+; CHECK-NEXT: [[EXTEND210:%.*]] = extractelement <8 x i16> [[TMP1]], i64 7
; CHECK-NEXT: ret void
;
%p.0 = getelementptr i16, ptr %p, i32 0
@@ -96,8 +96,8 @@ define void @load3to4_unaligned(ptr %p) {
; CHECK-NEXT: [[P_0:%.*]] = getelementptr i32, ptr [[P]], i32 0
; CHECK-NEXT: [[P_2:%.*]] = getelementptr i32, ptr [[P]], i32 2
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[P_0]], align 8
-; CHECK-NEXT: [[V01:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[V12:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[V01:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[V12:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[V2:%.*]] = load i32, ptr [[P_2]], align 8
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-cleanup.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-cleanup.ll
index 7b659b0feeb03..eab696725ac55 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-cleanup.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-cleanup.ll
@@ -9,10 +9,10 @@ define void @fillTwoGapsCanVectorize(ptr %in) {
; CHECK-LABEL: define void @fillTwoGapsCanVectorize(
; CHECK-SAME: ptr [[IN:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[IN]], <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> poison)
-; CHECK-NEXT: [[LOAD03:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[GAPFILL4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[GAPFILL25:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LOAD36:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[LOAD03:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[GAPFILL4:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[GAPFILL25:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LOAD36:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: ret void
;
%load0 = load i32, ptr %in, align 16
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-invariant.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-invariant.ll
index 145512863f4d7..a77ec1b4cb4f3 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-invariant.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-invariant.ll
@@ -9,10 +9,10 @@ define i32 @noGaps(ptr %in) {
; CHECK-LABEL: define i32 @noGaps(
; CHECK-SAME: ptr [[IN:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[IN]], align 16, !invariant.load [[META0:![0-9]+]]
-; CHECK-NEXT: [[TMP01:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP01:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: [[SUM01:%.*]] = add i32 [[TMP01]], [[TMP12]]
; CHECK-NEXT: [[SUM012:%.*]] = add i32 [[SUM01]], [[TMP23]]
; CHECK-NEXT: [[SUM0123:%.*]] = add i32 [[SUM012]], [[TMP34]]
@@ -36,10 +36,10 @@ define i32 @noGapsMissingInvariant(ptr %in) {
; CHECK-LABEL: define i32 @noGapsMissingInvariant(
; CHECK-SAME: ptr [[IN:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[IN]], align 16
-; CHECK-NEXT: [[TMP01:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP01:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[TMP34:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: [[SUM01:%.*]] = add i32 [[TMP01]], [[TMP12]]
; CHECK-NEXT: [[SUM012:%.*]] = add i32 [[SUM01]], [[TMP23]]
; CHECK-NEXT: [[SUM0123:%.*]] = add i32 [[SUM012]], [[TMP34]]
@@ -63,10 +63,10 @@ define i32 @twoGaps(ptr %in) {
; CHECK-LABEL: define i32 @twoGaps(
; CHECK-SAME: ptr [[IN:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[IN]], <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> poison), !invariant.load [[META0]]
-; CHECK-NEXT: [[LOAD03:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[GAPFILL4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[GAPFILL25:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LOAD36:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[LOAD03:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[GAPFILL4:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[GAPFILL25:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LOAD36:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: [[SUM:%.*]] = add i32 [[LOAD03]], [[LOAD36]]
; CHECK-NEXT: ret i32 [[SUM]]
;
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-with-redundant-elements.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-with-redundant-elements.ll
index e22035b4ed922..ea60e45af8a71 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-with-redundant-elements.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill-with-redundant-elements.ll
@@ -6,7 +6,7 @@ define void @test_redundant_no_gap(ptr addrspace(1) %ptr) {
; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr addrspace(1) [[PTR]], align 32
; CHECK-NEXT: [[LD03:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 0, i32 1>
-; CHECK-NEXT: [[LD14:%.*]] = extractelement <8 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[LD12:%.*]] = extractelement <8 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[LD25:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: [[LD37:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: [[LD45:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
@@ -32,7 +32,7 @@ define void @test_redundant_gap(ptr addrspace(1) %ptr) {
; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p1(ptr addrspace(1) align 32 [[PTR]], <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i32> poison)
; CHECK-NEXT: [[LD01:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 0, i32 1>
-; CHECK-NEXT: [[LD12:%.*]] = extractelement <8 x i32> [[TMP1]], i32 0
+; CHECK-NEXT: [[LD12:%.*]] = extractelement <8 x i32> [[TMP1]], i64 0
; CHECK-NEXT: [[GAPFILL3:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: [[LD34:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 4, i32 5>
; CHECK-NEXT: [[LD45:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
@@ -54,12 +54,12 @@ define void @test_redundant_gap_and_extend(ptr addrspace(1) %ptr) {
; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p1(ptr addrspace(1) align 32 [[PTR]], <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false>, <8 x i32> poison)
; CHECK-NEXT: [[LD03:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 0, i32 1>
-; CHECK-NEXT: [[LD14:%.*]] = extractelement <8 x i32> [[TMP1]], i32 0
+; CHECK-NEXT: [[LD14:%.*]] = extractelement <8 x i32> [[TMP1]], i64 0
; CHECK-NEXT: [[GAPFILL5:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: [[LD36:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <2 x i32> <i32 4, i32 5>
-; CHECK-NEXT: [[LD47:%.*]] = extractelement <8 x i32> [[TMP1]], i32 4
-; CHECK-NEXT: [[EXTEND8:%.*]] = extractelement <8 x i32> [[TMP1]], i32 6
-; CHECK-NEXT: [[EXTEND29:%.*]] = extractelement <8 x i32> [[TMP1]], i32 7
+; CHECK-NEXT: [[LD47:%.*]] = extractelement <8 x i32> [[TMP1]], i64 4
+; CHECK-NEXT: [[EXTEND8:%.*]] = extractelement <8 x i32> [[TMP1]], i64 6
+; CHECK-NEXT: [[EXTEND29:%.*]] = extractelement <8 x i32> [[TMP1]], i64 7
; CHECK-NEXT: ret void
;
%ld0 = load <2 x i32>, ptr addrspace(1) %ptr, align 32
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill.ll
index 83152ece5c4d1..36cb4064fe3a5 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/gap-fill.ll
@@ -6,10 +6,10 @@ define void @test(ptr %ptr) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[PTR]], <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i32> poison)
-; CHECK-NEXT: [[LD01:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LD12:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[GAPFILL3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LD34:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[LD01:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LD12:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[GAPFILL3:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LD34:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: ret void
;
%ld0 = load i32, ptr %ptr, align 16
@@ -25,10 +25,10 @@ define void @test2(ptr %ptr) {
; CHECK-LABEL: define void @test2(
; CHECK-SAME: ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[PTR]], <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> poison)
-; CHECK-NEXT: [[LD01:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[GAPFILL2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[LD23:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LD34:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[LD01:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[GAPFILL2:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[LD23:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LD34:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: ret void
;
%ld0 = load i32, ptr %ptr, align 16
@@ -45,8 +45,8 @@ define void @test3(ptr %ptr) {
; CHECK-LABEL: define void @test3(
; CHECK-SAME: ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[PTR]], align 16
-; CHECK-NEXT: [[LD01:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
-; CHECK-NEXT: [[LD12:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
+; CHECK-NEXT: [[LD01:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
+; CHECK-NEXT: [[LD12:%.*]] = extractelement <2 x i64> [[TMP1]], i64 1
; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 24
; CHECK-NEXT: [[LD3:%.*]] = load i64, ptr [[GEP3]], align 4
; CHECK-NEXT: ret void
@@ -67,8 +67,8 @@ define void @test4(ptr %ptr) {
; CHECK-NEXT: [[LD0:%.*]] = load i64, ptr [[PTR]], align 16
; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 16
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[GEP2]], align 16
-; CHECK-NEXT: [[LD21:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
-; CHECK-NEXT: [[LD32:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
+; CHECK-NEXT: [[LD21:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
+; CHECK-NEXT: [[LD32:%.*]] = extractelement <2 x i64> [[TMP1]], i64 1
; CHECK-NEXT: ret void
;
%ld0 = load i64, ptr %ptr, align 16
@@ -84,10 +84,10 @@ define void @test5(ptr %ptr) {
; CHECK-LABEL: define void @test5(
; CHECK-SAME: ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[PTR]], <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> poison)
-; CHECK-NEXT: [[LD03:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[GAPFILL4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[GAPFILL25:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LD36:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[LD03:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[GAPFILL4:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[GAPFILL25:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LD36:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: ret void
;
%ld0 = load i32, ptr %ptr, align 16
@@ -101,16 +101,16 @@ define void @test6(ptr %ptr) {
; CHECK-LABEL: define void @test6(
; CHECK-SAME: ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[PTR]], <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i32> poison)
-; CHECK-NEXT: [[LD03:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LD14:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[GAPFILL5:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LD36:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[LD03:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LD14:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[GAPFILL5:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LD36:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: [[GEP4:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 16
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[GEP4]], <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> poison)
-; CHECK-NEXT: [[LD47:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
-; CHECK-NEXT: [[GAPFILL28:%.*]] = extractelement <4 x i32> [[TMP2]], i32 1
-; CHECK-NEXT: [[LD69:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2
-; CHECK-NEXT: [[LD710:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3
+; CHECK-NEXT: [[LD47:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0
+; CHECK-NEXT: [[GAPFILL28:%.*]] = extractelement <4 x i32> [[TMP2]], i64 1
+; CHECK-NEXT: [[LD69:%.*]] = extractelement <4 x i32> [[TMP2]], i64 2
+; CHECK-NEXT: [[LD710:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3
; CHECK-NEXT: ret void
;
%ld0 = load i32, ptr %ptr, align 16
@@ -133,16 +133,16 @@ define void @test7(ptr %ptr) {
; CHECK-LABEL: define void @test7(
; CHECK-SAME: ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[PTR]], <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i32> poison)
-; CHECK-NEXT: [[LD05:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LD16:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[GAPFILL7:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LD38:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[LD05:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LD16:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[GAPFILL7:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LD38:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: [[GEP4:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 16
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[GEP4]], <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> poison)
-; CHECK-NEXT: [[LD49:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
-; CHECK-NEXT: [[GAPFILL210:%.*]] = extractelement <4 x i32> [[TMP2]], i32 1
-; CHECK-NEXT: [[GAPFILL411:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2
-; CHECK-NEXT: [[LD712:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3
+; CHECK-NEXT: [[LD49:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0
+; CHECK-NEXT: [[GAPFILL210:%.*]] = extractelement <4 x i32> [[TMP2]], i64 1
+; CHECK-NEXT: [[GAPFILL411:%.*]] = extractelement <4 x i32> [[TMP2]], i64 2
+; CHECK-NEXT: [[LD712:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3
; CHECK-NEXT: ret void
;
%ld0 = load i32, ptr %ptr, align 16
@@ -165,17 +165,17 @@ define void @test8(ptr %ptr) {
; CHECK-LABEL: define void @test8(
; CHECK-SAME: ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[PTR]], <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i32> poison)
-; CHECK-NEXT: [[LD03:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LD14:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[GAPFILL5:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LD36:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[LD03:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LD14:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[GAPFILL5:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LD36:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 12
; CHECK-NEXT: [[GAPFILLGEP1:%.*]] = getelementptr i8, ptr [[GEP3]], i64 4
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 16 [[GAPFILLGEP1]], <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> poison)
-; CHECK-NEXT: [[GAPFILL27:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
-; CHECK-NEXT: [[LD58:%.*]] = extractelement <4 x i32> [[TMP2]], i32 1
-; CHECK-NEXT: [[LD69:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2
-; CHECK-NEXT: [[LD710:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3
+; CHECK-NEXT: [[GAPFILL27:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0
+; CHECK-NEXT: [[LD58:%.*]] = extractelement <4 x i32> [[TMP2]], i64 1
+; CHECK-NEXT: [[LD69:%.*]] = extractelement <4 x i32> [[TMP2]], i64 2
+; CHECK-NEXT: [[LD710:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3
; CHECK-NEXT: ret void
;
%ld0 = load i32, ptr %ptr, align 16
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/load-store-256-bit.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/load-store-256-bit.ll
index 649347d455c67..bf73da54dbb8e 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/load-store-256-bit.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/load-store-256-bit.ll
@@ -22,72 +22,72 @@ define void @int8x32(ptr addrspace(1) %ptr) {
; SM90-NEXT: [[PTR0:%.*]] = getelementptr i8, ptr addrspace(1) [[PTR]], i64 0
; SM90-NEXT: [[PTR10:%.*]] = getelementptr i8, ptr addrspace(1) [[PTR]], i64 16
; SM90-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[L01:%.*]] = extractelement <16 x i8> [[TMP1]], i32 0
-; SM90-NEXT: [[L110:%.*]] = extractelement <16 x i8> [[TMP1]], i32 1
-; SM90-NEXT: [[L211:%.*]] = extractelement <16 x i8> [[TMP1]], i32 2
-; SM90-NEXT: [[L312:%.*]] = extractelement <16 x i8> [[TMP1]], i32 3
-; SM90-NEXT: [[L413:%.*]] = extractelement <16 x i8> [[TMP1]], i32 4
-; SM90-NEXT: [[L514:%.*]] = extractelement <16 x i8> [[TMP1]], i32 5
-; SM90-NEXT: [[L615:%.*]] = extractelement <16 x i8> [[TMP1]], i32 6
-; SM90-NEXT: [[L716:%.*]] = extractelement <16 x i8> [[TMP1]], i32 7
-; SM90-NEXT: [[L817:%.*]] = extractelement <16 x i8> [[TMP1]], i32 8
-; SM90-NEXT: [[L918:%.*]] = extractelement <16 x i8> [[TMP1]], i32 9
-; SM90-NEXT: [[LA19:%.*]] = extractelement <16 x i8> [[TMP1]], i32 10
-; SM90-NEXT: [[LB20:%.*]] = extractelement <16 x i8> [[TMP1]], i32 11
-; SM90-NEXT: [[LC21:%.*]] = extractelement <16 x i8> [[TMP1]], i32 12
-; SM90-NEXT: [[LD22:%.*]] = extractelement <16 x i8> [[TMP1]], i32 13
-; SM90-NEXT: [[LE23:%.*]] = extractelement <16 x i8> [[TMP1]], i32 14
-; SM90-NEXT: [[LF24:%.*]] = extractelement <16 x i8> [[TMP1]], i32 15
+; SM90-NEXT: [[L01:%.*]] = extractelement <16 x i8> [[TMP1]], i64 0
+; SM90-NEXT: [[L110:%.*]] = extractelement <16 x i8> [[TMP1]], i64 1
+; SM90-NEXT: [[L211:%.*]] = extractelement <16 x i8> [[TMP1]], i64 2
+; SM90-NEXT: [[L312:%.*]] = extractelement <16 x i8> [[TMP1]], i64 3
+; SM90-NEXT: [[L413:%.*]] = extractelement <16 x i8> [[TMP1]], i64 4
+; SM90-NEXT: [[L514:%.*]] = extractelement <16 x i8> [[TMP1]], i64 5
+; SM90-NEXT: [[L615:%.*]] = extractelement <16 x i8> [[TMP1]], i64 6
+; SM90-NEXT: [[L716:%.*]] = extractelement <16 x i8> [[TMP1]], i64 7
+; SM90-NEXT: [[L817:%.*]] = extractelement <16 x i8> [[TMP1]], i64 8
+; SM90-NEXT: [[L918:%.*]] = extractelement <16 x i8> [[TMP1]], i64 9
+; SM90-NEXT: [[LA19:%.*]] = extractelement <16 x i8> [[TMP1]], i64 10
+; SM90-NEXT: [[LB20:%.*]] = extractelement <16 x i8> [[TMP1]], i64 11
+; SM90-NEXT: [[LC21:%.*]] = extractelement <16 x i8> [[TMP1]], i64 12
+; SM90-NEXT: [[LD22:%.*]] = extractelement <16 x i8> [[TMP1]], i64 13
+; SM90-NEXT: [[LE23:%.*]] = extractelement <16 x i8> [[TMP1]], i64 14
+; SM90-NEXT: [[LF24:%.*]] = extractelement <16 x i8> [[TMP1]], i64 15
; SM90-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr addrspace(1) [[PTR10]], align 16
-; SM90-NEXT: [[L1025:%.*]] = extractelement <16 x i8> [[TMP2]], i32 0
-; SM90-NEXT: [[L1126:%.*]] = extractelement <16 x i8> [[TMP2]], i32 1
-; SM90-NEXT: [[L1227:%.*]] = extractelement <16 x i8> [[TMP2]], i32 2
-; SM90-NEXT: [[L1328:%.*]] = extractelement <16 x i8> [[TMP2]], i32 3
-; SM90-NEXT: [[L1429:%.*]] = extractelement <16 x i8> [[TMP2]], i32 4
-; SM90-NEXT: [[L1530:%.*]] = extractelement <16 x i8> [[TMP2]], i32 5
-; SM90-NEXT: [[L1631:%.*]] = extractelement <16 x i8> [[TMP2]], i32 6
-; SM90-NEXT: [[L1732:%.*]] = extractelement <16 x i8> [[TMP2]], i32 7
-; SM90-NEXT: [[L1833:%.*]] = extractelement <16 x i8> [[TMP2]], i32 8
-; SM90-NEXT: [[L1934:%.*]] = extractelement <16 x i8> [[TMP2]], i32 9
-; SM90-NEXT: [[L1A35:%.*]] = extractelement <16 x i8> [[TMP2]], i32 10
-; SM90-NEXT: [[L1B36:%.*]] = extractelement <16 x i8> [[TMP2]], i32 11
-; SM90-NEXT: [[L1C37:%.*]] = extractelement <16 x i8> [[TMP2]], i32 12
-; SM90-NEXT: [[L1D38:%.*]] = extractelement <16 x i8> [[TMP2]], i32 13
-; SM90-NEXT: [[L1E39:%.*]] = extractelement <16 x i8> [[TMP2]], i32 14
-; SM90-NEXT: [[L1F40:%.*]] = extractelement <16 x i8> [[TMP2]], i32 15
-; SM90-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> poison, i8 [[LB20]], i32 0
-; SM90-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> [[TMP3]], i8 [[LA19]], i32 1
-; SM90-NEXT: [[TMP5:%.*]] = insertelement <16 x i8> [[TMP4]], i8 [[L918]], i32 2
-; SM90-NEXT: [[TMP6:%.*]] = insertelement <16 x i8> [[TMP5]], i8 [[L817]], i32 3
-; SM90-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[TMP6]], i8 [[L716]], i32 4
-; SM90-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 [[L615]], i32 5
-; SM90-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[L514]], i32 6
-; SM90-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[L413]], i32 7
-; SM90-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[L312]], i32 8
-; SM90-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[L211]], i32 9
-; SM90-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[L110]], i32 10
-; SM90-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[L01]], i32 11
-; SM90-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[LF24]], i32 12
-; SM90-NEXT: [[TMP16:%.*]] = insertelement <16 x i8> [[TMP15]], i8 [[LE23]], i32 13
-; SM90-NEXT: [[TMP17:%.*]] = insertelement <16 x i8> [[TMP16]], i8 [[LD22]], i32 14
-; SM90-NEXT: [[TMP18:%.*]] = insertelement <16 x i8> [[TMP17]], i8 [[LC21]], i32 15
+; SM90-NEXT: [[L1025:%.*]] = extractelement <16 x i8> [[TMP2]], i64 0
+; SM90-NEXT: [[L1126:%.*]] = extractelement <16 x i8> [[TMP2]], i64 1
+; SM90-NEXT: [[L1227:%.*]] = extractelement <16 x i8> [[TMP2]], i64 2
+; SM90-NEXT: [[L1328:%.*]] = extractelement <16 x i8> [[TMP2]], i64 3
+; SM90-NEXT: [[L1429:%.*]] = extractelement <16 x i8> [[TMP2]], i64 4
+; SM90-NEXT: [[L1530:%.*]] = extractelement <16 x i8> [[TMP2]], i64 5
+; SM90-NEXT: [[L1631:%.*]] = extractelement <16 x i8> [[TMP2]], i64 6
+; SM90-NEXT: [[L1732:%.*]] = extractelement <16 x i8> [[TMP2]], i64 7
+; SM90-NEXT: [[L1833:%.*]] = extractelement <16 x i8> [[TMP2]], i64 8
+; SM90-NEXT: [[L1934:%.*]] = extractelement <16 x i8> [[TMP2]], i64 9
+; SM90-NEXT: [[L1A35:%.*]] = extractelement <16 x i8> [[TMP2]], i64 10
+; SM90-NEXT: [[L1B36:%.*]] = extractelement <16 x i8> [[TMP2]], i64 11
+; SM90-NEXT: [[L1C37:%.*]] = extractelement <16 x i8> [[TMP2]], i64 12
+; SM90-NEXT: [[L1D38:%.*]] = extractelement <16 x i8> [[TMP2]], i64 13
+; SM90-NEXT: [[L1E39:%.*]] = extractelement <16 x i8> [[TMP2]], i64 14
+; SM90-NEXT: [[L1F40:%.*]] = extractelement <16 x i8> [[TMP2]], i64 15
+; SM90-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> poison, i8 [[LB20]], i64 0
+; SM90-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> [[TMP3]], i8 [[LA19]], i64 1
+; SM90-NEXT: [[TMP5:%.*]] = insertelement <16 x i8> [[TMP4]], i8 [[L918]], i64 2
+; SM90-NEXT: [[TMP6:%.*]] = insertelement <16 x i8> [[TMP5]], i8 [[L817]], i64 3
+; SM90-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[TMP6]], i8 [[L716]], i64 4
+; SM90-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 [[L615]], i64 5
+; SM90-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 [[L514]], i64 6
+; SM90-NEXT: [[TMP10:%.*]] = insertelement <16 x i8> [[TMP9]], i8 [[L413]], i64 7
+; SM90-NEXT: [[TMP11:%.*]] = insertelement <16 x i8> [[TMP10]], i8 [[L312]], i64 8
+; SM90-NEXT: [[TMP12:%.*]] = insertelement <16 x i8> [[TMP11]], i8 [[L211]], i64 9
+; SM90-NEXT: [[TMP13:%.*]] = insertelement <16 x i8> [[TMP12]], i8 [[L110]], i64 10
+; SM90-NEXT: [[TMP14:%.*]] = insertelement <16 x i8> [[TMP13]], i8 [[L01]], i64 11
+; SM90-NEXT: [[TMP15:%.*]] = insertelement <16 x i8> [[TMP14]], i8 [[LF24]], i64 12
+; SM90-NEXT: [[TMP16:%.*]] = insertelement <16 x i8> [[TMP15]], i8 [[LE23]], i64 13
+; SM90-NEXT: [[TMP17:%.*]] = insertelement <16 x i8> [[TMP16]], i8 [[LD22]], i64 14
+; SM90-NEXT: [[TMP18:%.*]] = insertelement <16 x i8> [[TMP17]], i8 [[LC21]], i64 15
; SM90-NEXT: store <16 x i8> [[TMP18]], ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[TMP19:%.*]] = insertelement <16 x i8> poison, i8 [[L1B36]], i32 0
-; SM90-NEXT: [[TMP20:%.*]] = insertelement <16 x i8> [[TMP19]], i8 [[L1A35]], i32 1
-; SM90-NEXT: [[TMP21:%.*]] = insertelement <16 x i8> [[TMP20]], i8 [[L1934]], i32 2
-; SM90-NEXT: [[TMP22:%.*]] = insertelement <16 x i8> [[TMP21]], i8 [[L1833]], i32 3
-; SM90-NEXT: [[TMP23:%.*]] = insertelement <16 x i8> [[TMP22]], i8 [[L1732]], i32 4
-; SM90-NEXT: [[TMP24:%.*]] = insertelement <16 x i8> [[TMP23]], i8 [[L1631]], i32 5
-; SM90-NEXT: [[TMP25:%.*]] = insertelement <16 x i8> [[TMP24]], i8 [[L1530]], i32 6
-; SM90-NEXT: [[TMP26:%.*]] = insertelement <16 x i8> [[TMP25]], i8 [[L1429]], i32 7
-; SM90-NEXT: [[TMP27:%.*]] = insertelement <16 x i8> [[TMP26]], i8 [[L1328]], i32 8
-; SM90-NEXT: [[TMP28:%.*]] = insertelement <16 x i8> [[TMP27]], i8 [[L1227]], i32 9
-; SM90-NEXT: [[TMP29:%.*]] = insertelement <16 x i8> [[TMP28]], i8 [[L1126]], i32 10
-; SM90-NEXT: [[TMP30:%.*]] = insertelement <16 x i8> [[TMP29]], i8 [[L1025]], i32 11
-; SM90-NEXT: [[TMP31:%.*]] = insertelement <16 x i8> [[TMP30]], i8 [[L1F40]], i32 12
-; SM90-NEXT: [[TMP32:%.*]] = insertelement <16 x i8> [[TMP31]], i8 [[L1E39]], i32 13
-; SM90-NEXT: [[TMP33:%.*]] = insertelement <16 x i8> [[TMP32]], i8 [[L1D38]], i32 14
-; SM90-NEXT: [[TMP34:%.*]] = insertelement <16 x i8> [[TMP33]], i8 [[L1C37]], i32 15
+; SM90-NEXT: [[TMP19:%.*]] = insertelement <16 x i8> poison, i8 [[L1B36]], i64 0
+; SM90-NEXT: [[TMP20:%.*]] = insertelement <16 x i8> [[TMP19]], i8 [[L1A35]], i64 1
+; SM90-NEXT: [[TMP21:%.*]] = insertelement <16 x i8> [[TMP20]], i8 [[L1934]], i64 2
+; SM90-NEXT: [[TMP22:%.*]] = insertelement <16 x i8> [[TMP21]], i8 [[L1833]], i64 3
+; SM90-NEXT: [[TMP23:%.*]] = insertelement <16 x i8> [[TMP22]], i8 [[L1732]], i64 4
+; SM90-NEXT: [[TMP24:%.*]] = insertelement <16 x i8> [[TMP23]], i8 [[L1631]], i64 5
+; SM90-NEXT: [[TMP25:%.*]] = insertelement <16 x i8> [[TMP24]], i8 [[L1530]], i64 6
+; SM90-NEXT: [[TMP26:%.*]] = insertelement <16 x i8> [[TMP25]], i8 [[L1429]], i64 7
+; SM90-NEXT: [[TMP27:%.*]] = insertelement <16 x i8> [[TMP26]], i8 [[L1328]], i64 8
+; SM90-NEXT: [[TMP28:%.*]] = insertelement <16 x i8> [[TMP27]], i8 [[L1227]], i64 9
+; SM90-NEXT: [[TMP29:%.*]] = insertelement <16 x i8> [[TMP28]], i8 [[L1126]], i64 10
+; SM90-NEXT: [[TMP30:%.*]] = insertelement <16 x i8> [[TMP29]], i8 [[L1025]], i64 11
+; SM90-NEXT: [[TMP31:%.*]] = insertelement <16 x i8> [[TMP30]], i8 [[L1F40]], i64 12
+; SM90-NEXT: [[TMP32:%.*]] = insertelement <16 x i8> [[TMP31]], i8 [[L1E39]], i64 13
+; SM90-NEXT: [[TMP33:%.*]] = insertelement <16 x i8> [[TMP32]], i8 [[L1D38]], i64 14
+; SM90-NEXT: [[TMP34:%.*]] = insertelement <16 x i8> [[TMP33]], i8 [[L1C37]], i64 15
; SM90-NEXT: store <16 x i8> [[TMP34]], ptr addrspace(1) [[PTR10]], align 16
; SM90-NEXT: ret void
;
@@ -95,70 +95,70 @@ define void @int8x32(ptr addrspace(1) %ptr) {
; SM100-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
; SM100-NEXT: [[PTR0:%.*]] = getelementptr i8, ptr addrspace(1) [[PTR]], i64 0
; SM100-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr addrspace(1) [[PTR0]], align 32
-; SM100-NEXT: [[L01:%.*]] = extractelement <32 x i8> [[TMP1]], i32 0
-; SM100-NEXT: [[L110:%.*]] = extractelement <32 x i8> [[TMP1]], i32 1
-; SM100-NEXT: [[L211:%.*]] = extractelement <32 x i8> [[TMP1]], i32 2
-; SM100-NEXT: [[L312:%.*]] = extractelement <32 x i8> [[TMP1]], i32 3
-; SM100-NEXT: [[L413:%.*]] = extractelement <32 x i8> [[TMP1]], i32 4
-; SM100-NEXT: [[L514:%.*]] = extractelement <32 x i8> [[TMP1]], i32 5
-; SM100-NEXT: [[L615:%.*]] = extractelement <32 x i8> [[TMP1]], i32 6
-; SM100-NEXT: [[L716:%.*]] = extractelement <32 x i8> [[TMP1]], i32 7
-; SM100-NEXT: [[L817:%.*]] = extractelement <32 x i8> [[TMP1]], i32 8
-; SM100-NEXT: [[L918:%.*]] = extractelement <32 x i8> [[TMP1]], i32 9
-; SM100-NEXT: [[LA19:%.*]] = extractelement <32 x i8> [[TMP1]], i32 10
-; SM100-NEXT: [[LB20:%.*]] = extractelement <32 x i8> [[TMP1]], i32 11
-; SM100-NEXT: [[LC21:%.*]] = extractelement <32 x i8> [[TMP1]], i32 12
-; SM100-NEXT: [[LD22:%.*]] = extractelement <32 x i8> [[TMP1]], i32 13
-; SM100-NEXT: [[LE23:%.*]] = extractelement <32 x i8> [[TMP1]], i32 14
-; SM100-NEXT: [[LF24:%.*]] = extractelement <32 x i8> [[TMP1]], i32 15
-; SM100-NEXT: [[L1025:%.*]] = extractelement <32 x i8> [[TMP1]], i32 16
-; SM100-NEXT: [[L1126:%.*]] = extractelement <32 x i8> [[TMP1]], i32 17
-; SM100-NEXT: [[L1227:%.*]] = extractelement <32 x i8> [[TMP1]], i32 18
-; SM100-NEXT: [[L1328:%.*]] = extractelement <32 x i8> [[TMP1]], i32 19
-; SM100-NEXT: [[L1429:%.*]] = extractelement <32 x i8> [[TMP1]], i32 20
-; SM100-NEXT: [[L1530:%.*]] = extractelement <32 x i8> [[TMP1]], i32 21
-; SM100-NEXT: [[L1631:%.*]] = extractelement <32 x i8> [[TMP1]], i32 22
-; SM100-NEXT: [[L1732:%.*]] = extractelement <32 x i8> [[TMP1]], i32 23
-; SM100-NEXT: [[L1833:%.*]] = extractelement <32 x i8> [[TMP1]], i32 24
-; SM100-NEXT: [[L1934:%.*]] = extractelement <32 x i8> [[TMP1]], i32 25
-; SM100-NEXT: [[L1A35:%.*]] = extractelement <32 x i8> [[TMP1]], i32 26
-; SM100-NEXT: [[L1B36:%.*]] = extractelement <32 x i8> [[TMP1]], i32 27
-; SM100-NEXT: [[L1C37:%.*]] = extractelement <32 x i8> [[TMP1]], i32 28
-; SM100-NEXT: [[L1D38:%.*]] = extractelement <32 x i8> [[TMP1]], i32 29
-; SM100-NEXT: [[L1E39:%.*]] = extractelement <32 x i8> [[TMP1]], i32 30
-; SM100-NEXT: [[L1F40:%.*]] = extractelement <32 x i8> [[TMP1]], i32 31
-; SM100-NEXT: [[TMP2:%.*]] = insertelement <32 x i8> poison, i8 [[LB20]], i32 0
-; SM100-NEXT: [[TMP3:%.*]] = insertelement <32 x i8> [[TMP2]], i8 [[LA19]], i32 1
-; SM100-NEXT: [[TMP4:%.*]] = insertelement <32 x i8> [[TMP3]], i8 [[L918]], i32 2
-; SM100-NEXT: [[TMP5:%.*]] = insertelement <32 x i8> [[TMP4]], i8 [[L817]], i32 3
-; SM100-NEXT: [[TMP6:%.*]] = insertelement <32 x i8> [[TMP5]], i8 [[L716]], i32 4
-; SM100-NEXT: [[TMP7:%.*]] = insertelement <32 x i8> [[TMP6]], i8 [[L615]], i32 5
-; SM100-NEXT: [[TMP8:%.*]] = insertelement <32 x i8> [[TMP7]], i8 [[L514]], i32 6
-; SM100-NEXT: [[TMP9:%.*]] = insertelement <32 x i8> [[TMP8]], i8 [[L413]], i32 7
-; SM100-NEXT: [[TMP10:%.*]] = insertelement <32 x i8> [[TMP9]], i8 [[L312]], i32 8
-; SM100-NEXT: [[TMP11:%.*]] = insertelement <32 x i8> [[TMP10]], i8 [[L211]], i32 9
-; SM100-NEXT: [[TMP12:%.*]] = insertelement <32 x i8> [[TMP11]], i8 [[L110]], i32 10
-; SM100-NEXT: [[TMP13:%.*]] = insertelement <32 x i8> [[TMP12]], i8 [[L01]], i32 11
-; SM100-NEXT: [[TMP14:%.*]] = insertelement <32 x i8> [[TMP13]], i8 [[LF24]], i32 12
-; SM100-NEXT: [[TMP15:%.*]] = insertelement <32 x i8> [[TMP14]], i8 [[LE23]], i32 13
-; SM100-NEXT: [[TMP16:%.*]] = insertelement <32 x i8> [[TMP15]], i8 [[LD22]], i32 14
-; SM100-NEXT: [[TMP17:%.*]] = insertelement <32 x i8> [[TMP16]], i8 [[LC21]], i32 15
-; SM100-NEXT: [[TMP18:%.*]] = insertelement <32 x i8> [[TMP17]], i8 [[L1B36]], i32 16
-; SM100-NEXT: [[TMP19:%.*]] = insertelement <32 x i8> [[TMP18]], i8 [[L1A35]], i32 17
-; SM100-NEXT: [[TMP20:%.*]] = insertelement <32 x i8> [[TMP19]], i8 [[L1934]], i32 18
-; SM100-NEXT: [[TMP21:%.*]] = insertelement <32 x i8> [[TMP20]], i8 [[L1833]], i32 19
-; SM100-NEXT: [[TMP22:%.*]] = insertelement <32 x i8> [[TMP21]], i8 [[L1732]], i32 20
-; SM100-NEXT: [[TMP23:%.*]] = insertelement <32 x i8> [[TMP22]], i8 [[L1631]], i32 21
-; SM100-NEXT: [[TMP24:%.*]] = insertelement <32 x i8> [[TMP23]], i8 [[L1530]], i32 22
-; SM100-NEXT: [[TMP25:%.*]] = insertelement <32 x i8> [[TMP24]], i8 [[L1429]], i32 23
-; SM100-NEXT: [[TMP26:%.*]] = insertelement <32 x i8> [[TMP25]], i8 [[L1328]], i32 24
-; SM100-NEXT: [[TMP27:%.*]] = insertelement <32 x i8> [[TMP26]], i8 [[L1227]], i32 25
-; SM100-NEXT: [[TMP28:%.*]] = insertelement <32 x i8> [[TMP27]], i8 [[L1126]], i32 26
-; SM100-NEXT: [[TMP29:%.*]] = insertelement <32 x i8> [[TMP28]], i8 [[L1025]], i32 27
-; SM100-NEXT: [[TMP30:%.*]] = insertelement <32 x i8> [[TMP29]], i8 [[L1F40]], i32 28
-; SM100-NEXT: [[TMP31:%.*]] = insertelement <32 x i8> [[TMP30]], i8 [[L1E39]], i32 29
-; SM100-NEXT: [[TMP32:%.*]] = insertelement <32 x i8> [[TMP31]], i8 [[L1D38]], i32 30
-; SM100-NEXT: [[TMP33:%.*]] = insertelement <32 x i8> [[TMP32]], i8 [[L1C37]], i32 31
+; SM100-NEXT: [[L01:%.*]] = extractelement <32 x i8> [[TMP1]], i64 0
+; SM100-NEXT: [[L110:%.*]] = extractelement <32 x i8> [[TMP1]], i64 1
+; SM100-NEXT: [[L211:%.*]] = extractelement <32 x i8> [[TMP1]], i64 2
+; SM100-NEXT: [[L312:%.*]] = extractelement <32 x i8> [[TMP1]], i64 3
+; SM100-NEXT: [[L413:%.*]] = extractelement <32 x i8> [[TMP1]], i64 4
+; SM100-NEXT: [[L514:%.*]] = extractelement <32 x i8> [[TMP1]], i64 5
+; SM100-NEXT: [[L615:%.*]] = extractelement <32 x i8> [[TMP1]], i64 6
+; SM100-NEXT: [[L716:%.*]] = extractelement <32 x i8> [[TMP1]], i64 7
+; SM100-NEXT: [[L817:%.*]] = extractelement <32 x i8> [[TMP1]], i64 8
+; SM100-NEXT: [[L918:%.*]] = extractelement <32 x i8> [[TMP1]], i64 9
+; SM100-NEXT: [[LA19:%.*]] = extractelement <32 x i8> [[TMP1]], i64 10
+; SM100-NEXT: [[LB20:%.*]] = extractelement <32 x i8> [[TMP1]], i64 11
+; SM100-NEXT: [[LC21:%.*]] = extractelement <32 x i8> [[TMP1]], i64 12
+; SM100-NEXT: [[LD22:%.*]] = extractelement <32 x i8> [[TMP1]], i64 13
+; SM100-NEXT: [[LE23:%.*]] = extractelement <32 x i8> [[TMP1]], i64 14
+; SM100-NEXT: [[LF24:%.*]] = extractelement <32 x i8> [[TMP1]], i64 15
+; SM100-NEXT: [[L1025:%.*]] = extractelement <32 x i8> [[TMP1]], i64 16
+; SM100-NEXT: [[L1126:%.*]] = extractelement <32 x i8> [[TMP1]], i64 17
+; SM100-NEXT: [[L1227:%.*]] = extractelement <32 x i8> [[TMP1]], i64 18
+; SM100-NEXT: [[L1328:%.*]] = extractelement <32 x i8> [[TMP1]], i64 19
+; SM100-NEXT: [[L1429:%.*]] = extractelement <32 x i8> [[TMP1]], i64 20
+; SM100-NEXT: [[L1530:%.*]] = extractelement <32 x i8> [[TMP1]], i64 21
+; SM100-NEXT: [[L1631:%.*]] = extractelement <32 x i8> [[TMP1]], i64 22
+; SM100-NEXT: [[L1732:%.*]] = extractelement <32 x i8> [[TMP1]], i64 23
+; SM100-NEXT: [[L1833:%.*]] = extractelement <32 x i8> [[TMP1]], i64 24
+; SM100-NEXT: [[L1934:%.*]] = extractelement <32 x i8> [[TMP1]], i64 25
+; SM100-NEXT: [[L1A35:%.*]] = extractelement <32 x i8> [[TMP1]], i64 26
+; SM100-NEXT: [[L1B36:%.*]] = extractelement <32 x i8> [[TMP1]], i64 27
+; SM100-NEXT: [[L1C37:%.*]] = extractelement <32 x i8> [[TMP1]], i64 28
+; SM100-NEXT: [[L1D38:%.*]] = extractelement <32 x i8> [[TMP1]], i64 29
+; SM100-NEXT: [[L1E39:%.*]] = extractelement <32 x i8> [[TMP1]], i64 30
+; SM100-NEXT: [[L1F40:%.*]] = extractelement <32 x i8> [[TMP1]], i64 31
+; SM100-NEXT: [[TMP2:%.*]] = insertelement <32 x i8> poison, i8 [[LB20]], i64 0
+; SM100-NEXT: [[TMP3:%.*]] = insertelement <32 x i8> [[TMP2]], i8 [[LA19]], i64 1
+; SM100-NEXT: [[TMP4:%.*]] = insertelement <32 x i8> [[TMP3]], i8 [[L918]], i64 2
+; SM100-NEXT: [[TMP5:%.*]] = insertelement <32 x i8> [[TMP4]], i8 [[L817]], i64 3
+; SM100-NEXT: [[TMP6:%.*]] = insertelement <32 x i8> [[TMP5]], i8 [[L716]], i64 4
+; SM100-NEXT: [[TMP7:%.*]] = insertelement <32 x i8> [[TMP6]], i8 [[L615]], i64 5
+; SM100-NEXT: [[TMP8:%.*]] = insertelement <32 x i8> [[TMP7]], i8 [[L514]], i64 6
+; SM100-NEXT: [[TMP9:%.*]] = insertelement <32 x i8> [[TMP8]], i8 [[L413]], i64 7
+; SM100-NEXT: [[TMP10:%.*]] = insertelement <32 x i8> [[TMP9]], i8 [[L312]], i64 8
+; SM100-NEXT: [[TMP11:%.*]] = insertelement <32 x i8> [[TMP10]], i8 [[L211]], i64 9
+; SM100-NEXT: [[TMP12:%.*]] = insertelement <32 x i8> [[TMP11]], i8 [[L110]], i64 10
+; SM100-NEXT: [[TMP13:%.*]] = insertelement <32 x i8> [[TMP12]], i8 [[L01]], i64 11
+; SM100-NEXT: [[TMP14:%.*]] = insertelement <32 x i8> [[TMP13]], i8 [[LF24]], i64 12
+; SM100-NEXT: [[TMP15:%.*]] = insertelement <32 x i8> [[TMP14]], i8 [[LE23]], i64 13
+; SM100-NEXT: [[TMP16:%.*]] = insertelement <32 x i8> [[TMP15]], i8 [[LD22]], i64 14
+; SM100-NEXT: [[TMP17:%.*]] = insertelement <32 x i8> [[TMP16]], i8 [[LC21]], i64 15
+; SM100-NEXT: [[TMP18:%.*]] = insertelement <32 x i8> [[TMP17]], i8 [[L1B36]], i64 16
+; SM100-NEXT: [[TMP19:%.*]] = insertelement <32 x i8> [[TMP18]], i8 [[L1A35]], i64 17
+; SM100-NEXT: [[TMP20:%.*]] = insertelement <32 x i8> [[TMP19]], i8 [[L1934]], i64 18
+; SM100-NEXT: [[TMP21:%.*]] = insertelement <32 x i8> [[TMP20]], i8 [[L1833]], i64 19
+; SM100-NEXT: [[TMP22:%.*]] = insertelement <32 x i8> [[TMP21]], i8 [[L1732]], i64 20
+; SM100-NEXT: [[TMP23:%.*]] = insertelement <32 x i8> [[TMP22]], i8 [[L1631]], i64 21
+; SM100-NEXT: [[TMP24:%.*]] = insertelement <32 x i8> [[TMP23]], i8 [[L1530]], i64 22
+; SM100-NEXT: [[TMP25:%.*]] = insertelement <32 x i8> [[TMP24]], i8 [[L1429]], i64 23
+; SM100-NEXT: [[TMP26:%.*]] = insertelement <32 x i8> [[TMP25]], i8 [[L1328]], i64 24
+; SM100-NEXT: [[TMP27:%.*]] = insertelement <32 x i8> [[TMP26]], i8 [[L1227]], i64 25
+; SM100-NEXT: [[TMP28:%.*]] = insertelement <32 x i8> [[TMP27]], i8 [[L1126]], i64 26
+; SM100-NEXT: [[TMP29:%.*]] = insertelement <32 x i8> [[TMP28]], i8 [[L1025]], i64 27
+; SM100-NEXT: [[TMP30:%.*]] = insertelement <32 x i8> [[TMP29]], i8 [[L1F40]], i64 28
+; SM100-NEXT: [[TMP31:%.*]] = insertelement <32 x i8> [[TMP30]], i8 [[L1E39]], i64 29
+; SM100-NEXT: [[TMP32:%.*]] = insertelement <32 x i8> [[TMP31]], i8 [[L1D38]], i64 30
+; SM100-NEXT: [[TMP33:%.*]] = insertelement <32 x i8> [[TMP32]], i8 [[L1C37]], i64 31
; SM100-NEXT: store <32 x i8> [[TMP33]], ptr addrspace(1) [[PTR0]], align 32
; SM100-NEXT: ret void
;
@@ -271,40 +271,40 @@ define void @int16x16(ptr addrspace(1) %ptr) {
; SM90-NEXT: [[PTR0:%.*]] = getelementptr i16, ptr addrspace(1) [[PTR]], i64 0
; SM90-NEXT: [[PTR8:%.*]] = getelementptr i16, ptr addrspace(1) [[PTR]], i64 8
; SM90-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[L01:%.*]] = extractelement <8 x i16> [[TMP1]], i32 0
-; SM90-NEXT: [[L12:%.*]] = extractelement <8 x i16> [[TMP1]], i32 1
-; SM90-NEXT: [[L23:%.*]] = extractelement <8 x i16> [[TMP1]], i32 2
-; SM90-NEXT: [[L34:%.*]] = extractelement <8 x i16> [[TMP1]], i32 3
-; SM90-NEXT: [[L45:%.*]] = extractelement <8 x i16> [[TMP1]], i32 4
-; SM90-NEXT: [[L56:%.*]] = extractelement <8 x i16> [[TMP1]], i32 5
-; SM90-NEXT: [[L67:%.*]] = extractelement <8 x i16> [[TMP1]], i32 6
-; SM90-NEXT: [[L78:%.*]] = extractelement <8 x i16> [[TMP1]], i32 7
+; SM90-NEXT: [[L01:%.*]] = extractelement <8 x i16> [[TMP1]], i64 0
+; SM90-NEXT: [[L12:%.*]] = extractelement <8 x i16> [[TMP1]], i64 1
+; SM90-NEXT: [[L23:%.*]] = extractelement <8 x i16> [[TMP1]], i64 2
+; SM90-NEXT: [[L34:%.*]] = extractelement <8 x i16> [[TMP1]], i64 3
+; SM90-NEXT: [[L45:%.*]] = extractelement <8 x i16> [[TMP1]], i64 4
+; SM90-NEXT: [[L56:%.*]] = extractelement <8 x i16> [[TMP1]], i64 5
+; SM90-NEXT: [[L67:%.*]] = extractelement <8 x i16> [[TMP1]], i64 6
+; SM90-NEXT: [[L78:%.*]] = extractelement <8 x i16> [[TMP1]], i64 7
; SM90-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr addrspace(1) [[PTR8]], align 16
-; SM90-NEXT: [[L89:%.*]] = extractelement <8 x i16> [[TMP2]], i32 0
-; SM90-NEXT: [[L910:%.*]] = extractelement <8 x i16> [[TMP2]], i32 1
-; SM90-NEXT: [[LA11:%.*]] = extractelement <8 x i16> [[TMP2]], i32 2
-; SM90-NEXT: [[LB12:%.*]] = extractelement <8 x i16> [[TMP2]], i32 3
-; SM90-NEXT: [[LC13:%.*]] = extractelement <8 x i16> [[TMP2]], i32 4
-; SM90-NEXT: [[LD14:%.*]] = extractelement <8 x i16> [[TMP2]], i32 5
-; SM90-NEXT: [[LE15:%.*]] = extractelement <8 x i16> [[TMP2]], i32 6
-; SM90-NEXT: [[LF16:%.*]] = extractelement <8 x i16> [[TMP2]], i32 7
-; SM90-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> poison, i16 [[LB12]], i32 0
-; SM90-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[LA11]], i32 1
-; SM90-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[L910]], i32 2
-; SM90-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[L89]], i32 3
-; SM90-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[L78]], i32 4
-; SM90-NEXT: [[TMP8:%.*]] = insertelement <8 x i16> [[TMP7]], i16 [[L67]], i32 5
-; SM90-NEXT: [[TMP9:%.*]] = insertelement <8 x i16> [[TMP8]], i16 [[L56]], i32 6
-; SM90-NEXT: [[TMP10:%.*]] = insertelement <8 x i16> [[TMP9]], i16 [[L45]], i32 7
+; SM90-NEXT: [[L89:%.*]] = extractelement <8 x i16> [[TMP2]], i64 0
+; SM90-NEXT: [[L910:%.*]] = extractelement <8 x i16> [[TMP2]], i64 1
+; SM90-NEXT: [[LA11:%.*]] = extractelement <8 x i16> [[TMP2]], i64 2
+; SM90-NEXT: [[LB12:%.*]] = extractelement <8 x i16> [[TMP2]], i64 3
+; SM90-NEXT: [[LC13:%.*]] = extractelement <8 x i16> [[TMP2]], i64 4
+; SM90-NEXT: [[LD14:%.*]] = extractelement <8 x i16> [[TMP2]], i64 5
+; SM90-NEXT: [[LE15:%.*]] = extractelement <8 x i16> [[TMP2]], i64 6
+; SM90-NEXT: [[LF16:%.*]] = extractelement <8 x i16> [[TMP2]], i64 7
+; SM90-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> poison, i16 [[LB12]], i64 0
+; SM90-NEXT: [[TMP4:%.*]] = insertelement <8 x i16> [[TMP3]], i16 [[LA11]], i64 1
+; SM90-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[L910]], i64 2
+; SM90-NEXT: [[TMP6:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[L89]], i64 3
+; SM90-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP6]], i16 [[L78]], i64 4
+; SM90-NEXT: [[TMP8:%.*]] = insertelement <8 x i16> [[TMP7]], i16 [[L67]], i64 5
+; SM90-NEXT: [[TMP9:%.*]] = insertelement <8 x i16> [[TMP8]], i16 [[L56]], i64 6
+; SM90-NEXT: [[TMP10:%.*]] = insertelement <8 x i16> [[TMP9]], i16 [[L45]], i64 7
; SM90-NEXT: store <8 x i16> [[TMP10]], ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[TMP11:%.*]] = insertelement <8 x i16> poison, i16 [[L34]], i32 0
-; SM90-NEXT: [[TMP12:%.*]] = insertelement <8 x i16> [[TMP11]], i16 [[L23]], i32 1
-; SM90-NEXT: [[TMP13:%.*]] = insertelement <8 x i16> [[TMP12]], i16 [[L12]], i32 2
-; SM90-NEXT: [[TMP14:%.*]] = insertelement <8 x i16> [[TMP13]], i16 [[L01]], i32 3
-; SM90-NEXT: [[TMP15:%.*]] = insertelement <8 x i16> [[TMP14]], i16 [[LF16]], i32 4
-; SM90-NEXT: [[TMP16:%.*]] = insertelement <8 x i16> [[TMP15]], i16 [[LE15]], i32 5
-; SM90-NEXT: [[TMP17:%.*]] = insertelement <8 x i16> [[TMP16]], i16 [[LD14]], i32 6
-; SM90-NEXT: [[TMP18:%.*]] = insertelement <8 x i16> [[TMP17]], i16 [[LC13]], i32 7
+; SM90-NEXT: [[TMP11:%.*]] = insertelement <8 x i16> poison, i16 [[L34]], i64 0
+; SM90-NEXT: [[TMP12:%.*]] = insertelement <8 x i16> [[TMP11]], i16 [[L23]], i64 1
+; SM90-NEXT: [[TMP13:%.*]] = insertelement <8 x i16> [[TMP12]], i16 [[L12]], i64 2
+; SM90-NEXT: [[TMP14:%.*]] = insertelement <8 x i16> [[TMP13]], i16 [[L01]], i64 3
+; SM90-NEXT: [[TMP15:%.*]] = insertelement <8 x i16> [[TMP14]], i16 [[LF16]], i64 4
+; SM90-NEXT: [[TMP16:%.*]] = insertelement <8 x i16> [[TMP15]], i16 [[LE15]], i64 5
+; SM90-NEXT: [[TMP17:%.*]] = insertelement <8 x i16> [[TMP16]], i16 [[LD14]], i64 6
+; SM90-NEXT: [[TMP18:%.*]] = insertelement <8 x i16> [[TMP17]], i16 [[LC13]], i64 7
; SM90-NEXT: store <8 x i16> [[TMP18]], ptr addrspace(1) [[PTR8]], align 16
; SM90-NEXT: ret void
;
@@ -312,38 +312,38 @@ define void @int16x16(ptr addrspace(1) %ptr) {
; SM100-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
; SM100-NEXT: [[PTR0:%.*]] = getelementptr i16, ptr addrspace(1) [[PTR]], i64 0
; SM100-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr addrspace(1) [[PTR0]], align 32
-; SM100-NEXT: [[L01:%.*]] = extractelement <16 x i16> [[TMP1]], i32 0
-; SM100-NEXT: [[L12:%.*]] = extractelement <16 x i16> [[TMP1]], i32 1
-; SM100-NEXT: [[L23:%.*]] = extractelement <16 x i16> [[TMP1]], i32 2
-; SM100-NEXT: [[L34:%.*]] = extractelement <16 x i16> [[TMP1]], i32 3
-; SM100-NEXT: [[L45:%.*]] = extractelement <16 x i16> [[TMP1]], i32 4
-; SM100-NEXT: [[L56:%.*]] = extractelement <16 x i16> [[TMP1]], i32 5
-; SM100-NEXT: [[L67:%.*]] = extractelement <16 x i16> [[TMP1]], i32 6
-; SM100-NEXT: [[L78:%.*]] = extractelement <16 x i16> [[TMP1]], i32 7
-; SM100-NEXT: [[L89:%.*]] = extractelement <16 x i16> [[TMP1]], i32 8
-; SM100-NEXT: [[L910:%.*]] = extractelement <16 x i16> [[TMP1]], i32 9
-; SM100-NEXT: [[LA11:%.*]] = extractelement <16 x i16> [[TMP1]], i32 10
-; SM100-NEXT: [[LB12:%.*]] = extractelement <16 x i16> [[TMP1]], i32 11
-; SM100-NEXT: [[LC13:%.*]] = extractelement <16 x i16> [[TMP1]], i32 12
-; SM100-NEXT: [[LD14:%.*]] = extractelement <16 x i16> [[TMP1]], i32 13
-; SM100-NEXT: [[LE15:%.*]] = extractelement <16 x i16> [[TMP1]], i32 14
-; SM100-NEXT: [[LF16:%.*]] = extractelement <16 x i16> [[TMP1]], i32 15
-; SM100-NEXT: [[TMP2:%.*]] = insertelement <16 x i16> poison, i16 [[LB12]], i32 0
-; SM100-NEXT: [[TMP3:%.*]] = insertelement <16 x i16> [[TMP2]], i16 [[LA11]], i32 1
-; SM100-NEXT: [[TMP4:%.*]] = insertelement <16 x i16> [[TMP3]], i16 [[L910]], i32 2
-; SM100-NEXT: [[TMP5:%.*]] = insertelement <16 x i16> [[TMP4]], i16 [[L89]], i32 3
-; SM100-NEXT: [[TMP6:%.*]] = insertelement <16 x i16> [[TMP5]], i16 [[L78]], i32 4
-; SM100-NEXT: [[TMP7:%.*]] = insertelement <16 x i16> [[TMP6]], i16 [[L67]], i32 5
-; SM100-NEXT: [[TMP8:%.*]] = insertelement <16 x i16> [[TMP7]], i16 [[L56]], i32 6
-; SM100-NEXT: [[TMP9:%.*]] = insertelement <16 x i16> [[TMP8]], i16 [[L45]], i32 7
-; SM100-NEXT: [[TMP10:%.*]] = insertelement <16 x i16> [[TMP9]], i16 [[L34]], i32 8
-; SM100-NEXT: [[TMP11:%.*]] = insertelement <16 x i16> [[TMP10]], i16 [[L23]], i32 9
-; SM100-NEXT: [[TMP12:%.*]] = insertelement <16 x i16> [[TMP11]], i16 [[L12]], i32 10
-; SM100-NEXT: [[TMP13:%.*]] = insertelement <16 x i16> [[TMP12]], i16 [[L01]], i32 11
-; SM100-NEXT: [[TMP14:%.*]] = insertelement <16 x i16> [[TMP13]], i16 [[LF16]], i32 12
-; SM100-NEXT: [[TMP15:%.*]] = insertelement <16 x i16> [[TMP14]], i16 [[LE15]], i32 13
-; SM100-NEXT: [[TMP16:%.*]] = insertelement <16 x i16> [[TMP15]], i16 [[LD14]], i32 14
-; SM100-NEXT: [[TMP17:%.*]] = insertelement <16 x i16> [[TMP16]], i16 [[LC13]], i32 15
+; SM100-NEXT: [[L01:%.*]] = extractelement <16 x i16> [[TMP1]], i64 0
+; SM100-NEXT: [[L12:%.*]] = extractelement <16 x i16> [[TMP1]], i64 1
+; SM100-NEXT: [[L23:%.*]] = extractelement <16 x i16> [[TMP1]], i64 2
+; SM100-NEXT: [[L34:%.*]] = extractelement <16 x i16> [[TMP1]], i64 3
+; SM100-NEXT: [[L45:%.*]] = extractelement <16 x i16> [[TMP1]], i64 4
+; SM100-NEXT: [[L56:%.*]] = extractelement <16 x i16> [[TMP1]], i64 5
+; SM100-NEXT: [[L67:%.*]] = extractelement <16 x i16> [[TMP1]], i64 6
+; SM100-NEXT: [[L78:%.*]] = extractelement <16 x i16> [[TMP1]], i64 7
+; SM100-NEXT: [[L89:%.*]] = extractelement <16 x i16> [[TMP1]], i64 8
+; SM100-NEXT: [[L910:%.*]] = extractelement <16 x i16> [[TMP1]], i64 9
+; SM100-NEXT: [[LA11:%.*]] = extractelement <16 x i16> [[TMP1]], i64 10
+; SM100-NEXT: [[LB12:%.*]] = extractelement <16 x i16> [[TMP1]], i64 11
+; SM100-NEXT: [[LC13:%.*]] = extractelement <16 x i16> [[TMP1]], i64 12
+; SM100-NEXT: [[LD14:%.*]] = extractelement <16 x i16> [[TMP1]], i64 13
+; SM100-NEXT: [[LE15:%.*]] = extractelement <16 x i16> [[TMP1]], i64 14
+; SM100-NEXT: [[LF16:%.*]] = extractelement <16 x i16> [[TMP1]], i64 15
+; SM100-NEXT: [[TMP2:%.*]] = insertelement <16 x i16> poison, i16 [[LB12]], i64 0
+; SM100-NEXT: [[TMP3:%.*]] = insertelement <16 x i16> [[TMP2]], i16 [[LA11]], i64 1
+; SM100-NEXT: [[TMP4:%.*]] = insertelement <16 x i16> [[TMP3]], i16 [[L910]], i64 2
+; SM100-NEXT: [[TMP5:%.*]] = insertelement <16 x i16> [[TMP4]], i16 [[L89]], i64 3
+; SM100-NEXT: [[TMP6:%.*]] = insertelement <16 x i16> [[TMP5]], i16 [[L78]], i64 4
+; SM100-NEXT: [[TMP7:%.*]] = insertelement <16 x i16> [[TMP6]], i16 [[L67]], i64 5
+; SM100-NEXT: [[TMP8:%.*]] = insertelement <16 x i16> [[TMP7]], i16 [[L56]], i64 6
+; SM100-NEXT: [[TMP9:%.*]] = insertelement <16 x i16> [[TMP8]], i16 [[L45]], i64 7
+; SM100-NEXT: [[TMP10:%.*]] = insertelement <16 x i16> [[TMP9]], i16 [[L34]], i64 8
+; SM100-NEXT: [[TMP11:%.*]] = insertelement <16 x i16> [[TMP10]], i16 [[L23]], i64 9
+; SM100-NEXT: [[TMP12:%.*]] = insertelement <16 x i16> [[TMP11]], i16 [[L12]], i64 10
+; SM100-NEXT: [[TMP13:%.*]] = insertelement <16 x i16> [[TMP12]], i16 [[L01]], i64 11
+; SM100-NEXT: [[TMP14:%.*]] = insertelement <16 x i16> [[TMP13]], i16 [[LF16]], i64 12
+; SM100-NEXT: [[TMP15:%.*]] = insertelement <16 x i16> [[TMP14]], i16 [[LE15]], i64 13
+; SM100-NEXT: [[TMP16:%.*]] = insertelement <16 x i16> [[TMP15]], i16 [[LD14]], i64 14
+; SM100-NEXT: [[TMP17:%.*]] = insertelement <16 x i16> [[TMP16]], i16 [[LC13]], i64 15
; SM100-NEXT: store <16 x i16> [[TMP17]], ptr addrspace(1) [[PTR0]], align 32
; SM100-NEXT: ret void
;
@@ -408,24 +408,24 @@ define void @int32x8(ptr addrspace(1) %ptr) {
; SM90-NEXT: [[PTR0:%.*]] = getelementptr i32, ptr addrspace(1) [[PTR]], i64 0
; SM90-NEXT: [[PTR4:%.*]] = getelementptr i32, ptr addrspace(1) [[PTR]], i64 4
; SM90-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[L01:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; SM90-NEXT: [[L12:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; SM90-NEXT: [[L23:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; SM90-NEXT: [[L34:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; SM90-NEXT: [[L01:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; SM90-NEXT: [[L12:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; SM90-NEXT: [[L23:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; SM90-NEXT: [[L34:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; SM90-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr addrspace(1) [[PTR4]], align 16
-; SM90-NEXT: [[L45:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
-; SM90-NEXT: [[L56:%.*]] = extractelement <4 x i32> [[TMP2]], i32 1
-; SM90-NEXT: [[L67:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2
-; SM90-NEXT: [[L78:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3
-; SM90-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> poison, i32 [[L78]], i32 0
-; SM90-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[L67]], i32 1
-; SM90-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[L56]], i32 2
-; SM90-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[L45]], i32 3
+; SM90-NEXT: [[L45:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0
+; SM90-NEXT: [[L56:%.*]] = extractelement <4 x i32> [[TMP2]], i64 1
+; SM90-NEXT: [[L67:%.*]] = extractelement <4 x i32> [[TMP2]], i64 2
+; SM90-NEXT: [[L78:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3
+; SM90-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> poison, i32 [[L78]], i64 0
+; SM90-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[L67]], i64 1
+; SM90-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[L56]], i64 2
+; SM90-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[L45]], i64 3
; SM90-NEXT: store <4 x i32> [[TMP6]], ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[L34]], i32 0
-; SM90-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[L23]], i32 1
-; SM90-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[L12]], i32 2
-; SM90-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[L01]], i32 3
+; SM90-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[L34]], i64 0
+; SM90-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[L23]], i64 1
+; SM90-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[L12]], i64 2
+; SM90-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[L01]], i64 3
; SM90-NEXT: store <4 x i32> [[TMP10]], ptr addrspace(1) [[PTR4]], align 16
; SM90-NEXT: ret void
;
@@ -433,22 +433,22 @@ define void @int32x8(ptr addrspace(1) %ptr) {
; SM100-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
; SM100-NEXT: [[PTR0:%.*]] = getelementptr i32, ptr addrspace(1) [[PTR]], i64 0
; SM100-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr addrspace(1) [[PTR0]], align 32
-; SM100-NEXT: [[L01:%.*]] = extractelement <8 x i32> [[TMP1]], i32 0
-; SM100-NEXT: [[L12:%.*]] = extractelement <8 x i32> [[TMP1]], i32 1
-; SM100-NEXT: [[L23:%.*]] = extractelement <8 x i32> [[TMP1]], i32 2
-; SM100-NEXT: [[L34:%.*]] = extractelement <8 x i32> [[TMP1]], i32 3
-; SM100-NEXT: [[L45:%.*]] = extractelement <8 x i32> [[TMP1]], i32 4
-; SM100-NEXT: [[L56:%.*]] = extractelement <8 x i32> [[TMP1]], i32 5
-; SM100-NEXT: [[L67:%.*]] = extractelement <8 x i32> [[TMP1]], i32 6
-; SM100-NEXT: [[L78:%.*]] = extractelement <8 x i32> [[TMP1]], i32 7
-; SM100-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[L78]], i32 0
-; SM100-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[L67]], i32 1
-; SM100-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[L56]], i32 2
-; SM100-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[L45]], i32 3
-; SM100-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[L34]], i32 4
-; SM100-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[L23]], i32 5
-; SM100-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[L12]], i32 6
-; SM100-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 [[L01]], i32 7
+; SM100-NEXT: [[L01:%.*]] = extractelement <8 x i32> [[TMP1]], i64 0
+; SM100-NEXT: [[L12:%.*]] = extractelement <8 x i32> [[TMP1]], i64 1
+; SM100-NEXT: [[L23:%.*]] = extractelement <8 x i32> [[TMP1]], i64 2
+; SM100-NEXT: [[L34:%.*]] = extractelement <8 x i32> [[TMP1]], i64 3
+; SM100-NEXT: [[L45:%.*]] = extractelement <8 x i32> [[TMP1]], i64 4
+; SM100-NEXT: [[L56:%.*]] = extractelement <8 x i32> [[TMP1]], i64 5
+; SM100-NEXT: [[L67:%.*]] = extractelement <8 x i32> [[TMP1]], i64 6
+; SM100-NEXT: [[L78:%.*]] = extractelement <8 x i32> [[TMP1]], i64 7
+; SM100-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[L78]], i64 0
+; SM100-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[L67]], i64 1
+; SM100-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[L56]], i64 2
+; SM100-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[L45]], i64 3
+; SM100-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[L34]], i64 4
+; SM100-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[L23]], i64 5
+; SM100-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[L12]], i64 6
+; SM100-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 [[L01]], i64 7
; SM100-NEXT: store <8 x i32> [[TMP9]], ptr addrspace(1) [[PTR0]], align 32
; SM100-NEXT: ret void
;
@@ -489,16 +489,16 @@ define void @int64x4(ptr addrspace(1) %ptr) {
; SM90-NEXT: [[PTR0:%.*]] = getelementptr i64, ptr addrspace(1) [[PTR]], i64 0
; SM90-NEXT: [[PTR2:%.*]] = getelementptr i64, ptr addrspace(1) [[PTR]], i64 2
; SM90-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[L01:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
-; SM90-NEXT: [[L12:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
+; SM90-NEXT: [[L01:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
+; SM90-NEXT: [[L12:%.*]] = extractelement <2 x i64> [[TMP1]], i64 1
; SM90-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr addrspace(1) [[PTR2]], align 16
-; SM90-NEXT: [[L23:%.*]] = extractelement <2 x i64> [[TMP2]], i32 0
-; SM90-NEXT: [[L34:%.*]] = extractelement <2 x i64> [[TMP2]], i32 1
-; SM90-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[L34]], i32 0
-; SM90-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[L23]], i32 1
+; SM90-NEXT: [[L23:%.*]] = extractelement <2 x i64> [[TMP2]], i64 0
+; SM90-NEXT: [[L34:%.*]] = extractelement <2 x i64> [[TMP2]], i64 1
+; SM90-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[L34]], i64 0
+; SM90-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[L23]], i64 1
; SM90-NEXT: store <2 x i64> [[TMP4]], ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[TMP5:%.*]] = insertelement <2 x i64> poison, i64 [[L12]], i32 0
-; SM90-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP5]], i64 [[L01]], i32 1
+; SM90-NEXT: [[TMP5:%.*]] = insertelement <2 x i64> poison, i64 [[L12]], i64 0
+; SM90-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP5]], i64 [[L01]], i64 1
; SM90-NEXT: store <2 x i64> [[TMP6]], ptr addrspace(1) [[PTR2]], align 16
; SM90-NEXT: ret void
;
@@ -506,14 +506,14 @@ define void @int64x4(ptr addrspace(1) %ptr) {
; SM100-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
; SM100-NEXT: [[PTR0:%.*]] = getelementptr i64, ptr addrspace(1) [[PTR]], i64 0
; SM100-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr addrspace(1) [[PTR0]], align 32
-; SM100-NEXT: [[L01:%.*]] = extractelement <4 x i64> [[TMP1]], i32 0
-; SM100-NEXT: [[L12:%.*]] = extractelement <4 x i64> [[TMP1]], i32 1
-; SM100-NEXT: [[L23:%.*]] = extractelement <4 x i64> [[TMP1]], i32 2
-; SM100-NEXT: [[L34:%.*]] = extractelement <4 x i64> [[TMP1]], i32 3
-; SM100-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> poison, i64 [[L34]], i32 0
-; SM100-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[L23]], i32 1
-; SM100-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> [[TMP3]], i64 [[L12]], i32 2
-; SM100-NEXT: [[TMP5:%.*]] = insertelement <4 x i64> [[TMP4]], i64 [[L01]], i32 3
+; SM100-NEXT: [[L01:%.*]] = extractelement <4 x i64> [[TMP1]], i64 0
+; SM100-NEXT: [[L12:%.*]] = extractelement <4 x i64> [[TMP1]], i64 1
+; SM100-NEXT: [[L23:%.*]] = extractelement <4 x i64> [[TMP1]], i64 2
+; SM100-NEXT: [[L34:%.*]] = extractelement <4 x i64> [[TMP1]], i64 3
+; SM100-NEXT: [[TMP2:%.*]] = insertelement <4 x i64> poison, i64 [[L34]], i64 0
+; SM100-NEXT: [[TMP3:%.*]] = insertelement <4 x i64> [[TMP2]], i64 [[L23]], i64 1
+; SM100-NEXT: [[TMP4:%.*]] = insertelement <4 x i64> [[TMP3]], i64 [[L12]], i64 2
+; SM100-NEXT: [[TMP5:%.*]] = insertelement <4 x i64> [[TMP4]], i64 [[L01]], i64 3
; SM100-NEXT: store <4 x i64> [[TMP5]], ptr addrspace(1) [[PTR0]], align 32
; SM100-NEXT: ret void
;
@@ -542,24 +542,24 @@ define void @float32x8(ptr addrspace(1) %ptr) {
; SM90-NEXT: [[PTR0:%.*]] = getelementptr float, ptr addrspace(1) [[PTR]], i64 0
; SM90-NEXT: [[PTR4:%.*]] = getelementptr float, ptr addrspace(1) [[PTR]], i64 4
; SM90-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[L01:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
-; SM90-NEXT: [[L12:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
-; SM90-NEXT: [[L23:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
-; SM90-NEXT: [[L34:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; SM90-NEXT: [[L01:%.*]] = extractelement <4 x float> [[TMP1]], i64 0
+; SM90-NEXT: [[L12:%.*]] = extractelement <4 x float> [[TMP1]], i64 1
+; SM90-NEXT: [[L23:%.*]] = extractelement <4 x float> [[TMP1]], i64 2
+; SM90-NEXT: [[L34:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; SM90-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr addrspace(1) [[PTR4]], align 16
-; SM90-NEXT: [[L45:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
-; SM90-NEXT: [[L56:%.*]] = extractelement <4 x float> [[TMP2]], i32 1
-; SM90-NEXT: [[L67:%.*]] = extractelement <4 x float> [[TMP2]], i32 2
-; SM90-NEXT: [[L78:%.*]] = extractelement <4 x float> [[TMP2]], i32 3
-; SM90-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[L78]], i32 0
-; SM90-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[L67]], i32 1
-; SM90-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[L56]], i32 2
-; SM90-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[L45]], i32 3
+; SM90-NEXT: [[L45:%.*]] = extractelement <4 x float> [[TMP2]], i64 0
+; SM90-NEXT: [[L56:%.*]] = extractelement <4 x float> [[TMP2]], i64 1
+; SM90-NEXT: [[L67:%.*]] = extractelement <4 x float> [[TMP2]], i64 2
+; SM90-NEXT: [[L78:%.*]] = extractelement <4 x float> [[TMP2]], i64 3
+; SM90-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[L78]], i64 0
+; SM90-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[L67]], i64 1
+; SM90-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[L56]], i64 2
+; SM90-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[L45]], i64 3
; SM90-NEXT: store <4 x float> [[TMP6]], ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[TMP7:%.*]] = insertelement <4 x float> poison, float [[L34]], i32 0
-; SM90-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[L23]], i32 1
-; SM90-NEXT: [[TMP9:%.*]] = insertelement <4 x float> [[TMP8]], float [[L12]], i32 2
-; SM90-NEXT: [[TMP10:%.*]] = insertelement <4 x float> [[TMP9]], float [[L01]], i32 3
+; SM90-NEXT: [[TMP7:%.*]] = insertelement <4 x float> poison, float [[L34]], i64 0
+; SM90-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[L23]], i64 1
+; SM90-NEXT: [[TMP9:%.*]] = insertelement <4 x float> [[TMP8]], float [[L12]], i64 2
+; SM90-NEXT: [[TMP10:%.*]] = insertelement <4 x float> [[TMP9]], float [[L01]], i64 3
; SM90-NEXT: store <4 x float> [[TMP10]], ptr addrspace(1) [[PTR4]], align 16
; SM90-NEXT: ret void
;
@@ -567,22 +567,22 @@ define void @float32x8(ptr addrspace(1) %ptr) {
; SM100-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
; SM100-NEXT: [[PTR0:%.*]] = getelementptr float, ptr addrspace(1) [[PTR]], i64 0
; SM100-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr addrspace(1) [[PTR0]], align 32
-; SM100-NEXT: [[L01:%.*]] = extractelement <8 x float> [[TMP1]], i32 0
-; SM100-NEXT: [[L12:%.*]] = extractelement <8 x float> [[TMP1]], i32 1
-; SM100-NEXT: [[L23:%.*]] = extractelement <8 x float> [[TMP1]], i32 2
-; SM100-NEXT: [[L34:%.*]] = extractelement <8 x float> [[TMP1]], i32 3
-; SM100-NEXT: [[L45:%.*]] = extractelement <8 x float> [[TMP1]], i32 4
-; SM100-NEXT: [[L56:%.*]] = extractelement <8 x float> [[TMP1]], i32 5
-; SM100-NEXT: [[L67:%.*]] = extractelement <8 x float> [[TMP1]], i32 6
-; SM100-NEXT: [[L78:%.*]] = extractelement <8 x float> [[TMP1]], i32 7
-; SM100-NEXT: [[TMP2:%.*]] = insertelement <8 x float> poison, float [[L78]], i32 0
-; SM100-NEXT: [[TMP3:%.*]] = insertelement <8 x float> [[TMP2]], float [[L67]], i32 1
-; SM100-NEXT: [[TMP4:%.*]] = insertelement <8 x float> [[TMP3]], float [[L56]], i32 2
-; SM100-NEXT: [[TMP5:%.*]] = insertelement <8 x float> [[TMP4]], float [[L45]], i32 3
-; SM100-NEXT: [[TMP6:%.*]] = insertelement <8 x float> [[TMP5]], float [[L34]], i32 4
-; SM100-NEXT: [[TMP7:%.*]] = insertelement <8 x float> [[TMP6]], float [[L23]], i32 5
-; SM100-NEXT: [[TMP8:%.*]] = insertelement <8 x float> [[TMP7]], float [[L12]], i32 6
-; SM100-NEXT: [[TMP9:%.*]] = insertelement <8 x float> [[TMP8]], float [[L01]], i32 7
+; SM100-NEXT: [[L01:%.*]] = extractelement <8 x float> [[TMP1]], i64 0
+; SM100-NEXT: [[L12:%.*]] = extractelement <8 x float> [[TMP1]], i64 1
+; SM100-NEXT: [[L23:%.*]] = extractelement <8 x float> [[TMP1]], i64 2
+; SM100-NEXT: [[L34:%.*]] = extractelement <8 x float> [[TMP1]], i64 3
+; SM100-NEXT: [[L45:%.*]] = extractelement <8 x float> [[TMP1]], i64 4
+; SM100-NEXT: [[L56:%.*]] = extractelement <8 x float> [[TMP1]], i64 5
+; SM100-NEXT: [[L67:%.*]] = extractelement <8 x float> [[TMP1]], i64 6
+; SM100-NEXT: [[L78:%.*]] = extractelement <8 x float> [[TMP1]], i64 7
+; SM100-NEXT: [[TMP2:%.*]] = insertelement <8 x float> poison, float [[L78]], i64 0
+; SM100-NEXT: [[TMP3:%.*]] = insertelement <8 x float> [[TMP2]], float [[L67]], i64 1
+; SM100-NEXT: [[TMP4:%.*]] = insertelement <8 x float> [[TMP3]], float [[L56]], i64 2
+; SM100-NEXT: [[TMP5:%.*]] = insertelement <8 x float> [[TMP4]], float [[L45]], i64 3
+; SM100-NEXT: [[TMP6:%.*]] = insertelement <8 x float> [[TMP5]], float [[L34]], i64 4
+; SM100-NEXT: [[TMP7:%.*]] = insertelement <8 x float> [[TMP6]], float [[L23]], i64 5
+; SM100-NEXT: [[TMP8:%.*]] = insertelement <8 x float> [[TMP7]], float [[L12]], i64 6
+; SM100-NEXT: [[TMP9:%.*]] = insertelement <8 x float> [[TMP8]], float [[L01]], i64 7
; SM100-NEXT: store <8 x float> [[TMP9]], ptr addrspace(1) [[PTR0]], align 32
; SM100-NEXT: ret void
;
@@ -623,16 +623,16 @@ define void @float64x4(ptr addrspace(1) %ptr) {
; SM90-NEXT: [[PTR0:%.*]] = getelementptr double, ptr addrspace(1) [[PTR]], i64 0
; SM90-NEXT: [[PTR2:%.*]] = getelementptr double, ptr addrspace(1) [[PTR]], i64 2
; SM90-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[L01:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
-; SM90-NEXT: [[L12:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; SM90-NEXT: [[L01:%.*]] = extractelement <2 x double> [[TMP1]], i64 0
+; SM90-NEXT: [[L12:%.*]] = extractelement <2 x double> [[TMP1]], i64 1
; SM90-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr addrspace(1) [[PTR2]], align 16
-; SM90-NEXT: [[L23:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
-; SM90-NEXT: [[L34:%.*]] = extractelement <2 x double> [[TMP2]], i32 1
-; SM90-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[L34]], i32 0
-; SM90-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[L23]], i32 1
+; SM90-NEXT: [[L23:%.*]] = extractelement <2 x double> [[TMP2]], i64 0
+; SM90-NEXT: [[L34:%.*]] = extractelement <2 x double> [[TMP2]], i64 1
+; SM90-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[L34]], i64 0
+; SM90-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[L23]], i64 1
; SM90-NEXT: store <2 x double> [[TMP4]], ptr addrspace(1) [[PTR0]], align 32
-; SM90-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[L12]], i32 0
-; SM90-NEXT: [[TMP6:%.*]] = insertelement <2 x double> [[TMP5]], double [[L01]], i32 1
+; SM90-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[L12]], i64 0
+; SM90-NEXT: [[TMP6:%.*]] = insertelement <2 x double> [[TMP5]], double [[L01]], i64 1
; SM90-NEXT: store <2 x double> [[TMP6]], ptr addrspace(1) [[PTR2]], align 16
; SM90-NEXT: ret void
;
@@ -640,14 +640,14 @@ define void @float64x4(ptr addrspace(1) %ptr) {
; SM100-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
; SM100-NEXT: [[PTR0:%.*]] = getelementptr double, ptr addrspace(1) [[PTR]], i64 0
; SM100-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr addrspace(1) [[PTR0]], align 32
-; SM100-NEXT: [[L01:%.*]] = extractelement <4 x double> [[TMP1]], i32 0
-; SM100-NEXT: [[L12:%.*]] = extractelement <4 x double> [[TMP1]], i32 1
-; SM100-NEXT: [[L23:%.*]] = extractelement <4 x double> [[TMP1]], i32 2
-; SM100-NEXT: [[L34:%.*]] = extractelement <4 x double> [[TMP1]], i32 3
-; SM100-NEXT: [[TMP2:%.*]] = insertelement <4 x double> poison, double [[L34]], i32 0
-; SM100-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[L23]], i32 1
-; SM100-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[L12]], i32 2
-; SM100-NEXT: [[TMP5:%.*]] = insertelement <4 x double> [[TMP4]], double [[L01]], i32 3
+; SM100-NEXT: [[L01:%.*]] = extractelement <4 x double> [[TMP1]], i64 0
+; SM100-NEXT: [[L12:%.*]] = extractelement <4 x double> [[TMP1]], i64 1
+; SM100-NEXT: [[L23:%.*]] = extractelement <4 x double> [[TMP1]], i64 2
+; SM100-NEXT: [[L34:%.*]] = extractelement <4 x double> [[TMP1]], i64 3
+; SM100-NEXT: [[TMP2:%.*]] = insertelement <4 x double> poison, double [[L34]], i64 0
+; SM100-NEXT: [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[L23]], i64 1
+; SM100-NEXT: [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[L12]], i64 2
+; SM100-NEXT: [[TMP5:%.*]] = insertelement <4 x double> [[TMP4]], double [[L01]], i64 3
; SM100-NEXT: store <4 x double> [[TMP5]], ptr addrspace(1) [[PTR0]], align 32
; SM100-NEXT: ret void
;
@@ -676,26 +676,27 @@ define void @int32x8_non_global(ptr %ptr) {
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr i32, ptr [[PTR]], i64 0
; CHECK-NEXT: [[PTR4:%.*]] = getelementptr i32, ptr [[PTR]], i64 4
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[PTR0]], align 32
-; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[L34:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[L34:%.*]] = extractelement <4 x i32> [[TMP1]], i64 3
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[PTR4]], align 16
-; CHECK-NEXT: [[L45:%.*]] = extractelement <4 x i32> [[TMP2]], i32 0
-; CHECK-NEXT: [[L56:%.*]] = extractelement <4 x i32> [[TMP2]], i32 1
-; CHECK-NEXT: [[L67:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2
-; CHECK-NEXT: [[L78:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> poison, i32 [[L78]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[L67]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[L56]], i32 2
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[L45]], i32 3
+; CHECK-NEXT: [[L45:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0
+; CHECK-NEXT: [[L56:%.*]] = extractelement <4 x i32> [[TMP2]], i64 1
+; CHECK-NEXT: [[L67:%.*]] = extractelement <4 x i32> [[TMP2]], i64 2
+; CHECK-NEXT: [[L78:%.*]] = extractelement <4 x i32> [[TMP2]], i64 3
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> poison, i32 [[L78]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[L67]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[L56]], i64 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[L45]], i64 3
; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr [[PTR0]], align 32
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[L34]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[L23]], i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[L12]], i32 2
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[L01]], i32 3
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[L34]], i64 0
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[L23]], i64 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[L12]], i64 2
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[L01]], i64 3
; CHECK-NEXT: store <4 x i32> [[TMP10]], ptr [[PTR4]], align 16
; CHECK-NEXT: ret void
+;
%ptr0 = getelementptr i32, ptr %ptr, i64 0
%ptr1 = getelementptr i32, ptr %ptr, i64 1
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/masked-store.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/masked-store.ll
index a9e9cf674c72e..5f456bf96796a 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/masked-store.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/masked-store.ll
@@ -161,22 +161,22 @@ define void @extendStoresFromLoads8xi32(ptr addrspace(1) %in, ptr addrspace(1) %
; CHECK-LABEL: define void @extendStoresFromLoads8xi32(
; CHECK-SAME: ptr addrspace(1) [[IN:%.*]], ptr addrspace(1) [[OUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p1(ptr addrspace(1) align 32 [[IN]], <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false>, <8 x i32> poison)
-; CHECK-NEXT: [[LOAD05:%.*]] = extractelement <8 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD16:%.*]] = extractelement <8 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[LOAD27:%.*]] = extractelement <8 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LOAD38:%.*]] = extractelement <8 x i32> [[TMP1]], i32 3
-; CHECK-NEXT: [[LOAD49:%.*]] = extractelement <8 x i32> [[TMP1]], i32 4
-; CHECK-NEXT: [[EXTENDLOAD10:%.*]] = extractelement <8 x i32> [[TMP1]], i32 5
-; CHECK-NEXT: [[EXTENDLOAD211:%.*]] = extractelement <8 x i32> [[TMP1]], i32 6
-; CHECK-NEXT: [[EXTENDLOAD412:%.*]] = extractelement <8 x i32> [[TMP1]], i32 7
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[LOAD05]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[LOAD16]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[LOAD27]], i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[LOAD38]], i32 3
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[LOAD49]], i32 4
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 poison, i32 5
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 poison, i32 6
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 poison, i32 7
+; CHECK-NEXT: [[LOAD05:%.*]] = extractelement <8 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD16:%.*]] = extractelement <8 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[LOAD27:%.*]] = extractelement <8 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LOAD38:%.*]] = extractelement <8 x i32> [[TMP1]], i64 3
+; CHECK-NEXT: [[LOAD49:%.*]] = extractelement <8 x i32> [[TMP1]], i64 4
+; CHECK-NEXT: [[EXTEND10:%.*]] = extractelement <8 x i32> [[TMP1]], i64 5
+; CHECK-NEXT: [[EXTEND211:%.*]] = extractelement <8 x i32> [[TMP1]], i64 6
+; CHECK-NEXT: [[EXTEND412:%.*]] = extractelement <8 x i32> [[TMP1]], i64 7
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[LOAD05]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[LOAD16]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 [[LOAD27]], i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[LOAD38]], i64 3
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[LOAD49]], i64 4
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 poison, i64 5
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 poison, i64 6
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 poison, i64 7
; CHECK-NEXT: call void @llvm.masked.store.v8i32.p1(<8 x i32> [[TMP9]], ptr addrspace(1) align 32 [[OUT]], <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false>)
; CHECK-NEXT: ret void
;
@@ -207,22 +207,22 @@ define void @extendAndGapFillStoresFromLoads8xi32(ptr addrspace(1) %in, ptr addr
; CHECK-LABEL: define void @extendAndGapFillStoresFromLoads8xi32(
; CHECK-SAME: ptr addrspace(1) [[IN:%.*]], ptr addrspace(1) [[OUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p1(ptr addrspace(1) align 32 [[IN]], <8 x i1> <i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false>, <8 x i32> poison)
-; CHECK-NEXT: [[LOAD05:%.*]] = extractelement <8 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LOAD16:%.*]] = extractelement <8 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[LOAD27:%.*]] = extractelement <8 x i32> [[TMP1]], i32 2
-; CHECK-NEXT: [[LOAD38:%.*]] = extractelement <8 x i32> [[TMP1]], i32 3
-; CHECK-NEXT: [[LOAD49:%.*]] = extractelement <8 x i32> [[TMP1]], i32 4
-; CHECK-NEXT: [[EXTENDLOAD10:%.*]] = extractelement <8 x i32> [[TMP1]], i32 5
-; CHECK-NEXT: [[EXTENDLOAD211:%.*]] = extractelement <8 x i32> [[TMP1]], i32 6
-; CHECK-NEXT: [[EXTENDLOAD412:%.*]] = extractelement <8 x i32> [[TMP1]], i32 7
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[LOAD05]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[LOAD16]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 poison, i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[LOAD38]], i32 3
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[LOAD49]], i32 4
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 poison, i32 5
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 poison, i32 6
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 poison, i32 7
+; CHECK-NEXT: [[LOAD05:%.*]] = extractelement <8 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LOAD16:%.*]] = extractelement <8 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[GAPFILL7:%.*]] = extractelement <8 x i32> [[TMP1]], i64 2
+; CHECK-NEXT: [[LOAD38:%.*]] = extractelement <8 x i32> [[TMP1]], i64 3
+; CHECK-NEXT: [[LOAD49:%.*]] = extractelement <8 x i32> [[TMP1]], i64 4
+; CHECK-NEXT: [[EXTEND10:%.*]] = extractelement <8 x i32> [[TMP1]], i64 5
+; CHECK-NEXT: [[EXTEND211:%.*]] = extractelement <8 x i32> [[TMP1]], i64 6
+; CHECK-NEXT: [[EXTEND412:%.*]] = extractelement <8 x i32> [[TMP1]], i64 7
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[LOAD05]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[LOAD16]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP3]], i32 poison, i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 [[LOAD38]], i64 3
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[LOAD49]], i64 4
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 poison, i64 5
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 poison, i64 6
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 poison, i64 7
; CHECK-NEXT: call void @llvm.masked.store.v8i32.p1(<8 x i32> [[TMP9]], ptr addrspace(1) align 32 [[OUT]], <8 x i1> <i1 true, i1 true, i1 false, i1 true, i1 true, i1 false, i1 false, i1 false>)
; CHECK-NEXT: ret void
;
@@ -333,38 +333,38 @@ define void @cantMaski8(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; CHECK-LABEL: define void @cantMaski8(
; CHECK-SAME: ptr addrspace(1) [[IN:%.*]], ptr addrspace(1) [[OUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = call <32 x i8> @llvm.masked.load.v32i8.p1(ptr addrspace(1) align 32 [[IN]], <32 x i1> <i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true>, <32 x i8> poison)
-; CHECK-NEXT: [[LOAD031:%.*]] = extractelement <32 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[GAPFILL32:%.*]] = extractelement <32 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[GAPFILL233:%.*]] = extractelement <32 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[LOAD334:%.*]] = extractelement <32 x i8> [[TMP1]], i32 3
-; CHECK-NEXT: [[LOAD435:%.*]] = extractelement <32 x i8> [[TMP1]], i32 4
-; CHECK-NEXT: [[GAPFILL436:%.*]] = extractelement <32 x i8> [[TMP1]], i32 5
-; CHECK-NEXT: [[GAPFILL637:%.*]] = extractelement <32 x i8> [[TMP1]], i32 6
-; CHECK-NEXT: [[LOAD738:%.*]] = extractelement <32 x i8> [[TMP1]], i32 7
-; CHECK-NEXT: [[LOAD839:%.*]] = extractelement <32 x i8> [[TMP1]], i32 8
-; CHECK-NEXT: [[GAPFILL840:%.*]] = extractelement <32 x i8> [[TMP1]], i32 9
-; CHECK-NEXT: [[GAPFILL1041:%.*]] = extractelement <32 x i8> [[TMP1]], i32 10
-; CHECK-NEXT: [[LOAD1142:%.*]] = extractelement <32 x i8> [[TMP1]], i32 11
-; CHECK-NEXT: [[LOAD1243:%.*]] = extractelement <32 x i8> [[TMP1]], i32 12
-; CHECK-NEXT: [[GAPFILL1244:%.*]] = extractelement <32 x i8> [[TMP1]], i32 13
-; CHECK-NEXT: [[GAPFILL1445:%.*]] = extractelement <32 x i8> [[TMP1]], i32 14
-; CHECK-NEXT: [[LOAD1546:%.*]] = extractelement <32 x i8> [[TMP1]], i32 15
-; CHECK-NEXT: [[LOAD1647:%.*]] = extractelement <32 x i8> [[TMP1]], i32 16
-; CHECK-NEXT: [[GAPFILL1648:%.*]] = extractelement <32 x i8> [[TMP1]], i32 17
-; CHECK-NEXT: [[GAPFILL1849:%.*]] = extractelement <32 x i8> [[TMP1]], i32 18
-; CHECK-NEXT: [[LOAD1950:%.*]] = extractelement <32 x i8> [[TMP1]], i32 19
-; CHECK-NEXT: [[LOAD2051:%.*]] = extractelement <32 x i8> [[TMP1]], i32 20
-; CHECK-NEXT: [[GAPFILL2052:%.*]] = extractelement <32 x i8> [[TMP1]], i32 21
-; CHECK-NEXT: [[GAPFILL2253:%.*]] = extractelement <32 x i8> [[TMP1]], i32 22
-; CHECK-NEXT: [[LOAD2354:%.*]] = extractelement <32 x i8> [[TMP1]], i32 23
-; CHECK-NEXT: [[LOAD2455:%.*]] = extractelement <32 x i8> [[TMP1]], i32 24
-; CHECK-NEXT: [[GAPFILL2456:%.*]] = extractelement <32 x i8> [[TMP1]], i32 25
-; CHECK-NEXT: [[GAPFILL2657:%.*]] = extractelement <32 x i8> [[TMP1]], i32 26
-; CHECK-NEXT: [[LOAD2758:%.*]] = extractelement <32 x i8> [[TMP1]], i32 27
-; CHECK-NEXT: [[LOAD2859:%.*]] = extractelement <32 x i8> [[TMP1]], i32 28
-; CHECK-NEXT: [[GAPFILL2860:%.*]] = extractelement <32 x i8> [[TMP1]], i32 29
-; CHECK-NEXT: [[GAPFILL3061:%.*]] = extractelement <32 x i8> [[TMP1]], i32 30
-; CHECK-NEXT: [[LOAD3162:%.*]] = extractelement <32 x i8> [[TMP1]], i32 31
+; CHECK-NEXT: [[LOAD031:%.*]] = extractelement <32 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[GAPFILL32:%.*]] = extractelement <32 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[GAPFILL233:%.*]] = extractelement <32 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[LOAD334:%.*]] = extractelement <32 x i8> [[TMP1]], i64 3
+; CHECK-NEXT: [[LOAD435:%.*]] = extractelement <32 x i8> [[TMP1]], i64 4
+; CHECK-NEXT: [[GAPFILL436:%.*]] = extractelement <32 x i8> [[TMP1]], i64 5
+; CHECK-NEXT: [[GAPFILL637:%.*]] = extractelement <32 x i8> [[TMP1]], i64 6
+; CHECK-NEXT: [[LOAD738:%.*]] = extractelement <32 x i8> [[TMP1]], i64 7
+; CHECK-NEXT: [[LOAD839:%.*]] = extractelement <32 x i8> [[TMP1]], i64 8
+; CHECK-NEXT: [[GAPFILL840:%.*]] = extractelement <32 x i8> [[TMP1]], i64 9
+; CHECK-NEXT: [[GAPFILL1041:%.*]] = extractelement <32 x i8> [[TMP1]], i64 10
+; CHECK-NEXT: [[LOAD1142:%.*]] = extractelement <32 x i8> [[TMP1]], i64 11
+; CHECK-NEXT: [[LOAD1243:%.*]] = extractelement <32 x i8> [[TMP1]], i64 12
+; CHECK-NEXT: [[GAPFILL1244:%.*]] = extractelement <32 x i8> [[TMP1]], i64 13
+; CHECK-NEXT: [[GAPFILL1445:%.*]] = extractelement <32 x i8> [[TMP1]], i64 14
+; CHECK-NEXT: [[LOAD1546:%.*]] = extractelement <32 x i8> [[TMP1]], i64 15
+; CHECK-NEXT: [[LOAD1647:%.*]] = extractelement <32 x i8> [[TMP1]], i64 16
+; CHECK-NEXT: [[GAPFILL1648:%.*]] = extractelement <32 x i8> [[TMP1]], i64 17
+; CHECK-NEXT: [[GAPFILL1849:%.*]] = extractelement <32 x i8> [[TMP1]], i64 18
+; CHECK-NEXT: [[LOAD1950:%.*]] = extractelement <32 x i8> [[TMP1]], i64 19
+; CHECK-NEXT: [[LOAD2051:%.*]] = extractelement <32 x i8> [[TMP1]], i64 20
+; CHECK-NEXT: [[GAPFILL2052:%.*]] = extractelement <32 x i8> [[TMP1]], i64 21
+; CHECK-NEXT: [[GAPFILL2253:%.*]] = extractelement <32 x i8> [[TMP1]], i64 22
+; CHECK-NEXT: [[LOAD2354:%.*]] = extractelement <32 x i8> [[TMP1]], i64 23
+; CHECK-NEXT: [[LOAD2455:%.*]] = extractelement <32 x i8> [[TMP1]], i64 24
+; CHECK-NEXT: [[GAPFILL2456:%.*]] = extractelement <32 x i8> [[TMP1]], i64 25
+; CHECK-NEXT: [[GAPFILL2657:%.*]] = extractelement <32 x i8> [[TMP1]], i64 26
+; CHECK-NEXT: [[LOAD2758:%.*]] = extractelement <32 x i8> [[TMP1]], i64 27
+; CHECK-NEXT: [[LOAD2859:%.*]] = extractelement <32 x i8> [[TMP1]], i64 28
+; CHECK-NEXT: [[GAPFILL2860:%.*]] = extractelement <32 x i8> [[TMP1]], i64 29
+; CHECK-NEXT: [[GAPFILL3061:%.*]] = extractelement <32 x i8> [[TMP1]], i64 30
+; CHECK-NEXT: [[LOAD3162:%.*]] = extractelement <32 x i8> [[TMP1]], i64 31
; CHECK-NEXT: store i8 [[LOAD031]], ptr addrspace(1) [[OUT]], align 32
; CHECK-NEXT: [[OUTELEM3:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[OUT]], i32 3
; CHECK-NEXT: store i8 [[LOAD334]], ptr addrspace(1) [[OUTELEM3]], align 1
@@ -472,22 +472,22 @@ define void @cantMaski16(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; CHECK-LABEL: define void @cantMaski16(
; CHECK-SAME: ptr addrspace(1) [[IN:%.*]], ptr addrspace(1) [[OUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i16> @llvm.masked.load.v16i16.p1(ptr addrspace(1) align 32 [[IN]], <16 x i1> <i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true, i1 true, i1 false, i1 false, i1 true>, <16 x i16> poison)
-; CHECK-NEXT: [[LOAD015:%.*]] = extractelement <16 x i16> [[TMP1]], i32 0
-; CHECK-NEXT: [[GAPFILL16:%.*]] = extractelement <16 x i16> [[TMP1]], i32 1
-; CHECK-NEXT: [[GAPFILL217:%.*]] = extractelement <16 x i16> [[TMP1]], i32 2
-; CHECK-NEXT: [[LOAD318:%.*]] = extractelement <16 x i16> [[TMP1]], i32 3
-; CHECK-NEXT: [[LOAD419:%.*]] = extractelement <16 x i16> [[TMP1]], i32 4
-; CHECK-NEXT: [[GAPFILL420:%.*]] = extractelement <16 x i16> [[TMP1]], i32 5
-; CHECK-NEXT: [[GAPFILL621:%.*]] = extractelement <16 x i16> [[TMP1]], i32 6
-; CHECK-NEXT: [[LOAD722:%.*]] = extractelement <16 x i16> [[TMP1]], i32 7
-; CHECK-NEXT: [[LOAD823:%.*]] = extractelement <16 x i16> [[TMP1]], i32 8
-; CHECK-NEXT: [[GAPFILL824:%.*]] = extractelement <16 x i16> [[TMP1]], i32 9
-; CHECK-NEXT: [[GAPFILL1025:%.*]] = extractelement <16 x i16> [[TMP1]], i32 10
-; CHECK-NEXT: [[LOAD1126:%.*]] = extractelement <16 x i16> [[TMP1]], i32 11
-; CHECK-NEXT: [[LOAD1227:%.*]] = extractelement <16 x i16> [[TMP1]], i32 12
-; CHECK-NEXT: [[GAPFILL1228:%.*]] = extractelement <16 x i16> [[TMP1]], i32 13
-; CHECK-NEXT: [[GAPFILL1429:%.*]] = extractelement <16 x i16> [[TMP1]], i32 14
-; CHECK-NEXT: [[LOAD1530:%.*]] = extractelement <16 x i16> [[TMP1]], i32 15
+; CHECK-NEXT: [[LOAD015:%.*]] = extractelement <16 x i16> [[TMP1]], i64 0
+; CHECK-NEXT: [[GAPFILL16:%.*]] = extractelement <16 x i16> [[TMP1]], i64 1
+; CHECK-NEXT: [[GAPFILL217:%.*]] = extractelement <16 x i16> [[TMP1]], i64 2
+; CHECK-NEXT: [[LOAD318:%.*]] = extractelement <16 x i16> [[TMP1]], i64 3
+; CHECK-NEXT: [[LOAD419:%.*]] = extractelement <16 x i16> [[TMP1]], i64 4
+; CHECK-NEXT: [[GAPFILL420:%.*]] = extractelement <16 x i16> [[TMP1]], i64 5
+; CHECK-NEXT: [[GAPFILL621:%.*]] = extractelement <16 x i16> [[TMP1]], i64 6
+; CHECK-NEXT: [[LOAD722:%.*]] = extractelement <16 x i16> [[TMP1]], i64 7
+; CHECK-NEXT: [[LOAD823:%.*]] = extractelement <16 x i16> [[TMP1]], i64 8
+; CHECK-NEXT: [[GAPFILL824:%.*]] = extractelement <16 x i16> [[TMP1]], i64 9
+; CHECK-NEXT: [[GAPFILL1025:%.*]] = extractelement <16 x i16> [[TMP1]], i64 10
+; CHECK-NEXT: [[LOAD1126:%.*]] = extractelement <16 x i16> [[TMP1]], i64 11
+; CHECK-NEXT: [[LOAD1227:%.*]] = extractelement <16 x i16> [[TMP1]], i64 12
+; CHECK-NEXT: [[GAPFILL1228:%.*]] = extractelement <16 x i16> [[TMP1]], i64 13
+; CHECK-NEXT: [[GAPFILL1429:%.*]] = extractelement <16 x i16> [[TMP1]], i64 14
+; CHECK-NEXT: [[LOAD1530:%.*]] = extractelement <16 x i16> [[TMP1]], i64 15
; CHECK-NEXT: store i16 [[LOAD015]], ptr addrspace(1) [[OUT]], align 32
; CHECK-NEXT: [[OUTELEM6:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[OUT]], i32 6
; CHECK-NEXT: store i16 [[LOAD318]], ptr addrspace(1) [[OUTELEM6]], align 2
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
index f2d4ea20230d7..cbc0640df7686 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
@@ -8,9 +8,9 @@ define i32 @foo(ptr %ptr) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: [[PTR1:%.*]] = getelementptr i32, ptr [[PTR:%.*]], i32 1
; CHECK-NEXT: [[P1:%.*]] = addrspacecast ptr [[PTR1]] to ptr addrspace(1)
-; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[PTR]], align 8, !invariant.load !0
-; CHECK-NEXT: [[V01:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
-; CHECK-NEXT: [[V12:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[PTR]], align 8, !invariant.load [[META0:![0-9]+]]
+; CHECK-NEXT: [[V01:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[V12:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[SUM:%.*]] = add i32 [[V01]], [[V12]]
; CHECK-NEXT: ret i32 [[SUM]]
;
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/vectorize_i8.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/vectorize_i8.ll
index 47c9d9a88d958..3b38412f0688b 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/vectorize_i8.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/vectorize_i8.ll
@@ -9,11 +9,11 @@ define void @int8x3a2(ptr nocapture align 2 %ptr) {
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr i8, ptr [[PTR]], i64 0
; CHECK-NEXT: [[PTR2:%.*]] = getelementptr i8, ptr [[PTR]], i64 2
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr [[PTR0]], align 2
-; CHECK-NEXT: [[L01:%.*]] = extractelement <2 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <2 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[L01:%.*]] = extractelement <2 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <2 x i8> [[TMP1]], i64 1
; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[PTR2]], align 2
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> poison, i8 [[L2]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i8> [[TMP2]], i8 [[L12]], i32 1
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> poison, i8 [[L2]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i8> [[TMP2]], i8 [[L12]], i64 1
; CHECK-NEXT: store <2 x i8> [[TMP3]], ptr [[PTR0]], align 2
; CHECK-NEXT: store i8 [[L01]], ptr [[PTR2]], align 2
; CHECK-NEXT: ret void
@@ -40,12 +40,12 @@ define void @int8x3a4(ptr nocapture align 4 %ptr) {
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr i8, ptr [[PTR]], i64 0
; CHECK-NEXT: [[PTR2:%.*]] = getelementptr i8, ptr [[PTR]], i64 2
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr align 4 [[PTR0]], <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x i8> poison)
-; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[EXTEND4:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> poison, i8 [[L23]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i8> [[TMP2]], i8 [[L12]], i32 1
+; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[EXTEND4:%.*]] = extractelement <4 x i8> [[TMP1]], i64 3
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> poison, i8 [[L23]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i8> [[TMP2]], i8 [[L12]], i64 1
; CHECK-NEXT: store <2 x i8> [[TMP3]], ptr [[PTR0]], align 4
; CHECK-NEXT: store i8 [[L01]], ptr [[PTR2]], align 2
; CHECK-NEXT: ret void
@@ -73,34 +73,34 @@ define void @int8x12a4(ptr nocapture align 4 %ptr) {
; CHECK-NEXT: [[PTR4:%.*]] = getelementptr i8, ptr [[PTR]], i64 4
; CHECK-NEXT: [[PTR8:%.*]] = getelementptr i8, ptr [[PTR]], i64 8
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[PTR0]], align 4
-; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[L34:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[L34:%.*]] = extractelement <4 x i8> [[TMP1]], i64 3
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[PTR4]], align 4
-; CHECK-NEXT: [[L45:%.*]] = extractelement <4 x i8> [[TMP2]], i32 0
-; CHECK-NEXT: [[L56:%.*]] = extractelement <4 x i8> [[TMP2]], i32 1
-; CHECK-NEXT: [[L67:%.*]] = extractelement <4 x i8> [[TMP2]], i32 2
-; CHECK-NEXT: [[L78:%.*]] = extractelement <4 x i8> [[TMP2]], i32 3
+; CHECK-NEXT: [[L45:%.*]] = extractelement <4 x i8> [[TMP2]], i64 0
+; CHECK-NEXT: [[L56:%.*]] = extractelement <4 x i8> [[TMP2]], i64 1
+; CHECK-NEXT: [[L67:%.*]] = extractelement <4 x i8> [[TMP2]], i64 2
+; CHECK-NEXT: [[L78:%.*]] = extractelement <4 x i8> [[TMP2]], i64 3
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr [[PTR8]], align 4
-; CHECK-NEXT: [[L89:%.*]] = extractelement <4 x i8> [[TMP3]], i32 0
-; CHECK-NEXT: [[L910:%.*]] = extractelement <4 x i8> [[TMP3]], i32 1
-; CHECK-NEXT: [[LA11:%.*]] = extractelement <4 x i8> [[TMP3]], i32 2
-; CHECK-NEXT: [[LB12:%.*]] = extractelement <4 x i8> [[TMP3]], i32 3
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> poison, i8 [[LB12]], i32 0
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> [[TMP4]], i8 [[LA11]], i32 1
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i8> [[TMP5]], i8 [[L910]], i32 2
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i8> [[TMP6]], i8 [[L89]], i32 3
+; CHECK-NEXT: [[L89:%.*]] = extractelement <4 x i8> [[TMP3]], i64 0
+; CHECK-NEXT: [[L910:%.*]] = extractelement <4 x i8> [[TMP3]], i64 1
+; CHECK-NEXT: [[LA11:%.*]] = extractelement <4 x i8> [[TMP3]], i64 2
+; CHECK-NEXT: [[LB12:%.*]] = extractelement <4 x i8> [[TMP3]], i64 3
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> poison, i8 [[LB12]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> [[TMP4]], i8 [[LA11]], i64 1
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i8> [[TMP5]], i8 [[L910]], i64 2
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i8> [[TMP6]], i8 [[L89]], i64 3
; CHECK-NEXT: store <4 x i8> [[TMP7]], ptr [[PTR0]], align 4
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i8> poison, i8 [[L78]], i32 0
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i8> [[TMP8]], i8 [[L67]], i32 1
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i8> [[TMP9]], i8 [[L56]], i32 2
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i8> [[TMP10]], i8 [[L45]], i32 3
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i8> poison, i8 [[L78]], i64 0
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i8> [[TMP8]], i8 [[L67]], i64 1
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i8> [[TMP9]], i8 [[L56]], i64 2
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i8> [[TMP10]], i8 [[L45]], i64 3
; CHECK-NEXT: store <4 x i8> [[TMP11]], ptr [[PTR4]], align 4
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i8> poison, i8 [[L34]], i32 0
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i8> [[TMP12]], i8 [[L23]], i32 1
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i8> [[TMP13]], i8 [[L12]], i32 2
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i8> [[TMP14]], i8 [[L01]], i32 3
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i8> poison, i8 [[L34]], i64 0
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i8> [[TMP12]], i8 [[L23]], i64 1
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i8> [[TMP13]], i8 [[L12]], i64 2
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i8> [[TMP14]], i8 [[L01]], i64 3
; CHECK-NEXT: store <4 x i8> [[TMP15]], ptr [[PTR8]], align 4
; CHECK-NEXT: ret void
;
@@ -156,44 +156,44 @@ define void @int8x16a4(ptr nocapture align 4 %ptr) {
; CHECK-NEXT: [[PTR8:%.*]] = getelementptr i8, ptr [[PTR]], i64 8
; CHECK-NEXT: [[PTRC:%.*]] = getelementptr i8, ptr [[PTR]], i64 12
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[PTR0]], align 4
-; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[L34:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[L34:%.*]] = extractelement <4 x i8> [[TMP1]], i64 3
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[PTR4]], align 4
-; CHECK-NEXT: [[L45:%.*]] = extractelement <4 x i8> [[TMP2]], i32 0
-; CHECK-NEXT: [[L56:%.*]] = extractelement <4 x i8> [[TMP2]], i32 1
-; CHECK-NEXT: [[L67:%.*]] = extractelement <4 x i8> [[TMP2]], i32 2
-; CHECK-NEXT: [[L78:%.*]] = extractelement <4 x i8> [[TMP2]], i32 3
+; CHECK-NEXT: [[L45:%.*]] = extractelement <4 x i8> [[TMP2]], i64 0
+; CHECK-NEXT: [[L56:%.*]] = extractelement <4 x i8> [[TMP2]], i64 1
+; CHECK-NEXT: [[L67:%.*]] = extractelement <4 x i8> [[TMP2]], i64 2
+; CHECK-NEXT: [[L78:%.*]] = extractelement <4 x i8> [[TMP2]], i64 3
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr [[PTR8]], align 4
-; CHECK-NEXT: [[L89:%.*]] = extractelement <4 x i8> [[TMP3]], i32 0
-; CHECK-NEXT: [[L910:%.*]] = extractelement <4 x i8> [[TMP3]], i32 1
-; CHECK-NEXT: [[LA11:%.*]] = extractelement <4 x i8> [[TMP3]], i32 2
-; CHECK-NEXT: [[LB12:%.*]] = extractelement <4 x i8> [[TMP3]], i32 3
+; CHECK-NEXT: [[L89:%.*]] = extractelement <4 x i8> [[TMP3]], i64 0
+; CHECK-NEXT: [[L910:%.*]] = extractelement <4 x i8> [[TMP3]], i64 1
+; CHECK-NEXT: [[LA11:%.*]] = extractelement <4 x i8> [[TMP3]], i64 2
+; CHECK-NEXT: [[LB12:%.*]] = extractelement <4 x i8> [[TMP3]], i64 3
; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i8>, ptr [[PTRC]], align 4
-; CHECK-NEXT: [[LC13:%.*]] = extractelement <4 x i8> [[TMP4]], i32 0
-; CHECK-NEXT: [[LD14:%.*]] = extractelement <4 x i8> [[TMP4]], i32 1
-; CHECK-NEXT: [[LE15:%.*]] = extractelement <4 x i8> [[TMP4]], i32 2
-; CHECK-NEXT: [[LF16:%.*]] = extractelement <4 x i8> [[TMP4]], i32 3
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> poison, i8 [[LF16]], i32 0
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i8> [[TMP5]], i8 [[LE15]], i32 1
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i8> [[TMP6]], i8 [[LD14]], i32 2
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i8> [[TMP7]], i8 [[LC13]], i32 3
+; CHECK-NEXT: [[LC13:%.*]] = extractelement <4 x i8> [[TMP4]], i64 0
+; CHECK-NEXT: [[LD14:%.*]] = extractelement <4 x i8> [[TMP4]], i64 1
+; CHECK-NEXT: [[LE15:%.*]] = extractelement <4 x i8> [[TMP4]], i64 2
+; CHECK-NEXT: [[LF16:%.*]] = extractelement <4 x i8> [[TMP4]], i64 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i8> poison, i8 [[LF16]], i64 0
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i8> [[TMP5]], i8 [[LE15]], i64 1
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i8> [[TMP6]], i8 [[LD14]], i64 2
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i8> [[TMP7]], i8 [[LC13]], i64 3
; CHECK-NEXT: store <4 x i8> [[TMP8]], ptr [[PTRC]], align 4
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i8> poison, i8 [[LB12]], i32 0
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i8> [[TMP9]], i8 [[LA11]], i32 1
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i8> [[TMP10]], i8 [[L910]], i32 2
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i8> [[TMP11]], i8 [[L89]], i32 3
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i8> poison, i8 [[LB12]], i64 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i8> [[TMP9]], i8 [[LA11]], i64 1
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i8> [[TMP10]], i8 [[L910]], i64 2
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i8> [[TMP11]], i8 [[L89]], i64 3
; CHECK-NEXT: store <4 x i8> [[TMP12]], ptr [[PTR0]], align 4
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i8> poison, i8 [[L78]], i32 0
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i8> [[TMP13]], i8 [[L67]], i32 1
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i8> [[TMP14]], i8 [[L56]], i32 2
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i8> [[TMP15]], i8 [[L45]], i32 3
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i8> poison, i8 [[L78]], i64 0
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i8> [[TMP13]], i8 [[L67]], i64 1
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i8> [[TMP14]], i8 [[L56]], i64 2
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i8> [[TMP15]], i8 [[L45]], i64 3
; CHECK-NEXT: store <4 x i8> [[TMP16]], ptr [[PTR4]], align 4
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x i8> poison, i8 [[L34]], i32 0
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x i8> [[TMP17]], i8 [[L23]], i32 1
-; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> [[TMP18]], i8 [[L12]], i32 2
-; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[L01]], i32 3
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x i8> poison, i8 [[L34]], i64 0
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x i8> [[TMP17]], i8 [[L23]], i64 1
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> [[TMP18]], i8 [[L12]], i64 2
+; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[L01]], i64 3
; CHECK-NEXT: store <4 x i8> [[TMP20]], ptr [[PTR8]], align 4
; CHECK-NEXT: ret void
;
@@ -257,22 +257,22 @@ define void @int8x8a8(ptr nocapture align 8 %ptr) {
; CHECK-SAME: ptr align 8 captures(none) [[PTR:%.*]]) {
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr i8, ptr [[PTR]], i64 0
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[PTR0]], align 8
-; CHECK-NEXT: [[L01:%.*]] = extractelement <8 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <8 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[L23:%.*]] = extractelement <8 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[L34:%.*]] = extractelement <8 x i8> [[TMP1]], i32 3
-; CHECK-NEXT: [[L45:%.*]] = extractelement <8 x i8> [[TMP1]], i32 4
-; CHECK-NEXT: [[L56:%.*]] = extractelement <8 x i8> [[TMP1]], i32 5
-; CHECK-NEXT: [[L67:%.*]] = extractelement <8 x i8> [[TMP1]], i32 6
-; CHECK-NEXT: [[L78:%.*]] = extractelement <8 x i8> [[TMP1]], i32 7
-; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i8> poison, i8 [[L78]], i32 0
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> [[TMP2]], i8 [[L67]], i32 1
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i8> [[TMP3]], i8 [[L56]], i32 2
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i8> [[TMP4]], i8 [[L45]], i32 3
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i8> [[TMP5]], i8 [[L34]], i32 4
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[TMP6]], i8 [[L23]], i32 5
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i8> [[TMP7]], i8 [[L12]], i32 6
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> [[TMP8]], i8 [[L01]], i32 7
+; CHECK-NEXT: [[L01:%.*]] = extractelement <8 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <8 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[L23:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[L34:%.*]] = extractelement <8 x i8> [[TMP1]], i64 3
+; CHECK-NEXT: [[L45:%.*]] = extractelement <8 x i8> [[TMP1]], i64 4
+; CHECK-NEXT: [[L56:%.*]] = extractelement <8 x i8> [[TMP1]], i64 5
+; CHECK-NEXT: [[L67:%.*]] = extractelement <8 x i8> [[TMP1]], i64 6
+; CHECK-NEXT: [[L78:%.*]] = extractelement <8 x i8> [[TMP1]], i64 7
+; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i8> poison, i8 [[L78]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> [[TMP2]], i8 [[L67]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i8> [[TMP3]], i8 [[L56]], i64 2
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i8> [[TMP4]], i8 [[L45]], i64 3
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i8> [[TMP5]], i8 [[L34]], i64 4
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[TMP6]], i8 [[L23]], i64 5
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i8> [[TMP7]], i8 [[L12]], i64 6
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> [[TMP8]], i8 [[L01]], i64 7
; CHECK-NEXT: store <8 x i8> [[TMP9]], ptr [[PTR0]], align 8
; CHECK-NEXT: ret void
;
@@ -313,32 +313,32 @@ define void @int8x12a8(ptr nocapture align 8 %ptr) {
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr i8, ptr [[PTR]], i64 0
; CHECK-NEXT: [[PTR8:%.*]] = getelementptr i8, ptr [[PTR]], i64 8
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[PTR0]], align 8
-; CHECK-NEXT: [[L01:%.*]] = extractelement <8 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <8 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[L23:%.*]] = extractelement <8 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[L34:%.*]] = extractelement <8 x i8> [[TMP1]], i32 3
-; CHECK-NEXT: [[L45:%.*]] = extractelement <8 x i8> [[TMP1]], i32 4
-; CHECK-NEXT: [[L56:%.*]] = extractelement <8 x i8> [[TMP1]], i32 5
-; CHECK-NEXT: [[L67:%.*]] = extractelement <8 x i8> [[TMP1]], i32 6
-; CHECK-NEXT: [[L78:%.*]] = extractelement <8 x i8> [[TMP1]], i32 7
+; CHECK-NEXT: [[L01:%.*]] = extractelement <8 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <8 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[L23:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[L34:%.*]] = extractelement <8 x i8> [[TMP1]], i64 3
+; CHECK-NEXT: [[L45:%.*]] = extractelement <8 x i8> [[TMP1]], i64 4
+; CHECK-NEXT: [[L56:%.*]] = extractelement <8 x i8> [[TMP1]], i64 5
+; CHECK-NEXT: [[L67:%.*]] = extractelement <8 x i8> [[TMP1]], i64 6
+; CHECK-NEXT: [[L78:%.*]] = extractelement <8 x i8> [[TMP1]], i64 7
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[PTR8]], align 8
-; CHECK-NEXT: [[L89:%.*]] = extractelement <4 x i8> [[TMP2]], i32 0
-; CHECK-NEXT: [[L910:%.*]] = extractelement <4 x i8> [[TMP2]], i32 1
-; CHECK-NEXT: [[LA11:%.*]] = extractelement <4 x i8> [[TMP2]], i32 2
-; CHECK-NEXT: [[LB12:%.*]] = extractelement <4 x i8> [[TMP2]], i32 3
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[LB12]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i8> [[TMP3]], i8 [[LA11]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i8> [[TMP4]], i8 [[L910]], i32 2
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i8> [[TMP5]], i8 [[L89]], i32 3
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[TMP6]], i8 [[L78]], i32 4
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i8> [[TMP7]], i8 [[L67]], i32 5
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> [[TMP8]], i8 [[L56]], i32 6
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i8> [[TMP9]], i8 [[L45]], i32 7
+; CHECK-NEXT: [[L89:%.*]] = extractelement <4 x i8> [[TMP2]], i64 0
+; CHECK-NEXT: [[L910:%.*]] = extractelement <4 x i8> [[TMP2]], i64 1
+; CHECK-NEXT: [[LA11:%.*]] = extractelement <4 x i8> [[TMP2]], i64 2
+; CHECK-NEXT: [[LB12:%.*]] = extractelement <4 x i8> [[TMP2]], i64 3
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[LB12]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i8> [[TMP3]], i8 [[LA11]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i8> [[TMP4]], i8 [[L910]], i64 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i8> [[TMP5]], i8 [[L89]], i64 3
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[TMP6]], i8 [[L78]], i64 4
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i8> [[TMP7]], i8 [[L67]], i64 5
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> [[TMP8]], i8 [[L56]], i64 6
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i8> [[TMP9]], i8 [[L45]], i64 7
; CHECK-NEXT: store <8 x i8> [[TMP10]], ptr [[PTR0]], align 8
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i8> poison, i8 [[L34]], i32 0
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i8> [[TMP11]], i8 [[L23]], i32 1
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i8> [[TMP12]], i8 [[L12]], i32 2
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i8> [[TMP13]], i8 [[L01]], i32 3
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i8> poison, i8 [[L34]], i64 0
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i8> [[TMP11]], i8 [[L23]], i64 1
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i8> [[TMP12]], i8 [[L12]], i64 2
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <4 x i8> [[TMP13]], i8 [[L01]], i64 3
; CHECK-NEXT: store <4 x i8> [[TMP14]], ptr [[PTR8]], align 8
; CHECK-NEXT: ret void
;
@@ -392,40 +392,40 @@ define void @int8x16a8(ptr nocapture align 8 %ptr) {
; CHECK-NEXT: [[PTR0:%.*]] = getelementptr i8, ptr [[PTR]], i64 0
; CHECK-NEXT: [[PTR8:%.*]] = getelementptr i8, ptr [[PTR]], i64 8
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[PTR0]], align 8
-; CHECK-NEXT: [[L01:%.*]] = extractelement <8 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <8 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[L23:%.*]] = extractelement <8 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[L34:%.*]] = extractelement <8 x i8> [[TMP1]], i32 3
-; CHECK-NEXT: [[L45:%.*]] = extractelement <8 x i8> [[TMP1]], i32 4
-; CHECK-NEXT: [[L56:%.*]] = extractelement <8 x i8> [[TMP1]], i32 5
-; CHECK-NEXT: [[L67:%.*]] = extractelement <8 x i8> [[TMP1]], i32 6
-; CHECK-NEXT: [[L78:%.*]] = extractelement <8 x i8> [[TMP1]], i32 7
+; CHECK-NEXT: [[L01:%.*]] = extractelement <8 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <8 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[L23:%.*]] = extractelement <8 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[L34:%.*]] = extractelement <8 x i8> [[TMP1]], i64 3
+; CHECK-NEXT: [[L45:%.*]] = extractelement <8 x i8> [[TMP1]], i64 4
+; CHECK-NEXT: [[L56:%.*]] = extractelement <8 x i8> [[TMP1]], i64 5
+; CHECK-NEXT: [[L67:%.*]] = extractelement <8 x i8> [[TMP1]], i64 6
+; CHECK-NEXT: [[L78:%.*]] = extractelement <8 x i8> [[TMP1]], i64 7
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[PTR8]], align 8
-; CHECK-NEXT: [[L89:%.*]] = extractelement <8 x i8> [[TMP2]], i32 0
-; CHECK-NEXT: [[L910:%.*]] = extractelement <8 x i8> [[TMP2]], i32 1
-; CHECK-NEXT: [[LA11:%.*]] = extractelement <8 x i8> [[TMP2]], i32 2
-; CHECK-NEXT: [[LB12:%.*]] = extractelement <8 x i8> [[TMP2]], i32 3
-; CHECK-NEXT: [[LC13:%.*]] = extractelement <8 x i8> [[TMP2]], i32 4
-; CHECK-NEXT: [[LD14:%.*]] = extractelement <8 x i8> [[TMP2]], i32 5
-; CHECK-NEXT: [[LE15:%.*]] = extractelement <8 x i8> [[TMP2]], i32 6
-; CHECK-NEXT: [[LF16:%.*]] = extractelement <8 x i8> [[TMP2]], i32 7
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[LF16]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i8> [[TMP3]], i8 [[LE15]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i8> [[TMP4]], i8 [[LD14]], i32 2
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i8> [[TMP5]], i8 [[LC13]], i32 3
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[TMP6]], i8 [[LB12]], i32 4
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i8> [[TMP7]], i8 [[LA11]], i32 5
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> [[TMP8]], i8 [[L910]], i32 6
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i8> [[TMP9]], i8 [[L89]], i32 7
+; CHECK-NEXT: [[L89:%.*]] = extractelement <8 x i8> [[TMP2]], i64 0
+; CHECK-NEXT: [[L910:%.*]] = extractelement <8 x i8> [[TMP2]], i64 1
+; CHECK-NEXT: [[LA11:%.*]] = extractelement <8 x i8> [[TMP2]], i64 2
+; CHECK-NEXT: [[LB12:%.*]] = extractelement <8 x i8> [[TMP2]], i64 3
+; CHECK-NEXT: [[LC13:%.*]] = extractelement <8 x i8> [[TMP2]], i64 4
+; CHECK-NEXT: [[LD14:%.*]] = extractelement <8 x i8> [[TMP2]], i64 5
+; CHECK-NEXT: [[LE15:%.*]] = extractelement <8 x i8> [[TMP2]], i64 6
+; CHECK-NEXT: [[LF16:%.*]] = extractelement <8 x i8> [[TMP2]], i64 7
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[LF16]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i8> [[TMP3]], i8 [[LE15]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i8> [[TMP4]], i8 [[LD14]], i64 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i8> [[TMP5]], i8 [[LC13]], i64 3
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[TMP6]], i8 [[LB12]], i64 4
+; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i8> [[TMP7]], i8 [[LA11]], i64 5
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> [[TMP8]], i8 [[L910]], i64 6
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i8> [[TMP9]], i8 [[L89]], i64 7
; CHECK-NEXT: store <8 x i8> [[TMP10]], ptr [[PTR0]], align 8
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i8> poison, i8 [[L78]], i32 0
-; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i8> [[TMP11]], i8 [[L67]], i32 1
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i8> [[TMP12]], i8 [[L56]], i32 2
-; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i8> [[TMP13]], i8 [[L45]], i32 3
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i8> [[TMP14]], i8 [[L34]], i32 4
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x i8> [[TMP15]], i8 [[L23]], i32 5
-; CHECK-NEXT: [[TMP17:%.*]] = insertelement <8 x i8> [[TMP16]], i8 [[L12]], i32 6
-; CHECK-NEXT: [[TMP18:%.*]] = insertelement <8 x i8> [[TMP17]], i8 [[L01]], i32 7
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i8> poison, i8 [[L78]], i64 0
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i8> [[TMP11]], i8 [[L67]], i64 1
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i8> [[TMP12]], i8 [[L56]], i64 2
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i8> [[TMP13]], i8 [[L45]], i64 3
+; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i8> [[TMP14]], i8 [[L34]], i64 4
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x i8> [[TMP15]], i8 [[L23]], i64 5
+; CHECK-NEXT: [[TMP17:%.*]] = insertelement <8 x i8> [[TMP16]], i8 [[L12]], i64 6
+; CHECK-NEXT: [[TMP18:%.*]] = insertelement <8 x i8> [[TMP17]], i8 [[L01]], i64 7
; CHECK-NEXT: store <8 x i8> [[TMP18]], ptr [[PTR8]], align 8
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/correct-order.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/correct-order.ll
index 0fc2ac01e9315..2c4c0b04fc5c0 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/X86/correct-order.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/correct-order.ll
@@ -8,12 +8,12 @@ define void @correct_order(ptr noalias %ptr) {
; CHECK-LABEL: @correct_order(
; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i32, ptr [[PTR:%.*]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[PTR]], align 4
-; CHECK-NEXT: [[L21:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[L21:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[PTR]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[NEXT_GEP1]], align 4
-; CHECK-NEXT: [[L33:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
-; CHECK-NEXT: [[L44:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1
+; CHECK-NEXT: [[L33:%.*]] = extractelement <2 x i32> [[TMP2]], i64 0
+; CHECK-NEXT: [[L44:%.*]] = extractelement <2 x i32> [[TMP2]], i64 1
; CHECK-NEXT: ret void
;
%next.gep1 = getelementptr i32, ptr %ptr, i64 1
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
index 6a7a5dac40c83..bf8b8d4075a03 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/massive_indirection.ll
@@ -95,16 +95,16 @@ define void @v1_4_4_4_2_1_to_v8_8_levels_6_7(i32 %arg0, ptr addrspace(3) align 1
; CHECK: [[_LR_PH:.*:]]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP5]], i32 [[ARG4]]
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[GEP]], i32 [[ARG5]]
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x half> poison, half [[ARG6_HALF]], i32 0
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x half> [[TMP7]], half 0.000000e+00, i32 1
-; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x half> [[TMP8]], half 0.000000e+00, i32 2
-; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x half> [[TMP9]], half 0.000000e+00, i32 3
-; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x half> [[TMP10]], half 0.000000e+00, i32 4
-; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x half> [[ARG8_2XHALF]], i32 0
-; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x half> [[TMP11]], half [[TMP12]], i32 5
-; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x half> [[ARG8_2XHALF]], i32 1
-; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x half> [[TMP13]], half [[TMP14]], i32 6
-; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x half> [[TMP15]], half [[ARG7_HALF]], i32 7
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x half> poison, half [[ARG6_HALF]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x half> [[TMP10]], half 0.000000e+00, i64 1
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x half> [[TMP11]], half 0.000000e+00, i64 2
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x half> [[TMP12]], half 0.000000e+00, i64 3
+; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x half> [[TMP13]], half 0.000000e+00, i64 4
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x half> [[ARG8_2XHALF]], i64 0
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x half> [[TMP14]], half [[TMP15]], i64 5
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x half> [[ARG8_2XHALF]], i64 1
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x half> [[TMP7]], half [[TMP8]], i64 6
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x half> [[TMP9]], half [[ARG7_HALF]], i64 7
; CHECK-NEXT: store <8 x half> [[TMP16]], ptr addrspace(3) [[TMP6]], align 2
; CHECK-NEXT: br [[DOTEXIT_POINT]]
; CHECK: [[_EXIT_POINT:.*:]]
@@ -156,8 +156,8 @@ define void @variadics1(ptr %vlist) {
; CHECK-NEXT: [[X2:%.*]] = getelementptr i8, ptr [[ARGP_NEXT12]], i32 7
; CHECK-NEXT: [[ARGP_CUR16_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[X2]], i64 0)
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARGP_CUR16_ALIGNED]], align 4294967296
-; CHECK-NEXT: [[X31:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
-; CHECK-NEXT: [[X42:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; CHECK-NEXT: [[X31:%.*]] = extractelement <2 x double> [[TMP1]], i64 0
+; CHECK-NEXT: [[X42:%.*]] = extractelement <2 x double> [[TMP1]], i64 1
; CHECK-NEXT: [[X5:%.*]] = fadd double [[X42]], [[X31]]
; CHECK-NEXT: store double [[X5]], ptr null, align 8
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/opaque-ptr.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/opaque-ptr.ll
index 12d06df448fbb..1060f7a567d79 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/X86/opaque-ptr.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/opaque-ptr.ll
@@ -4,8 +4,8 @@
define void @test(ptr %ptr) {
; CHECK-LABEL: @test(
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[PTR:%.*]], align 4
-; CHECK-NEXT: [[L11:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[L22:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[L11:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[L22:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[PTR]], align 4
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-nested-add.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-nested-add.ll
index ed77318936ff3..cc90f19fe02af 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-nested-add.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-nested-add.ll
@@ -24,10 +24,10 @@ define void @or_disjoint_inner(i32 %v0, i32 %v1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[EA:%.*]] = sext i32 [[A]] to i64
; CHECK-NEXT: [[GA:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[EA]]
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[GA]], align 1
-; CHECK-NEXT: [[LA1:%.*]] = extractelement <4 x i8> [[TMP0]], i32 0
-; CHECK-NEXT: [[LB2:%.*]] = extractelement <4 x i8> [[TMP0]], i32 1
-; CHECK-NEXT: [[LC3:%.*]] = extractelement <4 x i8> [[TMP0]], i32 2
-; CHECK-NEXT: [[LD4:%.*]] = extractelement <4 x i8> [[TMP0]], i32 3
+; CHECK-NEXT: [[LA1:%.*]] = extractelement <4 x i8> [[TMP0]], i64 0
+; CHECK-NEXT: [[LB2:%.*]] = extractelement <4 x i8> [[TMP0]], i64 1
+; CHECK-NEXT: [[LC3:%.*]] = extractelement <4 x i8> [[TMP0]], i64 2
+; CHECK-NEXT: [[LD4:%.*]] = extractelement <4 x i8> [[TMP0]], i64 3
; CHECK-NEXT: [[R0:%.*]] = insertelement <4 x i8> poison, i8 [[LA1]], i32 0
; CHECK-NEXT: [[R1:%.*]] = insertelement <4 x i8> [[R0]], i8 [[LB2]], i32 1
; CHECK-NEXT: [[R2:%.*]] = insertelement <4 x i8> [[R1]], i8 [[LC3]], i32 2
@@ -79,10 +79,10 @@ define void @or_disjoint_both_inner(i32 %v0, i32 %v1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[EA:%.*]] = sext i32 [[A]] to i64
; CHECK-NEXT: [[GA:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[EA]]
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[GA]], align 1
-; CHECK-NEXT: [[LA1:%.*]] = extractelement <4 x i8> [[TMP0]], i32 0
-; CHECK-NEXT: [[LB2:%.*]] = extractelement <4 x i8> [[TMP0]], i32 1
-; CHECK-NEXT: [[LC3:%.*]] = extractelement <4 x i8> [[TMP0]], i32 2
-; CHECK-NEXT: [[LD4:%.*]] = extractelement <4 x i8> [[TMP0]], i32 3
+; CHECK-NEXT: [[LA1:%.*]] = extractelement <4 x i8> [[TMP0]], i64 0
+; CHECK-NEXT: [[LB2:%.*]] = extractelement <4 x i8> [[TMP0]], i64 1
+; CHECK-NEXT: [[LC3:%.*]] = extractelement <4 x i8> [[TMP0]], i64 2
+; CHECK-NEXT: [[LD4:%.*]] = extractelement <4 x i8> [[TMP0]], i64 3
; CHECK-NEXT: [[R0:%.*]] = insertelement <4 x i8> poison, i8 [[LA1]], i32 0
; CHECK-NEXT: [[R1:%.*]] = insertelement <4 x i8> [[R0]], i8 [[LB2]], i32 1
; CHECK-NEXT: [[R2:%.*]] = insertelement <4 x i8> [[R1]], i8 [[LC3]], i32 2
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-zext.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-zext.ll
index 4ec22a18479b7..e26df87b8d986 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-zext.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/or-disjoint-zext.ll
@@ -13,9 +13,9 @@ define void @test_zext_add(ptr %base, i32 %idx) {
; CHECK-NEXT: [[I0:%.*]] = zext i32 [[IDX]] to i64
; CHECK-NEXT: [[G0:%.*]] = getelementptr inbounds i32, ptr [[BASE]], i64 [[I0]]
; CHECK-NEXT: [[TMP1:%.*]] = load <3 x i32>, ptr [[G0]], align 4
-; CHECK-NEXT: [[V01:%.*]] = extractelement <3 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[V12:%.*]] = extractelement <3 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[V23:%.*]] = extractelement <3 x i32> [[TMP1]], i32 2
+; CHECK-NEXT: [[V01:%.*]] = extractelement <3 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[V12:%.*]] = extractelement <3 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[V23:%.*]] = extractelement <3 x i32> [[TMP1]], i64 2
; CHECK-NEXT: [[IDX3:%.*]] = add nuw i32 [[IDX]], 3
; CHECK-NEXT: [[I3:%.*]] = zext i32 [[IDX3]] to i64
; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i32, ptr [[BASE]], i64 [[I3]]
@@ -63,9 +63,9 @@ define void @test_zext_or_disjoint(ptr %base, i32 %idx) {
; CHECK-NEXT: [[I0:%.*]] = zext i32 [[IDX]] to i64
; CHECK-NEXT: [[G0:%.*]] = getelementptr inbounds i32, ptr [[BASE]], i64 [[I0]]
; CHECK-NEXT: [[TMP1:%.*]] = load <3 x i32>, ptr [[G0]], align 4
-; CHECK-NEXT: [[V01:%.*]] = extractelement <3 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[V12:%.*]] = extractelement <3 x i32> [[TMP1]], i32 1
-; CHECK-NEXT: [[V23:%.*]] = extractelement <3 x i32> [[TMP1]], i32 2
+; CHECK-NEXT: [[V01:%.*]] = extractelement <3 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[V12:%.*]] = extractelement <3 x i32> [[TMP1]], i64 1
+; CHECK-NEXT: [[V23:%.*]] = extractelement <3 x i32> [[TMP1]], i64 2
; CHECK-NEXT: [[B3:%.*]] = or disjoint i32 [[IDX]], 3
; CHECK-NEXT: [[I3:%.*]] = zext i32 [[B3]] to i64
; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i32, ptr [[BASE]], i64 [[I3]]
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/scev-range-zext.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/scev-range-zext.ll
index 74fe2bc4f1c1a..b4dc080411408 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/X86/scev-range-zext.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/scev-range-zext.ll
@@ -26,8 +26,8 @@ define void @scev_range_urem_bounded(ptr noalias %in, ptr noalias %out, i32 %idx
; CHECK-NEXT: [[EXT0:%.*]] = zext i32 [[BOUNDED]] to i64
; CHECK-NEXT: [[GEP0:%.*]] = getelementptr i8, ptr [[IN]], i64 [[EXT0]]
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[GEP0]], align 4
-; CHECK-NEXT: [[V01:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[V42:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[V01:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[V42:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[S:%.*]] = add i32 [[V01]], [[V42]]
; CHECK-NEXT: store i32 [[S]], ptr [[OUT]], align 4
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add-inseltpoison.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add-inseltpoison.ll
index 6b9229e8dfd6d..416c756668de3 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add-inseltpoison.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add-inseltpoison.ll
@@ -15,11 +15,11 @@ define void @ld_v4i8_add_nsw(i32 %v0, i32 %v1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[V1:%.*]], [[TMP]]
; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP2]]
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1
-; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP133:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[TMP184:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i8> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i8> [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP133:%.*]] = extractelement <4 x i8> [[TMP0]], i64 2
+; CHECK-NEXT: [[TMP184:%.*]] = extractelement <4 x i8> [[TMP0]], i64 3
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> poison, i8 [[TMP41]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP82]], i32 1
; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP133]], i32 2
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll
index cf575cef2d1ba..82ae3241303c4 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll
@@ -15,16 +15,16 @@ define void @ld_v4i8_add_nsw(i32 %v0, i32 %v1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[V1:%.*]], [[TMP]]
; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP2]]
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1
-; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP133:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[TMP184:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i8> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i8> [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP133:%.*]] = extractelement <4 x i8> [[TMP0]], i64 2
+; CHECK-NEXT: [[TMP184:%.*]] = extractelement <4 x i8> [[TMP0]], i64 3
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> undef, i8 [[TMP41]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP82]], i32 1
; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP133]], i32 2
; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP184]], i32 3
-; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]], align 4
; CHECK-NEXT: ret void
;
bb:
@@ -63,16 +63,16 @@ define void @ld_v4i8_add_nsw_operand_orders(i32 %v0, i32 %v1, ptr %src, ptr %dst
; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[V1:%.*]], [[TMP]]
; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP2]]
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1
-; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP133:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[TMP184:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1
+; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i8> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i8> [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP133:%.*]] = extractelement <4 x i8> [[TMP0]], i64 2
+; CHECK-NEXT: [[TMP184:%.*]] = extractelement <4 x i8> [[TMP0]], i64 3
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> undef, i8 [[TMP41]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP82]], i32 1
; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP133]], i32 2
; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP184]], i32 3
-; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]], align 4
; CHECK-NEXT: ret void
;
bb:
@@ -116,15 +116,15 @@ define void @ld_v4i8_add_known_bits(i32 %ind0, i32 %ind1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[V1]], [[V0]]
; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[TMP6]]
-; CHECK-NEXT: [[TMP1:%.*]] = load <3 x i8>, ptr [[TMP7]], align 1
-; CHECK-NEXT: [[TMP81:%.*]] = extractelement <3 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP132:%.*]] = extractelement <3 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP183:%.*]] = extractelement <3 x i8> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP0:%.*]] = load <3 x i8>, ptr [[TMP7]], align 1
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <3 x i8> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP132:%.*]] = extractelement <3 x i8> [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP183:%.*]] = extractelement <3 x i8> [[TMP0]], i64 2
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> undef, i8 [[TMP4]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP81]], i32 1
; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP132]], i32 2
; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP183]], i32 3
-; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]], align 4
; CHECK-NEXT: ret void
;
bb:
@@ -166,15 +166,15 @@ define void @ld_v4i8_add_known_bits1(i32 %ind0, i32 %ind1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP6]]
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[TMP7]], align 1
-; CHECK-NEXT: [[TMP81:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP132:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP183:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <4 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP132:%.*]] = extractelement <4 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP183:%.*]] = extractelement <4 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i8> [[TMP1]], i64 3
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> undef, i8 [[TMP44]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP81]], i32 1
; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP132]], i32 2
; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP183]], i32 3
-; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]], align 4
; CHECK-NEXT: ret void
;
bb:
@@ -222,15 +222,15 @@ define void @ld_v4i8_add_known_bits_by_assume(i32 %ind0, i32 %ind1, ptr %src, pt
; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP6]]
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[TMP7]], align 1
-; CHECK-NEXT: [[TMP81:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP132:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP183:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <4 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP132:%.*]] = extractelement <4 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP183:%.*]] = extractelement <4 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i8> [[TMP1]], i64 3
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> undef, i8 [[TMP44]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP81]], i32 1
; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP132]], i32 2
; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP183]], i32 3
-; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]], align 4
; CHECK-NEXT: ret void
;
bb:
@@ -288,15 +288,15 @@ define void @ld_v4i8_add_assume_on_arg(i32 %v0, i32 %v1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[V1]], [[V0]]
; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[TMP6]]
-; CHECK-NEXT: [[TMP1:%.*]] = load <3 x i8>, ptr [[TMP7]], align 1
-; CHECK-NEXT: [[TMP81:%.*]] = extractelement <3 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP132:%.*]] = extractelement <3 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP183:%.*]] = extractelement <3 x i8> [[TMP1]], i32 2
+; CHECK-NEXT: [[TMP0:%.*]] = load <3 x i8>, ptr [[TMP7]], align 1
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <3 x i8> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP132:%.*]] = extractelement <3 x i8> [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP183:%.*]] = extractelement <3 x i8> [[TMP0]], i64 2
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> undef, i8 [[TMP4]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP81]], i32 1
; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP132]], i32 2
; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP183]], i32 3
-; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]], align 4
; CHECK-NEXT: ret void
;
bb:
@@ -346,15 +346,15 @@ define void @ld_v4i8_add_assume_on_arg1(i32 %v0, i32 %v1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP6]]
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[TMP7]], align 1
-; CHECK-NEXT: [[TMP81:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP132:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
-; CHECK-NEXT: [[TMP183:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
-; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <4 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP132:%.*]] = extractelement <4 x i8> [[TMP1]], i64 1
+; CHECK-NEXT: [[TMP183:%.*]] = extractelement <4 x i8> [[TMP1]], i64 2
+; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i8> [[TMP1]], i64 3
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> undef, i8 [[TMP44]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP81]], i32 1
; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP132]], i32 2
; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP183]], i32 3
-; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]], align 4
; CHECK-NEXT: ret void
;
bb:
@@ -407,11 +407,11 @@ define void @ld_v2i8_add_different_contexts(i32 %ind0, i32 %ind1, ptr %src, ptr
; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP6]]
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr [[TMP7]], align 1
-; CHECK-NEXT: [[TMP81:%.*]] = extractelement <2 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <2 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i8> [[TMP1]], i64 1
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <2 x i8> undef, i8 [[TMP42]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <2 x i8> [[TMP19]], i8 [[TMP81]], i32 1
-; CHECK-NEXT: store <2 x i8> [[TMP20]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <2 x i8> [[TMP20]], ptr [[DST:%.*]], align 2
; CHECK-NEXT: br label [[BB_SKIP]]
; CHECK: bb.skip:
; CHECK-NEXT: ret void
@@ -456,12 +456,12 @@ define void @ld_v2i8_add_different_contexts1(i32 %ind0, i32 %ind1, ptr %src, ptr
; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP6]]
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr [[TMP7]], align 1
-; CHECK-NEXT: [[TMP81:%.*]] = extractelement <2 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <2 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i8> [[TMP1]], i64 1
; CHECK-NEXT: call void @llvm.assume(i1 [[BIT_COND]])
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <2 x i8> undef, i8 [[TMP42]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <2 x i8> [[TMP19]], i8 [[TMP81]], i32 1
-; CHECK-NEXT: store <2 x i8> [[TMP20]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <2 x i8> [[TMP20]], ptr [[DST:%.*]], align 2
; CHECK-NEXT: br label [[BB_SKIP]]
; CHECK: bb.skip:
; CHECK-NEXT: ret void
@@ -503,13 +503,13 @@ define void @ld_v2i8_add_context(i32 %ind0, i32 %ind1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP6]]
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr [[TMP7]], align 1
-; CHECK-NEXT: [[TMP81:%.*]] = extractelement <2 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <2 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i8> [[TMP1]], i64 1
; CHECK-NEXT: [[BIT_COND:%.*]] = icmp eq i32 [[TMP5]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[BIT_COND]])
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <2 x i8> undef, i8 [[TMP42]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <2 x i8> [[TMP19]], i8 [[TMP81]], i32 1
-; CHECK-NEXT: store <2 x i8> [[TMP20]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <2 x i8> [[TMP20]], ptr [[DST:%.*]], align 2
; CHECK-NEXT: ret void
;
bb:
@@ -543,11 +543,11 @@ define void @ld_v2i8_add_context1(i32 %ind0, i32 %ind1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[TMP6]]
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr [[TMP7]], align 1
-; CHECK-NEXT: [[TMP81:%.*]] = extractelement <2 x i8> [[TMP1]], i32 0
-; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i8> [[TMP1]], i32 1
+; CHECK-NEXT: [[TMP81:%.*]] = extractelement <2 x i8> [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i8> [[TMP1]], i64 1
; CHECK-NEXT: [[TMP19:%.*]] = insertelement <2 x i8> undef, i8 [[TMP42]], i32 0
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <2 x i8> [[TMP19]], i8 [[TMP81]], i32 1
-; CHECK-NEXT: store <2 x i8> [[TMP20]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <2 x i8> [[TMP20]], ptr [[DST:%.*]], align 2
; CHECK-NEXT: [[BIT_COND:%.*]] = icmp eq i32 [[TMP5]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[BIT_COND]])
; CHECK-NEXT: ret void
@@ -602,7 +602,7 @@ define void @ld_v4i8_add_not_safe(i32 %v0, i32 %v1, ptr %src, ptr %dst) {
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP8]], i32 1
; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP13]], i32 2
; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP18]], i32 3
-; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]]
+; CHECK-NEXT: store <4 x i8> [[TMP22]], ptr [[DST:%.*]], align 4
; CHECK-NEXT: ret void
;
bb:
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-redund-loads.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-redund-loads.ll
index e2744d778fb1d..02c67802c5d2a 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-redund-loads.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-redund-loads.ll
@@ -5,12 +5,12 @@ define void @test(ptr %ptr) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[PTR]], align 8
-; CHECK-NEXT: [[LD01:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
-; CHECK-NEXT: [[LD12:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
+; CHECK-NEXT: [[LD01:%.*]] = extractelement <2 x i32> [[TMP1]], i64 0
+; CHECK-NEXT: [[LD12:%.*]] = extractelement <2 x i32> [[TMP1]], i64 1
; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i32 8
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[GEP2]], align 8
; CHECK-NEXT: [[LD23:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <2 x i32> <i32 0, i32 1>
-; CHECK-NEXT: [[LD34:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0
+; CHECK-NEXT: [[LD34:%.*]] = extractelement <2 x i32> [[TMP2]], i64 0
; CHECK-NEXT: ret void
;
%ld0 = load i32, ptr %ptr, align 8
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/int_sideeffect.ll b/llvm/test/Transforms/LoadStoreVectorizer/int_sideeffect.ll
index b20d3ca4f6029..d644300682268 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/int_sideeffect.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/int_sideeffect.ll
@@ -9,16 +9,16 @@ declare void @llvm.sideeffect()
define void @test_sideeffect(ptr %p) {
; CHECK-LABEL: @test_sideeffect(
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[P:%.*]], align 16
-; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x float> [[TMP2]], i32 1
-; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x float> [[TMP2]], i32 2
-; CHECK-NEXT: [[L34:%.*]] = extractelement <4 x float> [[TMP2]], i32 3
+; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x float> [[TMP2]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x float> [[TMP2]], i64 1
+; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x float> [[TMP2]], i64 2
+; CHECK-NEXT: [[L34:%.*]] = extractelement <4 x float> [[TMP2]], i64 3
; CHECK-NEXT: call void @llvm.sideeffect()
; CHECK-NEXT: call void @llvm.sideeffect()
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[L01]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[L12]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[L23]], i32 2
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[L34]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> poison, float [[L01]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP5]], float [[L12]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[L23]], i64 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP4]], float [[L34]], i64 3
; CHECK-NEXT: store <4 x float> [[TMP6]], ptr [[P]], align 16
; CHECK-NEXT: ret void
;
@@ -43,16 +43,16 @@ declare void @foo()
define void @test_inaccessiblememonly_nounwind_willreturn(ptr %p) {
; CHECK-LABEL: @test_inaccessiblememonly_nounwind_willreturn(
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[P:%.*]], align 16
-; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
-; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x float> [[TMP2]], i32 1
-; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x float> [[TMP2]], i32 2
-; CHECK-NEXT: [[L34:%.*]] = extractelement <4 x float> [[TMP2]], i32 3
+; CHECK-NEXT: [[L01:%.*]] = extractelement <4 x float> [[TMP2]], i64 0
+; CHECK-NEXT: [[L12:%.*]] = extractelement <4 x float> [[TMP2]], i64 1
+; CHECK-NEXT: [[L23:%.*]] = extractelement <4 x float> [[TMP2]], i64 2
+; CHECK-NEXT: [[L34:%.*]] = extractelement <4 x float> [[TMP2]], i64 3
; CHECK-NEXT: call void @foo() #[[ATTR1:[0-9]+]]
; CHECK-NEXT: call void @foo() #[[ATTR1]]
-; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[L01]], i32 0
-; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[L12]], i32 1
-; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[L23]], i32 2
-; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP5]], float [[L34]], i32 3
+; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> poison, float [[L01]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP5]], float [[L12]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float [[L23]], i64 2
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x float> [[TMP4]], float [[L34]], i64 3
; CHECK-NEXT: store <4 x float> [[TMP6]], ptr [[P]], align 16
; CHECK-NEXT: ret void
;
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