[llvm] [RISCV][P-ext] Move v2i16 and v4i8 extract_subvector handling to tablegen. NFC (PR #208863)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/208863.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+3-15) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+10) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index df0a34ea27685..f58d947390f68 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3112,25 +3112,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
   }
   case ISD::EXTRACT_SUBVECTOR:
   case RISCVISD::TUPLE_EXTRACT: {
+    if (Subtarget->hasStdExtP())
+      break;
+
     SDValue V = Node->getOperand(0);
     auto Idx = Node->getConstantOperandVal(1);
     MVT InVT = V.getSimpleValueType();
 
-    // Handle P-extension extract_subvector for v2i16 from v4i16 and v4i8 from
-    // v8i8
-    if (Subtarget->hasStdExtP() && !Subtarget->is64Bit() &&
-        ((InVT == MVT::v4i16 && VT == MVT::v2i16) ||
-         (InVT == MVT::v8i8 && VT == MVT::v4i8))) {
-      unsigned NumElts = VT.getVectorNumElements();
-      if (Idx != 0 && Idx != NumElts)
-        break;
-
-      unsigned SubRegIdx = Idx == 0 ? RISCV::sub_gpr_even : RISCV::sub_gpr_odd;
-      SDValue Extract = CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, V);
-      ReplaceNode(Node, Extract.getNode());
-      return;
-    }
-
     SDLoc DL(V);
 
     const RISCVTargetLowering &TLI = *Subtarget->getTargetLowering();
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 7fa7c96ca99ca..1b2a652259ca2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2539,6 +2539,16 @@ let append Predicates = [IsRV32] in {
             (EXTRACT_SUBREG GPRPair:$vec, sub_gpr_even)>;
   def : Pat<(i32 (extractelt (v2i32 GPRPair:$vec), (i32 1))),
             (EXTRACT_SUBREG GPRPair:$vec, sub_gpr_odd)>;
+
+  def : Pat<(v2i16 (extract_subvector (v4i16 GPRPair:$vec), (i32 0))),
+            (EXTRACT_SUBREG GPRPair:$vec, sub_gpr_even)>;
+  def : Pat<(v2i16 (extract_subvector (v4i16 GPRPair:$vec), (i32 2))),
+            (EXTRACT_SUBREG GPRPair:$vec, sub_gpr_odd)>;
+
+  def : Pat<(v4i8 (extract_subvector (v8i8 GPRPair:$vec), (i32 0))),
+            (EXTRACT_SUBREG GPRPair:$vec, sub_gpr_even)>;
+  def : Pat<(v4i8 (extract_subvector (v8i8 GPRPair:$vec), (i32 4))),
+            (EXTRACT_SUBREG GPRPair:$vec, sub_gpr_odd)>;
 } // append Predicates = [IsRV32]
 
 let append Predicates = [IsRV64] in {

``````````

</details>


https://github.com/llvm/llvm-project/pull/208863