[llvm] [AMDGPU][TTI] Refine gfx9 packed FP32 SLP costs for pair formation and shuffles (PR #208572)

[Krzysztof Drewniak via llvm-commits]

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@@ -1344,6 +1355,15 @@ InstructionCost GCNTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
   Kind = improveShuffleKindFromMask(Kind, Mask, SrcTy, Index, SubTp);
 
   unsigned ScalarSize = DL.getTypeSizeInBits(SrcTy->getElementType());
+
+  // Gfx9 packed FP32 shuffles are free. InsertElement above already taxes
+  // assembling <2 x f32> pairs, and a per-lane shuffle cost stacks on top and
+  // over-penalizes SLP. f32-only on gfx9 targets with packed FP32 ops.
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krzysz00 wrote:

Wait, *are* there non-gfx9 workloads this would impact? I thought I read that the flag you're testing is only true on gfx9.

(The point of my comment is "I've seen reviewers get annoyed with generation checks that should've been feature checks")

https://github.com/llvm/llvm-project/pull/208572