[llvm] DAGCombiner: use actual downstream demand when calling SimplifyDemandedBits for SRL (PR #208772)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/unittests/CodeGen/DAGCombinerTest.cpp llvm/include/llvm/CodeGen/SelectionDAG.h llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index e71744459..36ac7149d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -15345,8 +15345,7 @@ static APInt computeDemandedBitsFromUsesImpl(SDValue Op, unsigned Depth,
     // must not borrow that result's demand), so each case is guarded on Op's
     // operand position.  Anything not modeled falls through to all-ones.
     bool OpIsLHS = User->getOperand(0) == Op;
-    bool OpIsRHS =
-        User->getNumOperands() > 1 && User->getOperand(1) == Op;
+    bool OpIsRHS = User->getNumOperands() > 1 && User->getOperand(1) == Op;
 
     APInt Contrib = AllOnes;
     switch (User->getOpcode()) {
diff --git a/llvm/unittests/CodeGen/DAGCombinerTest.cpp b/llvm/unittests/CodeGen/DAGCombinerTest.cpp
index 2b8ac1c55..cdbe81b19 100644
--- a/llvm/unittests/CodeGen/DAGCombinerTest.cpp
+++ b/llvm/unittests/CodeGen/DAGCombinerTest.cpp
@@ -23,8 +23,9 @@ using namespace llvm;
 // computeDemandedBitsFromUses walks the use chain of an SRL upward and
 // returns the union of bits demanded by all downstream users.  These tests
 // verify the demand computation directly against constructed DAG nodes,
-// without running the full DAGCombiner pass (which requires FunctionLoweringInfo
-// and other infrastructure not available in this lightweight fixture).
+// without running the full DAGCombiner pass (which requires
+// FunctionLoweringInfo and other infrastructure not available in this
+// lightweight fixture).
 //
 // The fixture uses x86-64 rather than AArch64 because this test suite is
 // compiled with X86 always enabled; SelectionDAGTestBase uses AArch64 and
@@ -94,8 +95,7 @@ TEST_F(DAGCombinerTest, SimpleDownstreamAndAnchorsDemand) {
 
   SDValue X = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
                                   Register::index2VirtReg(1), VT);
-  SDValue Srl = DAG->getNode(ISD::SRL, DL, VT, X,
-                             DAG->getConstant(8, DL, VT));
+  SDValue Srl = DAG->getNode(ISD::SRL, DL, VT, X, DAG->getConstant(8, DL, VT));
   // Downstream consumer: only bits[0:7] demanded.
   DAG->getNode(ISD::AND, DL, VT, Srl, DAG->getConstant(255, DL, VT));
 
@@ -115,8 +115,7 @@ TEST_F(DAGCombinerTest, XorUserWithNoAnchorReturnsAllOnes) {
                                   Register::index2VirtReg(1), VT);
   SDValue Y = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
                                   Register::index2VirtReg(2), VT);
-  SDValue Srl = DAG->getNode(ISD::SRL, DL, VT, X,
-                             DAG->getConstant(8, DL, VT));
+  SDValue Srl = DAG->getNode(ISD::SRL, DL, VT, X, DAG->getConstant(8, DL, VT));
   // XOR with no further narrowing consumer: all bits demanded.
   DAG->getNode(ISD::XOR, DL, VT, Srl, Y);
 
@@ -145,11 +144,11 @@ TEST_F(DAGCombinerTest, MultiHopXorSrlChainPropagatesDemand) {
                                   Register::index2VirtReg(1), VT);
 
   // Inner SRL — the node under test.
-  SDValue InnerSrl = DAG->getNode(ISD::SRL, DL, VT, X,
-                                  DAG->getConstant(8, DL, VT));
+  SDValue InnerSrl =
+      DAG->getNode(ISD::SRL, DL, VT, X, DAG->getConstant(8, DL, VT));
   SDValue Xor1 = DAG->getNode(ISD::XOR, DL, VT, InnerSrl, X);
-  SDValue OuterSrl = DAG->getNode(ISD::SRL, DL, VT, Xor1,
-                                  DAG->getConstant(4, DL, VT));
+  SDValue OuterSrl =
+      DAG->getNode(ISD::SRL, DL, VT, Xor1, DAG->getConstant(4, DL, VT));
   SDValue Xor2 = DAG->getNode(ISD::XOR, DL, VT, OuterSrl, Xor1);
   // Anchor: only bits[0:3] demanded from the chain.
   DAG->getNode(ISD::AND, DL, VT, Xor2, DAG->getConstant(15, DL, VT));

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https://github.com/llvm/llvm-project/pull/208772