[llvm] [AMDGPU][TTI] Refine gfx9 packed FP32 SLP costs for pair formation and shuffles (PR #208572)

[Akash Dutta via llvm-commits]

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@@ -1042,6 +1042,17 @@ InstructionCost GCNTTIImpl::getVectorInstrCost(
                                        VIC);
     }
 
+    // Gfx9 packed <2 x f32> pair formation for v_pk_*_f32: lanes must occupy an
+    // aligned VGPR pair. A load-fed insert can be allocated into its slot for
+    // free; a compute-fed insert typically needs an alignment move, so charge 1.
+    // f32-only on gfx9 targets with packed FP32 ops.
+    if (Opcode == Instruction::InsertElement && EltSize == 32 &&
+        ST->hasPackedFP32Ops() && ST->getGeneration() == AMDGPUSubtarget::GFX9)
+      if (auto *VecTy = dyn_cast<FixedVectorType>(ValTy))
+        if (VecTy->getNumElements() == 2 &&
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akadutta wrote:

1. v_pk_{add,mul,fma}_f32 is 2-wide. SLP's relevant AMDGPU pattern is <2 x float> from AMDGPU TTI. getMaximumVF for f32 with packed FP32 for arithmetic ops is already 2 in AMDGPU TTI.
2. getVectorInstrCost is per instruction, not per vector. It returns the cost of one insertelement. A formula like NumElements / 2 would charge a single insert into <4 x f32> as cost 2, even though only one lane is being placed. If SLP does four inserts, that becomes 8 total insert cost — likely overestimates the cost of assembling wider vectors from scalar lanes..
3. Wider vectors are unchanged today: only <2 x f32> hits this path; other widths fall through to the existing default insert cost of 0.

https://github.com/llvm/llvm-project/pull/208572